A communication method for an on-chip external interface

Abstract

The present application provides a communication method for an on-chip external interface, which relates to the field of data transmission technology. After receiving an external access request from a CPU or other master device, it detects whether the external bus is idle; wherein, when the external bus is detected to be in an idle state, a bus request signal is generated; when no valid chip select signal is detected on the external bus within a set clock, a valid chip select signal is generated to obtain the right to use the external bus to access the outside as a host; bus communication is performed according to the configured single-line control mode or two-line control mode, and after completing data transmission, the right to use the external bus is relinquished to be accessed by an external host as a slave. Thus, the chip has the function of switching between master and slave modes, enabling the chip to access the outside as a host or to be accessed by an external host as a slave, thereby flexibly responding to different communication scenarios.

Description

Technical Field

[0001] The present application relates to the technical field of data transmission, and in particular to a communication method of an on-chip external interface. Background Art

[0002] Currently, the chip does not support master-slave switching, that is, it only supports a single master device or slave device mode, and does not support master-slave mode. Among them, the external storage device is SRAM. The timing diagram of the chip's read and write access to the external device is shown in the appendix of the manual. Figure 2 For example, in a simple memory system, a microprocessor, acting as a master, can send read and write commands to an SRAM (slave). The master is responsible for generating address signals (ADDR), control signals (such as the read signal RD_n and the write signal WR_n), and providing the data signal (DATA) during write operations. When the master performs a read operation, it first selects the SRAM chip to be read by enabling the relevant chip select signal (MSx_n). The master then pulls the read signal (RD_n) low while simultaneously sending the specified address (ADDR) to the SRAM. After receiving these signals, the SRAM places the data from the corresponding memory cell on the data line (DATA) based on the address. The master then retrieves the data from the data line. During a write operation, the master first enables the chip select signal, pulls the write signal (WR_n) low, places the data to be written on the data line, and simultaneously sends the address of the target memory cell. The SRAM then writes the data on the data line to the memory cell specified by the address.

[0003] However, if a chip doesn't support master-slave switching, its role in the bus architecture is fixed, making it inflexible in complex multi-master systems. For example, in the growing smart home system, multiple controllers (such as mobile phones and smart gateways) may all want to access data from a sensor chip. If the sensor chip can't switch to a slave, it can't meet the communication needs of these multi-master devices. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a communication method for an on-chip external interface, which can switch the master / slave mode of the chip, allowing the chip to access the outside as a host or allow the chip to be accessed by an external host as a slave, thereby flexibly responding to different communication scenarios.

[0005] In a first aspect, an embodiment of the present application provides a communication method for an on-chip external interface, the method comprising the following steps:

[0006] After receiving an external access request from a CPU or other master device, detecting whether the external bus is idle; wherein, when the external bus is detected to be in an idle state, generating a bus request signal;

[0007] Within a set clock after the bus request signal is generated, detecting whether there is a valid chip select signal on the external bus; wherein, if no valid chip select signal is detected on the external bus within the set clock, generating a valid chip select signal to obtain the right to use the external bus to access the outside as a host; if a valid chip select signal is detected on the external bus within the set clock, and the chip select signal is invalid, re-detecting whether there is a valid chip select signal on the external bus within the set clock;

[0008] The bus communication is performed according to the configured single-line control mode or two-line control mode, and after completing the data transmission, the external bus usage right is given up to be accessed by the external host as a slave.

[0009] In a possible implementation, the CPU inside the chip configures the ID register of the external interface to assign an ID number to each chip, and the larger the ID number, the lower the priority of obtaining the right to use the external bus.

[0010] In a possible implementation, within ID+1 clocks after the bus request signal is generated, it is detected whether there is a valid chip select signal on the external bus.

[0011] In a possible implementation, performing bus communication according to the configured single-line control mode or dual-line control mode includes the following steps:

[0012] While generating the address signal, the base address control signal is output according to the base address control register for address offset;

[0013] Send a write operation command once, and write the ID number of the chip to be received at address zero to enable the chip that needs to receive information; if the data written to address zero is all zero, it means that all chips need to receive the write data request sent by the chip;

[0014] The valid bit of the write data is determined according to the defined write data valid flag.

[0015] In a possible implementation, a shared bus is used to connect multiple chips to the same bus.

[0016] In a possible implementation, giving up the right to use the external bus so as to be accessed by the external host as a slave includes the following steps:

[0017] Receive command signals sent by the host;

[0018] When receiving an operation with a write address of zero, determine the data to be written; if the written data is zero, receive subsequent write operation requests; if the written data is not zero, determine whether it matches the chip ID number, and if so, process subsequent data access requests.

[0019] In one possible implementation, if the command signal received from the host is a write operation command, an operation of writing the write data to the corresponding address is performed; if the command signal received from the host is a read operation command, an operation of reading the register of the corresponding address and placing it on the bus is performed.

[0020] In one possible implementation, when executing an operation of writing write data to a corresponding address, or executing an operation of reading a register of a corresponding address and placing it on a bus, if the read data cannot be returned in time or the bus is busy when writing data, the bus is maintained in a valid state until valid data of the host read address is returned or the host write operation is completed, and then the bus valid state is released.

[0021] In a second aspect, the present application provides an electronic device comprising: a processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor and the memory communicate through the bus, and when the machine-readable instructions are executed by the processor, the steps of the on-chip external interface communication method as described in any one of the first aspects are performed.

[0022] In a third aspect, the present application provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the on-chip external interface communication method as described in any one of the first aspects are executed.

[0023] The technical solutions provided by the embodiments of the present application may have the following beneficial effects:

[0024] The present application provides a communication method for an on-chip external interface, which detects whether an external bus is idle after receiving an external access request from a CPU or other master device; wherein, when the external bus is detected to be in an idle state, a bus request signal is generated; within a set clock after the bus request signal is generated, whether there is a valid chip select signal on the external bus is detected; wherein, when no valid chip select signal is detected on the external bus within the set clock, a valid chip select signal is generated to obtain the right to use the external bus to access the outside as a host; when a valid chip select signal is detected on the external bus within the set clock, if the chip select signal is invalid, re-detects whether there is a valid chip select signal on the external bus within the set clock; performs bus communication according to a configured single-line control mode or a two-line control mode, and after completing data transmission, gives up the right to use the external bus to be accessed by an external host as a slave. Thus, the chip has the function of switching between master and slave modes, enabling the chip to access the outside as a host or to be accessed by an external host as a slave, thereby flexibly responding to different communication scenarios.

[0025] In some embodiments, an ID number is assigned to each chip, and the larger the ID number, the lower the priority of obtaining the right to use the external bus, thereby avoiding bus conflicts and data transmission errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 A flow chart showing a communication method for an on-chip external interface provided in an embodiment of the present application is shown;

[0028] Figure 2 The figure shows a timing diagram of the chip performing read and write access to the external storage device in the prior art, when the external storage device is SRAM;

[0029] Figure 3 This figure shows a flowchart of the chip in the master mode as a host accessing the outside world in an embodiment of the present application;

[0030] Figure 4 A flowchart showing the chip in the embodiment of the present application being accessed externally as a slave device when the chip is in slave mode;

[0031] Figure 5 A schematic diagram of an external interface bus according to an embodiment of the present application is shown;

[0032] Figure 6 A schematic diagram of a data transmission protocol using a single-line control mode is shown for a chip according to an embodiment of the present application;

[0033] Figure 7 A schematic diagram of a data transmission protocol using a dual-wire control mode in a chip according to an embodiment of the present application is shown;

[0034] Figure 8 The timing diagram of the chip with ID 3 in the embodiment of the present application applying for and occupying the bus is shown;

[0035] Figure 9 The timing diagram of the embodiment of the present application shows the chip with ID 1 performing a write address A1 and then a read operation;

[0036] Figure 10 The figure shows a structural block diagram of the electronic device described in the embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of illustration and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowcharts can be implemented out of sequence, and steps without logical context can be reversed or implemented simultaneously. In addition, those skilled in the art, under the guidance of the contents of this application, can add one or more other operations to the flowchart, or remove one or more operations from the flowchart.

[0038] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0039] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.

[0040] In view of the technical problems raised by the background technology, the present application provides a communication method for an on-chip external interface, which can switch the master / slave mode of the chip, allowing the chip to access the outside as a host or allow the chip to be accessed by an external host as a slave, thereby flexibly responding to different communication scenarios.

[0041] See the instructions attached Figure 1 , the present application provides a communication method for an on-chip external interface, the method comprising the following steps:

[0042] S1. After receiving an external access request from a CPU or other master device, detecting whether the external bus is idle; wherein, when the external bus is detected to be in an idle state, generating a bus request signal;

[0043] S2. Within a set clock after the bus request signal is generated, detecting whether there is a valid chip select signal on the external bus; wherein, if no valid chip select signal is detected on the external bus within the set clock, generating a valid chip select signal to obtain the right to use the external bus to access the outside as the host; if a valid chip select signal is detected on the external bus within the set clock, and the chip select signal is invalid, re-detecting whether there is a valid chip select signal on the external bus within the set clock;

[0044] S3. Perform bus communication according to the configured single-line control mode or dual-line control mode, and after completing data transmission, give up the right to use the external bus to be accessed by the external host as a slave.

[0045] In the communication method of an on-chip external interface provided in this application, the chip external interface is in slave mode by default, and only switches to master mode after receiving an external access request from the CPU or other master device and checking the current state of the external bus. Figure 3 In host mode, the chip acts as a host to access the outside. Specifically, the chip's external interface line obtains permission by applying for the bus, then initiates data access, and releases the bus after the data access is completed; see the attached manual. Figure 4 , exiting master mode and entering slave mode, allowing the chip to be accessed as a slave by an external host. Specifically, the external host interface applies for the bus, the chip grants authorization, receives the access request, and releases the bus after data access is completed. This allows different communication modes to be adopted according to actual needs, flexibly responding to different communication scenarios. Furthermore, during system expansion, chips that support master-slave switching can better adapt to the addition of new devices, simplifying and improving system expansion performance.

[0046] In order to clearly understand the technical solution of the embodiment of the present application, the external interface of the chip of the present application can be described first. Figure 2In one embodiment, the external interface communicates with the external host through A[7:0], ADDRSEL[3:0], D[31:0], DE[3:0], CS, OE, WE, READY, and REQ signals. Among them, A[7:0] is the address bus, which serves as the address accessed by the master and slave; ADDRSEL[3:0] is the access base address selection signal, which selects the base address of the access address; D[31:0] is the data bus; DE[3:0] is the write data valid flag bit, and each bit controls one byte, which can define the valid data bit of data transmission. For example, when DE[0]=1 is valid, it means that D[7:0] is valid; when DE[1]=1 is valid, it means that D[15:8] is valid; when DE[2]=1 is valid, it means that D[23:16] is valid; when DE[3]=1 is valid, Indicates that D[31:24] is valid; CS is the chip select signal, and in this embodiment, a low level is valid; OE is the read-write control signal. In this embodiment, when a single-line control mode is used to control data transmission, a high level indicates read and a low level indicates write; when a two-line control mode is used, a low level indicates read; WE is the write control signal. In this embodiment, when a two-line control mode is used to control data transmission, a low level indicates write; READY is the bus valid state. In this embodiment, a high level indicates that the current transmission can continue, and a low level indicates that the current state needs to be maintained; REQ is the bus request signal.

[0047] In this application, single and dual-line control modes are provided for the on-chip external interface. The data transmission protocol of the chip using the single-line control mode is shown in the appendix of the specification. Figure 6 The chip adopts the dual-line control mode data transmission protocol. Please refer to the manual for the attached Figure 6 . Its specific working principle should be a technical means well known to those skilled in the art, and will not be elaborated here. The reason why this application provides single- and dual-wire control modes is that it can meet the needs of different application scenarios. For example, in the single-wire control mode, the chip pins can be saved, which is suitable for chips with small packages (chips with fewer pins); in the dual-wire control mode, although the chip pins are increased and the cost is increased, it is more functional and has stronger anti-interference ability than the single-wire control mode.

[0048] It should be noted that, in this application, multiple chips are connected to the same bus in a shared bus manner, and the device corresponding to each chip can act as a host or a slave. From the perspective of hardware connection, the use of a shared bus can simplify the wiring of the system. Compared with establishing a separate set of connection channels for each chip, the use of a shared bus only requires one set of buses to connect multiple chips, thereby achieving resource sharing and collaborative work. In addition, in this application, the chip external interface is in slave mode by default. In step S1, only after receiving an external access request from the CPU or other master device and checking the current status of the external bus, will it switch to host mode.

[0049] First, after receiving an external access request from the CPU or other master device, it is necessary to check whether the other device (CPU) is using the external bus, that is, whether REQ is low. If REQ is high, it means that another device is applying for and using the bus at this time, and the bus cannot be applied for at this time; if REQ is low, it means that no other device is applying for and using the bus at this time, and the bus is idle, and the right to use the bus can be applied for. After applying for the right to use the bus, REQ is generated at a high level.

[0050] However, in this application, the right to use the bus is not obtained immediately after applying for the right to use the bus. This is because this application sets up a waiting mechanism to ensure that devices in a system based on a shared bus can use bus resources in an orderly manner. As described in step S2, within the set clock CLK after generating the bus request signal, it is detected whether there is a valid chip select signal CS on the external bus; wherein, when it is detected that there is no valid chip select signal CS on the external bus within the set clock CLK, a valid chip select signal CS is generated to obtain the right to use the external bus in order to access the outside as the host; when it is detected that there is a valid chip select signal CS on the external bus within the set clock CLK, if the chip select signal CS is invalid, it is re-detected whether there is a valid chip select signal CS on the external bus within the set clock CLK.

[0051] In one embodiment, the chip's internal CPU configures the ID register of the external interface, assigning each chip an ID number. The larger the ID number, the lower its priority for obtaining external bus access rights; the smaller the ID number, the higher its priority for obtaining external bus access rights. A waiting mechanism is configured to detect whether there is a valid chip select signal on the external bus within ID+1 clocks after generating a bus request signal. That is, based on the chip's ID number, if there is no CS valid signal (CS=0) on the bus within (ID+1) CLKs after generating the REQ signal, the chip outputs a CS signal. If there is a CS valid signal, it indicates that another device has generated a REQ request at the same time, and the ID number of the other device generating the REQ request is smaller than that of the current device. Therefore, the chip must wait until the data transmission of the other device is completed, that is, (ID+1) clocks after CS is pulled high, to generate a CS valid signal to obtain bus access rights.

[0052] The established waiting mechanism ensures that devices in a shared bus system can use bus resources in an orderly manner. If multiple devices simultaneously request bus access, priority is determined by comparing their ID numbers, avoiding bus conflicts and data transmission errors. Devices with lower ID numbers have higher priority and receive priority bus access, which helps ensure that critical or urgent tasks are processed promptly. For example, the accompanying figure in the specification shows a timing diagram of a chip with ID 3 requesting and occupying the bus. When the REQ signal is generated, the counter begins counting. If the CS signal remains high for 3 + 1 = 4 CLK cycles, a low CS valid signal is generated.

[0053] In step S3, after the chip obtains bus access, bus communication is performed based on the configured single-wire or dual-wire mode protocol. While generating the address signal, it is necessary to output a base address control signal ADDRSEL based on the base address control register. The base address control register is a register that stores a specific address value (i.e., a base address). This base address is a reference point used to determine the starting position of the address range. The system generates the ADDRSEL signal based on the value in the base address control register.

[0054] Furthermore, a write operation command is first sent, and the ID number of the device to be received is written to address O to enable the device that needs to receive information. If the data written is all 0, it means that all devices need to receive the write data request sent by the master device. That is, the subsequent write operation to all devices can be completed; if the corresponding ID is written, such as ID = 1, the device with ID number 1 receives the access request sent by the host, and the other devices do not process the request. Among them, the timing information of the read operation after writing address A1 to the device with ID number 1 is as shown in the attached manual. Figure 9 shown.

[0055] In addition, the valid bits of the write data can be determined according to the DE control signal. If 8-bit data is written, the 1 bit corresponding to DE needs to be generated as 1 according to actual needs; if it is 16-bit data, 2 valid bits need to be generated; if it is 32-bit data, 4 bits need to be effective at the same time.

[0056] If the slave device does not process the request, it will pull down the bus valid state READY signal. The host needs to determine whether the request has been completed by judging the bus valid state READY signal. After completing the data transmission, it abandons the bus application and returns to slave mode.

[0057] In slave mode, it is also necessary to configure the slave enable and the slave working mode as single-line control mode or dual-line control mode; at the same time, configure the offset address corresponding to addrsel (there are multiple registers, and in one embodiment there are 15 registers, where basesel = 0 is the address information of the external interface module); the enabled slave device receives the command signal sent by the host, and when an operation with a write address of 0 is received, the written data is judged. If the write data is 0, it is necessary to receive subsequent write operation requests; if the written data is not 0, it is necessary to determine whether it matches the ID number of this device. If it matches, subsequent data access requests are processed.

[0058] Among them, the access address needs to be processed, and the offset address of the corresponding configuration register information is selected according to the information of ADDRSEL. If the address accessed by the host is ADDRSEL=0, the offset address of the external interface is accessed at this time. If it is other address information, it is necessary to determine which part of the address is accessed based on the addrsel address configured by the CPU. For example, when the host accesses ADDRSEL[3:0]=1 and A=0x55, the base_addr1 register configured by the CPU is 0xff00, then the address accessed at this time is 0xff55 address, that is, the base_addr1 address selected by ADDRSEL needs to be added to A to obtain the real address inside the chip. If it is a write operation, the write data needs to be written to the corresponding operation, and the read operation reads the register of the corresponding address and places it on the bus.

[0059] If the read data cannot be returned in time or the bus inside the chip system is busy when writing data, you need to

[0060] The bus valid state READY signal is pulled low until valid data of the host read address is returned or the host write operation is completed, and then the bus valid state READY signal is released. When the host completes the data transmission, that is, when CS becomes high, the slave device enables the receive enable and waits for the next data transmission.

[0061] It can be seen that the communication method of an on-chip external interface provided by the present application provides the function of switching the chip master / slave mode, which enables the chip to access the outside as a host or allows the chip to be accessed by an external host as a slave, thereby being able to flexibly respond to different communication scenarios; and in the process of switching from slave mode to host mode, a waiting mechanism based on the chip ID number is adopted to obtain the right to use the bus, thereby avoiding bus conflicts and data transmission errors.

[0062] Based on the same concept of the present invention, the specification Figure 10 As shown, an embodiment of the present application provides a structure of an electronic device 1000, which includes: at least one processor 1001, at least one network interface 1004 or other user interface 1003, a memory 1005, and at least one communication bus 1002. The communication bus 1002 is used to achieve connection and communication between these components. The electronic device 1000 optionally includes a user interface 1003, including a display (for example, a touch screen, LCD, CRT, holographic imaging (Holographic) or projection (Projector), etc.), a keyboard or a pointing device (for example, a mouse, trackball (trackball), touchpad or touch screen, etc.).

[0063] The memory 1005 may include a read-only memory and a random access memory, and provides instructions and data to the processor 1001. A portion of the memory 1005 may also include a non-volatile random access memory (NVRAM).

[0064] In some embodiments, the memory 1005 stores the following elements, executable modules, or data structures, or a subset or extended set thereof:

[0065] Operating system 10051, including various system programs, used to implement various basic services and process hardware-based tasks;

[0066] The application module 10052 includes various application programs, such as a launcher, a media player, a browser, etc., which are used to implement various application services.

[0067] In an embodiment of the present application, by calling the program or instructions stored in the memory 1005, the processor 1001 is used to execute steps in an intelligent question-answering method based on a large model, and can switch the master / slave mode of the chip, allowing the chip to access the outside as a host or allowing the chip to be accessed by an external host as a slave, thereby flexibly responding to different communication scenarios.

[0068] The present application also provides a computer-readable storage medium having a computer program stored thereon, which executes the steps in the intelligent question-answering method of the large model when the computer program is executed by a processor.

[0069] Specifically, the storage medium can be a general storage medium, such as a mobile disk, a hard disk, etc. When the computer program on the storage medium is run, it can execute the above-mentioned intelligent question-answering method based on the large model.

[0070] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interface, the indirect coupling or communication connection of the device or unit can be electrical, mechanical or other forms.

[0071] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0072] In addition, each functional unit in the embodiments provided in the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0073] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0074] Finally, it should be noted that the above embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The scope of protection of the present application is not limited thereto. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the above embodiments within the technical scope disclosed in the present application, or replace some of the technical features therein with equivalents. However, these modifications, changes, or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application. They should all be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A communication method for an on-chip external interface, characterized in that: The method comprises the following steps: After receiving an external access request from a CPU or other master device, detecting whether the external bus is idle; wherein, when the external bus is detected to be in an idle state, generating a bus request signal; The CPU inside the chip configures the ID register of the external interface and assigns an ID number to each chip. The larger the ID number, the lower the priority of obtaining the right to use the external bus. Within ID+1 clocks after generating the bus request signal, it detects whether there is a valid chip select signal on the external bus. If no valid chip select signal is detected on the external bus within ID+1 clocks, a valid chip select signal is generated to obtain the right to use the external bus and access the outside as the host. If a valid chip select signal is detected on the external bus within ID+1 clocks, and the chip select signal is invalid, it re-detects whether there is a valid chip select signal on the external bus within ID+1 clocks. The bus communication is performed according to the configured single-line control mode or two-line control mode, and after completing the data transmission, the external bus usage right is given up to be accessed by the external host as a slave.

2. The on-chip external interface communication method according to claim 1, characterized in that: The bus communication is performed according to the configured single-line control mode or dual-line control mode, comprising the following steps: While generating the address signal, the base address control signal is output according to the base address control register for address offset; Send a write operation command once, and write the ID number of the chip to be received at address zero to enable the chip that needs to receive information; if the data written to address zero is all zero, it means that all chips need to receive the write data request sent by the chip; The valid bit of the write data is determined according to the defined write data valid flag.

3. The communication method of the on-chip external interface according to claim 2, characterized in that: in, A shared bus is used to connect multiple chips to the same bus.

4. The on-chip external interface communication method according to claim 3, characterized in that: The method of giving up the right to use the external bus so as to be accessed by the external host as a slave comprises the following steps: Receive command signals sent by the host; When receiving an operation with a write address of zero, determine the data to be written; if the written data is zero, receive subsequent write operation requests; if the written data is not zero, determine whether it matches the chip ID number, and if so, process subsequent data access requests.

5. The on-chip external interface communication method according to claim 4, characterized in that: in, If the command signal received from the host is a write operation command, the write data is written to the corresponding operation; if the command signal received from the host is a read operation command, the register of the corresponding address is read out and placed on the bus.

6. The on-chip external interface communication method according to claim 5, characterized in that: in, When executing the operation of writing write data to the corresponding address, or executing the operation of reading the register of the corresponding address and placing it on the bus, if the read data cannot be returned in time or the bus is busy when writing data, the bus is maintained in a valid state until the valid data of the host read address is returned or the host write operation is completed, and then the bus valid state is released.

7. An electronic device, characterized in that: include: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate via the bus, and when the machine-readable instructions are executed by the processor, the steps of the communication method of the on-chip external interface as described in any one of claims 1 to 6 are performed.

8. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the on-chip external interface communication method according to any one of claims 1 to 6 are executed.

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