DRAM testing methods, electronic devices and storage media

Abstract

This invention discloses a DRAM testing method, comprising the following steps: acquiring timing parameters of a DRAM, wherein the DRAM has two RANKs, each RANK having a corresponding chip select pin and a clock enable pin; initializing the DRAM according to the timing parameters; testing the first RANK of the DRAM; after the test is completed, the DRAM controller enters a self-refresh mode; synchronizing the enable clock of the second RANK, activating the initial verification parameters of the second RANK, and switching the chip select clock from the first RANK to the second RANK to test the second RANK; after the second RANK test is completed, the DRAM controller exits the self-refresh mode. According to the DRAM testing method of this invention, switching tests between two RANKs can be performed, and the same address can represent the actual row and column addresses of two parts of the DRAM, thereby achieving a significant increase in the testable DRAM capacity.

Description

Technical Field

[0001] This invention relates to the field of DRAM technology, and in particular to a DRAM testing method, electronic device, and storage medium. Background Technology

[0002] With the development of integrated circuits, their density and speed are increasing, but at the same time, their failure rate is also rising. For DRAM (Dynamic Random Access Memory), without ECC (Error Checking and Correcting), even a single bit of data error cannot be tolerated; otherwise, the product used in devices such as mobile phones and tablets will cause system crashes, application restarts, and other adverse phenomena.

[0003] To improve the user experience and stability of DRAM, necessary functional tests are required. Currently, most smart platforms cannot directly use boot and system tests for DRAM testing, necessitating verification and testing during the DRAM initialization phase. However, boot firmware based on the commonly used 32-bit mode has significant limitations for testing large-capacity memory. For example, if the memory exceeds 4GB, the boot firmware cannot fully cover the testing (a 32-bit boot system can only support a maximum of 4GB of addressing). Summary of the Invention

[0004] This invention aims to address at least one of the technical problems existing in the prior art. To this end, this invention proposes a DRAM testing method, electronic device, and storage medium that can improve the testable DRAM capacity.

[0005] On one hand, the DRAM testing method according to an embodiment of the present invention includes the following steps: obtaining timing parameters of the DRAM, wherein the DRAM has two RANKs, each RANK having a corresponding chip select pin and a clock enable pin; initializing the DRAM according to the timing parameters; testing the first RANK of the DRAM; after the test is completed, the DRAM controller enters a self-refresh mode; synchronizing the enable clock of the second RANK, activating the initial verification parameters of the second RANK, and switching the chip select clock from the first RANK to the second RANK to test the second RANK; after the second RANK test is completed, the DRAM controller exits the self-refresh mode.

[0006] The DRAM testing method according to embodiments of the present invention has at least the following beneficial effects: it enables switching tests between two RANKs, and the same address can represent the actual row and column addresses of the two parts of the DRAM, thereby multiplying the testable DRAM capacity; at the same time, according to the DRAM testing method of this application, the addressing capability can be improved in 32-bit initialization mode, and full-coverage functional testing can be performed before entering the system and before the DRAM is used, maximizing the improvement of testing accuracy and precision.

[0007] According to some embodiments of the present invention, the initialization of the DRAM according to the timing parameters specifically includes: configuring the registers of the external memory interface of the test platform according to the timing parameters to initialize the DRAM.

[0008] According to some embodiments of the present invention, the DRAM controller enters a self-refresh mode by: configuring the DRAM register of the DRAM controller to enable the DRAM controller to enter a self-refresh mode by pulling down the clock enable pin of the second RANK.

[0009] According to some embodiments of the present invention, synchronizing the enable clock of the second RANK specifically includes: configuring the CKE register of the DRAM controller to synchronize the enable clock of the second RANK.

[0010] According to some embodiments of the present invention, activating the initial verification parameters of the second RANK specifically includes: configuring the TXrank register of the DRAM controller to activate the initial verification parameters of the second RANK.

[0011] According to some embodiments of the present invention, switching the chip select clock from the first RANK to the second RANK specifically includes: configuring the CS SWAP register of the test platform to switch the chip select clock from the first RANK to the second RANK.

[0012] On the other hand, an electronic device according to an embodiment of the present invention includes a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the DRAM testing method described above.

[0013] On the other hand, according to an embodiment of the present invention, a computer-readable storage medium stores a program that, when executed by a processor, implements the DRAM testing method described above.

[0014] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0015] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0016] Figure 1 This is a flowchart illustrating the steps of a DRAM testing method according to an embodiment of the present invention. Detailed Implementation

[0017] This section will describe in detail specific embodiments of the present invention. Preferred embodiments of the present invention are shown in the accompanying drawings. The purpose of the drawings is to supplement the textual description with graphics, so that people can intuitively and vividly understand each technical feature and overall technical solution of the present invention, but they should not be construed as limiting the scope of protection of the present invention.

[0018] In the description of this invention, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0019] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0020] RANK: A memory module has many memory chips attached to it. The number of sides with memory chips attached is called the RANK. If only one side has memory chips, it's called a single RANK; if both sides have memory chips, it's called a dual RANK. The DRAM testing method in this invention is mainly applicable to DRAMs with two RANKs.

[0021] like Figure 1 As shown, the DRAM testing method according to an embodiment of the present invention includes the following steps:

[0022] Step S100: Obtain the timing parameters of the DRAM, which has two RANKs, each with a corresponding chip select pin CS and clock enable pin CKE;

[0023] Step S200: Initialize the DRAM according to its timing parameters;

[0024] Step S300: Test the first RANK of the DRAM;

[0025] Step S400: After the first RANK test is completed, the DRAM controller enters self-refresh mode;

[0026] Step S500: Synchronize the enable clock of the second RANK, activate the initial verification parameters of the second RANK, and switch the chip select clock from the first RANK to the second RANK to test the second RANK;

[0027] Step S600: After the second RANK test is completed, the DRAM controller exits the self-refresh mode.

[0028] Specifically, before testing the DRAM, the material specification sheet (MAS) should be consulted to understand its timing parameters. These parameters characterize the DRAM's RANK count, memory capacity, and the row and column distribution of memory chips. After obtaining the DRAM's timing parameters, the external memory interface (EMI) registers of the test platform are configured. At this point, the test platform's internal program automatically identifies the DRAM's timing parameters and begins initializing the DRAM. It should be noted that in this application example, the test platform refers to the MTK (MediaTek) platform; it is understood that the method described in this application can also be applied to other similar platforms.

[0029] After the DRAM initialization is complete, the test platform will begin testing the first RANK of the DRAM. It should be noted that when testing the first RANK, the normal testing procedure can be followed. This is the default setting of the test platform and will not be elaborated upon here.

[0030] After the first RANK test is completed, the second RANK test begins. At this point, the DRAM controller's DRAM registers need to be configured to put the DRAM controller into self-refresh mode. In this mode, the DRAM clock enable pin CKE can be pulled low to prevent errors caused by other commands. Next, the DRAM controller's CKE register is configured to synchronize the enable clock of the second RANK. Since each RANK uses a different enable clock, synchronization of the two RANK's enable clocks is necessary. Then, the DRAM controller's TXrank register is configured to activate the initial checksum TX parameter of the second RANK, allowing it to accept read and write commands. Next, the CS SWAP register is configured to switch the chip select clock from the first RANK to the second RANK, enabling the test platform to begin testing the second RANK. After the second RANK test is completed, the DRAM controller exits self-refresh mode. At this point, the entire DRAM can be read and written.

[0031] According to the DRAM testing method of this invention, switching tests between two RANKs can be performed. The same address can represent the actual row and column addresses of the two DRAM parts, thereby significantly increasing the testable DRAM capacity. For example, assuming the DRAM capacity is 4GB, in the case of a single RANK, due to the limitation of the 32-bit mode of the test platform, addresses larger than 3GB cannot be tested (32-bit mode can only access a maximum of 4GB of space, and due to register address occupation, the first 1GB of space is occupied, so the maximum test capacity is 3GB). However, with two RANKs of 4GB DRAM, each with a capacity of 2GB, by grouping and switching RANKs simultaneously, only 2GB of addresses are needed to represent 4GB of addresses, thus allowing for successful and complete testing of all memory addresses. In other words, according to the DRAM testing method of this application, addressing capability can be improved in 32-bit initialization mode, and full-coverage functional testing can be performed before entering the system and before the DRAM is used, maximizing the improvement of testing accuracy and precision.

[0032] On the other hand, the present invention also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the above-described DRAM testing method.

[0033] On the other hand, the present invention also provides a computer-readable storage medium storing a program that, when executed by a processor, implements the above-described scene processing method.

[0034] Although specific embodiments are described herein, those skilled in the art will recognize that many other modifications or alternative embodiments are also within the scope of this disclosure. For example, any of the functions and / or processing capabilities described in connection with a particular device or component can be performed by any other device or component. Furthermore, while various exemplary embodiments and architectures have been described according to embodiments of this disclosure, those skilled in the art will recognize that many other modifications to the exemplary embodiments and architectures described herein are also within the scope of this disclosure.

[0035] The foregoing description, with reference to block diagrams and flowcharts of systems, methods, systems, and / or computer program products according to exemplary embodiments, has described certain aspects of this disclosure. It should be understood that one or more blocks in the block diagrams and flowcharts, as well as combinations of blocks in the block diagrams and flowcharts, can be implemented by executing computer-executable program instructions, respectively. Similarly, according to some embodiments, some blocks in the block diagrams and flowcharts may not need to be executed in the order shown, or may not all need to be executed. Furthermore, additional components and / or operations beyond those shown in the blocks in the block diagrams and flowcharts may exist in some embodiments.

[0036] Therefore, blocks in block diagrams and flowcharts support combinations of means for performing a specified function, combinations of elements or steps for performing a specified function, and program instruction means for performing a specified function. It should also be understood that each block in a block diagram and flowchart, and combinations of blocks in block diagrams and flowcharts, can be implemented by a dedicated hardware computer system or a combination of dedicated hardware and computer instructions that performs a specific function, element, or step.

[0037] The program modules, applications, etc., described herein may include one or more software components, including, for example, software objects, methods, data structures, etc. Each such software component may include computer-executable instructions that, in response to execution, cause at least a portion of the functionality described herein (e.g., one or more operations of the exemplary methods described herein) to be performed.

[0038] Software components can be coded using any of a variety of programming languages. An exemplary programming language could be a low-level programming language, such as assembly language associated with a specific hardware architecture and / or operating system platform. Software components including assembly language instructions may need to be converted into executable machine code by an assembler before being executed by the hardware architecture and / or platform. Another exemplary programming language could be a higher-level programming language that is portable across multiple architectures. Software components including higher-level programming languages ​​may need to be converted into an intermediate representation by an interpreter or compiler before execution. Other examples of programming languages ​​include, but are not limited to, macro languages, shell or command languages, job control languages, scripting languages, database query or search languages, or report writing languages. In one or more exemplary embodiments, a software component containing instructions from one of the above-described programming language examples can be executed directly by the operating system or other software components without first being converted into another form.

[0039] Software components can be stored as files or other data storage structures. Software components of similar type or related function can be stored together in a specific directory, folder, or library. Software components can be static (e.g., pre-defined or fixed) or dynamic (e.g., created or modified at runtime).

[0040] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A DRAM testing method, characterized by, The method comprises the following steps: obtaining timing parameters of a DRAM, the DRAM having two RANKs, each RANK having a corresponding chip select pin and clock enable pin; initializing the DRAM according to the timing parameters; testing a first RANK of the DRAM; after the testing is completed, configuring a DRAM register of a DRAM controller to make the DRAM controller enter a self-refresh mode to pull down a clock enable pin of a second RANK; configuring a CKE register of the DRAM controller to synchronize the enable clock of the second RANK, activate initial check parameters of the second RANK, and switch the chip select pin from the first RANK to the second RANK to test the second RANK; after the testing of the second RANK is completed, the DRAM controller exits the self-refresh mode.

2. The DRAM test method of claim 1, wherein, The initializing the DRAM according to the timing parameters specifically comprises: configuring a register of an external memory interface of a test platform according to the timing parameters to initialize the DRAM.

3. The DRAM test method of claim 1, wherein, The activating the initial check parameters of the second RANK specifically comprises: configuring a TXrank register of the DRAM controller to activate the initial check parameters of the second RANK.

4. The DRAM test method of claim 1, wherein, The switching the chip select clock from the first RANK to the second RANK specifically comprises: configuring a CS SWAP register of the test platform to switch the chip select clock from the first RANK to the second RANK. 5.An electronic device comprising a memory and a processor, the memory storing a computer program, wherein, The processor executes the computer program to implement the DRAM test method in any one of claims 1 to 4.

6. A computer-readable storage medium storing a program, the program comprising instructions that, when executed by a computer, cause the computer to perform operations comprising: The program is executed by the processor to implement the DRAM test method in any one of claims 1 to 4.

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