A method and circuit for expanding the local bus interface based on FPGA
By generating a read enable signal using an FPGA, the problem of the lack of RD signals in the local bus interface of domestic chips was solved, enabling efficient data acquisition and transmission, and reducing system burden and cost.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ZHUHAI FEISEN POWER TECH CO LTD
- Filing Date
- 2026-05-08
- Publication Date
- 2026-06-02
AI Technical Summary
Some domestically produced chips lack an independent read enable (RD) signal for their Local bus interface, resulting in poor data real-time performance and increased system load, making it difficult to meet the requirements for high-performance data transmission.
Through FPGA logic translation and processing, a read enable signal is generated and data is transmitted in real time, realizing the expansion of the local bus interface and ensuring the real-time performance of data acquisition and transmission speed.
It improves the efficiency and real-time response capability of data acquisition and processing, reduces hardware costs, and enhances the convenience of system maintenance and upgrades.
Smart Images
Figure CN122132337A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of bus interface expansion technology, and specifically to a method and circuit for expanding the local bus interface based on FPGA. Background Technology
[0002] The local bus is a high-bandwidth, low-latency bus interface that connects the CPU core to peripherals. Compared to interfaces such as SPI and I2C, the local bus interface can provide higher data transfer speeds and greater bandwidth, making it suitable for applications requiring higher performance and more complex data transfer. A local bus interface typically consists of multiple parallel data lines, address lines, control lines, and clock lines. The data lines are used to transfer data between the CPU and peripherals, the address lines are used to specify the address of the peripheral, the control lines are used to send read, write, and other control signals, and the clock line is used to synchronize data transfer.
[0003] Currently, some well-developed local buses, such as TI's GPMC bus and the GPCM bus of the domestic power voltaic chip H2, have relatively complete signal lines and data buses, which can directly connect to ADC acquisition chips such as AD7616. However, some chips, such as the domestic T536, while supporting signal lines for chip select (CS), write enable (WR), address latch enable (ALE), and data bus, lack a dedicated read enable (RD) signal line. The AD7616's parallel interface requires complete CS, RD, and WR signals to function properly. Therefore, it is necessary to use an external FPGA (programmable logic device) to generate the RD signal from the T536 chip's existing control signals. The current solution is to use the T536's CS, WR, and address lines; the FPGA generates a low-level active RD pulse when a read operation is detected. The FPGA first acquires batch data and then sends it centrally to the T536 chip's CPU. However, this results in poor data real-time performance, and data transmission requires specific protocols, adding extra burden to the system.
[0004] Therefore, in order to solve the problem of insufficient signal lines in the Local bus of some domestically produced chips and accelerate the realization of domestic chip substitution, it is urgent to design a Local bus interface expansion method and circuit that can ensure real-time data acquisition and data transmission speed. Summary of the Invention
[0005] To address the common problems in existing technologies, the present invention aims to provide a method and circuit for expanding the Local bus interface based on FPGA. This invention uses the logic translation processing of FPGA to acquire data in real time and output it to the CPU, thereby expanding the Local bus interface and ensuring the real-time performance of data acquisition and the speed of data transmission.
[0006] The present invention achieves the above objectives through the following technical solutions: A method for expanding the local bus interface based on FPGA, wherein the CPU of an embedded system is connected to the FPGA via the local bus, comprising: S1: When the system is powered on, the CPU starts up and reads the FPGA firmware file stored internally, and transmits the FPGA firmware file to the FPGA through the port to simulate the FPGA serial configuration timing according to the mode configuration protocol.
[0007] S2: The FPGA automatically loads the FPGA firmware file and, after loading, continuously listens for bus operation signals initiated by the CPU through the Local bus.
[0008] The bus operation signals include at least a chip select signal and a write enable signal.
[0009] S3: The FPGA identifies the current operation request of the CPU based on the combined logic state of the chip select signal and the write enable signal.
[0010] S4: If the current operation request is a read operation request, the FPGA generates a read enable signal according to the preset timing logic.
[0011] S5: During the period when the read enable signal is valid, the FPGA acquires the collected data from the peripheral module through the analog-to-digital converter chip, and transmits the collected data to the CPU in real time through the Local bus.
[0012] According to the FPGA-based Local bus interface extension method provided by the present invention, the simulation step of the FPGA serial configuration timing in step S1 includes: S11: The CPU disables global interrupts before reading the internally stored FPGA firmware file.
[0013] S12: The CPU, according to the serial slave mode configuration protocol, simulates the PROGRAM_B pulse, clock CCLK and data DIN signals through several input and output ports respectively, and writes the FPGA firmware file bit by bit into the configuration port of the FPGA.
[0014] According to the FPGA-based Local bus interface extension method provided by the present invention, the logic update steps of the FPGA include: S13: Transmit the new FPGA firmware file to the CPU via the network interface or JTAG interface, and replace the FPGA firmware file in the CPU's file system.
[0015] S14: The system restarts and returns to steps S11-S12 to complete the logic update of the FPGA.
[0016] According to the FPGA-based Local bus interface expansion method provided by the present invention, the identification step of the CPU's current operation request in step S3 includes: S31: The FPGA synchronously samples the chip select signal and the write enable signal.
[0017] S32: The FPGA performs real-time decoding on the sampled chip select signal and write enable signal, and obtains two sets of signal states.
[0018] S33: Determine the current operation request of the CPU based on the states of the two sets of signals.
[0019] Specifically, when the chip select signal is active and the write enable signal is active, the current operation request of the CPU is determined to be a write operation request.
[0020] The duration for which the chip select signal is at an active level and the write enable signal is at an inactive level is determined to be the current operation request of the CPU as a read operation request.
[0021] When the chip select signal is at an invalid level, it is determined that the CPU currently has no operation request and the Local bus is idle.
[0022] According to the FPGA-based Local bus interface expansion method provided by the present invention, the step of generating the read enable signal in step S4 includes: S41: After the FPGA recognizes the current operation request as a read operation request, it generates a low-level read enable signal. The analog-to-digital converter chip samples data from the peripheral module according to the read enable signal.
[0023] S42: The FPGA determines whether the data conversion is complete by monitoring the status signal of the analog-to-digital converter chip or waiting for a preset conversion time.
[0024] S43: If the conversion is complete, the FPGA generates a low-level active read strobe signal and outputs it to the analog-to-digital converter chip to select the data output channel of the analog-to-digital converter chip.
[0025] According to the FPGA-based Local bus interface expansion method provided by the present invention, the FPGA generates a pair of low-level active parallel bus control signals at the rising edge of each system clock according to the setup time, hold time and pulse width of the chip select signal, read operation signal and write operation signal required by the analog-to-digital converter chip. The parallel bus control signals include register operation signals and the read enable signal.
[0026] According to the FPGA-based Local bus interface expansion method provided by the present invention, step S5 further includes: the FPGA latches the sampled data of the analog-to-digital converter chip into its internal buffer, and initiates a direct memory access transfer request to the CPU, and writes the batch of sampled data into the memory of the CPU through direct memory access.
[0027] A local bus interface expansion circuit based on FPGA, applying the aforementioned FPGA-based local bus interface expansion method, includes a CPU, an FPGA, and an analog-to-digital converter (ADC). The CPU is configured with a local bus interface and several input / output ports, used to simulate serial configuration timing through the input / output ports, load the FPGA firmware file onto the FPGA, and initiate read or write operation requests through the local bus. The FPGA is used to monitor bus operation signals on the local bus. The FPGA is used to generate peripheral read operation signals based on the bus operation signals and output them to the ADC. The ADC is used to collect data from peripheral modules and transmit it to the CPU in real time through the local bus.
[0028] The FPGA-based Local bus interface expansion circuit provided by the present invention further includes: The JTAG debugging interface is connected to the FPGA via TMS signal line, TCK signal line, TDI signal line and TDO signal line, respectively, and is used for FPGA logic debugging during the development phase.
[0029] According to the FPGA-based Local bus interface expansion circuit provided by the present invention, the FPGA integrates a configuration memory, and the CPU connects the analog clock signal line, analog data input line, analog chip select line and analog reset line to the corresponding configuration pins of the FPGA through multiple input and output ports to form an online programming link. Therefore, compared with the prior art, the present invention has the following beneficial effects: 1. This invention uses FPGA as a translation layer for local bus interface expansion, which expands the limited CPU bus resources into multiple external device control signals, thereby expanding the application scope of domestically produced chips in industrial control and data acquisition.
[0030] 2. The operation of the external expansion chip in this invention is still carried out by a CPU with local bus function. The FPGA performs the reading and writing of the external expansion chip according to the timing sequence, which eliminates the complex handshake and interrupt coordination mechanism between the CPU and FPGA in the traditional solution, avoids the overhead of protocol encapsulation and parsing, and thus greatly improves the efficiency of data acquisition and processing and the real-time response capability.
[0031] 3. The FPGA's runtime configuration file is loaded by the CPU through a general-purpose I / O-simulated online serial interface when the system powers on, eliminating the need for an external dedicated non-volatile memory chip and directly reducing hardware BOM costs. Furthermore, it implements software definition of FPGA logic functions. Users only need to push the updated firmware file to the CPU via the network, and the FPGA logic will be automatically dynamically reconfigured upon restart, avoiding the tedious physical programming in the field and greatly improving the convenience of system maintenance and upgrades.
[0032] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. Attached Figure Description
[0033] Figure 1 This is a flowchart of a method embodiment of an FPGA-based Local bus interface expansion method of the present invention.
[0034] Figure 2 This is a circuit schematic diagram of 16 extended chip select signals in an embodiment of an FPGA-based Local bus interface expansion circuit of the present invention.
[0035] Figure 3 This is a circuit schematic diagram of a 16-bit data bus in an embodiment of a FPGA-based Local bus interface expansion circuit of the present invention.
[0036] Figure 4 This is a schematic diagram of the power supply circuit of the FPGA in an embodiment of the FPGA-based Local bus interface expansion circuit of the present invention.
[0037] Figure 5 This is a schematic diagram of the JTAG debugging circuit in an embodiment of the FPGA-based Local bus interface expansion circuit of the present invention.
[0038] Figure 6This is a schematic diagram of the power conversion circuit of the FPGA in an embodiment of the FPGA-based Local bus interface expansion circuit of the present invention.
[0039] Figure 7 This is a schematic diagram of the clock circuit of the FPGA in an embodiment of the FPGA-based Local bus interface expansion circuit of the present invention.
[0040] Figure 8 This is a schematic diagram of the FPGA status indication and reset circuit in an embodiment of the FPGA-based Local bus interface expansion circuit of the present invention. Detailed Implementation
[0041] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.
[0042] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0043] See Figure 1 This invention discloses a method for expanding the Local bus interface based on FPGA, wherein the CPU of an embedded system is connected to the FPGA via the Local bus, comprising: S1: When the system is powered on, the CPU starts up and reads the FPGA firmware file stored internally, and transmits the FPGA firmware file to the FPGA through the port to simulate the FPGA serial configuration timing according to the mode configuration protocol.
[0044] S2: The FPGA automatically loads the FPGA firmware file and, after loading, continuously listens for bus operation signals initiated by the CPU through the Local bus.
[0045] The bus operation signals include at least a chip select signal and a write enable signal.
[0046] S3: The FPGA identifies the current operation request of the CPU based on the combined logic state of the chip select signal and the write enable signal.
[0047] S4: If the current operation request is a read operation request, the FPGA generates a read enable signal according to the preset timing logic.
[0048] S5: During the period when the read enable signal is valid, the FPGA acquires the collected data from the peripheral module through the analog-to-digital converter chip, and transmits the collected data to the CPU in real time through the Local bus.
[0049] In this embodiment, the simulation step of the FPGA serial configuration timing in step S1 includes: S11: The CPU disables global interrupts before reading the internally stored FPGA firmware file.
[0050] S12: The CPU, according to the serial slave mode configuration protocol, simulates the PROGRAM_B pulse, clock CCLK and data DIN signals through several input and output ports respectively, and writes the FPGA firmware file bit by bit into the configuration port of the FPGA.
[0051] In this embodiment, the logic update step of the FPGA includes: S13: Transmit the new FPGA firmware file to the CPU via the network interface or JTAG interface, and replace the FPGA firmware file in the CPU's file system.
[0052] S14: The system restarts and returns to steps S11-S12 to complete the logic update of the FPGA.
[0053] In this embodiment, the step of identifying the CPU's current operation request in step S3 includes: S31: The FPGA synchronously samples the chip select signal and the write enable signal.
[0054] S32: The FPGA performs real-time decoding on the sampled chip select signal and write enable signal, and obtains two sets of signal states.
[0055] S33: Determine the current operation request of the CPU based on the states of the two sets of signals.
[0056] Specifically, when the chip select signal is active and the write enable signal is active, the current operation request of the CPU is determined to be a write operation request.
[0057] The duration for which the chip select signal is at an active level and the write enable signal is at an inactive level is determined to be the current operation request of the CPU as a read operation request.
[0058] When the chip select signal is at an invalid level, it is determined that the CPU currently has no operation request and the Local bus is idle.
[0059] In this embodiment, the step of generating the read enable signal in step S4 includes: S41: After the FPGA recognizes the current operation request as a read operation request, it generates a low-level read enable signal. The analog-to-digital converter chip samples data from the peripheral module according to the read enable signal.
[0060] S42: The FPGA determines whether the data conversion is complete by monitoring the status signal of the analog-to-digital converter chip or waiting for a preset conversion time.
[0061] S43: If the conversion is complete, the FPGA generates a low-level active read strobe signal and outputs it to the analog-to-digital converter chip to select the data output channel of the analog-to-digital converter chip.
[0062] In this embodiment, the FPGA generates a pair of low-level active parallel bus control signals at the rising edge of each system clock according to the setup time, hold time, and pulse width of the chip select signal, read operation signal, and write operation signal required by the analog-to-digital converter chip. The parallel bus control signals include register operation signals and the read enable signal.
[0063] Specifically, in this embodiment, the FPGA translates the bus operation signals into read enable signals. The translation logic code is as follows: always@(posedge pll_lbc_clk) begin adc_wr_n_tmp<= ~(ale_in&wr_in); end assign adc_rd_n_tmp = ~(ale_in&(~wr_in)); always@(posedge pll_lbc_clk) begin adc_wr_n <= adc_wr_n_tmp; adc_rd_n <= adc_rd_n_tmp; end Specifically, on the rising edge of the Local bus clock pll_lbc_clk, a logical AND operation is performed on the chip select signal ale_in and the write enable signal wr_in, followed by an inversion. When the CPU initiates a write operation request, both the chip select signal ale_in and the write enable signal wr_in are at a high level simultaneously, resulting in a low level, indicating that the current cycle is a write register operation. The FPGA then generates a low-active write pulse to directly drive the write enable pin of the external analog-to-digital converter chip.
[0064] Specifically, when the chip select signal ale_in is high and the write enable signal wr_in is low, a low level is output, indicating that the CPU is initiating a read data operation. Since the CPU does not support the RD signal, the FPGA uses the reverse logic of the write enable signal wr_in to synthesize a read enable signal that meets the timing requirements of the analog-to-digital converter chip.
[0065] To ensure that the read enable signal meets the setup / hold time requirements of the analog-to-digital converter (ADC) chip and to eliminate potential glitches from combinational logic, the FPGA performs a first-level registering process on the generated temporary signals. This aligns the edges of the final ADC chip select signal, read operation signal, and write operation signal with the pll_lbc_clk clock, facilitating timing convergence. Furthermore, glitches during combinational logic transitions are filtered out to prevent accidental triggering of the ADC chip. A fixed two-stage pipeline delay is established by delaying the write operation signal by two clock cycles and the read operation signal by one clock cycle, facilitating system-level timing budgeting.
[0066] In this embodiment, step S5 further includes: the FPGA latches the sampling data of the analog-to-digital converter chip into its internal buffer, and initiates a direct memory access transfer request to the CPU, writing the batch of sampling data into the CPU's memory through direct memory access.
[0067] A local bus interface expansion circuit based on FPGA, applying the aforementioned FPGA-based local bus interface expansion method, includes a CPU, an FPGA, and an analog-to-digital converter (ADC). The CPU is configured with a local bus interface and several input / output ports, used to simulate serial configuration timing through the input / output ports, load the FPGA firmware file onto the FPGA, and initiate read or write operation requests through the local bus. The FPGA is used to monitor bus operation signals on the local bus. The FPGA is used to generate peripheral read operation signals based on the bus operation signals and output them to the ADC. The ADC is used to collect data from peripheral modules and transmit it to the CPU in real time through the local bus.
[0068] See Figure 2 Specifically, in this embodiment, the analog-to-digital converter chip includes a telemetry acquisition chip and a remote signaling acquisition chip. The telemetry acquisition chip uses an AD7616 ADC, and the remote signaling acquisition chip uses a 74LVCH162245. The FPGA is connected to the 16-bit data bus and read / write signal lines of the telemetry acquisition chip and the remote signaling acquisition chip through the memory bank (BANK) U297A. It expands 16 channels of extended chip select signals through U297B, supporting a total of 16 external analog-to-digital converter chips.
[0069] See Figure 3 Specifically, in this embodiment, U297C and U297D are signal connection chips connected to the local bus interface of the CPU, including a 16-bit data bus of LBUS-LD0 to LBUS-LD15. Multiple input / output ports of the CPU, including GPIO_PG2, GPIO_PG3, GPIO_PG4, GPIO_PG5, and GPIO_PG12, are connected via the 16-bit data bus for online FPGA firmware file download.
[0070] See Figure 4 Specifically, the power supply circuit of the FPGA in this embodiment includes a decoupling capacitor network, which includes multiple capacitors connected in parallel. A large 10uF capacitor provides energy storage to meet the transient current requirements of the FPGA core and input / output ports during high-speed operation. A small 100nF capacitor filters out high-frequency noise to ensure power supply stability.
[0071] In this embodiment, the FPGA integrates a configuration memory, and the CPU connects the analog clock signal line, analog data input line, analog chip select line, and analog reset line to the corresponding configuration pins of the FPGA through multiple input / output ports to form an in-circuit programming link.
[0072] See Figure 5 Specifically, this embodiment also includes a JTAG debugging interface, which is connected to the FPGA via TMS signal line, TCK signal line, TDI signal line and TDO signal line, respectively, for FPGA logic debugging during the development phase.
[0073] See Figure 6Specifically, this embodiment also includes a power conversion circuit, which comprises a DC-DC converter, an LC filter network, and a voltage divider network. This circuit converts the input +5V voltage to the 3.3V voltage required by the FPGA. Its input is filtered by capacitor C891 and then enters the IN pin of the DC-DC converter. Its output, through the LC filter network composed of inductor L19 and capacitors C892 and C893, outputs a stable VCC-FPGA-3V3 voltage. The voltage divider network includes resistors R966 and R968, which feed the output back to the FB pin of the DC-DC converter to set the output voltage.
[0074] See Figure 7 Specifically, this embodiment also includes a clock circuit, which provides a 25MHz main clock signal to the FPGA. The clock circuit includes a 25MHz active crystal oscillator, a filter capacitor, and an impedance matching circuit. The VCC pin of the active crystal oscillator is connected to a 3.3V power supply and is decoupled and filtered by capacitors C882 and C0603. Its output terminal outputs the FPGA-25MHz clock signal to the FPGA. The impedance matching circuit includes resistors R931 and R932 for impedance matching.
[0075] See Figure 8 Specifically, this embodiment also includes a status indication and reset circuit, which includes a status indicator light, a push-button switch, and a TVS diode. When the FPGA is in working state and FPGA-CFG-DONE is at a high level, current flows through resistor R918 to illuminate the status indicator light LED9, and the PROGRAM signal line remains at a high level. The TVS diode is used to protect the PROGRAM signal line from damage caused by electrostatic discharge or voltage surges. When the push-button switch K5 is pressed, the PROGRAM signal is pulled low to ground. After the FPGA detects this low-level pulse, it will stop the current operation and enter the reconfiguration mode.
[0076] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0077] The above embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of protection of the present invention. Any non-substantial changes and substitutions made by those skilled in the art based on the present invention shall fall within the scope of protection claimed by the present invention.
Claims
1. A method for expanding the Local bus interface based on FPGA, characterized in that, The CPU of the embedded system is connected to the FPGA via a local bus, including: S1: When the system is powered on, the CPU starts up and reads the FPGA firmware file stored internally, and transmits the FPGA firmware file to the FPGA through the port to simulate the FPGA serial configuration timing according to the mode configuration protocol; S2: The FPGA automatically loads the FPGA firmware file and continuously listens for bus operation signals initiated by the CPU through the Local bus after loading is complete; The bus operation signals include at least a chip select signal and a write enable signal; S3: The FPGA identifies the current operation request of the CPU based on the combined logic state of the chip select signal and the write enable signal; S4: If the current operation request is a read operation request, the FPGA generates a read enable signal according to the preset timing logic; S5: During the period when the read enable signal is valid, the FPGA acquires the collected data from the peripheral module through the analog-to-digital converter chip, and transmits the collected data to the CPU in real time through the Local bus.
2. The FPGA-based Local bus interface expansion method according to claim 1, characterized in that, The simulation steps for the FPGA serial configuration timing in step S1 include: S11: Before reading the internally stored FPGA firmware file, the CPU disables global interrupts; S12: The CPU, according to the serial slave mode configuration protocol, simulates the PROGRAM_B pulse, clock CCLK and data DIN signals through several input and output ports respectively, and writes the FPGA firmware file bit by bit into the configuration port of the FPGA.
3. The FPGA-based Local bus interface expansion method according to claim 2, characterized in that, The logic update steps of the FPGA include: S13: Transmit the new FPGA firmware file to the CPU via the network interface or JTAG interface, and replace the FPGA firmware file in the CPU's file system. S14: The system restarts and returns to steps S11-S12 to complete the logic update of the FPGA.
4. The FPGA-based Local bus interface expansion method according to claim 1, characterized in that, The step of identifying the CPU's current operation request in step S3 includes: S31: The FPGA synchronously samples the chip select signal and the write enable signal; S32: The FPGA performs real-time decoding on the sampled chip select signal and write enable signal, and obtains two sets of signal states; S33: Determine the current operation request of the CPU based on the states of the two sets of signals; Wherein, when the chip select signal is at an active level and the write enable signal is at an active level, the current operation request of the CPU is determined to be a write operation request; The duration for which the chip select signal is at an active level and the write enable signal is at an inactive level is determined to be the current operation request of the CPU as a read operation request. When the chip select signal is at an invalid level, it is determined that the CPU currently has no operation request and the Local bus is idle.
5. The FPGA-based Local bus interface expansion method according to claim 4, characterized in that, The step of generating the read enable signal in step S4 includes: S41: After the FPGA recognizes the current operation request as a read operation request, it generates a low-level read enable signal. The analog-to-digital converter chip samples data from the peripheral module according to the read enable signal. S42: The FPGA determines whether the data conversion is complete by monitoring the status signal of the analog-to-digital converter chip or waiting for a preset conversion time; S43: If the conversion is complete, the FPGA generates a low-level active read strobe signal and outputs it to the analog-to-digital converter chip to select the data output channel of the analog-to-digital converter chip.
6. The FPGA-based Local bus interface expansion method according to claim 5, characterized in that: The FPGA generates a pair of low-level active parallel bus control signals at the rising edge of each system clock, based on the setup time, hold time, and pulse width of the chip select signal, read operation signal, and write operation signal required by the analog-to-digital converter chip. The parallel bus control signals include register operation signals and the read enable signal.
7. The FPGA-based Local bus interface expansion method according to claim 6, characterized in that, Step S5 also includes: The FPGA latches the sampled data from the analog-to-digital converter chip into its internal buffer and initiates a direct memory access transfer request to the CPU, writing the batch of sampled data into the CPU's memory via direct memory access.
8. A Local bus interface expansion circuit based on FPGA, characterized in that, The method for extending the FPGA-based Local bus interface as described in any one of claims 1-7 includes: The system comprises a CPU, an FPGA, and an analog-to-digital converter (ADC). The CPU is configured with a local bus interface and several input / output ports. It is used to simulate serial configuration timing via these input / output ports, load the FPGA firmware file onto the FPGA, and initiate read or write operation requests via the local bus. The FPGA listens for bus operation signals on the local bus. The FPGA generates peripheral read operation signals based on the bus operation signals and outputs them to the ADC. The ADC collects data from peripheral modules and transmits it to the CPU in real time via the local bus.
9. The FPGA-based Local bus interface expansion circuit according to claim 8, characterized in that, Also includes: The JTAG debugging interface is connected to the FPGA via TMS signal line, TCK signal line, TDI signal line and TDO signal line, respectively, and is used for FPGA logic debugging during the development phase.
10. The FPGA-based Local bus interface expansion circuit according to claim 8, characterized in that: The FPGA integrates a configuration memory. The CPU connects the analog clock signal line, analog data input line, analog chip select line, and analog reset line to the corresponding configuration pins of the FPGA through multiple input / output ports to form an in-circuit programming link.