An improved hard reset circuit

Abstract

The application discloses an improved hard reset circuit, which comprises a low-power chip U0, the low-power chip U0 has a plurality of GPIO pins, a plurality of SNS pins, a GND pin and a VCC pin, the low-power chip U0 internally protects the conduction of a secondary tube, and 3.0V voltage connected to the GPIO pin is poured back to the VCC pin, thereby causing 2.8V of the VCC pin. The connection structure of the improved hard reset circuit is that one end of a resistor R28 is connected to the VCC pin, and the other end is connected to a battery output voltage terminal; one end of a capacitor C26 is connected to the VCC pin, and the other end is grounded; one end of a capacitor C22 is connected to a VUSB terminal; a drain D of an N-channel MOS tube Q3 is connected to the VCC pin, a source S of the N-channel MOS tube Q3 is connected to a ground end of the capacitor C26, and a gate G of the N-channel MOS tube Q3 is connected to the other end of the capacitor C22; and the resistor R24 has two ends connected to the source S of the N-channel MOS tube Q3 and the gate G of the N-channel MOS tube Q3, respectively. The improved hard reset circuit can forcibly reset the power supply pin of the chip even if the chip selected can pour back voltage, and the software of the chip is prevented from running dead.

Description

Technical Field

[0001] This invention relates to the field of charging technology, and more specifically to an improved hard reset circuit. Background Technology

[0002] In the field of headphone charging, various portable electronic products have developed rapidly in recent years, and wireless headphones are one of the most representative portable electronic products today. Wireless headphones require internal lithium batteries for power.

[0003] When wireless earbuds are used in conjunction with the charging case, the charging case is initially in standby mode. When the wireless earbuds are placed in the charging case, the charging case detects the insertion and activates its DC 5V boost output to charge the earbuds. When the charging case detects that the earbuds have been removed, it returns to standby mode to reduce its own power consumption.

[0004] like Figure 1 As shown, Figure 1 It is a traditional charging hard reset circuit. Figure 1 In the chip, the low-power chip U0 has multiple GPIO pins, multiple SNS pins, one GND pin, and one VCC pin. The multiple SNS pins are connected to the headphone sensor terminals through resistors. The outputs of the multiple GPIO pins on the low-power chip U0 are connected to external circuits. When the external circuit is normally at a high level of 3.0V, the voltage will flow back to the input of the GPIO pins. The GPIO pins are then turned on by the protection diodes of the internal circuit of the low-power chip U0. The low-power chip U0 outputs a 2.8V voltage to the VCC pin.

[0005] The VCC pin is connected to the drain (D) of the P-channel MOSFET Q2 and one end of a capacitor C26. The other end of capacitor C26 is grounded. The gate (G) of the P-channel MOSFET Q2 is connected to capacitor C22 and resistor R24. The other end of capacitor C22 is connected to the VUSB terminal. The other end of resistor R24 ​​is connected to the ground terminal of capacitor C26. The source (S) of the P-channel MOSFET Q2 is connected to the VBAT terminal of the battery.

[0006] In the traditional charging hard reset circuit described above, a power-off method is used for hard reset. Before charging, the gate G of the P-channel MOSFET Q2 is grounded to GND through resistor R24, and the gate G potential of the P-channel MOSFET Q2 is 0V. Its source S is at a high level of 4.2V. The voltage of the gate G of the P-channel MOSFET Q2 is lower than that of the source S of the P-channel MOSFET Q2. The source S and drain D of the P-channel MOSFET Q2 are connected, and the voltage on the VBAT terminal supplies power to the VCC pin of the low-power chip U0 through the P-channel MOSFET Q2. In the first 2 seconds after the earphone is placed in the charging case for charging, the P-channel MOSFET... The gate G of Q2 is at a high level of 5V, and the source S of the P-channel MOSFET Q2 is at a high level of 4.2V. The gate G voltage of the P-channel MOSFET is higher than the source S voltage of the P-channel MOSFET. The source S and drain D of the P-channel MOSFET are disconnected. The voltage on the VBAT terminal stops supplying power to the VCC pin of the low-power chip U0 through the disconnection of the P-channel MOSFET Q2. At this time, there is a reverse voltage on the VCC pin of the low-power chip U0. The VCC pin of the low-power chip U0 is powered by the internal reverse voltage, and the software is still running.

[0007] Therefore, the low-power chip U0 may fail to undergo a hard reset.

[0008] Therefore, it is necessary to design a hard reset circuit that can instantly pull the power supply VCC pin down to 0V even if there is a reverse voltage on the power supply VCC pin of the low-power chip U0. Summary of the Invention

[0009] To address the shortcomings of existing technologies, the present invention aims to provide an improved hard reset circuit. The purpose of this improved hard reset circuit is to force the chip with reverse voltage to ground, thereby achieving a fast hard reset of the circuit.

[0010] To solve the above technical problems, the present invention achieves this through the following solution: An improved hard reset circuit of the present invention includes a low-power chip U0, which has multiple GPIO pins, multiple SNS pins, a GND pin, and a VCC pin. The multiple SNS pins are each connected to the headphone terminal via resistors. The outputs of the multiple GPIO pins of the low-power chip U0 are connected to an external circuit. When the external circuit is normally at a high level of 3.0V, the voltage will flow back to the GPIO pin input. The GPIO pin is then protected by a diode within the low-power chip U0, allowing the low-power chip U0 to output a 2.8V voltage to the VCC pin, thus enabling a forced hard reset. The improved hard reset circuit also includes:

[0011] Resistor R28, one end is connected to the VCC pin, and the other end is connected to the battery output voltage terminal;

[0012] Capacitor C26 has one end connected to the VCC pin and the other end grounded.

[0013] Capacitor C22, one end of which is connected to the VUSB terminal;

[0014] An N-channel MOSFET Q3 is provided, with its drain D connected to the VCC pin, its source S connected to the ground terminal of capacitor C26, and its gate G connected to the other end of capacitor C22.

[0015] Resistor R24 ​​is connected at both ends to the source S and the gate of the N-channel MOSFET Q3, respectively.

[0016] Furthermore, the resistance of the resistor R28 is 1K.

[0017] Furthermore, the capacitor C26 is a 104 capacitor.

[0018] Furthermore, the capacitor C22 is a 105 capacitor.

[0019] Furthermore, the N-channel MOSFET Q3 is model CJ3134K.

[0020] Furthermore, the resistance of the resistor R24 ​​is 470K.

[0021] Furthermore, the low-power chip U0 is a programmable microcontroller.

[0022] Compared with the prior art, the beneficial effects of the present invention are: the present invention improves the traditional hard reset circuit. The improved hard reset circuit can force a hard reset when a chip that may generate reverse voltage is selected, thus avoiding the chip software from crashing. Attached Figure Description

[0023] Figure 1 This is a conventional hard reset circuit diagram for this invention.

[0024] Figure 2 This is a circuit diagram of the improved hard reset circuit of the present invention. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the scope of protection of the present invention. Obviously, the embodiments described in this invention are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0027] Example 1: The specific structure of the present invention is as follows:

[0028] Please refer to the appendix. Figure 2 An improved hard reset circuit of the present invention includes a low-power chip U0, which has multiple GPIO pins, multiple SNS pins, a GND pin, and a VCC pin. The multiple SNS pins are each connected to an earphone sensor terminal via resistors. The outputs of the multiple GPIO pins on the low-power chip U0 are connected to an external circuit. When the external circuit is normally at a high level of 3.0V, the voltage flows back to the GPIO pin input. The GPIO pin is then protected by a diode within the low-power chip U0, allowing the low-power chip U0 to output a 2.8V voltage to the VCC pin. The improved hard reset circuit also includes:

[0029] Resistor R28, one end is connected to the VCC pin, and the other end is connected to the battery output voltage terminal;

[0030] Capacitor C26 has one end connected to the VCC pin and the other end grounded.

[0031] Capacitor C22, one end connected to the VUSB terminal;

[0032] An N-channel MOSFET Q3 is provided, with its drain D connected to the VCC pin, its source S connected to the ground terminal of capacitor C26, and its gate G connected to the other end of capacitor C22.

[0033] Resistor R24 ​​is connected at both ends to the source S and the gate G of the N-channel MOSFET Q3, respectively.

[0034] A preferred embodiment of this technical solution is that the resistance of resistor R28 is 1K.

[0035] A preferred embodiment of this technical solution: the capacitor C26 is a 104 capacitor.

[0036] A preferred embodiment of this technical solution: the capacitor C22 is a 105 capacitor.

[0037] A preferred embodiment of this technical solution: the N-channel MOSFET Q3 is model CJ3134K.

[0038] A preferred embodiment of this technical solution is that the resistance of resistor R24 ​​is 470K.

[0039] A preferred embodiment of this technical solution is that the low-power chip U0 is a programmable microcontroller.

[0040] Example 2:

[0041] The following is the working principle of the improved hard reset circuit of this invention:

[0042] like Figure 2 As shown, the low-power chip U0 of this invention has 9 pins, including four GPIO pins: GPIO0, GPIO1, GPIO2, and GPIO3. The GPIO0 pin is connected to the PWRKEY circuit and resistor R26, with the other end of resistor R26 connected to the NTCVDD circuit. The GPIO1 pin is connected to the EARIN circuit and resistor R27, with the other end of resistor R27 connected to the NTCVDD circuit. The GPIO2 pin is connected to resistor R25, with the other end of resistor R25 connected to the INT circuit.

[0043] Figure 2 Before the earphones are placed in the charging case, the gate G of the N-channel MOSFET Q3 is grounded to GND through resistor R24, the potential of the gate G of the N-channel MOSFET Q3 is 0V, the source S of the N-channel MOSFET Q3 is at a low level of 0V, the voltage of the gate G of the N-channel MOSFET Q3 is equal to the voltage of the source S of the N-channel MOSFET Q3, the source S of the N-channel MOSFET Q3 and the drain D of the N-channel MOSFET Q3 are disconnected, and the VBAT voltage supplies power to the VCC pin of the low-power chip U0 through resistor R28.

[0044] Figure 2 In the initial 2 seconds after the earphones are placed in the charging case, due to the characteristics of capacitor charging, the charging response time of capacitor C22 needs to be within 2 seconds. The gate G of N-channel MOSFET Q3 is charged to a high level of 5V through capacitor C22 (the voltage gradually decreases). The potential of the gate G of N-channel MOSFET Q3 is high, and the source S of N-channel MOSFET Q3 is low level of 0V. The voltage of the gate G of N-channel MOSFET Q3 is higher than that of the source S of N-channel MOSFET Q3. The source S and drain D of N-channel MOSFET Q3 are turned on. The VBAT voltage is shorted to ground GND by the drain D and source S of N-channel MOSFET Q3 through resistor R28. The power supply of the VCC pin of low-power chip U0 is also shorted to ground by the drain D and source S of N-channel MOSFET Q3. Finally, low-power chip U0 achieves a hard reset. Even if the software runs out of power, it can be restarted.

[0045] In summary, this invention improves upon the traditional hard reset circuit. The improved hard reset circuit can force a hard reset when a chip that may generate reverse voltage is selected, thus preventing the chip software from crashing.

[0046] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. An improved hard reset circuit, comprising a low-power chip U0, the low-power chip U0 having multiple GPIO pins, multiple SNS pins, a GND pin, and a VCC pin, wherein the multiple SNS pins are each connected to an earphone sensor terminal via resistors, the outputs of the multiple GPIO pins on the low-power chip U0 are connected to an external circuit, when the external circuit is normally at a high level of 3.0V, the voltage will flow back to the GPIO pin input, and the GPIO pin will be turned on by a protection diode in the internal circuit of the low-power chip U0, and the low-power chip U0 internally outputs a 2.8V voltage to the VCC pin, characterized in that... The improved hard reset circuit also includes: Resistor R28, one end is connected to the VCC pin, and the other end is connected to the battery output voltage terminal; Capacitor C26 has one end connected to the VCC pin and the other end grounded. One end of capacitor C22 is connected to the VUSB terminal; An N-channel MOSFET Q3 is provided, with its drain D connected to the VCC pin, its source S connected to the ground terminal of capacitor C26, and its gate G connected to the other end of capacitor C22. Resistor R24 ​​is connected at both ends to the source S and the gate G of the N-channel MOSFET Q3, respectively.

2. The improved hard reset circuit according to claim 1, characterized in that, The resistance of resistor R28 is 1K.

3. The improved hard reset circuit according to claim 1, characterized in that, The capacitor C26 is a 104 capacitor.

4. An improved hard reset circuit according to claim 1, characterized in that, The capacitor C22 is a 105 capacitor.

5. An improved hard reset circuit according to claim 1, characterized in that, The N-channel MOSFET Q3 is model CJ3134K.

6. An improved hard reset circuit according to claim 1, characterized in that, The resistance of resistor R24 ​​is 470K.

7. An improved hard reset circuit according to claim 1, characterized in that, The low-power chip U0 is a programmable microcontroller.

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