High performance storage device with multiple master chips

Abstract

The embodiment of the application provides a high-performance storage device with multiple master chips, and relates to the technical field of storage. The storage device comprises a first control component and a second control component; the first control component comprises a first host interface, a first host command processing unit, a first storage command processing unit, a first storage medium management unit and a first medium interface controller; the second control component comprises a second host interface, a second host command processing unit, a second storage command processing unit, a second storage medium management unit and a second medium interface controller; the first control component is coupled with a first host through the first host interface, and the second control component is coupled with a second host through the second host interface. The first control component and the second control component can cooperatively process the IO commands received by each other to access NVM chips, so that the demand of a large-capacity and high-performance storage device is met.

Description

Technical Field

[0001] This application relates to the field of storage technology, and more particularly to a storage device. Background Technology

[0002] Figure 1A A block diagram of a solid-state storage device (SSD) is shown. The SSD 102 is coupled to a host computer to provide storage capabilities. The host computer and the SSD 102 can be coupled in various ways, including but not limited to connections via SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIe (Peripheral Component Interconnect Express), NVMe (NVM Express), Ethernet, Fibre Channel, and wireless communication networks. The host computer can be an information processing device capable of communicating with the storage device via the above methods, such as a personal computer, tablet computer, server, laptop computer, network switch, router, cellular phone, or personal digital assistant. Storage device 102 (hereinafter referred to as storage device) includes interface 103, control unit 104, one or more NVM chips 105 and DRAM (Dynamic Random Access Memory) 110.

[0003] The aforementioned NVM chip 105 includes NAND flash memory, phase-change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), etc., which are common storage media.

[0004] The aforementioned interface 103 can be adapted to exchange data with the host via methods such as SATA, IDE, USB, PCIe, NVMe, SAS, Ethernet, and Fibre Channel.

[0005] The aforementioned control unit 104 is used to control data transmission between interface 103, NVM chip 105, and DRAM 110, and is also used for memory management, host logical address to flash physical address mapping, erase leveling, bad block management, etc. Control unit 104 can be implemented in various ways, including software, hardware, firmware, or combinations thereof. For example, control unit 104 can be in the form of an FPGA (Field-programmable gate array), ASIC (Application Specific Integrated Circuit), or a combination thereof. Control unit 104 may also include a processor or controller, in which software is executed to manipulate the hardware of control unit 104 to process I / O (Input / Output) commands. Control unit 104 can also be coupled to DRAM 110 and can access data in DRAM 110. FTL tables and / or cached I / O command data can be stored in DRAM.

[0006] The control unit 104 issues commands to the NVM chip 105 in accordance with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives the command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle" and "ONFI".

[0007] A memory target is one or more logic units (LUNs) within a NAND flash memory package that share a chip enable (CE) signal. A NAND flash memory package may include one or more dies. Typically, a logic unit corresponds to a single die. A logic unit may include multiple planes. Multiple planes within a logic unit can be accessed in parallel, while multiple logic units within a NAND flash memory chip can execute commands and report status independently of each other.

[0008] Figure 1B A block diagram of non-volatile memory is shown. For example... Figure 2 As shown, the non-volatile memory 105 includes one or more logic units (LUNs). A logic unit (LUN) is the smallest unit within an NVM chip that independently executes commands and reports its status. A logic unit may include multiple planes. Multiple planes within a logic unit can access data in parallel. While multiple planes within a logic unit can access data in parallel, multiple logic units within the non-volatile memory can independently execute commands and report their status. The meanings of target, logic unit (LUN), and plane are part of the prior art.

[0009] Data is typically stored and retrieved in pages on storage media, while data is erased in blocks. A block (also called a physical block) contains multiple pages. Pages on a storage medium (called physical pages) have a fixed size, such as 17664 bytes. Physical pages can also have other sizes.

[0010] In storage device 102, an FTL (Flash Translation Layer) is used to maintain mapping information from logical addresses (LBAs) to physical addresses. Logical addresses constitute the storage space of the solid-state storage device as perceived by upper-layer software such as the operating system. Physical addresses are the addresses used to access the physical storage units of the solid-state storage device. In related technologies, address mapping can also be implemented using intermediate address formats. For example, a logical address can be mapped to an intermediate address, and then the intermediate address can be further mapped to a physical address. The table structure that stores the mapping information from logical addresses to physical addresses is called the FTL table. The FTL table is important metadata in the storage device. The data items in the FTL table record the address mapping relationships in the storage device, unit by unit.

[0011] The host accesses the storage device using I / O commands that conform to the storage protocol. The control unit generates one or more media interface commands based on the I / O commands from the host and provides them to the media interface controller. The media interface controller generates storage media access commands (e.g., programming commands, read commands, erase commands) that conform to the NVM chip's interface protocol based on the media interface commands. The control unit also tracks the completion of all media interface commands generated from a single I / O command and indicates the processing results of the I / O commands to the host.

[0012] See Figure 1C The control components include a host interface 1041, a host command processing unit 1042, a storage command processing unit 1043, a media interface controller 1044, and a storage media management unit 1045. The host interface 1041 receives I / O commands from the host. The host command processing unit 1042 generates storage commands based on the I / O commands and provides them to the storage command processing unit 1043. Each storage command can access a storage space of the same size, such as 4KB. The data unit recorded in the NVM chip corresponding to the data accessed by a storage command is called a data frame. A physical page records one or more data frames. For example, if the size of a physical page is 17664 bytes and the size of a data frame is 4KB, then one physical page can store four data frames.

[0013] The storage media management unit 1045 maintains the logical address to physical address translation for each storage command. For example, the storage media management unit 1045 includes an FTL table (explained below). For a read command, the storage media management unit 1045 outputs the physical address corresponding to the logical address (LBA) accessed by the storage command. For a write command, the storage media management unit 1045 allocates an available physical address and records the mapping between the accessed logical address (LBA) and the allocated physical address. The storage media management unit 1045 also maintains functions required for managing the NVM chip, such as garbage collection and wear leveling.

[0014] The storage command processing unit 1043, based on the physical address provided by the storage media management unit 1045, operates the media interface controller 1044 to send a storage media access command to the NVM chip 105.

[0015] For clarity, commands sent from the host to storage device 102 are called I / O commands (including, for example, NVMe read commands and NVMe write commands), commands sent from host command processing unit 1042 to storage command processing unit 1043 are called storage commands, commands sent from storage command processing unit 1043 to media interface controller 1044 are called media interface commands, and commands sent from media interface controller 1044 to NVM chip 105 are called storage media access commands. Storage media access commands follow the interface protocol of the NVM chip. Summary of the Invention

[0016] With the increasing demand for high-capacity storage devices, there is a need for higher performance and larger capacity storage. The performance of a storage device is limited by the performance of its control unit. For example, the capacity of a storage device is limited by the number of flash channels in the control unit. A flash channel includes the I / O pins required for the control unit to connect to the NVM chip. Through I / O pin multiplexing, each flash channel can typically connect to two NVM chips. If a larger number of NVM chips needs to be placed in the storage device, a larger number of flash channels are required. For example, a single control unit includes eight flash channels, managing a capacity of 16TB or 32TB. For larger capacities such as 64TB or 128TB, the control unit needs to provide even more flash channels. Each flash channel also includes a LUN controller; more flash channels allow more LUN controllers to access the NVM chip in parallel, improving the performance of the control unit. However, for integrated circuit chips, as the number of flash channels increases, the manufacturing and testing costs also rise exponentially. This application aims to provide a high-capacity, high-performance storage device with a limited number of flash channels provided by the control unit.

[0017] In view of this, embodiments of this application provide a storage device comprising two control components, each control component including a host interface, a host command processing unit, a storage command processing unit, a storage media management unit, and a media interface controller. Optionally, an inter-chip communication link exists between the two control components, and the two control components collaboratively process IO commands sent by the host through this inter-chip communication link to access the NVM chip, thereby meeting the requirements of a high-capacity and high-performance storage device.

[0018] According to a first aspect of the embodiments of this application, a storage device is provided, including a master control component, a slave control component, and an inter-chip communication link; the master control component includes a first host interface, a first host command processing unit, a first storage command processing unit, a first storage medium management unit, and a first medium interface controller; the slave control component includes a second host interface, a second host command processing unit, a second storage command processing unit, a second storage medium management unit, and a second medium interface controller; the first host interface is coupled to a host, and the inter-chip communication link couples the second storage command processing unit to lead the first host command processing unit; the master control component and the slave control component collaboratively process IO commands received from the first host interface through the inter-chip communication link.

[0019] Optionally, the main control unit receives IO commands sent by the host through the first host interface and sends the IO commands to the first host command processing unit; the first host command processing unit generates one or more storage commands based on the IO commands and assigns one or more storage commands to the first storage command processing unit and the second storage command processing unit.

[0020] Optionally, the first host command processing unit assigns one or more storage commands to the first storage command processing unit and the second storage command processing unit based on the logical address indicated by one or more storage commands.

[0021] Optionally, if the IO command is an NVMe write command, the first host command processing unit generates one or more first storage commands based on the NVMe write command, and alternately assigns one or more first storage commands to the first storage command processing unit and the second storage command processing unit.

[0022] Optionally, if the IO command is an NVMe write command, and the NVMe write command indicates a logical address range, the first host command processing unit generates one or more first storage commands based on the logical address range and assigns them to the first storage command processing unit and the second storage command processing unit.

[0023] Optionally, the logical address range includes a first logical address range and a second logical address range. The first host command processing unit assigns a first storage command whose indicated logical address is within the first logical address range to the first storage command processing unit, and assigns a first storage command whose indicated logical address is within the second logical address range to the second storage command processing unit.

[0024] Optionally, if the IO command is an NVMe write command, the first host command processing unit generates one or more first storage commands based on the NVMe write command, and assigns the first storage commands to the first storage command processing unit and the second storage command processing unit according to the parity of the logical address indicated by each first storage command.

[0025] Optionally, the first host command processing unit assigns a first storage command with an even logical address to the first storage command processing unit, and assigns a first storage command with an odd logical address to the second storage command processing unit; or, the first host command processing unit assigns a first storage command with an odd logical address to the first storage command processing unit, and assigns a first storage command with an even logical address to the second storage command processing unit.

[0026] Optionally, if the IO command is an NVMe read command, the first host command processing unit generates one or more second storage commands based on the NVMe read command, and assigns each second storage command to the storage command processing unit corresponding to its corresponding first storage command, wherein the logical address indicated by the second storage command is the same as the logical address indicated by its corresponding first storage command.

[0027] Optionally, the first storage medium management unit includes a first FTL table, which records the physical address corresponding to the logical address of the storage command instruction allocated to the first storage command processing unit; the second storage medium management unit includes a second FTL table, which records the physical address corresponding to the logical address of the storage command instruction allocated to the second storage command processing unit.

[0028] Optionally, if the IO command is an NVMe write command, the first host command processing unit moves the data indicated by the NVMe write command from the host to the cache of the storage device; and in response to the completion of the NVMe write command processing, sends an NVMe write command processing completion message to the host through the first host interface. If the IO command is an NVMe read command, the first host command processing unit moves the data indicated by the NVMe read command from the cache of the storage device to the host; and in response to the completion of the NVMe read command processing, sends an NVMe read command processing completion message to the host through the first host interface.

[0029] Optionally, the second storage command processing unit, in response to receiving a storage command from the first host command processing unit and indicating that the storage command processing is complete, sends a storage command processing completion message to the first host command processing unit; the first storage command processing unit, in response to receiving a storage command from the first host command processing unit and indicating that the storage command processing is complete, sends a storage command processing completion message to the first host command processing unit.

[0030] Optionally, the master control unit and the slave control unit share the cache of the storage device.

[0031] According to a second aspect of the embodiments of this application, a storage device is provided, including a master control unit, a slave control unit, and an inter-chip communication link; the master control unit includes a first host interface, a first host command processing unit, a first storage command processing unit, a first storage medium management unit, and a first medium interface controller; the slave control unit includes a second host interface, a second host command processing unit, a second storage command processing unit, a second storage medium management unit, and a second medium interface controller; the master control unit and the slave control unit communicate through the inter-chip communication link; the first host interface is coupled to a host; the master control unit and the slave control unit collaboratively process IO commands received from the first host interface through the inter-chip communication link.

[0032] In an optional embodiment, the second host interface, the second host command processing unit, the second storage command processing unit, and the second storage medium management unit are not operational; the inter-chip communication link couples the second medium interface controller as a bus device to the main control unit.

[0033] In an optional embodiment, the chip-to-chip communication link couples the second media interface controller to the first storage command processing unit in the first control component.

[0034] In an optional embodiment, the main control unit receives IO commands sent by the host through the first host interface and sends the IO commands to the first host command processing unit; the first host command processing unit generates one or more storage commands based on the IO commands and sends the one or more storage commands to the first storage command processing unit; the first storage command processing unit generates one or more media interface commands based on the one or more storage commands and assigns the media interface commands to the first media interface controller and the second media interface controller.

[0035] In an optional embodiment, the main control unit is connected to the cache of the storage device, while the slave control unit is not connected to the cache of the storage device; the second media interface controller accesses the cache of the storage device through an inter-chip communication link to obtain the data indicated by the media interface command it receives.

[0036] In an optional embodiment, the first media interface controller, in response to completing the processing of a received media interface command, sends a media interface command processing completion message to the first storage command processing unit; the second media interface controller, in response to completing the processing of a received media interface command, sends a media interface command processing completion message to the first storage command processing unit; the first storage command processing unit receives the media interface command processing completion messages from the first and second media interface controllers, generates a storage command processing completion message corresponding to the received media interface command processing completion messages, and sends it to the first host command processing unit.

[0037] In an optional embodiment, the first storage command processing unit assigns one or more media interface commands to the first media interface controller and the second media interface controller based on the physical address indicated by one or more media interface commands.

[0038] In an optional embodiment, the first storage command processing unit determines the logical unit to be accessed based on the physical address indicated by each media interface command, and determines the NVM chip corresponding to the logical unit, and assigns the media interface command to the media interface controller in the control unit coupled to the NVM chip.

[0039] In an optional embodiment, if the IO command is an NVMe write command, the first host command processing unit generates one or more first storage commands based on the NVMe write command, the first storage command processing unit allocates physical addresses for the logical addresses indicated by the one or more first storage commands based on page stripes, and generates one or more first media interface commands based on the physical addresses corresponding to the logical addresses indicated by the one or more first storage commands.

[0040] In an optional embodiment, the page stripe consists of physical pages from logic cells on the NVM chip coupled from the main control unit and logic cells on the NVM chip coupled from the control unit.

[0041] In an optional embodiment, a page strip consists of physical pages of logic cells from all NVM chips coupled to the main control unit and logic cells from all NVM chips coupled to the control unit.

[0042] In an optional embodiment, a page stripe consists of physical pages of logic cells from a portion of the NVM chip coupled to the main control unit and logic cells from a portion of the NVM chip coupled to the control unit.

[0043] Optionally, the first storage command processing unit assigns the physical address corresponding to a physical page in the page stripe to the logical address indicated by one or more storage commands.

[0044] Optionally, in response to receiving a first storage command, if the physical addresses in the first page strip are not fully allocated, the first storage command processing unit allocates a physical address from the unallocated physical addresses in the first page strip for the logical address indicated by the first storage command; if the physical addresses in the first page strip are fully allocated, it allocates a physical address from the physical addresses in the second page strip for the logical address indicated by the first storage command; the second page strip is a different page strip from the first page strip.

[0045] Optionally, the expected number of storage commands corresponding to the first page stripe is determined based on the storage space capacity corresponding to the first page stripe and the storage cell capacity indicated by the logical address; if the number of storage commands currently allocating physical addresses from the first page stripe is less than the expected number, it indicates that the physical addresses in the first page stripe have not been fully allocated; if the number of storage commands currently allocating physical addresses from the first page stripe is equal to the expected number, it indicates that the physical addresses in the first page stripe have been fully allocated.

[0046] Optionally, the first storage media management unit is coupled to an FTL table, which records the physical addresses allocated by the first storage command processing unit for the logical addresses indicated by the various storage commands received.

[0047] Optionally, if the IO command is an NVMe read command, the first host command processing unit generates one or more second storage commands based on the NVMe read command; the first storage command processing unit determines the physical address corresponding to the logical address indicated by the second storage command by querying the FTL table, and generates one or more second media interface commands based on the physical address.

[0048] Optionally, if the IO command is an NVMe write command, the first host command processing unit moves the data indicated by the NVMe write command from the host to the cache of the storage device; and in response to the completion of the NVMe write command processing, sends an NVMe write command processing completion message to the host through the first host interface; if the IO command is an NVMe read command, the first host command processing unit moves the data indicated by the NVMe read command from the cache of the storage device to the host; and in response to the completion of the NVMe read command processing, sends an NVMe read command processing completion message to the host through the first host interface.

[0049] Optionally, the first control unit and the second control unit have the same circuit structure.

[0050] According to a third aspect of the embodiments of this application, a storage device is provided, including: a first control component and a second control component; the first control component includes a first host interface, a first host command processing unit, a first storage command processing unit, a first storage medium management unit, and a first medium interface controller; the second control component includes a second host interface, a second host command processing unit, a second storage command processing unit, a second storage medium management unit, and a second medium interface controller; the first control component is coupled to a first host through the first host interface, and the second control component is coupled to a second host through the second host interface.

[0051] Optionally, the first control unit receives IO commands sent by the first host through the first host interface, and the second control unit receives IO commands sent by the second host through the second host interface. The IO commands sent by the first host to the first control unit and the IO commands sent by the second host to the second control unit are different IO commands.

[0052] Optionally, the first control unit and the second control unit independently process their respective received IO commands.

[0053] Optionally, the storage device further includes: an inter-chip communication link; the first control unit and the second unit cooperate in processing the received IO commands through the inter-chip communication link.

[0054] Optionally, the inter-chip communication link includes at least one of the following: a first inter-chip communication link formed by coupling the second storage command processing unit and the first host command processing unit; a second inter-chip communication link formed by coupling the first storage command processing unit and the second host command processing unit; a third inter-chip communication link formed by coupling the second host interface and the first host command processing unit; and a fourth inter-chip communication link formed by coupling the first storage command processing unit and the second media interface controller.

[0055] Optionally, the first control unit receives a first IO command sent by the first host through the first host interface and sends the first IO command to the first host command processing unit; the first host command processing unit generates one or more first storage commands according to the first IO command, and assigns one or more first storage commands to the first storage command processing unit and to the second storage command processing unit through the first inter-chip communication link.

[0056] Optionally, the first host command processing unit distributes some of the first storage commands to the second storage command processing unit through the first inter-chip communication link.

[0057] Optionally, the first host command processing unit assigns one or more first storage commands to the first storage command processing unit and the second storage command processing unit according to the logical address indicated by one or more first storage commands.

[0058] Optionally, if the first IO command is an NVMe write command, the first host command processing unit generates one or more second storage commands based on the NVMe write command, and alternately assigns one or more second storage commands to the first storage command processing unit and the second storage command processing unit.

[0059] Optionally, if the first IO command is an NVMe write command, and the NVMe write command indicates a logical address range, one or more second storage commands generated by the first host command processing unit according to the NVMe write command are allocated to the first storage command processing unit and the second storage command processing unit according to the logical address range.

[0060] Optionally, the logical address range includes a first logical address range and a second logical address range. The first host command processing unit assigns a second storage command whose indicated logical address is within the first logical address range to the first storage command processing unit, and assigns a second storage command whose indicated logical address is within the second logical address range to the second storage command processing unit.

[0061] Optionally, if the first IO command is an NVMe write command, the first host command processing unit generates one or more second storage commands based on the NVMe write command, and assigns the second storage commands to the first storage command processing unit and the second storage command processing unit according to the parity of the logical address indicated by each second storage command.

[0062] Optionally, the first host command processing unit assigns the second storage command with an even logical address to the first storage command processing unit and assigns the second storage command with an odd logical address to the second storage command processing unit; or, the first host command processing unit assigns the second storage command with an odd logical address to the first storage command processing unit and assigns the second storage command with an even logical address to the second storage command processing unit.

[0063] Optionally, if the first IO command is an NVMe read command, the first host command processing unit generates one or more third storage commands based on the NVMe read command, and assigns each third storage command to the storage command processing unit corresponding to its corresponding second storage command, wherein the logical address indicated by the third storage command is the same as the logical address indicated by its corresponding second storage command.

[0064] Optionally, the second control unit receives the second IO command sent by the second host through the second host interface, and sends the second IO command to the second host command processing unit; the second host command processing unit generates one or more fourth storage commands according to the second IO command, and assigns one or more fourth storage commands to the first storage command processing unit and to the second storage command processing unit through the second inter-chip communication link.

[0065] Optionally, the second host command processing unit distributes some of the fourth storage commands to the first storage command processing unit via the second inter-chip communication link.

[0066] Optionally, the second host interface in the second control unit may assign one or more third IO commands received to the first host command processing unit and to the second host command processing unit via a third inter-chip communication link.

[0067] Optionally, the second control unit distributes some of the third I / O commands to the first host command processing unit via a third inter-chip communication link.

[0068] Optionally, the first control unit receives a fourth IO command through a first host interface and sends the fourth IO command to a first host command processing unit; the second control unit receives a fifth IO command through a second host interface and sends the fifth IO command to a first host command processing unit through a third inter-chip communication link; the first host command processing unit generates one or more fifth storage commands and one or more sixth storage commands based on the fourth IO command, and assigns the one or more fifth storage commands and one or more sixth storage commands to the first storage command processing unit and to the second storage command processing unit through the first inter-chip communication link.

[0069] Optionally, the first host command processing unit distributes some of the fifth storage commands and some of the sixth storage commands to the second storage command processing unit through the first inter-chip communication link.

[0070] Optionally, the second host command processing unit in the second control component is not working, and the second control component sends all the fifth IO commands it receives to the first host command processing unit through the third inter-chip communication link.

[0071] Optionally, the first storage command processing unit generates one or more media interface commands based on the received seventh storage command, and assigns one or more media interface commands to the first media interface controller and to the second media interface controller via a fourth inter-chip communication link.

[0072] Optionally, the first storage command processing unit distributes some media interface commands to the second media interface controller via the fourth inter-chip communication link.

[0073] Optionally, the first storage command processing unit assigns one or more media interface commands to the first media interface controller and the second media interface controller based on the physical address indicated by one or more media interface commands.

[0074] Optionally, the first storage command processing unit determines the logical unit to be accessed based on the physical address indicated by each media interface command, and determines the NVM chip corresponding to the logical unit, and assigns the media interface command to the media interface controller in the control unit coupled to the NVM chip.

[0075] Optionally, if the seventh storage command is a storage command corresponding to an NVMe write command, the first storage command processing unit allocates a physical address to the logical address indicated by the seventh storage command according to the page stripe, and generates one or more first media interface commands according to the physical address corresponding to the logical address indicated by the seventh storage command.

[0076] Optionally, the page stripe consists of physical pages from NVM chip logic cells coupled to the first control unit and NVM chip logic cells coupled to the second control unit.

[0077] Optionally, the page stripe consists of physical pages of logic cells from all NVM chips coupled to the first control unit and logic cells from all NVM chips coupled to the second control unit.

[0078] Optionally, the page stripe consists of physical pages from logic cells on a portion of the NVM chip coupled to the first control unit and logic cells on a portion of the NVM chip coupled to the second control unit.

[0079] Optionally, the first storage command processing unit assigns the physical address corresponding to a physical page in the page stripe to one or more logical addresses indicated by the sixth storage command.

[0080] Optionally, in response to receiving a new seventh storage command, if the physical addresses in the first page strip are not fully allocated, the first storage command processing unit allocates a physical address from the unallocated physical addresses in the first page strip for the logical address indicated by the new seventh storage command; if the physical addresses in the first page strip are fully allocated, the first storage command allocates a physical address from the physical addresses in the second page strip for the logical address indicated by the new seventh storage command; the second page strip and the first page strip are different page strips.

[0081] Optionally, the expected number of storage commands corresponding to the first page stripe is determined based on the storage space capacity corresponding to the first page stripe and the storage cell capacity indicated by the logical address; if the number of storage commands currently allocating physical addresses from the first page stripe is less than the expected number, it indicates that the physical addresses in the first page stripe have not been fully allocated; if the number of storage commands currently allocating physical addresses from the first page stripe is equal to the expected number, it indicates that the physical addresses in the first page stripe have been fully allocated.

[0082] Optionally, if the seventh storage command is a storage command corresponding to an NVMe read command, the first storage command processing unit determines the physical address corresponding to the logical address indicated by the seventh storage command by querying the first FTL table coupled to the first storage media management unit, and generates one or more second media interface commands based on the physical address.

[0083] Optionally, the first control unit receives a sixth IO command through a first host interface and sends the sixth IO command to a first host command processing unit; the second control unit receives a seventh IO command through a second host interface and sends the seventh IO command to the first host command processing unit through a third inter-chip communication link; the first host command processing unit generates one or more eighth storage commands based on the sixth IO command and one or more ninth storage commands based on the seventh IO command, and sends the one or more eighth storage commands and one or more ninth storage commands to the first storage command processing unit; the first storage command processing unit generates corresponding media interface commands based on each received eighth and ninth storage command, and assigns the generated media interface commands to the first media interface controller and to the second media interface controller through a fourth inter-chip communication link.

[0084] Optionally, the second host command processing unit, the second storage command processing unit, and the second storage medium management unit may not operate.

[0085] Optionally, the first storage media management unit is coupled to a first FTL table, and the second storage media management unit is coupled to a second FTL table. The first FTL table and the second FTL table manage and maintain the logical address space provided by the storage device.

[0086] Optionally, the first control unit and the second control unit share the first FTL table managed and maintained by the first storage medium management unit; the first FTL table manages and maintains the logical address space provided by the storage device. Attached Figure Description

[0087] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0088] Figure 1A A block diagram of a solid-state storage device in prior art is shown;

[0089] Figure 1B A block diagram showing the logical units in a solid-state storage device;

[0090] Figure 1C A block diagram of the control components in a prior art solid-state storage device is shown;

[0091] Figure 2 A schematic diagram of the structure of a storage device according to an embodiment of this application is shown;

[0092] Figure 3 This application illustrates a schematic diagram showing the structure of the control component coupled to the host in a storage device according to an embodiment of the present application;

[0093] Figure 4 A schematic diagram illustrating the allocation of storage commands by the host command processing unit 1 according to an embodiment of this application is shown;

[0094] Figure 5 A schematic diagram illustrating the allocation of storage commands by the host command processing unit 1 according to another embodiment of this application is shown;

[0095] Figure 6 A schematic diagram illustrating the allocation of storage commands by the host command processing unit 1 according to another embodiment of this application is shown;

[0096] Figure 7 A schematic diagram illustrating the processing of NVMe read commands by a storage device according to an embodiment of this application is shown;

[0097] Figure 8 This application illustrates a schematic diagram showing the connection between control component 3 and control component 4 in a storage device provided in an embodiment of the present application;

[0098] Figure 9 A schematic diagram illustrating the allocation of physical addresses according to page stripes in a storage device according to an embodiment of this application is shown;

[0099] Figure 10 A schematic diagram of the construction page strip provided in an embodiment of this application is shown;

[0100] Figure 11 This illustration shows another schematic diagram of a page strip structure provided by an embodiment of this application;

[0101] Figure 12 This illustration shows a schematic diagram of a storage device processing NVMe read commands according to an embodiment of this application;

[0102] Figure 13 This illustration shows a schematic diagram of the structure in a storage device according to another embodiment of the present application, showing the coupling between the control component and the host.

[0103] Figures 14A-14E This application illustrates a schematic diagram showing the connection between control component 5 and control component 6 in an embodiment of the present application.

[0104] Figure 15 This application illustrates a schematic diagram showing the connection between control component 5 and control component 6 in an embodiment of the present application.

[0105] Figure 16 A schematic diagram showing the connection between control component 5 and control component 6 in an embodiment of this application is provided. Detailed Implementation

[0106] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0107] Figure 2 A schematic diagram of a storage device according to an embodiment of this application is shown.

[0108] For example, such as Figure 2 As shown, the storage device includes a control unit 1 and a control unit 2.

[0109] Control unit 1 includes: host interface 1, host command processing unit 1, storage command processing unit 1, storage media management unit 1, and media interface controller 1. Control unit 1 can be coupled to one or more NVM chips. For example... Figure 2 As shown, control unit 1 is coupled to four NVM chips.

[0110] Control unit 2 includes: host interface 2, host command processing unit 2, storage command processing unit 2, storage media management unit 2, and media interface controller 2. Control unit 2 can be coupled to one or more NVM chips, for example... Figure 2 As shown, the control unit 2 is coupled to four NVM chips. The number of NVM chips coupled to the control unit 2 may be equal to or different from the number of NVM chips coupled to the control unit 1; this application does not impose any restrictions on this.

[0111] The storage device processes I / O commands sent by the host through control unit 1 and control unit 2. For example, control unit 1 and control unit 2 can both be coupled to the host, or they can be coupled to the same host or different hosts. Control unit 1 and control unit 2 respectively receive I / O commands from the host they are coupled to and process the received I / O commands. Alternatively, only one of control unit 1 and control unit 2 can be coupled to the host to receive I / O commands sent by the host. Control unit 1 and control unit 2 communicate with each other through an inter-chip communication link to collaboratively process the I / O commands sent by the host. The inter-chip communication link is, for example, a die-to-die link. Commonly used inter-chip interconnects include communication links based on the UCIe (Universal Chipplet Interconnect Express) protocol, NVLink, and EMIB (Embedded Multi-die Interconnect Bridge).

[0112] In a storage device where one control unit is coupled to the host and the other is not, the host-coupled control unit will be referred to as the master control unit, and the uncoupled control unit as the slave control unit. In this case, the master and slave control units cooperate to process I / O commands sent by the host. For example, if the master control unit receives an I / O command from the host and distributes the processing work between the master and slave control units, they can work together to process the I / O command.

[0113] It should be understood that, depending on different needs, more control components can be set in the storage device, and this application is not limited to such... Figure 2 The diagram shows two control units configured in the storage device. Regardless of the number of control units configured in the storage device, as long as the method of processing IO commands through the cooperation of multiple control units is implemented using the scheme provided in this application embodiment, it is within the protection scope of this application embodiment and is not limited herein.

[0114] Figure 3 This illustration shows a schematic diagram of the structure in the storage device provided in this application, where the control component is coupled to the host.

[0115] For example, such as Figure 3As shown, control unit 1 is coupled to the host via host interface 1, while control unit 2 is not coupled to the host. Since control unit 2 is not coupled to the host, it cannot interact with the host via its host interface 2; therefore, host interface 2 in control unit 2 will not function. To enable control unit 1 and control unit 2 to collaboratively process I / O commands, control unit 2 will participate in part of the I / O command processing. For example, the storage command processing unit 2 in control unit 2 is coupled to the host command processing unit 1 in control unit 1, and control unit 2 participates in processing some storage commands corresponding to the I / O commands, as well as the corresponding media interface commands and storage media access commands.

[0116] Control unit 1 receives IO commands conforming to the NVMe protocol sent by the host through host interface 1 and sends the IO commands to host command processing unit 1. Host command processing unit 1 generates one or more storage commands based on the IO commands and assigns the generated one or more storage commands to storage command processing unit 1 and storage command processing unit 2. This distributes the processing of the storage commands corresponding to the IO commands and subsequent related work to the two control units, which then work together to complete the processing of the storage commands, media interface commands, and storage media access commands corresponding to the IO commands.

[0117] The storage device in this application embodiment uses two control components to collaboratively process IO commands conforming to the NVMe protocol in order to access the NVM chip, thereby achieving the requirements of large capacity and high performance.

[0118] Figure 3 As can be seen, in this embodiment, all units in control component 1 participate in the operation, while only the storage command processing unit, storage media management unit, and media interface controller in control component 2 participate in the operation. Operations prior to the storage command are handled by control component 1; control component 2 does not participate in operations prior to storage command processing, but only in the operation from storage command processing to accessing the NVM chip.

[0119] Optionally, Figure 3 There is an inter-chip communication link between the control unit 1 and the control unit 2 shown. The control unit 1 communicates with the control unit 2 through the inter-chip communication link. For example, the host command processing unit 1 in the control unit 1 sends a storage command to the storage command processing unit 2 in the control unit 2 through the inter-chip communication link.

[0120] In an optional embodiment, the host command processing unit 1 of the main control unit generates one or more storage commands based on the logical address range indicated by the IO command, with each logical address corresponding to one storage command. Then, the host command processing unit of the main control unit assigns the one or more storage commands corresponding to the IO command to the storage command processing unit 1 in the main control unit and the storage command processing unit 2 in the slave control unit for processing, based on the logical address indicated by the storage command.

[0121] The following is combined with Figure 3 Taking the IO command sent by the host as an NVMe write command as an example, this describes the process of the master control unit and the slave control unit 2 working together to process the IO command from the host.

[0122] Process (1): The host interface 1 of the control unit 1 receives the NVMe write command sent by the host and sends the NVMe write command to the host command processing unit 1.

[0123] Process (2): Host command processing unit 1 parses the received NVMe write command and generates one or more storage commands according to the logical address range indicated by the NVMe write command. Each logical address corresponds to one storage command. For example, if the logical address range indicated by the NVMe write command is LBA0-LBA100, host command processing unit 1 generates 101 storage commands according to the NVMe write command. Host command processing unit 1 then assigns each storage command to either storage command processing unit 1 or storage command processing unit 2 for processing according to the logical address indicated by each storage command.

[0124] Process (3-1): The storage command processing unit 1 parses the received storage command, allocates a physical address to the logical address indicated by the storage command, and generates a media interface command based on the physical address corresponding to the logical address.

[0125] Process (4-1): The storage command processing unit 1 sends the media interface command to the media interface controller 1.

[0126] Process (5-1): The media interface controller 1 generates a corresponding storage media access command based on the received media interface command, accesses the NVM chip coupled to the control unit 1 based on the storage media access command, and writes data to the NVM chip.

[0127] Process (3-2): The storage command processing unit 2 parses the received storage command, allocates a physical address to the logical address indicated by the storage command, and generates a media interface command for the physical address corresponding to the logical address.

[0128] Process (4-2): The storage command processing unit 2 sends the media interface command to the media interface controller 2.

[0129] Process (5-2): The media interface controller 2 generates a corresponding storage media access command based on the received media interface command, and accesses the NVM chip coupled to the access control unit 2 based on the storage media access command, and writes data to the NVM chip.

[0130] Optionally, in response to completing the processing of a storage command assigned by the host command processing unit 1, the storage command processing unit 1 sends a storage command processing completion message to the host command processing unit 1. Similarly, in response to completing the processing of a storage command assigned by the host command processing unit 1, the storage command processing unit 2 sends a storage command processing completion message to the host command processing unit 1.

[0131] In control unit 1, storage media management unit 1 manages and maintains FTL table 1, and in control unit 2, storage media management unit 2 manages and maintains FTL table 2. Optionally, FTL table 1 and FTL table 2 record and manage the physical addresses corresponding to different logical addresses. FTL table 1 records and manages the physical addresses corresponding to the logical addresses indicated by storage commands sent from host command processing unit 1 to storage command processing unit 1, and FTL table 2 records and manages the physical addresses corresponding to the logical addresses indicated by storage commands sent from host command processing unit 1 to storage command processing unit 2. In another optional embodiment, FTL table 1 and FTL table 2 can record the physical addresses corresponding to the same logical addresses, and both FTL table 1 and FTL table 2 record the physical addresses corresponding to all logical addresses indicated by IO commands.

[0132] Optionally, control unit 1 and control unit 2 share the cache of the storage device, such as DRAM. The host command processing unit 1 of control unit 1 generates a DMA command based on the received NVMe write command, and performs an operation to move the data indicated by the NVMe write command from the host to the storage device cache, such as DRAM, according to the DMA command. The process of host command processing unit 1 generating the DMA command and moving the data can be found in Chinese Patents 202110746142.2 or 202310788448.3, and will not be elaborated here. In response to the data being moved to DRAM as indicated by the NVMe write command, host command processing unit 1 generates one or more storage commands corresponding to the data. Media interface controller 1 and media interface controller 2 respectively write the data in DRAM to the NVM chip based on the received media interface commands. In response to the completion of the NVMe write command processing, host command processing unit 1 sends an NVMe write command processing completion message to the host through host interface 1.

[0133] Figure 4 A schematic diagram of the host command processing unit 1 allocating storage commands according to an embodiment of this application is shown.

[0134] For example, such as Figure 4 As shown, host command processing unit 1 alternately sends storage commands to storage command processing unit 1 and storage command processing unit 2. For example, if the logical address range indicated by the NVMe write command is LBA51-LBA71, 21 storage commands are generated based on this NVMe write command. Host command processing unit 1 then alternately allocates these 21 storage commands to storage command processing unit 1 and storage command processing unit 2. For instance, allocation begins with storage command processing unit 1, assigning storage commands indicating LBA51 to storage command processing unit 1, storage commands indicating LBA52 to storage command processing unit 2, storage commands indicating LBA53 to storage command processing unit 1, storage commands indicating LBA54 to storage command processing unit 2, and so on, until all storage commands have been allocated.

[0135] In response to receiving a storage command from host command processing unit 1, storage command processing unit 1 and storage command processing unit 2 allocate physical addresses for the logical addresses indicated by the storage commands and record the allocated physical addresses in the corresponding FTL table entries. For example, in response to receiving a storage command indicating LBA51, storage command processing unit 1 determines the corresponding entry 0 in FTL table 1 based on LBA51; allocates a physical address for LBA51 and stores the physical address corresponding to LBA51 in entry 0 of FTL table 1. In response to receiving a storage command indicating LBA53, storage command processing unit 1 determines the corresponding entry 1 in FTL table 1 based on LBA53; allocates a physical address for LBA53 and stores the physical address corresponding to LBA53 in entry 1 of FTL table 1. This process continues, recording the physical addresses corresponding to the logical addresses indicated by all storage commands allocated by host command processing unit 1 to storage command processing unit 1 in entries of FTL table 1, with each entry recording the physical address corresponding to one logical address. Similarly, the physical addresses corresponding to the logical addresses indicated by all storage commands assigned by the host command processing unit 1 to the storage command processing unit 2 are recorded in the entries of FTL table 2, with each entry recording the physical address corresponding to one logical address. For example, in response to receiving a storage command indicating LBA52, the storage command processing unit 2 determines the corresponding entry 0 of FTL table 2 based on LBA52; allocates a physical address for LBA52, and stores the physical address corresponding to LBA52 in entry 0 of FTL table 2. In response to receiving a storage command indicating LBA54, the storage command processing unit 2 determines the corresponding entry 1 of FTL table 2 based on LBA54; allocates a physical address for LBA54, and stores the physical address corresponding to LBA54 in entry 1 of FTL table 2.

[0136] In an optional embodiment, host command processing unit 1 continuously sends a specified number of storage commands to storage command processing unit 1 or storage command processing unit 2, wherein the sum of the number of storage commands sent to storage command processing unit 1 and the number of storage commands sent to storage command processing unit 2 is equal to the number of storage commands corresponding to the NVMe write commands. For example, host command processing unit 1 generates P storage commands based on NVMe write commands, continuously sends Q storage commands to storage command processing unit 1, and then continuously sends (PQ) storage commands to storage command processing unit 2, where P is an integer greater than 1, and Q is an integer greater than or equal to 1 and Q is less than P. If the NVMe write commands correspond to 100 storage commands, host command processing unit 1 sends the first 50 generated storage commands to storage command processing unit 1 and the last 50 generated storage commands to storage command processing unit 2. In another optional embodiment, host command processing unit 1 allocates storage commands to storage command processing unit 1 and storage command processing unit 2 according to the logical address range corresponding to the NVMe write commands. If the logical address range indicated by the NVMe write command is LBAn-LBAk, host command processing unit 1 will assign storage commands with logical addresses in [LBAn, LBAm] to storage command processing unit 2, and will assign storage commands with logical addresses in [LBA(m+1), LBAk] to storage command processing unit 2. Here, n, m, and k are all integers, and n... <m<k。

[0137] For example, such as Figure 5 As shown, host command processing unit 1 receives NVMe write command 1, where the logical address range indicated by NVMe write command 1 is [LBA0, LBA200]. Based on this NVMe write command 1, multiple storage commands are generated. For each storage command, if the logical address indicated by the storage command is within [LBA0, LBA100], the storage command is assigned to storage command processing unit 1, and the physical address assigned to the logical address within [LBA0, LBA100] is recorded in the entry of FTL table 1. If the logical address indicated by the storage command is within [LBA101, LBA200], the storage command is assigned to storage command processing unit 2, and the physical address assigned to the logical address within [LBA101, LBA200] is recorded in the entry of FTL table 2. For example, host command processing unit 1 assigns a storage command with logical address LBA45 to storage command processing unit 1, and assigns a storage command with logical address LBA170 to storage command processing unit 2.

[0138] In an optional embodiment, host command processing unit 1 allocates storage commands to storage command processing unit 1 and storage command processing unit 2 based on the parity of the logical address indicated by the storage command. For example... Figure 6As shown, the logical address range indicated by the NVMe write command is LBA40-LBA100. The host command processing unit 1 assigns storage commands with even logical addresses (such as LBA40, LBA42, LBA44, ..., LBA100) to the storage command processing unit 2, and assigns storage commands with odd logical addresses (such as LBA41, LBA43, LBA45, ..., LBA99) to the storage command processing unit 2. The physical addresses assigned to storage commands with even logical addresses (such as LBA40, LBA42, LBA44, ..., LBA100) are recorded in the entries of FTL table 1, and the physical addresses assigned to storage commands with odd logical addresses (such as LBA41, LBA43, LBA45, ..., LBA99) are recorded in FTL table 2.

[0139] Optionally, the host command processing unit 1 may also assign storage commands with odd logical addresses (such as LBA41, LBA43, LBA45, ..., LBA99) to the storage command processing unit 1, and assign storage commands with even logical addresses (such as LBA40, LBA42, LBA44, ..., LBA100) to the storage command processing unit 1.

[0140] The process of the master control unit and slave control unit working together to process NVMe read commands is similar to the process of processing NVMe write commands. The following section will combine... Figure 7 Please provide an explanation.

[0141] like Figure 7 As shown, the process of the master control unit and the slave control unit working together to process NVMe read commands includes:

[0142] Process (1-1): The host interface 1 of the control unit 1 receives the NVMe read command sent by the host and sends the NVMe read command to the host command processing unit 1.

[0143] Process (1-2): The host command processing unit 1 parses the received NVMe read command, generates one or more storage commands according to the LBA range indicated by the NVMe read command (the storage commands generated according to the NVMe read command are different from the storage commands generated according to the NVMe write command), and assigns one or more storage commands to the storage command processing unit 1 and the storage command processing unit 2.

[0144] The host command processing unit 1 assigns storage commands to storage command processing unit 1 and storage command processing unit 2.

[0145] The strategy for host command processing unit 1 to allocate storage commands corresponding to NVMe read commands is consistent with the strategy for host command processing unit 1 to allocate storage commands corresponding to NVMe write commands. For example, storage commands corresponding to NVMe write commands and NVMe read commands that indicate the same logical address should be allocated to the same storage command processing unit in the same control unit. For instance, when host command processing unit 1 processes an NVMe write command, it allocates the storage command corresponding to LBA0 to storage command processing unit 1 in control unit 1; when reading data corresponding to LBA0, it also allocates its corresponding storage command to storage command processing unit 1. As another example, when host command processing unit 1 processes an NVMe write command, it allocates storage commands with even-numbered logical addresses to storage command processing unit 1 and storage commands with odd-numbered logical addresses to storage command processing unit 2. Then, when host command processing unit 1 processes an NVMe read command, it allocates storage commands with even-numbered logical addresses to storage command processing unit 1 and storage commands with odd-numbered logical addresses to storage command processing unit 2.

[0146] For example, in response to completing the processing of a storage command assigned by the host command processing unit 1, the storage command processing unit 1 sends a storage command processing completion message to the host command processing unit 1. Similarly, in response to completing the processing of a storage command assigned by the host command processing unit 1, the storage command processing unit 2 sends a storage command processing completion message to the host command processing unit 1.

[0147] Process (1-3): Storage command processing unit 1 generates a media interface command based on the received storage command and sends the media interface command to media interface controller 1. Storage command processing unit 2 generates a media interface command based on the received storage command and sends the media interface command to media interface controller 2.

[0148] Process (1-4): Media interface controller 1 accesses the NVM chip coupled to control component 1 according to the received media interface command, reads the corresponding data from the NVM chip, and stores the read data in DRAM. Media interface controller 2 accesses the NVM chip coupled to control component 2 according to the received media interface command, reads the corresponding data from the NVM chip, and stores the read data in DRAM.

[0149] Process (1-5): The host command processing unit 1 moves the data stored in the DRAM by the media interface controller 1 and the media interface controller 2 to the host. The process of the host command processing unit 1 moving the data stored in the DRAM to the host can be found in Chinese Patents 202110746144.1 or 202310788454.9, and will not be described in detail here.

[0150] Process (1-6): In response to the completion of the NVMe read command processing, host command processing unit 1 sends an NVMe read command processing completion message to the host.

[0151] Figure 8 A schematic diagram illustrating the structure of the control component coupled to the host in a storage device according to another embodiment of this application is shown.

[0152] like Figure 8 As shown, control unit 3 is coupled to the host via host interface 3, while control unit 4 is not coupled to the host. Control unit 3 receives I / O commands sent by the host, and control unit 3 and control unit 4 collaboratively process the I / O commands received by control unit 3 through an inter-chip communication link. In control unit 4, host interface 4, host command processing unit 4, storage media management unit 4, and storage command processing unit 4 are not operational. Figure 8 (The shaded areas represent inactive functional units within the control unit). To facilitate collaborative processing of I / O commands by control units 3 and 4, in an optional embodiment, an inter-chip communication link couples the media interface controller 4 in control unit 4 to control unit 3 as a bus device. A bus is a set of common communication lines that enable information transmission between multiple control units. The media interface controller 4 in control unit 4 is connected to the bus, acting as a bus device coupled to control unit 3.

[0153] In some alternative embodiments, the inter-chip communication link couples the media interface controller 4 to the storage command processing unit 3 in the control unit 3, and receives media interface commands sent by the storage command processing unit 3. The control unit 4 participates in the processing of a portion of the media interface commands corresponding to the IO commands and the corresponding storage media access commands.

[0154] Control unit 3 receives I / O commands sent by the host through host interface 3 and sends the I / O commands to host command processing unit 3. Host command processing unit 3 generates one or more storage commands based on the I / O commands and sends the generated one or more storage commands to storage command processing unit 3. Storage command processing unit 3 generates one or more media interface commands based on the received storage commands and assigns one or more media interface commands to media interface controller 3 and media interface controller 4, so that the processing work of the media interface commands corresponding to the I / O commands is distributed to the two control units, and the two control units cooperate to process the I / O commands from the host. In this embodiment, all operations before processing the media interface commands are completed by control unit 3. Control unit 4 does not participate in the operations before processing the media interface commands, but only participates in the operation of the media interface commands and the operation of accessing the NVM chip.

[0155] The media interface command indicates a physical address, which includes information such as the LUN to be accessed and the physical block. When the storage command processing unit 3 distributes media interface commands to the media interface controller 3 and media interface controller 4, it can determine the corresponding LUN based on the physical address indicated by each media interface command, and then determine the NVM chip it resides in based on the LUN. The storage command processing unit 3, based on the NVM chip to be accessed by the media interface command, distributes each media interface command to the media interface controller of the corresponding control unit coupled to the NVM chip. For example... Figure 8 As shown, control unit 1 is coupled to NVM0 and NVM1. NVM1 includes LUN0 and LUN1. Control unit 2 is coupled to NVM2 and NVM3. NVM2 includes LUN8 and LUN9. If the physical address indicated by media interface command 1 indicates access to LUN0, storage command processing unit 3 sends media interface command 1 to media interface controller 3 in control unit 3. If the physical address indicated by media interface command 2 indicates access to LUN9, storage command processing unit 3 sends media interface command 2 to media interface controller 4 in control unit 4.

[0156] Media interface controller 3 and media interface controller 4 generate storage media access commands based on the received media interface commands, and access their coupled NVM chips according to their respective storage media access commands. Optionally, media interface controller 3 and media interface controller 4 can process the corresponding media interface commands in parallel without interfering with each other. In response to completing the processing of the received media interface command, media interface controller 3 sends a media interface command processing completion message to storage command processing unit 1. Media interface controller 4, in response to completing the processing of the received media interface command, sends a media interface command processing completion message to storage command processing unit 1. Storage command processing unit 1 generates a storage command processing completion message based on the media interface command processing completion message and sends a storage command processing completion message to host command processing unit 1.

[0157] The storage device's cache, such as DRAM, is coupled to control unit 3, while control unit 4 is not directly connected to DRAM. When processing media interface commands, media interface controller 4 accesses DRAM through the inter-chip communication link to obtain data that needs to be transferred between DRAM and NVM chips.

[0158] exist Figure 8In the illustrated embodiment, the storage medium management unit 3 in the control unit 3 manages and maintains the FTL table 3. The FTL table 3 records and manages the physical addresses corresponding to the logical addresses indicated by the storage commands received by the storage command processing unit 3. Since the storage command processing unit 3 and the storage medium management unit 4 in the control unit 4 are not working, the FTL table 3 can record and manage the physical addresses corresponding to the logical addresses in the entire logical address space. That is, the FTL table 3 manages the mapping relationship between logical addresses and physical addresses in the entire logical address space.

[0159] The following is combined with Figure 8 Taking the IO command sent by the host as an NVMe write command as an example, the process of control unit 3 and control unit 4 working together to process the NVMe write command from the host is described.

[0160] Process (1): The control unit 3 receives the NVMe write command sent by the host through the host interface 3 and sends the NVMe write command to the host command processing unit 3.

[0161] Process (2): The host command processing unit 3 parses the received NVMe write command, generates one or more storage commands according to the logical address range indicated by the NVMe write command, and sends the generated one or more storage commands to the storage command processing unit 3.

[0162] Process (3): The storage command processing unit 3 parses the received storage command, allocates a physical address to the logical address indicated by the storage command, and records the allocated physical address in the FTL table 3.

[0163] Process (4): The storage command processing unit 3 generates a media interface command based on the physical address corresponding to the logical address. The storage command processing unit 3 then assigns the media interface command to the media interface controller 3 or the media interface controller 4 based on the physical address indicated by the media interface command.

[0164] Process (5): The media interface controller 3 generates a corresponding storage media access command based on the received media interface command, and writes data to the NVM chip coupled to the access control unit 3 based on the storage media access command. The media interface controller 4 generates a corresponding storage media access command based on the received media interface command, and writes data to the NVM chip coupled to the access control unit 4 based on the storage media access command.

[0165] In this process, host command processing unit 1 moves the data indicated by the NVMe write command from the host to the cache of the storage device, such as DRAM. Media interface controller 3, based on the received media interface command, moves the data indicated by the media interface command from the DRAM to the NVM chip coupled to control unit 3. Media interface controller 4 accesses the DRAM via an inter-chip communication link and moves the data indicated by the received media interface command from the DRAM to the NVM chip coupled to control unit 4. In response to the completion of the NVMe write command processing, host command processing unit 1 sends an NVMe write command processing completion message to the host via host interface 3.

[0166] For example, such as Figure 8 In the process (3) shown, the storage command processing unit 3 allocates physical addresses to the logical addresses indicated by the NVMe write commands in an alternating manner. For example, the storage command processing unit 3 allocates the physical address on the NVM chip coupled to the control unit 3 to the logical address indicated by the first storage command, the storage command processing unit 3 allocates the physical address on the NVM chip coupled to the control unit 4 to the logical address indicated by the second storage command, and so on.

[0167] As another example, the storage command processing unit 3 allocates the corresponding physical address to the logical address according to the parity of the logical address. For example, it allocates the physical address on the NVM chip coupled to the control unit 3 to the odd logical address, and allocates the physical address on the NVM chip coupled to the control unit 4 to the even logical address, and so on.

[0168] As another example, the storage command processing unit 3 can also allocate physical addresses to the logical addresses indicated by NVMe write commands according to page striping, allocating the physical address corresponding to a physical page in a page stripe to the logical addresses indicated by one or more storage commands. When allocating physical addresses according to page striping, if a page stripe is not fully allocated, the physical addresses of physical pages in other page stripes will not be allocated to the logical addresses indicated by the received storage commands. For example, the storage space size of each page stripe is equal to the storage space size represented by 100 LBAs indicated by storage commands, and each page stripe corresponds to 100 storage commands. If the number of storage commands that allocate physical addresses for the logical addresses indicated by the received storage commands from a page stripe, such as page stripe 0, is less than 100, it indicates that page stripe 0 has not been fully allocated. If storage command processing unit 3 receives another storage command, such as storage command 5, it will still allocate the physical addresses corresponding to the unallocated physical pages in page stripe 0 to the logical addresses indicated by storage command 5. If the number of storage commands that allocate physical addresses for the logical addresses indicated by the received storage commands from page stripe 0 is equal to 100, it indicates that the page stripe has been fully allocated. If storage command processing unit 3 receives another storage command, such as storage command 6, it will allocate physical addresses for the logical addresses indicated by storage command 6 from a new page stripe, such as page stripe 2.

[0169] Figure 9 This application provides a schematic diagram illustrating the allocation of physical addresses according to page stripes.

[0170] For example, such as Figure 9 As shown, the NVM chip coupled to the control unit in the storage device includes LUN0 to LUN15. A page stripe consists of physical pages from LUN0 to LUN15. For example, page stripe 0 consists of 15 physical pages (P0-0, P0-1, P0-2…P0-14, P0-15) from LUN0 to LUN15; where P0-0, P0-1, P0-2…P0-14 are used to store user data, and P0-15 is used to store parity data. If the size of each physical page in the page stripe is equal to the size of the storage unit represented by the LBA indicated by a storage command, such as… Figure 9 Page stripe 0 and page stripe 2, as shown, each correspond to 15 memory commands. For example, the physical addresses corresponding to physical pages P0-0, P0-1, P0-2…P0-14 in page stripe 0 will be assigned to the logical addresses indicated by the 15 memory commands, respectively. Memory command processing unit 3 (e.g., Figure 8(As shown) Starting from page stripe 0, physical addresses are allocated for received memory commands. In response to the first memory command (e.g., memory command 1 indicating LBA1), the physical address of physical page P0-0 in page stripe 0 is allocated to LBA1; in response to the second memory command (e.g., memory command 2 indicating LBA3), the physical address of physical page P1-0 in page stripe 0 is allocated to LBA3; in response to the third memory command (e.g., memory command 3 indicating LBA10), the physical address of physical page P2-0 in page stripe 0 is allocated to LBA10; and so on. When memory command processing unit 3 receives the fifteenth memory command (e.g., memory command 15 indicating LBA2), the physical address of physical page P14-0 in page stripe 0 is allocated to LBA2, at which point page stripe 0 is fully allocated. When memory command processing unit 3 receives the sixteenth memory command (e.g., memory command 16 indicating LBAm), it needs to allocate physical addresses for LBAm from other page stripes, such as allocating the physical address of physical page P2-0 in page stripe 2 to LBAm, and so on.

[0171] See also Figure 8 The storage command processing unit 3 allocates physical addresses for the logical addresses indicated by storage commands according to page stripes. This requires constructing page stripes from physical pages of LUNs on the NVM chips coupled to the two control units. The page stripes span the NVM chips coupled to the two control units. For example, the constructed page stripes include physical pages of LUNs on both the NVM chips coupled to control unit 3 and control unit 4.

[0172] Figure 10 This illustrates the construction method of the page strip provided in the embodiments of this application. For example... Figure 10 As shown, control unit 3 couples NVM0 and NVM1, and control unit 4 couples NVM2 and NVM3; wherein, NVM0 includes logic units LUN0 and LUN1, NVM1 includes logic units LUN2 and LUN3, NVM2 includes logic units LUN4 and LUN5, and NVM4 includes logic units LUN6 and LUN7. Figure 10Page stripes are constructed from physical pages of LUNs on a portion of the NVM chip coupled to control unit 3 and physical pages of LUNs on a portion of the NVM chip coupled to control unit 4. For example, page stripe 0 includes physical pages (P0-0, P0-1) from NVM0 coupled to control unit 3 and physical pages (P0-4, P0-5) of LUNs on NVM2 coupled to control unit 4. Page stripe 1 includes physical pages (P0-2, P0-3) from NVM1 coupled to control unit 3 and physical pages (P0-6, P0-7) from NVM3 coupled to control unit 4. Page stripe 2 includes physical pages (P1-0, P1-1) from NVM0 coupled to control unit 3 and physical pages (P1-4, P1-5) from NVM2 coupled to control unit 4. Page stripe 3 includes physical pages (P1-2, P1-3) from NVM1 of coupling control unit 3 and physical pages (P1-6, P1-7) from NVM3 of coupling control unit 4. In page stripe 0, P0-0, P0-1, and P0-4 are used to store user data, and P0-5 is used to store parity data. In page stripe 1, P0-2, P0-3, and P0-6 are used to store user data, and P0-7 is used to store parity data. In page stripe 2, P1-0, P1-1, and P1-4 are used to store user data, and P1-5 is used to store parity data. In page stripe 3, P1-2, P1-3, and P1-6 are used to store user data, and P1-7 is used to store parity data. If the size of each physical page in the page stripe is equal to the size of the storage unit represented by the LBA indicated by a storage command, such as... Figure 10 Page stripes 0-3 as shown each correspond to three storage commands. For example, the physical addresses corresponding to physical pages P0-0, P0-1, and P0-4 in page stripe 0 will be assigned to the logical addresses indicated by the three storage commands, respectively. For instance, host command processing unit 3 receives NVMe write command 1 and NVMe write command 2 sequentially. The logical address range indicated by NVMe write command 1 is LBA20-LBA24, and the logical address range indicated by NVMe write command 2 is LBA30-LBA36. Host command processing unit 3 generates five storage commands based on NVMe write command 1 (e.g., storage command A1, storage command A2, storage command A3, storage command A4, and storage command A5), and generates seven storage commands based on NVMe write command 2 (e.g., storage command B1, storage command B2, storage command B3, storage command B4, storage command B5, storage command B6, and storage command B7). Storage command processing unit 3 allocates physical addresses for the received storage commands starting from page stripe 0. The storage command processing unit 3 allocates physical addresses for the logical addresses indicated by each storage command, for example, in the following manner:

[0173] Allocate the physical address of physical page P0-0 in page stripe 0 for LBA20 indicated by storage command A1; allocate the physical address of physical page P0-1 in page stripe 0 for LBA21 indicated by storage command A2; allocate the physical address of physical page P0-4 in page stripe 0 for LBA22 indicated by storage command A3; allocate the physical address of physical page P0-2 in page stripe 1 for LBA23 indicated by storage command A4; allocate the physical address of physical page P0-3 in page stripe 1 for LBA24 indicated by storage command A5; allocate the physical address of physical page P0-6 in page stripe 1 for LBA30 indicated by storage command B1. Allocate the physical address of physical page P1-0 in page stripe 2 for LBA31 indicated by storage command B2; allocate the physical address of physical page P1-1 in page stripe 2 for LBA32 indicated by storage command B3; allocate the physical address of physical page P1-4 in page stripe 2 for LBA33 indicated by storage command B4; allocate the physical address of physical page P1-2 in page stripe 3 for LBA34 indicated by storage command B5; allocate the physical address of physical page P1-3 in page stripe 3 for LBA35 indicated by storage command B6; allocate the physical address of physical page P1-6 in page stripe 3 for LBA36 indicated by storage command B7.

[0174] Storage command processing unit 3 allocates physical addresses for multiple storage commands corresponding to NVMe write command 1 and NVMe write command 2 from page stripes 0-3. That is, it allocates physical addresses for multiple storage commands corresponding to NVMe write command 1 and NVMe write command 2 from the physical pages of the LUN on the NVM0 chip of coupled control unit 3 and the physical pages of the LUN on the NVM2 chip of coupled control unit 4. This distributes the multiple media interface commands corresponding to NVMe write command 1 and NVMe write command 2 to the media interface controller 3 in control unit 3 and the media interface controller in control unit 4, and writes the data indicated by NVMe write command 1 and NVMe write command 2 to the NVM0 chip coupled to control unit 3 and the NVM2 chip coupled to control unit 4.

[0175] Figure 11 This illustrates another method of constructing a strip provided in an embodiment of this application. For example... Figure 11 As shown, the NVM chip coupled to control unit 3 and control unit 4 is... Figure 10 Similarly, I won't elaborate further here. Figure 11Page stripes are constructed by combining the physical pages of the LUNs on all NVM chips coupled to control unit 3 with the physical pages of the LUNs on all NVM chips coupled to control unit 4. For example, page stripe 0 is constructed by combining the physical pages (P0-0, P0-1, P0-2, P0-3) of the LUNs on NVM0-NVM1 chips coupled to control unit 3 with the physical pages (P0-4, P0-5, P0-6, P0-7) of the LUNs on NVM2-NVM3 chips coupled to control unit 4. Page stripe 2 is constructed by combining the physical pages (P2-0, P2-1, P2-2, P2-3) of the LUNs on NVM0-NVM1 chips coupled to control unit 3 with the physical pages (P2-4, P2-5, P2-6, P2-7) of the LUNs on NVM2-NVM3 chips coupled to control unit 4. For example, host command processing unit 3 receives NVMe write command 3, NVMe write command 4, and NVMe write command 5 successively. NVMe write command 3 indicates a logical address range of LBA40-LBA44, NVMe write command 4 indicates a logical address range of LBA50-LBA56, and NVMe write command 5 indicates a logical address range of LBA60-LBA61. Host command processing unit 3 generates 5 storage commands based on NVMe write command 3 (e.g., storage commands C1, C2, C3, C4, and C5), 7 storage commands based on NVMe write command 4 (e.g., storage commands D1, D2, D3, D4, D5, D6, and D7), and 2 storage commands based on NVMe write command 5 (e.g., storage commands E1 and E7). Storage command processing unit 3 allocates physical addresses to the logical addresses indicated by each storage command, for example, in the following manner:

[0176] Allocate the physical address of physical page P0-0 in page stripe 0 for LBA40 indicated by storage command C1; allocate the physical address of physical page P0-1 in page stripe 0 for LBA41 indicated by storage command C2; allocate the physical address of physical page P0-2 in page stripe 0 for LBA42 indicated by storage command C3; allocate the physical address of physical page P0-3 in page stripe 0 for LBA43 indicated by storage command C4; allocate the physical address of physical page P0-4 in page stripe 0 for LBA44 indicated by storage command C5; allocate the physical address of physical page P0-5 in page stripe 0 for LBA50 indicated by storage command D1; allocate the physical address of physical page P0-6 in page stripe 0 for LBA51 indicated by storage command D2. Allocate the physical address of physical page P2-0 in page stripe 2 for LBA52 as indicated by storage command D3; allocate the physical address of physical page P2-1 in page stripe 2 for LBA53 as indicated by storage command D4; allocate the physical address of physical page P2-2 in page stripe 2 for LBA54 as indicated by storage command D5; allocate the physical address of physical page P2-3 in page stripe 2 for LBA55 as indicated by storage command D6; allocate the physical address of physical page P2-4 in page stripe 2 for LBA56 as indicated by storage command D7; allocate the physical address of physical page P2-5 in page stripe 2 for LBA60 as indicated by storage command E1; allocate the physical address of physical page P2-6 in page stripe 2 for LBA61 as indicated by storage command E2.

[0177] Storage command processing unit 3 allocates physical addresses for multiple storage commands corresponding to NVMe write command 3, NVMe write command 4, and NVMe write command 5 from page stripe 0 and page stripe 2. That is, it allocates physical addresses for multiple storage commands corresponding to NVMe write command 3, NVMe write command 4, and NVMe write command 5 from the physical pages of the LUNs of all NVM chips in the coupling control unit 3 and all NVM chips in the coupling control unit. This distributes multiple media interface commands corresponding to NVMe write command 3, NVMe write command 4, and NVMe write command 5 to the media interface controller 3 in the control unit 3 and the media interface controller in the control unit 4. Then, it writes the data indicated by NVMe write command 3, NVMe write command 4, and NVMe write command 5 to the NVM0 chip and NVM1 chip coupled to the control unit 3 and the NVM2 chip and NVM4 chip coupled to the control unit 4.

[0178] Depend on Figure 10 and Figure 11It is understood that by constructing page stripes from the physical pages of the LUNs on the NVM chips coupled to control unit 3 and NVM chips coupled to control unit 4, storage command processing unit 3 can allocate physical addresses from the page stripes of the LUNs on the NVM chips coupled to control unit 3 and NVM chips coupled to control unit 4 for receiving, for example, logical addresses indicated by one or more storage commands. This allows the generated media interface commands to be allocated to the media interface controller 3 in control unit 3 and the media interface controller 4 in control unit 4, thereby enabling the processing of one or more NVMe commands to be distributed between control unit 3 and control unit 4, achieving load balancing.

[0179] The process by which control unit 3 and control unit 4 collaboratively process NVMe read commands is similar to the process of processing NVMe write commands. For example... Figure 12 As shown, the process by which control unit 3 and control unit 4 collaboratively process NVMe read commands includes:

[0180] Process (1): The host interface 3 of the control unit 3 receives the NVMe read command sent by the host and sends the NVMe read command to the host command processing unit 3.

[0181] Process (2): The host command processing unit 3 parses the received NVMe read command, generates one or more storage commands according to the logical address range indicated by the NVMe read command, and sends the generated one or more storage commands to the storage command processing unit 3.

[0182] Process (3): The storage command received by the storage command processing unit 3 is processed by querying the FTL table (e.g., ...). Figure 12 The FTL table 3 shows the physical address corresponding to the logical address indicated by the storage command, and a media interface command is generated based on this physical address. The storage command processing unit 3 assigns the media interface command to the media interface controller 3 or the media interface controller 4 based on the physical address indicated by the media interface command.

[0183] The storage command processing unit 3 determines the LUN corresponding to the physical address indicated by the media interface command, identifies the NVM chip where the LUN resides, and then determines the media interface controller coupled to the NVM chip. The storage command processing unit 3 assigns media interface commands corresponding to NVMe write commands and NVMe read commands that indicate the same physical address to the media interface controller within the same control unit for processing. For example, when processing an NVMe write command, the storage command processing unit 3 assigns the media interface command for physical address PPA0 to the media interface controller 3 within the control unit 3; when reading data corresponding to PPA0, it also assigns the corresponding media interface command to the media interface controller 4.

[0184] Process (4): The media interface controller 3 generates a corresponding storage media access command based on the received media interface command, accesses the NVM chip coupled to the access control unit 3 based on the storage media access command, reads the corresponding data from the NVM chip, and stores the read data in DRAM. The media interface controller 4 generates a corresponding storage media access command based on the received media interface command, accesses the NVM chip coupled to the access control unit 4 based on the storage media access command, reads the corresponding data from the NVM chip, and stores the read data in DRAM through the inter-chip communication link.

[0185] Process (5): The host command processing unit 3 moves the data stored in the DRAM of the media interface controller 3 and the media interface controller 4 to the host.

[0186] The host command processing unit 3 moves the data indicated by the NVMe read command from the cache of the storage device to the host. In response to the completion of the NVMe read command processing, it sends an NVMe read command processing completion message to the host through the host interface 3.

[0187] Figures 3-12 In the illustrated embodiment, only one control component (such as control component 1 or control component 3) is coupled to the host, while other control components (such as control component 2 or control component 4) are not coupled to the host. In other alternative embodiments, both control components are coupled to the host. The two control components can be coupled to the same host or to different hosts. Figure 13 As shown, the storage device includes a control unit 5 and a control unit 6. Control unit 5 is coupled to host 1 and receives I / O commands (e.g., NVMe write commands and NVMe read commands) from host 1. Control unit 6 is coupled to host 2 and receives I / O commands (e.g., NVMe write commands and NVMe read commands) from host 2. The I / O commands sent from host 1 to control unit 5 and the I / O commands sent from host 2 to control unit 6 are different I / O commands. Control unit 5 and control unit 6 process their respective received I / O commands independently, or they can process the received I / O commands collaboratively. Host 1 and host 2 can be the same host or different hosts.

[0188] Optionally, there is no inter-chip communication link between control unit 5 and control unit 6. Control unit 5 and control unit 6 independently process their respective received I / O commands. For example, control unit 5 is coupled to host 1 through host interface 5, receives I / O commands sent by host 1, and sends them to host command processing unit 5. Host command processing unit 5 generates one or more storage commands based on the received I / O commands and sends the generated storage commands to storage command processing unit 5. Storage command processing unit 5 generates one or more media interface commands based on the received storage commands and sends the generated media interface commands to media interface controller 5. Media interface controller 5 accesses the NVM chip coupled to control unit 5 based on the received media interface commands. Control unit 6 is coupled to host 2 through host interface 6, receives I / O commands sent by host 2, and sends them to host command processing unit 6. Host command processing unit 6 generates one or more storage commands based on the received I / O commands and sends the generated storage commands to storage command processing unit 6. Storage command processing unit 6 generates one or more media interface commands based on the received storage commands and sends the generated media interface commands to media interface controller 6. The media interface controller 6 accesses the NVM chip coupled to the control unit 6 according to the received media interface command.

[0189] For example, assuming there is no communication link between control unit 5 and control unit 6, and control unit 5 and control unit 6 operate independently, if host 1 sends NVMe write command 1 to control unit 5 through host interface 5, the data indicated by NVMe write command 1 is stored in the NVM chip coupled to control unit 5. When host 1 wants to read the data indicated by NVMe write command 1 from the NVM chip, it sends the corresponding NVMe read command 1 to control unit 5 through host interface 5. Control unit 5 then processes the NVMe read command 1 and reads the data from the NVM chip coupled to control unit 5. When host 1 sends the corresponding NVMe read command 1 to control unit 6 through host interface 6, control unit 6 sends a message to host indicating a data read failure.

[0190] Optionally, the storage media management unit 5 manages and maintains FTL table 5. FTL table 5 records and manages the physical addresses corresponding to the logical addresses indicated by the storage commands sent by the host command processing unit 5 to the storage command processing unit 5. The storage media management unit 6 manages and maintains FTL table 6. FTL table 6 records and manages the physical addresses corresponding to the logical addresses indicated by the storage commands sent by the host command processing unit 6 to the storage command processing unit 6.

[0191] When host 1 and host 2 are the same host, host 1 (or host 2) can alternately send I / O commands to control unit 5 and control unit 6. For example, host 1 (or host 2) sends M I / O commands to control unit 5 through host interface 5, and then sends N I / O commands to control unit 6 through host interface 6. Here, M and N are integers greater than or equal to 1. Optionally, host 1 (or host 2) does not send the same I / O command to both control unit 5 and control unit 6. Again, optionally, both FTL table 5 and FTL table 6 manage and maintain the physical addresses corresponding to logical addresses in the entire logical address space, where the entire logical address space includes the logical address spaces corresponding to all NVM chips coupled by control unit 5 and control unit 6. Therefore, host 1 (or host 2) can access data stored in any physical address managed by the FTL table through host interface 5 or host interface 6.

[0192] In some optional embodiments, an inter-chip communication link exists between control unit 5 and control unit 6, allowing them to collaboratively process received I / O commands. All functional units in control unit 5 participate in processing I / O commands. Functional units in control unit 6 may participate fully or partially in processing I / O commands; for example, the host command processing unit in control unit 6 may not operate, while other functional units operate.

[0193] Optionally, the inter-chip communication link between control unit 5 and control unit 6 includes one or more of the following:

[0194] (1) The inter-chip communication link 1 formed by the coupling of the storage command processing unit 6 and the host command processing unit 5;

[0195] (2) The inter-chip communication link 2 formed by the coupling of the storage command processing unit 5 and the host command processing unit 6;

[0196] (3) The inter-chip communication link 3 formed by the coupling of the host interface 6 and the host command processing unit 5;

[0197] (4) The inter-chip communication link 4 is formed by the coupling of the storage command processing unit 5 and the media interface controller 6.

[0198] Optionally, such as Figure 14AAs shown, the host command processing unit 5 in control component 5 is coupled to the storage command processing unit 6 in control component 6, and there is an inter-chip communication link 1 between control component 5 and control component 6. Control component 5 receives IO commands sent by host 1 through host interface 5 and sends the IO commands to host command processing unit 5. Host command processing unit 5 generates multiple storage commands based on the IO commands, and can send the multiple storage commands corresponding to the IO commands to storage command unit 5 and / or storage command processing unit 6. For example, host command processing unit 5 can assign all storage commands corresponding to the IO commands to storage command processing unit 5; or host command processing unit 5 can assign all storage commands corresponding to the IO commands to storage command processing unit 6; or host command processing unit 5 can assign a portion of the storage commands corresponding to the IO commands to storage command processing unit 5, and assign another portion of the storage commands to storage command processing unit 6 through inter-chip communication link 1.

[0199] like Figure 14B As shown, the host command processing unit 6 in control component 6 is coupled to the storage command processing unit 5 in control component 5, and there is an inter-chip communication link 2 between control component 5 and control component 6. Control component 6 receives IO commands sent by host 2 through host interface 6 and sends the IO commands to host command processing unit 6. Host command processing unit 6 generates multiple storage commands based on the IO commands, and can send the multiple storage commands corresponding to the IO commands to storage command unit 5 and / or storage command processing unit 6. For example, host command processing unit 6 can assign all storage commands corresponding to the IO commands to storage command processing unit 5; or host command processing unit 6 can assign all storage commands corresponding to the IO commands to storage command processing unit 6; or host command processing unit 6 can assign a portion of the storage commands corresponding to the IO commands to storage command processing unit 5, and assign another portion of the storage commands to storage command processing unit 6 through the communication link between host command processing unit 6 and storage command processing unit 6.

[0200] like Figure 14CAs shown, the host command processing unit 5 in control component 5 is coupled to the storage command processing unit 6 in control component 6, and the host command processing unit 6 in control component 6 is also coupled to the storage command processing unit 5 in control component 5. There are both inter-chip communication links 1 and 2 between control component 5 and control component 6. The storage command processing unit 6 in control component 6 is coupled to the host command processing unit 5 in control component 5, and can receive storage commands sent by the host command processing unit 5. For example, control component 5 receives IO command 1 through host interface 5 and sends IO command 1 to host command processing unit 5. Host command processing unit 5 generates multiple storage commands based on IO command 1, allocates some storage commands to storage command processing unit 5, and allocates the remaining storage commands to storage command processing unit 6 through inter-chip communication link 1. Control component 6 receives IO command 2 through host interface 6 and sends IO command 2 to host command processing unit 6. The host command processing unit 6 generates multiple storage commands based on the IO command 2, and allocates a portion of these storage commands to the storage command processing unit 5. The remaining storage commands are allocated to the storage command processing unit 6 via the inter-chip communication link 2. The host command processing unit 5 and host command processing unit 6 can allocate the generated storage commands to each other based on the logical address indicated by the storage command. For example, Figure 14A , Figure 14B as well as Figure 14C The host command processing unit 5 and host command processing unit 6 distribute the storage commands corresponding to the received IO commands to the storage command processing units (storage command processing unit 5 and storage command processing unit 6) in the two control units for collaborative processing. The distribution method can be found in [reference needed]. Figures 3-7 The embodiments shown will not be described in detail here.

[0201] Optionally, the host command processing unit 5 may also assign all storage commands generated according to IO command 1 to either storage command processing unit 5 or storage command processing unit 6. Similarly, the host command processing unit 6 may assign all storage commands generated according to IO command 2 to either storage command processing unit 5 or storage command processing unit 6. The host command processing unit 5 may assign all storage commands generated according to IO command 1 to storage command processing unit 6, allowing the control unit 6 to access the NVM according to the IO commands received by the control unit 5. This ensures that in the event of a failure in the storage command processing unit 5 and / or the media interface controller 5, the IO commands sent by the host can be processed by the storage command processing unit 6 and the media interface controller 6 within the control unit 6. Likewise, the host command processing unit 6 may assign all storage commands generated according to IO command 2 to storage command processing unit 5, allowing the control unit 5 to access the NVM according to the IO commands received by the control unit 6.

[0202] like Figure 14D As shown, the host interface 6 in control unit 6 is coupled to the host command processing unit 5 in control unit 5, and there is an inter-chip communication link 3 between control unit 5 and control unit 6. Control unit 6 can independently process IO commands sent by host 2, or it can distribute all or part of the IO commands sent by host 2 to control unit 5 through the inter-chip communication link 3.

[0203] like Figure 14E As shown, the storage command processing unit 5 in control component 5 is coupled to the media interface controller 6 in control component 6, and there is an inter-chip communication link 4 between control component 5 and control component 6. The storage command processing unit 5 can distribute the generated media interface commands to the media interface controller 6 through the inter-chip communication link 4.

[0204] In some alternative embodiments, when there is an inter-chip communication link between control unit 5 and control unit 6, all functional units in control unit 5 participate in processing I / O commands. In control unit 6, some functional units participate in processing I / O commands, while others do not operate. For example... Figure 15 As shown, the host command processing unit 6 in the control component 6 is not working. For example... Figure 16 As shown, the host command processing unit 6, storage command processing unit 6, and storage medium management unit 6 in the control unit 6 are not working.

[0205] exist Figure 15In the illustrated embodiment, the host interface 6 and storage command processing unit 6 in control component 6 are coupled to the host command processing unit 5 in control component 5. Inter-chip communication link 1 and inter-chip communication link 3 exist simultaneously between control component 5 and control component 6. I / O commands (including NVMe write commands and NVMe read commands) received by control component 5 through host interface 5 and I / O commands (including NVMe write commands and NVMe read commands) received by control component 6 through host interface 6 are both sent to host command processing unit 5. Host command processing unit 5 generates one or more storage commands based on the received I / O commands and allocates these one or more storage commands to storage command processing unit 5 and / or storage command processing unit 6. For example, the strategy for host command processing unit 5 to allocate storage commands to storage command processing unit 5 and storage command processing unit 6 can be referenced. Figures 3-7 The illustrated embodiments will not be described in detail here. When host 1 and host 2 are the same host, for example, control unit 5 and control unit 6 are both coupled to host 1. Since host interface 5 and host interface 6 are both coupled to host 1, the processing completion message corresponding to the IO command received through host interface 5 can be fed back to host 1 through host interface 5 or through host interface 6. Similarly, the processing completion message corresponding to the IO command received through host interface 6 can be fed back to the host through host interface 6 or through host interface 5.

[0206] exist Figure 16 In the illustrated embodiment, the host interface 6 in the control unit 6 is coupled to the host command processing unit 5 in the control unit 5, and the media interface controller 6 is coupled to the storage command processing unit 5. Both the inter-chip communication link 3 and the inter-chip communication link 4 exist between the control unit 5 and the control unit 6. I / O commands (including NVMe write commands and NVMe read commands) received by the control unit 5 through the host interface 5 and I / O commands (including NVMe write commands and NVMe read commands) received by the control unit 6 through the host interface 6 are sent to the host command processing unit 5. The host command processing unit 5 generates one or more storage commands based on the received I / O commands and sends the generated storage commands to the storage command processing unit 5. The storage command processing unit 5 generates one or more media interface commands based on the received storage commands and allocates the generated media interface commands to the media interface controller 5 and the media interface controller 6. The storage command processing unit 5 can allocate media interface commands to the media interface controller 5 and the media interface controller 6 based on the physical address indicated by the media interface command. For example, the strategy for the storage command processing unit 5 to allocate media interface commands based on the physical address indicated by the media interface command can refer to... Figures 8-12 This application will not elaborate further.

[0207] Depend on Figures 2-16As can be seen from the embodiments shown, the storage device provided in this application provides a large-capacity and high-performance storage device by combining two or more control units to collaboratively process IO commands from the host, while the control units provide a limited number of flash memory channels.

[0208] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application. Clearly, those skilled in the art can make various alterations and variations to this application without departing from its spirit and scope. Thus, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A storage device, characterized in that, Includes a first control unit, a second control unit, and an inter-chip communication link; The first control component includes a first host interface, a first host command processing unit, a first storage command processing unit, a first storage media management unit, and a first media interface controller; The second control component includes a second host interface, a second host command processing unit, a second storage command processing unit, a second storage media management unit, and a second media interface controller; The first control unit is coupled to the first host through the first host interface, and the second control unit is coupled to the second host through the second host interface; the second host command processing unit does not participate in the operation. The first control unit and the second control unit cooperate in processing the received I / O commands through the inter-chip communication link; The first control unit receives the first IO command sent by the first host through the first host interface, and sends the first IO command to the first host command processing unit; The second control unit receives the second IO command sent by the second host through the second host interface, and sends the second IO command to the first host command processing unit through the third inter-chip communication link formed by coupling the second host interface and the first host command processing unit. The first host command processing unit generates one or more first storage commands based on the first IO command and generates one or more second storage commands based on the second IO command, and assigns the one or more first storage commands and the one or more second storage commands to the first storage command processing unit, and assigns the first inter-chip communication link formed by the coupling of the second storage command processing unit and the first host command processing unit to the second storage command processing unit.

2. The storage device according to claim 1, characterized in that, If the first IO command is an NVMe read command, the first host command processing unit generates one or more third storage commands based on the NVMe read command, and assigns each of the third storage commands to the storage command processing unit corresponding to its corresponding second storage command, wherein the logical address indicated by the third storage command is the same as the logical address indicated by its corresponding second storage command.

3. The storage device according to any one of claims 1-2, characterized in that, The first storage command processing unit generates one or more media interface commands based on the received seventh storage command, and assigns the one or more media interface commands to the first media interface controller and assigns the fourth inter-chip communication link formed by the coupling between the first storage command processing unit and the second media interface controller to the second media interface controller.

4. The storage device according to claim 3, characterized in that, The first control unit receives a sixth IO command through the first host interface and sends the sixth IO command to the first host command processing unit. The second control unit receives a seventh IO command through the second host interface and sends the seventh IO command to the first host command processing unit through the third inter-chip communication link. The first host command processing unit generates one or more eighth storage commands based on the sixth IO command and one or more ninth storage commands based on the seventh IO command, and sends the one or more eighth storage commands and the one or more ninth storage commands to the first storage command processing unit; The first storage command processing unit generates corresponding media interface commands based on the received eighth and ninth storage commands, and assigns the generated media interface commands to the first media interface controller and to the second media interface controller through the fourth inter-chip communication link.

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