Decomposition method and device based on multi-memristor array, electronic equipment and medium

Abstract

The application relates to the field of information technology, in particular to a deconvolution method and device based on a multi-memristor array, an electronic device and a medium, wherein the method comprises the following steps: obtaining target data to be calculated, and identifying each sub-data of each group of data in the target data; dispersing each sub-data of each group of data to different operation positions of the multi-memristor array; completing convolution operation on the different operation positions of the multi-memristor array, and accumulating the convolution operation results of the different operation positions to obtain the final convolution result of each group of data in the target data. Thus, the problems that in the related art, a plurality of groups of data complete convolution acceleration operation on a plurality of memristor arrays respectively, each group of convolution results calculated exists error, and the final calculation precision is affected are solved.

Description

Technical Field

[0001] This application relates to the field of information technology, and in particular to a deconvolution method, apparatus, electronic device and medium based on a multi-memristor array. Background Technology

[0002] Deconvolution is a widely used algorithm that plays a crucial role in image processing, computational optics, and other fields. However, it involves numerous complex calculations and demands extremely high computational power. Memristor arrays, with their excellent matrix-vector multiplication acceleration capabilities, can accelerate deconvolution algorithms. Considering that deconvolution tasks typically involve massive amounts of data, practical applications often use multiple memristor arrays with identical hardware designs and stored parameter matrices to perform parallel acceleration of the deconvolution algorithm.

[0003] Data streams implemented using deconvolution algorithms based on multi-memristor arrays, commonly employed in related technologies, include... Figure 1 As shown, multiple sets of data undergo convolution acceleration operations on multiple memristor arrays. Following this, based on typical deconvolution algorithm requirements, each set of data is typically accumulated after convolution. For simplicity in data scheduling, multiple sets of data undergo convolution acceleration operations on multiple memristor arrays. For example, the first set of data undergoes convolution only on the first memristor array, the second set only on the second, and the third set only on the third. However, since the write bias (i.e., the deviation between the parameter matrix mapped to the memristor array and the actual parameter matrix) is fixed on each memristor array, each calculated "convolution result" for a given set of data will be subject to similar "interference." That is, the random variables representing the "interference" in each "convolution result" are highly correlated. Therefore, the final result obtained after accumulation will be severely "interfered," thus affecting the final computational accuracy. Summary of the Invention

[0004] This application provides a deconvolution method, apparatus, electronic device, and medium based on multiple memristor arrays to solve the problems in related technologies where multiple sets of data undergo convolution acceleration operations on multiple memristor arrays respectively, resulting in errors in each convolution result and affecting the final calculation accuracy.

[0005] The first aspect embodiment of the present application provides a deconvolution method based on a multi-memristor array, comprising the following steps: obtaining target data to be calculated, and identifying each sub-data of each group of data in the target data; dispersing each sub-data of each group of data to different operation positions of the multi-memristor array; completing convolution operation on the different operation positions of the multi-memristor array, and accumulating convolution operation results of the different operation positions to obtain a final convolution result of each group of data in the target data.

[0006] Optionally, the different operation positions of the multi-memristor array include at least one of different memristor arrays and different sub-arrays in a memristor array.

[0007] Optionally, if the different operation positions of the multi-memristor array are different memristor arrays, accumulating the convolution operation results of the different operation positions to obtain the final convolution result of each group of data in the target data comprises: obtaining output data of a memristor array participating in operation in the multi-memristor array; and accumulating the output data of the memristor array participating in operation to obtain the final convolution result.

[0008] Optionally, if the different operation positions of the multi-memristor array are different sub-arrays in a memristor array, accumulating the convolution operation results of the different operation positions to obtain the final convolution result of each group of data in the target data comprises: obtaining output data of a sub-array participating in operation in the memristor array; and accumulating the output data of the sub-array participating in operation to obtain the final convolution result.

[0009] Optionally, the different sub-arrays in the memristor array include a first data stream sub-array and a second data stream sub-array, wherein the first data stream sub-array and the second data stream sub-array complete data stream modes of discrete Fourier transform differently.

[0010] Optionally, the data stream mode includes a first data stream and a second data stream, wherein the first data stream is based on a first side sub-array to complete real part operation and based on a second side sub-array to complete imaginary part operation, and the second data stream is based on the first side sub-array to complete imaginary part operation and based on the second side sub-array to complete real part operation.

[0011] Optionally, the multi-memristor array is a plurality of memristor arrays with the same structure, a plurality of memristor arrays with different structures, or a plurality of different kinds of memristor arrays.

[0012] The second aspect embodiment of the present application provides a deconvolution device based on a multi-memristor array, comprising: an acquisition module, configured to obtain target data to be calculated, and identify each sub-data of each group of data in the target data; a dispersion module, configured to disperse each sub-data of each group of data to different operation positions of the multi-memristor array; and a processing model, configured to complete convolution operation on the different operation positions of the multi-memristor array, and accumulate convolution operation results of the different operation positions to obtain a final convolution result of each group of data in the target data.

[0013] Optionally, the different operation positions of the multiple memristor arrays include at least one of different memristor arrays and different sub-arrays in the memristor array.

[0014] Optionally, if the different operation positions of the multiple memristor arrays are different memristor arrays, the processing module is further configured to obtain output data of the memristor array participating in the operation; and accumulate the output data of the memristor array participating in the operation to obtain the final convolution result.

[0015] Optionally, if the different operation positions of the multiple memristor arrays are different sub-arrays in the memristor array, the processing module is further configured to obtain output data of the sub-array participating in the operation; and accumulate the output data of the sub-array participating in the operation to obtain the final convolution result.

[0016] Optionally, the different sub-arrays in the memristor array include a first data stream sub-array and a second data stream sub-array, wherein the first data stream sub-array and the second data stream sub-array complete the data stream mode of the discrete Fourier transform in different ways.

[0017] Optionally, the data stream mode includes a first data stream and a second data stream, wherein the first data stream is based on the first side sub-array to complete the real part operation and based on the second side sub-array to complete the imaginary part operation, and the second data stream is based on the first side sub-array to complete the imaginary part operation and based on the second side sub-array to complete the real part operation.

[0018] Optionally, the multiple memristor arrays are multiple memristor arrays with the same structure, multiple memristor arrays with different structures, or multiple different kinds of memristor arrays.

[0019] The third aspect of the embodiments of the present application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor executes the program to implement the deconvolution method based on the multiple memristor arrays as described above.

[0020] The fourth aspect of the embodiments of the present application provides a computer readable storage medium, which stores a computer program executable by a processor to implement the deconvolution method based on the multiple memristor arrays as described above.

[0021] Therefore, the present application includes the following beneficial effects:

[0022] The embodiments of the present application can disperse each sub-data in a group of data to different memristor arrays to complete convolution operation, so as to effectively reduce the influence of non-ideal characteristics of the memristor on the calculation result, improve the calculation precision, and make the final calculation result after accumulation more accurate. Thus, the problems in the related art that each group of convolution results obtained by performing convolution acceleration operation on multiple groups of data in multiple memristor arrays respectively has errors, thereby affecting the final calculation precision and the like are solved.

[0023] The additional aspects and advantages of the present application will be in part apparent and in part pointed out hereinafter in the description. BRIEF DESCRIPTION OF DRAWINGS

[0024] The above and / or additional aspects and advantages of the present application will become apparent and be readily appreciated from the following description, including the appended drawings.

[0025] Figure 1 A data flow scheduling example diagram among multiple arrays in the related art;

[0026] Figure 2 A flowchart of a deconvolution method based on multiple memristor arrays according to an embodiment of the present application;

[0027] Figure 3 A result accumulation example diagram according to an embodiment of the present application;

[0028] Figure 4 A deconvolution data flow scheduling example diagram based on multiple memristor arrays according to an embodiment of the present application;

[0029] Figure 5 A structure diagram of a memristor discrete Fourier transform calculation module according to an embodiment of the present application;

[0030] Figure 6 Two data flow scheme diagrams of a memristor discrete Fourier transform according to an embodiment of the present application;

[0031] Figure 7 A discrete Fourier transform data flow scheduling example diagram according to an embodiment of the present application;

[0032] Figure 8 A simulation effect comparison diagram according to an embodiment of the present application;

[0033] Figure 9 A block diagram of a deconvolution device based on multiple memristor arrays according to an embodiment of the present application;

[0034] Figure 10 A structure diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0035] Embodiments of the present application are described below in detail, examples of which are shown in the accompanying drawings, in which the same or similar notations represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by reference to the drawings are exemplary and are intended to explain the present application, and cannot be understood as limiting the present application.

[0036] The method, device, electronic equipment and medium based on a multi-memristor array for deconvolution of embodiments of the present application are described below with reference to the accompanying drawings. In view of the problems mentioned in the above background art, the present application provides a method for deconvolution based on a multi-memristor array, in which each sub-data in a group of data is dispersed to different memristor arrays to complete convolution operation, so as to effectively reduce the influence of non-ideal characteristics of the memristor on the calculation result, improve the calculation accuracy, and make the final calculation result after accumulation more accurate. Thus, the problems in the related art that each group of data completes convolution acceleration operation on multiple memristor arrays, each group of convolution results calculated has errors, and thus affects the final calculation accuracy, etc. are solved.

[0037] Specifically, Figure 1 A flowchart of a method for deconvolution based on a multi-memristor array provided by embodiments of the present application is shown.

[0038] As Figure 1 shown, the method for deconvolution based on a multi-memristor array includes the following steps:

[0039] In step S101, the target data to be calculated is obtained, and each sub-data of each group of data in the target data is identified.

[0040] In step S102, each sub-data of each group of data is dispersed to different operation positions of the multi-memristor array.

[0041] The multi-memristor array can be a plurality of memristor arrays with the same structure, a plurality of memristor arrays with different structures, or a plurality of different types of memristor arrays.

[0042] Specifically, as Figure 3 shown, the sub-data of each group of data in the present application can be arranged on different memristor arrays to complete convolution operation. Since the write bias on the memristor array is randomly distributed, there is almost no correlation between the write biases of each array, so the correlation between the "interference" received by each group of data "convolution result" can be greatly reduced, making the last term 2Cov(X,Y) of formula (1) approximately equal to zero, and the variance value Var(X+Y) of the superimposed random variable is reduced.

[0043] Var(X+Y) = Var(X) + Var(Y) + 2Cov(X, Y) (1)

[0044] In step S103, the convolution operation is completed on different operation positions of the multi-memristor array, and the final convolution result of each group of data in the target data is obtained by accumulating the convolution operation results of the different operation positions.

[0045] It can be understood that the embodiments of the present application can disperse each sub-data in a group of data to different memristor arrays (and / or different sub-arrays of the memristor array) to complete the convolution operation, thereby reducing the correlation between the "interference" of each "convolution result", so that the "interference" variance of the "final result" is approximately equal to the sum of the "interference" variances of each "convolution result", as shown in Figure 3 , thereby effectively reducing the influence of the non-ideal characteristics of the memristor on the calculation result and improving the calculation accuracy.

[0046] The different operation positions of the multi-memristor array can include at least one of different memristor arrays and different sub-arrays in the memristor array. Therefore, the embodiments of the present application can use different memristor arrays or different sub-arrays in the memristor array alone to complete the convolution operation, or can use different memristor arrays and different sub-arrays in the memristor array in combination to complete the convolution operation, and the person skilled in the art can select according to the actual needs, without specific limitation. In the following embodiments, the use alone is taken as an example, and when used in combination, the steps in the following embodiments are combined, and to avoid redundancy, the combination is not described in detail. The use of different memristor arrays or different sub-arrays in the memristor array alone to complete the convolution operation will be specifically described below:

[0047] In an embodiment of the present application, if the different operation positions of the multi-memristor array are different memristor arrays, the final convolution result of each group of data in the target data is obtained by accumulating the convolution operation results of the different operation positions, comprising: obtaining the output data of the memristor array participating in the operation in the multi-memristor array; and accumulating the output data of the memristor array participating in the operation to obtain the final convolution result.

[0048] It can be understood that, as shown in Figure 4 , the embodiments of the present application can perform convolution operation on multiple memristor arrays in parallel, and each memristor array processes the sub-data assigned to it. Since there is almost no correlation between the "interference" generated on each memristor array, when these convolution results are accumulated, the "interference" variance of the "final result" is close to the sum of the "interference" variances of each "convolution result", rather than significantly increasing. Therefore, by accumulating the convolution results from different memristor arrays to form the final convolution result of the group of data, the error under the calculation of the multi-memristor array is reduced, and the calculation accuracy is maintained.

[0049] In an embodiment of the present application, if different operation positions of the memristor array are different sub-arrays in the memristor array, the convolution operation results of different operation positions are accumulated to obtain the final convolution result of each group of data in the target data, including obtaining the output data of the sub-arrays participating in the operation in the memristor array; and the output data of the sub-arrays participating in the operation is accumulated to obtain the final convolution result.

[0050] The different sub-arrays in the memristor array include a first data stream sub-array and a second data stream sub-array, wherein the first data stream sub-array and the second data stream sub-array complete the data stream mode of the discrete Fourier transform differently. The data stream mode includes a first data stream and a second data stream, wherein the first data stream is based on the first side sub-array to complete the real part operation and based on the second side sub-array to complete the imaginary part operation, and the second data stream is based on the first side sub-array to complete the imaginary part operation and based on the second side sub-array to complete the real part operation.

[0051] It can be understood that, in a single convolution acceleration core based on a memristor array, as shown in Figure 5 , the embodiments of the present application can use different sub-arrays in the memristor array (for example, the upper left corner and the lower right corner map the real part of the parameter matrix, and the upper right corner and the lower left corner map the imaginary part of the parameter matrix) to perform convolution operation to obtain respective convolution results, and then accumulate these results to obtain the final convolution result.

[0052] In actual execution, the operation core is a memristor discrete Fourier transform calculation module as shown in Figure 5 . The basic calculation principle is as follows: the real part Re(x) and the imaginary part Im(x) of the input signal x are input to the row line of the memristor array at the same time, and then the real part Re(y) and the imaginary part Im(y) of the output time-frequency transformed result y are output on the column line, wherein the calculation formula of the real part is Re(y)=Re(x)Re(W)-Im(x)Im(W), and the calculation formula of the imaginary part is Im(y)=Re(x)Im(W)+Im(x)Re(W). It should be noted that, for the sake of brevity, the positive and negative elements of the parameter matrix are not considered here; in fact, in order to map the parameter matrix containing positive and negative numbers, a memristor array twice the size is needed to represent the parameter matrix in a differential form; the processing of the positive and negative elements of the parameter matrix can refer to the prior art, which will not be described here, and in the schematic diagram, a memristor array is used to represent a parameter matrix (the elements can be positive or negative) by default.

[0053] In the current general method, the real part Re(x) and the imaginary part Im(x) of the input signal are input to the memristor array in the manner as shown in Figure 5 ; then the real part Re(y) and the imaginary part Im(y) of the frequency domain signal are output on the left side and the right side of the array output end respectively. However Figure 5There are two "same memristor sub-arrays" in the illustrated calculation module, that is, the upper left corner and the lower right corner map the real part of the parameter matrix, and the upper right corner and the lower left column map the imaginary part of the parameter matrix.

[0054] Therefore, the embodiments of the present application can be used to Figure 5 The same "sub-data dispersion to different sub-array operation" is completed inside the illustrated calculation module, thereby further reducing the correlation between the "interference" on each "convolution result". According to mathematical derivation, the following formula can be obtained:

[0055] -Im(y)=Re(x)·(-Im(W))+(-Im(x))·Re(W) (2)

[0056] Re(y)=Re(x)·Re(W)+(-Im(x))·Im(W) (3)

[0057] Further, as Figure 6 illustrated, the embodiments of the present application can use a new data flow scheme to complete the discrete Fourier transform on the Figure 6 memristor array illustrated. In actual execution process, the embodiments of the present application can refer to the traditional data flow scheme as the first data flow, that is, "DFT data flow A" in Figure 6 , and refer to the new data flow scheme as the second data flow, that is, "DFT data flow B" in Figure 6 . It should be noted that in "DFT data flow A", the real part Re(y) is based on the operation of the left two sub-arrays, and the imaginary part Im(y) is based on the operation of the right two sub-arrays; while in "DFT data flow B", the real part Re(y) is based on the operation of the right two sub-arrays, and the imaginary part Im(y) is based on the operation of the left two sub-arrays.

[0058] Therefore, the correlation between the "interference" of the calculation results obtained by "DFT data flow A" and "DFT data flow B" is very low. The overall calculation data flow scheduling scheme based on the above-mentioned "A, B" two schemes (new discrete Fourier transform data flow scheduling scheme) is as shown in Figure 7 . For a group of data sub-data A and B, "DFT data flow A" and "DFT data flow B" can be used to complete convolution operation respectively, to obtain "convolution results" A and B, and then accumulate. In this way, the correlation between the "interference" on "convolution results" A and B is very small.

[0059] In addition, the embodiments of the present application also analyze the actual application effect of the above-mentioned two new data flow schemes (multi-array data flow scheduling scheme and new discrete Fourier transform data flow scheduling scheme), Figure 8The front and back calculation results using the two new schemes are shown. In the traditional data flow scheme, a write bias of ±0.5 μS (equivalent to about 2.5%) is added to the memristor array, and the peak signal-to-noise ratio (PSNR) of the calculation result is 44 dB; a write bias of ±1 μS (equivalent to about 5%) is added to the memristor array, and the peak signal-to-noise ratio (PSNR) of the calculation result is 35 dB; a write bias of ±3 μS (equivalent to about 15%) is added to the memristor array, and the peak signal-to-noise ratio (PSNR) of the calculation result is 21 dB. In the new data flow scheme, a write bias of ±0.5 μS (equivalent to about 2.5%) is added to the memristor array, and the peak signal-to-noise ratio (PSNR) of the calculation result is 51 dB; a write bias of ±1 μS (equivalent to about 5%) is added to the memristor array, and the peak signal-to-noise ratio (PSNR) of the calculation result is 45 dB; a write bias of ±3 μS (equivalent to about 15%) is added to the memristor array, and the peak signal-to-noise ratio (PSNR) of the calculation result is 36 dB. It can be seen that the calculation result of the new data flow scheme is significantly better than that of the traditional data flow scheme at any level of write bias.

[0060] It should be noted that the memristor array of the embodiments of the present application can also have the following structures: different types of memristors (such as resistive random access memory, phase change memory, magnetic random access memory, etc.); different structures of integrated computing architecture or cells (such as 1T1R, 2T2R, 2T1R, etc.). Other algorithms with similar data flow (i.e., data is operated separately and then accumulated) can also use the method proposed in the embodiments of the present application to reduce the error under multi-memristor array calculation.

[0061] According to the deconvolution method for multi-memristor array proposed in the embodiments of the present application, each sub-data in a group of data is dispersed to different memristor arrays to complete convolution operation, which can effectively reduce the influence of non-ideal characteristics of the memristor on the calculation result, improve the calculation accuracy, and make the final calculation result after accumulation more accurate. Thus, the problems in the related art that each group of convolution results calculated by performing convolution acceleration operation on multiple groups of data in multiple memristor arrays respectively has error, thereby affecting the final calculation accuracy, etc. are solved.

[0062] Secondly, the deconvolution device based on multi-memristor array proposed in the embodiments of the present application is described with reference to the accompanying drawings.

[0063] Figure 9 is a block schematic diagram of the deconvolution device based on multi-memristor array of the embodiments of the present application.

[0064] As shown in Figure 9 , the deconvolution device based on multi-memristor array 10 includes an acquisition module 100, a dispersion module 200, and a processing module 300.

[0065] The obtaining module 100 is configured to obtain target data to be calculated, and identify each sub-data of each group of data in the target data. The dispersion module 200 is configured to disperse each sub-data of each group of data to different operation positions of a multi-memristor array. The processing model 300 is configured to complete convolution operation at the different operation positions of the multi-memristor array, and accumulate convolution operation results of the different operation positions to obtain a final convolution result of each group of data in the target data.

[0066] In an embodiment of the present application, the different operation positions of the multi-memristor array include at least one of different memristor arrays and different sub-arrays in a memristor array.

[0067] In an embodiment of the present application, if the different operation positions of the multi-memristor array are different memristor arrays, the processing module 300 is further configured to obtain output data of the memristor arrays participating in operation in the multi-memristor array; and accumulate the output data of the memristor arrays participating in operation to obtain the final convolution result.

[0068] In an embodiment of the present application, if the different operation positions of the multi-memristor array are different sub-arrays in a memristor array, the processing module 300 is further configured to obtain output data of the sub-arrays participating in operation in the memristor array; and accumulate the output data of the sub-arrays participating in operation to obtain the final convolution result.

[0069] In an embodiment of the present application, the different sub-arrays in the memristor array include a first data stream sub-array and a second data stream sub-array, wherein the first data stream sub-array and the second data stream sub-array complete data stream modes of discrete Fourier transform differently.

[0070] In an embodiment of the present application, the data stream mode includes a first data stream and a second data stream, wherein the first data stream is based on a first side sub-array to complete real part operation and based on a second side sub-array to complete imaginary part operation, and the second data stream is based on the first side sub-array to complete imaginary part operation and based on the second side sub-array to complete real part operation.

[0071] In an embodiment of the present application, the multi-memristor array is a plurality of memristor arrays with same structure, a plurality of memristor arrays with different structures, or a plurality of different kinds of memristor arrays.

[0072] It should be noted that the foregoing explanation and description of the embodiment of the deconvolution method based on the multi-memristor array also applies to the embodiment of the deconvolution device based on the multi-memristor array, which will not be described herein again.

[0073] According to the deconvolution device based on the multiple memristor array provided in the embodiments of the present application, each sub-data in a group of data is dispersed to different memristor arrays to complete convolution operation, so that the influence of the non-ideal characteristics of the memristor on the calculation result can be effectively reduced, the calculation precision is improved, and the precision of the final calculation result after accumulation is higher. Therefore, the problems in the related art that each group of convolution results calculated by performing convolution acceleration operation on multiple memristor arrays respectively has errors, thereby affecting the final calculation precision and the like are solved.

[0074] Figure 10 A structural schematic diagram of an electronic device provided in the embodiments of the present application is provided. The electronic device can include:

[0075] The memory 1001, the processor 1002 and the computer program stored in the memory 1001 and executable on the processor 1002.

[0076] The processor 1002 implements the deconvolution method based on the multiple memristor array provided in the above embodiments when executing the program.

[0077] Further, the electronic device further includes:

[0078] The communication interface 1003 is used for communication between the memory 1001 and the processor 1002.

[0079] The memory 1001 is used to store the computer program executable on the processor 1002.

[0080] The memory 1001 can include a high-speed RAM (Random Access Memory) memory, and can also include a non-volatile memory, for example, at least one disk memory.

[0081] If the memory 1001, the processor 1002 and the communication interface 1003 are independently implemented, the communication interface 1003, the memory 1001 and the processor 1002 can be connected to each other through a bus and complete communication between each other. The bus can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, Figure 10 In the figure, only one thick line is used to represent, but it does not mean that there is only one bus or one type of bus.

[0082] Optionally, in a specific implementation, if the memory 1001, processor 1002, and communication interface 1003 are integrated on a single chip, then the memory 1001, processor 1002, and communication interface 1003 can communicate with each other through an internal interface.

[0083] The processor 1002 may be a CPU (Central Processing Unit), an ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of this application.

[0084] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described deconvolution method based on a multi-memristor array.

[0085] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0086] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0087] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or N executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0088] It should be understood that portions of the application can be implemented in hardware, software, firmware, or combinations thereof. In the above embodiments, steps or methods can be implemented in software or firmware that is stored in memory and executed by a suitable instruction execution system. As such, if implemented in hardware, as in another embodiment, any of the following technology, known in the art, can be employed for implementing: a hybrid of the techniques described herein; discrete logic circuitry having logic gates for implementing logic functions upon data signals; application specific integrated circuits having appropriate combinational logic gates; programmable gate arrays; field programmable gate arrays, or the like.

[0089] Those skilled in the art can understand that all or part of the steps carried out by the method of the above-mentioned embodiments can be completed by a program instructing the relevant hardware, and the above-mentioned program can be stored in a computer readable storage medium. When the program is executed, it includes one of the steps of the method embodiment or a combination thereof.

[0090] Although the embodiments of the present application have been shown and described above, it should be understood that the above-mentioned embodiments are exemplary and cannot be understood as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above-mentioned embodiments within the scope of the present application.

Claims

1. A deconvolution method based on a multi-memristor array, characterized in that, Includes the following steps: Obtain the target data to be calculated, and identify each sub-data in each group of data in the target data; The sub-data of each group of data is distributed to different operation positions of the multi-memristor array, wherein the different operation positions include: different memristor arrays and at least one different sub-array in the memristor array; Convolution operations are performed at different computational locations of the multi-memristor array, and the convolution results at different computational locations are summed to obtain the final convolution result of each group of data in the target data.

2. The deconvolution method based on a multi-memristor array according to claim 1, characterized in that, If the different computation positions of the multi-memristor array are different memristor arrays, the summation of the convolution operation results at the different computation positions to obtain the final convolution result for each group of data in the target data includes: Obtain the output data of the memristor array participating in the operation in the multi-memristor array; The final convolution result is obtained by accumulating the output data of the memristor array involved in the operation.

3. The deconvolution method based on a multi-memristor array according to claim 1, characterized in that, If the different operation positions of the multi-memristor array are different subarrays in the memristor array, the convolution operation results of the different operation positions are accumulated to obtain the final convolution result of each group of data in the target data, including: Obtain the output data of the subarrays participating in the operation in the memristor array; The final convolution result is obtained by accumulating the output data of the subarrays involved in the operation.

4. The deconvolution method based on a multi-memristor array according to claim 1 or 3, characterized in that, The memristor array includes a first data stream subarray and a second data stream subarray, wherein the first data stream subarray and the second data stream subarray perform discrete Fourier transforms in different ways.

5. The deconvolution method based on a multi-memristor array according to claim 4, characterized in that, The data stream method includes a first data stream and a second data stream, wherein the first data stream performs real part operations based on a first side subarray and imaginary part operations based on a second side subarray, and the second data stream performs imaginary part operations based on a first side subarray and real part operations based on a second side subarray.

6. The deconvolution method based on a multi-memristor array according to claim 1, characterized in that, The multiple memristor array can be multiple memristor arrays with the same structure, multiple memristor arrays with different structures, or multiple memristor arrays of different types.

7. A deconvolution device based on a multi-memristor array, characterized in that, include: The acquisition module is used to acquire the target data to be calculated and identify each sub-data of each group of data in the target data. The distribution module is used to distribute each sub-data of each group of data to different operation positions of the multi-memristor array, wherein the different operation positions include: different memristor arrays and at least one different sub-array in the memristor array; The processing model is used to perform convolution operations at different computational positions of the multi-memristor array, and the convolution operation results at different computational positions are accumulated to obtain the final convolution result of each group of data in the target data.

8. An electronic device, characterized in that, include: A memory, a processor, and a computer program stored in the memory and executable on the processor, the processor executing the program to implement the deconvolution method based on a multi-memristor array as described in any one of claims 1-6.

9. A computer-readable storage medium having a computer program or instructions stored thereon, characterized in that, When the computer program or instructions are executed, they implement the deconvolution method based on a multi-memristor array as described in any one of claims 1-6.

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