Incremental cutting method, device, equipment and medium

Abstract

The invention discloses an increment cutting method and device, equipment and a medium. The increment cutting method comprises the steps that an increment hypergraph corresponding to a current increment design project is generated by referring to a historical design project and a historical hypergraph; obtaining a label of each node in the incremental hypergraph according to the historical hypergraph, and marking the labels on the nodes; obtaining a historical cutting result of the historical design project; based on the historical cutting result, the incremental hypergraph is cut by referring to the label to obtain an incremental cutting result, and the incremental cutting result comprises a changed FPGA and an unchanged FPGA. According to the method, a historical design project and information of a historical hypergraph are reused to the greatest extent to generate an incremental hypergraph, so that the difference between the generated incremental hypergraph and the historical hypergraph is reduced, a change condition in the incremental hypergraph is labeled, incremental cutting is performed on the incremental hypergraph by reusing a historical cutting result reference label, and the incremental hypergraph is obtained. Therefore, the result is similar to a historical cutting result as much as possible, and a user can reproduce and position the problem more easily.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to an incremental cutting method, device, equipment and medium. Background Art

[0002] With the rapid development of electronic technology, the scale of program design is getting larger and larger. Users cannot realize large-scale complex design in one Field Programmable Gate Array (FPGA), which seriously restricts user development work. Usually, users will use automatic cutting tools to cut the design, divide the functions into several modules and put them in multiple FPGAs, and realize the multi-FPGA collaborative work of the whole system according to the IO connection between FPGAs and the design communication protocol.

[0003] Currently, when users cut a design to multiple FPGAs and get an error, they will modify the design and cut it again. However, usually a slight change in the input will lead to a huge difference in the cutting result, so that the cutting result is completely different from the last time. Users cannot reproduce the problem of cutting result positioning, which makes the debugging process difficult. Summary of the invention

[0004] The present invention provides an incremental cutting method to realize accurate and efficient incremental cutting of FPGA.

[0005] According to a first aspect of the present invention, there is provided an incremental cutting method, comprising: generating an incremental hypergraph corresponding to a current incremental design project by referring to a historical design project and a historical hypergraph;

[0006] Obtaining labels of each node in the incremental hypergraph according to the historical hypergraph, and marking the labels on the nodes, wherein the labels include changed and unchanged;

[0007] Obtaining a historical cutting result of the historical design project, wherein the historical cutting result includes a field programmable gate array FPGA and distribution positions of historical hypergraph nodes on the FPGA;

[0008] The incremental hypergraph is cut based on the historical cutting results and with reference to the labels to obtain incremental cutting results, wherein the incremental cutting results include changed FPGAs and unchanged FPGAs.

[0009] According to another aspect of the present invention, there is provided an incremental cutting device, the device comprising:

[0010] An incremental hypergraph generation module, used to generate an incremental hypergraph corresponding to the current incremental design project by referring to the historical design project and the historical hypergraph;

[0011] A label marking module, used for obtaining the label of each node in the incremental hypergraph according to the historical hypergraph, and marking the label on the node, wherein the label includes changed and unchanged;

[0012] A historical cutting result acquisition module, used for acquiring the historical cutting result of the historical design project, wherein the historical cutting result includes a field programmable gate array FPGA and the distribution position of the historical hypergraph nodes on the FPGA;

[0013] The incremental cutting result acquisition module is used to cut the incremental hypergraph based on the historical cutting results and refer to the labels to obtain incremental cutting results, wherein the incremental cutting results include changed FPGAs and unchanged FPGAs.

[0014] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0015] at least one processor; and

[0016] a memory communicatively connected to the at least one processor; wherein,

[0017] The memory stores a computer program that can be executed by the at least one processor. The computer program is executed by the at least one processor so that the at least one processor can perform the method described in any embodiment of the present invention.

[0018] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the method described in any embodiment of the present invention when executed.

[0019] The technical solution of the embodiment of the present invention maximizes the reuse of information of historical design projects and historical hypergraphs to generate incremental hypergraphs, so that the difference between the generated incremental hypergraphs and the historical hypergraphs is reduced, and the changes in the incremental hypergraphs are labeled. The incremental hypergraphs are incrementally cut by reusing the historical cutting results and referring to the labels, so as to achieve the greatest possible similarity to the historical cutting results, making it easier for users to reproduce and locate problems.

[0020] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 is a flow chart of an incremental cutting method provided according to Embodiment 1 of the present invention;

[0023] Figure 2 is a schematic diagram of the structure of a historical design project provided according to the first embodiment of the present invention;

[0024] Figure 3 is a structural schematic diagram of a current incremental design project provided according to the first embodiment of the present invention;

[0025] Figure 4 is a schematic diagram of the structure of an incremental hypergraph provided according to Embodiment 1 of the present invention;

[0026] Figure 5 is a schematic diagram of a historical cutting result provided according to the first embodiment of the present invention;

[0027] Figure 6 is a schematic diagram of an incremental cutting result provided according to the first embodiment of the present invention;

[0028] Figure 7 is a flow chart of an incremental cutting method provided according to Embodiment 2 of the present invention;

[0029] Figure 8 is a schematic structural diagram of an incremental cutting device provided according to Embodiment 3 of the present invention;

[0030] Fig. 9 It is a schematic diagram of the structure of an electronic device provided by Embodiment 4 of the present invention. DETAILED DESCRIPTION

[0031] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0032] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0033] Embodiment 1

[0034] Figure 1 A flowchart of an incremental cutting method is provided for the first embodiment of the present invention. This embodiment is applicable to the case of accurately incrementally cutting an FPGA. The method can be executed by an incremental cutting device of a device, which can be implemented in the form of hardware and / or software. Figure 1 As shown, the method includes:

[0035] Step S101, generating an incremental hypergraph corresponding to the current incremental design project with reference to historical design projects and historical hypergraphs.

[0036] Optionally, an incremental hypergraph corresponding to the current incremental design project is generated with reference to historical design projects and historical hypergraphs, including: determining nodes in the incremental design project that have the same identifiers as those in the historical design project and newly added nodes; determining a first type of hypergraph nodes from nodes with the same identifiers with reference to the historical hypergraph; determining a second type of hypergraph nodes from newly added nodes according to a hypergraph node selection algorithm; and constructing an incremental hypergraph based on the first type of hypergraph nodes and the second type of hypergraph nodes.

[0037] Specifically, Figure 2 The figure shows the structure diagram of the historical design project in this embodiment, wherein the historical design project is the design project of the first cutting. Figure 2 When the historical design project shown in the figure is cut and run, an instance of a certain layer will be selected from the user design as a historical hypergraph node based on resources and ports. For example, Figure 2 The historical hypergraph nodes determined in are e, k, l, h and o, and the interconnection information and resource information of these historical hypergraph nodes are recorded at the same time, and a historical hypergraph is constructed based on the above information.

[0038] When a small change is made to the historical design project to generate the current incremental design project, in order to maintain the operating frequency of the first cut and to locate the problem more easily, the historical design project can be reused to the maximum extent when the current incremental design project is split. The reuse can include two aspects: one is the reuse of the incremental hypergraph generation process, and the other is the reuse of the incremental hypergraph segmentation process. First, for the first point, such as Figure 3 The figure shows the schematic diagram of the structure of the current incremental design project in this implementation mode. By comparison, it can be seen that: Figure 3 is Figure 2 is obtained by making a few modifications based on Figure 3 When the corresponding incremental hypergraph is Figure 3 Incremental Design Engineering as shown Figure 2 The historical design project shown has the same identification as the nodes and the newly added nodes. For example, the nodes with the same identification are: a bc defghoijklmn, and the newly added node is: pxy. Among them, for the current incremental design project, the first type of hypergraph nodes can be determined from the nodes with the same identification with reference to the historical hypergraph. For example, the historical hypergraph nodes e, k, l, h and o in the historical hypergraph are used as the first type of hypergraph nodes in the incremental hypergraph, that is, the nodes that were used as hypergraph nodes in the historical design project are still used as hypergraph nodes in the incremental design project; in addition, for the newly added nodes in the incremental design project, such as pxy, it is determined by calculation according to the hypergraph node selection algorithm whether they can be selected as hypergraph nodes, such as determining by calculation that the newly added node p is the second type of hypergraph node. In addition, in the process of hypergraph node selection, the interconnection relationship of the hypergraph nodes and the resources of the hypergraph nodes will be recorded in this embodiment to facilitate writing them into a file, and the incremental hypergraph will be constructed according to the first type of hypergraph nodes and the second type of hypergraph nodes based on the interconnection relationship, such as Figure 4 Shown is a schematic diagram of the structure of the constructed incremental hypergraph.

[0039] It should be noted that, in this embodiment, for nodes with the same identifier in the historical design project and the current incremental design project, if they were not selected as historical hypergraph nodes in the historical design project, they will still not be selected as hypergraph nodes in the current incremental design project. Therefore, in this embodiment, when constructing the incremental hypergraph of the incremental design project, the information in the historical hypergraph can be reused, and there is no need to repeatedly calculate the nodes with the same identifier through the hypergraph node selection algorithm. Only the newly added nodes need to be calculated separately, thereby maximizing the reuse of information in the historical design project and improving the efficiency and accuracy of the incremental hypergraph construction. Therefore, even when there is a problem with the incremental hypergraph and it needs to be checked, since the nodes with the same identifier have been verified to be no problem in the historical hypergraph, only the newly added nodes need to be checked. Of course, this embodiment is only an example and does not limit the specific structure of the incremental hypergraph.

[0040] Optionally, after generating the incremental hypergraph corresponding to the current incremental design project with reference to the historical design project and the historical hypergraph, the method further includes: detecting the incremental hypergraph; and generating an alarm prompt when an abnormality is detected in the generated incremental hypergraph.

[0041] Specifically, in this embodiment, after obtaining the incremental hypergraph, the correctness of the generated incremental hypergraph will be detected. When an abnormality is detected in the incremental hypergraph, an alarm prompt will be generated accordingly. For example, when an obvious logical error is detected in the generated incremental hypergraph, for example, the hypergraph node o and the hypergraph node e have no correlation in the historical design project, but in the generated incremental hypergraph, the two are directly connected, so the generated incremental hypergraph has a logical error; or there is no node g in the determined hypergraph node, but the generated incremental hypergraph includes the hypergraph node g, which is obviously an obvious error. For the above situations, an alarm prompt will be generated accordingly. And when an abnormality occurs, the alarm prompt generated can be in the form of voice or light. Of course, this embodiment is only an example, and does not limit the specific content of the detection and the specific form of the alarm. As long as it can play the role of abnormal situation prompt, it is within the protection scope of this application.

[0042] Step S102, obtaining the label of each node in the incremental hypergraph according to the historical hypergraph, and marking the label on the node.

[0043] Optionally, labels of each node in the incremental hypergraph are obtained based on the historical hypergraph, including: comparing each node in the historical hypergraph and the incremental hypergraph according to specified parameters, wherein the specified parameters include interconnection relationships and resource files; determining nodes in the incremental hypergraph that are different from the historical hypergraph and nodes that are not different based on the comparison results; determining that labels corresponding to nodes with differences are changed, and determining that labels corresponding to nodes with no differences are unchanged, wherein change types include parameter changes and node additions.

[0044] Specifically, after obtaining the incremental hypergraph, the present embodiment will compare the incremental hypergraph with the historical hypergraph to determine where the two are different, that is, the nodes that have changed, and mark the nodes with labels according to the changes, so that it is convenient to quickly obtain the specific changed position of the hypergraph node according to the labels during subsequent segmentation. When comparing, the specified parameters of the node can be obtained, and the changes can be determined by comparing according to the specified parameters. For example, the specified parameters include associations and resource files. Of course, the present embodiment is only an example, and does not limit the specific types of the specified parameters. Users can set them in advance according to actual needs.

[0045] For example, Figure 4 The incremental hypergraph shown, for the nodes with the same identification in the incremental design project and the historical design project, such as e, k, l, h and o, after comparing the association relationship and resource files, it is determined that the hypergraph nodes e and o have changed, that is, there are differences, so the labels corresponding to the above two hypergraph nodes are determined to be changed, and it is also determined that the hypergraph nodes k, l, h have not changed, that is, there are no differences, so the labels corresponding to the above three hypergraph nodes are determined to be unchanged; finally, for the nodes with different identification in the incremental design project and the historical design project, such as p, since it is a newly added node, it can be directly determined that the label corresponding to the hypergraph node is unchanged.

[0046] It should be noted that in this embodiment, after obtaining the labels of each node in the incremental hypergraph node, the obtained labels can be marked on the corresponding nodes. For example, the labels corresponding to the hypergraph nodes k, l, and h in the incremental hypergraph node are unchanged, so the unchanged labels, such as the clean symbol, can be marked on the above three nodes. The labels corresponding to the hypergraph nodes e, o, and p are changed, so the changed labels, such as the dirty symbol, can be marked on the above three nodes. Of course, this embodiment is only an example, and does not limit the specific symbols corresponding to each label. As long as it can facilitate subsequent identification, it is within the protection scope of this application and is not limited in this embodiment.

[0047] Step S103, obtaining historical cutting results of historical design projects.

[0048] Specifically, in this embodiment, after the incremental hypergraph is generated, the cutting results of the historical design project will be read in, such as Figure 5 Shown is a schematic diagram of the historical cutting results. As shown in the figure, for the historical design project, the historical hypergraph is specifically divided into four FPGAs F1, F2, F3 and F4, and nodes h and e are divided into F1, node o is divided into F2, node l is divided into F3, and node k is divided into F4. Of course, this implementation is only an example for illustration, and does not limit the specific cutting method of the historical cutting results.

[0049] It should be noted that in this embodiment, historical cutting results will be reused when the incremental hypergraph is segmented. In order to ensure the accuracy of subsequent cutting reuse, after obtaining the historical cutting results, the historical cutting results will be detected in this embodiment. Specifically, whether there are abnormalities in the segmentation results is detected. For example, node m is not a historical hypergraph node, but it is indeed segmented on F1, then it can be determined that the historical cutting result obtained is wrong; when it is detected that the historical hypergraph node k appears on 2 at the same time, it can be determined that the historical segmentation result obtained is wrong. Of course, this embodiment is only an example, and does not limit the specific detection content and abnormal conditions of the historical segmentation results. As long as the abnormalities in the historical segmentation results can be pre-selected and detected, they are all within the protection scope of this application, and this embodiment does not limit them.

[0050] Step S104, cutting the incremental hypergraph based on the historical cutting results and referring to the labels to obtain the incremental cutting results.

[0051] Optionally, the hypergraph is cut with reference to the labels based on the historical cutting results and incremental cutting results are obtained, including: for nodes with a label of unchanged, determining that their positions on the first type of FPGA located in the historical cutting results remain unchanged; for nodes with a label of changed and a change type of parameter change, determining that their positions on the second type of FPGA located in the historical cutting results remain unchanged, and marking the second type of FPGA as a changed FPGA; for nodes with a label of changed and a change type of node addition, splitting them according to a specified splitting algorithm, and determining the label of the first type of FPGA according to the distribution position after splitting.

[0052] Optionally, the mark of the first type of FPGA is determined according to the position after the segmentation, including: when determining whether a node with a label of change and a change type of node addition is segmented onto the first type of FPGA, if so, the first type of FPGA is marked as a changed FPGA; otherwise, the first type of FPGA is marked as an unchanged FPGA.

[0053] Specifically, as pointed out above, the present embodiment can include two aspects of reuse during reuse. One is that the generation process of the incremental hypergraph can be reused. The specific reuse process has been described in detail when the incremental hypergraph is generated. On the other hand, the segmentation process of the incremental hypergraph can be reused, and when the incremental hypergraph is segmented based on the historical cutting results, the labels previously marked on the hypergraph nodes will also be referred to.

[0054] For example, Figure 5 The following is a schematic diagram of the historical cutting results. First, Figure 4 In the incremental hypergraph, the nodes with the label unchanged and marked with clean, for example, the position of node l on F3 remains unchanged, the position of node k on F4 remains unchanged, and F3 and F4 are regarded as the first type of FPGA; for the nodes with the label changed and the change type is parameter change, for example, the position of node o on F2 remains unchanged, and F2 is regarded as the second type of FPGA. Among them, for the second type of FPGA, since there are changed nodes, it can be determined that the second type of FPGA has changed, and the second type of FPGA can be directly marked as a changed FPGA. However, to determine the label of the first type of FPGA, it is necessary to check whether the newly added node is split onto it. For example, when the newly added node p is split onto F3, F3 is marked as a changed FPGA. Therefore, the label type for the first type of FPGA needs to see the segmentation of the newly added node.

[0055] It should be noted that, for F1, since it simultaneously splits into a node e with a label of changed and a change type of parameter change, and a node h with a label of unchanged, the reference label of unchanged takes precedence, because as long as there is a changed node on the FPGA, the FPGA has changed compared to the previous one, so F1 is marked as a changed FPGA, such as Figure 6 What is shown is a schematic diagram of the incremental cutting result. Of course, this embodiment is only an example and does not limit the specific form of the incremental cutting result.

[0056] It is worth mentioning that in this implementation method, whether from the perspective of the hypergraph or the final cutting logic, the number of dirty nodes in the two cuts is very small, which achieves true maximum reuse. The dirty attribute is identified during the incremental cutting process, which is very convenient for subsequent processing. When selecting which nodes to use as the hypergraph, the hypergraph is incrementally generated by maximizing the reuse of the last hypergraph information, so that the difference between the two hypergraphs is as small as possible; after the user designs a certain level of flattening, each time the hypergraph is generated, the resources of the hypergraph nodes and the interconnection information between the nodes are recorded. After the hypergraph is incrementally generated, the node information of the two hypergraphs is compared, the different nodes are found, and they are marked as dirty or clean, and finally mapped to the dirty or clean state of the hypergraph nodes; after the hypergraph is selected, the last cutting result is read and reused to the maximum extent, and the same hypergraph nodes of the two hypergraphs are kept in the FPGA of the last cutting, and the newly added hypergraph nodes are cut freely; and when cutting, only the newly added nodes are cut, and the dirty or clean nodes are mapped to dirty / clean FPGAs, which are passed to the subsequent steps for use.

[0057] In the implementation mode of the present application, the incremental hypergraph is generated by maximally reusing the information of the historical design project and the historical hypergraph, so that the difference between the generated incremental hypergraph and the historical hypergraph is reduced, and the changes in the incremental hypergraph are labeled. The incremental hypergraph is incrementally cut by reusing the historical cutting results and referring to the labels, so as to achieve the best possible similarity with the historical cutting results, so that users can more easily reproduce and locate problems.

[0058] Embodiment 2

[0059] Figure 2 This is a flowchart of an incremental cutting method provided in the second embodiment of the present invention. This embodiment is based on the above embodiment. After cutting the incremental hypergraph based on the historical cutting results and referring to the labels to obtain the incremental cutting results, it also includes: mapping the nodes marked as changed to the changed FPGA, and generating a changed FPGA list according to the changed FPGA; determining the burning strategy according to the changed FPGA list, and re-burning the changed FPGA according to the burning strategy. Figure 7 As shown, the method includes:

[0060] Step S201, generating an incremental hypergraph corresponding to the current incremental design project with reference to historical design projects and historical hypergraphs.

[0061] Optionally, an incremental hypergraph corresponding to the current incremental design project is generated with reference to historical design projects and historical hypergraphs, including: determining nodes in the incremental design project that have the same identifiers as those in the historical design project and newly added nodes; determining a first type of hypergraph nodes from nodes with the same identifiers with reference to the historical hypergraph; determining a second type of hypergraph nodes from newly added nodes according to a hypergraph node selection algorithm; and constructing an incremental hypergraph based on the first type of hypergraph nodes and the second type of hypergraph nodes.

[0062] Optionally, after generating the incremental hypergraph corresponding to the current incremental design project with reference to the historical design project and the historical hypergraph, the method further includes: detecting the incremental hypergraph; and generating an alarm prompt when an abnormality is detected in the generated incremental hypergraph.

[0063] Step S202, obtaining the label of each node in the incremental hypergraph according to the historical hypergraph, and marking the label on the node.

[0064] Optionally, labels of each node in the incremental hypergraph are obtained based on the historical hypergraph, including: comparing each node in the historical hypergraph and the incremental hypergraph according to specified parameters, wherein the specified parameters include interconnection relationships and resource files; determining nodes in the incremental hypergraph that are different from the historical hypergraph and nodes that are not different based on the comparison results; determining that labels corresponding to nodes with differences are changed, and determining that labels corresponding to nodes with no differences are unchanged, wherein change types include parameter changes and node additions.

[0065] Step S203, obtaining the historical cutting results of the historical design project.

[0066] Step S204, cutting the incremental hypergraph based on the historical cutting results and referring to the labels to obtain the incremental cutting results.

[0067] Optionally, the hypergraph is cut with reference to the labels based on the historical cutting results and incremental cutting results are obtained, including: for nodes with a label of unchanged, determining that their positions on the first type of FPGA located in the historical cutting results remain unchanged; for nodes with a label of changed and a change type of parameter change, determining that their positions on the second type of FPGA located in the historical cutting results remain unchanged, and marking the second type of FPGA as a changed FPGA; for nodes with a label of changed and a change type of node addition, splitting them according to a specified splitting algorithm, and determining the label of the first type of FPGA according to the distribution position after splitting.

[0068] Optionally, the mark of the first type of FPGA is determined according to the position after the segmentation, including: when determining whether a node with a label of change and a change type of node addition is segmented onto the first type of FPGA, if so, the first type of FPGA is marked as a changed FPGA; otherwise, the first type of FPGA is marked as an unchanged FPGA.

[0069] Step S205: Map the nodes marked as changed to the changed FPGA, and generate a changed FPGA list according to the changed FPGA.

[0070] Specifically, in this embodiment, after the cutter is cut, the nodes marked as changed will be mapped to the changed FPGA, that is, the corresponding relationship between the changed nodes and the changed FPGA is established, for example, the mapping relationship between node e and F1, and the mapping relationship between nodes p and o and F2 are established. In addition, in this embodiment, a changed FPGA list will be generated according to the changed FPGA, for example, F1 and F2 are included in the changed FPGA list. Of course, this embodiment is only an example, and the number and type of the changed FPGAs included in the changed FPGA list are not specifically limited.

[0071] It should be noted that the changed FPGA list generated in this embodiment may be in the form of a chart or text. This embodiment does not limit the specific display form of the changed FPGA list, and the user may pre-set it according to actual display requirements.

[0072] Step S206, determining a programming strategy according to the changed FPGA list, and reprogramming the changed FPGA according to the programming strategy.

[0073] Among them, the FPGAs in the changed FPGA list are all the places where the current incremental design project has changed relative to the historical design project. In order to ensure that the current incremental design project can be executed normally, it is necessary to re-burn the FPGAs that have changed so that the current incremental design project can be executed normally. In addition, for FPGAs such as F3 and F4 that are not in the changed FPGA list, since they are the parts of the current incremental design project that have not occurred relative to the historical design project, they can be used directly in the current incremental design project without re-burning. Of course, in this embodiment, other related operations can also be performed according to the changed FPGA list, and it is not limited to determining the burning strategy. Users can use the generated changed FPGA list according to their needs.

[0074] It should be noted that in this implementation, when burning the FPGA in the changed FPGA list, either a parallel burning method or a parallel burning method can be used. The user can determine it according to the processing capability of the device. This implementation does not limit the specific burning method used. As long as the FPGA in the changed FPGA list can be burned efficiently and accurately, it is within the scope of protection of this application and is not limited in this implementation.

[0075] In the implementation mode of the present application, the incremental hypergraph is generated by maximally reusing the information of the historical design project and the historical hypergraph, so that the difference between the generated incremental hypergraph and the historical hypergraph is reduced, and the changes in the incremental hypergraph are labeled. The incremental hypergraph is incrementally cut by reusing the historical cutting results and referring to the labels, so as to achieve the best possible similarity with the historical cutting results, so that users can more easily reproduce and locate problems.

[0076] Embodiment 3

[0077] Figure 8 This is a schematic diagram of the structure of an incremental cutting device provided in Embodiment 3 of the present invention. Figure 8 As shown, the device includes: an incremental hypergraph generation module 310, a label marking module 320, a historical cutting result acquisition module 330 and an incremental cutting result acquisition module 340.

[0078] The incremental hypergraph generation module 310 is used to generate an incremental hypergraph corresponding to the current incremental design project by referring to the historical design project and the historical hypergraph;

[0079] A label marking module 320 is used to obtain the label of each node in the incremental hypergraph according to the historical hypergraph, and mark the label on the node, wherein the label includes changed and unchanged;

[0080] A historical cutting result acquisition module 330 is used to acquire historical cutting results of historical design projects, wherein the historical cutting results include a field programmable gate array FPGA and the distribution positions of historical hypergraph nodes on the FPGA;

[0081] The incremental cutting result acquisition module 340 is used to cut the incremental hypergraph based on the historical cutting results and reference the labels to obtain the incremental cutting results, wherein the incremental cutting results include the changed FPGA and the unchanged FPGA.

[0082] Optionally, an incremental hypergraph generation module is used to determine nodes in the incremental design project that have the same identifier as the historical design project and newly added nodes;

[0083] Determine the first type of hypergraph nodes from the nodes with the same identifier by referring to the historical hypergraph;

[0084] Determine the second type of hypergraph nodes from the newly added nodes according to the hypergraph node selection algorithm;

[0085] An incremental hypergraph is constructed based on the first-category hypergraph nodes and the second-category hypergraph nodes.

[0086] Optionally, a label marking module is used to compare each node in the historical hypergraph and the incremental hypergraph according to specified parameters, wherein the specified parameters include interconnection relationships and resource files;

[0087] Determine nodes that are different from the historical hypergraph and nodes that are not different from the incremental hypergraph according to the comparison results;

[0088] The labels corresponding to the nodes with differences are determined to be changed, and the labels corresponding to the nodes with no differences are determined to be unchanged, wherein the change types include parameter changes and node additions.

[0089] Optionally, an incremental cutting result acquisition module is used to determine that the position of the node whose label is unchanged on the first type of FPGA in the historical cutting result remains unchanged;

[0090] For the node whose label is change and whose change type is parameter change, determine that the position on the second type FPGA located in the historical cutting result remains unchanged, and mark the second type FPGA as a changed FPGA;

[0091] The nodes whose labels are changed and whose change types are node addition are segmented according to the specified segmentation algorithm, and the labels of the first type of FPGA are determined according to the distribution positions after segmentation.

[0092] Optionally, the incremental cutting result acquisition module is used to determine whether the node with the label of change and the change type of node addition is split onto the first type of FPGA. If so, the first type of FPGA is marked as a changed FPGA.

[0093] Otherwise, the first type of FPGA is marked as an unchanged FPGA.

[0094] Optionally, the device further includes a burning module, which is used to map the nodes marked as changed to the changed FPGA, and generate a changed FPGA list according to the changed FPGA;

[0095] Determine the programming strategy based on the changed FPGA list, and reprogram the changed FPGA based on the programming strategy.

[0096] Optionally, the device further includes an incremental hypergraph detection module, which is used to detect the incremental hypergraph;

[0097] Generate an alarm when an anomaly is detected in the generated incremental hypergraph.

[0098] The incremental cutting device provided in the embodiment of the present invention can execute the incremental cutting method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0099] Embodiment 4

[0100] Fig. 9A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0101] like Fig. 9 As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0102] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0103] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as the incremental cutting method.

[0104] In some embodiments, the incremental cutting method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the incremental cutting method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to perform the incremental cutting method in any other suitable manner (e.g., by means of firmware).

[0105] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0106] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0107] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0108] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0109] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0110] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0111] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0112] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An incremental cutting method, characterized in that: include: Generate an incremental hypergraph corresponding to the current incremental design project by referring to the historical design project and the historical hypergraph; Obtaining labels of each node in the incremental hypergraph according to the historical hypergraph, and marking the labels on the nodes, wherein the labels include changed and unchanged; Obtaining a historical cutting result of the historical design project, wherein the historical cutting result includes a field programmable gate array FPGA and distribution positions of historical hypergraph nodes on the FPGA; The incremental hypergraph is cut based on the historical cutting results and with reference to the labels to obtain incremental cutting results, wherein the incremental cutting results include changed FPGAs and unchanged FPGAs.

2. The method according to claim 1, characterized in that The step of generating an incremental hypergraph corresponding to the current incremental design project by referring to the historical design project and the historical hypergraph includes: Determine nodes in the incremental design project that have the same identifier as that in the historical design project and newly added nodes; Determine a first type of hypergraph node from the nodes with the same identifier by referring to the historical hypergraph; Determine a second type of hypergraph node from the newly added nodes according to a hypergraph node selection algorithm; The incremental hypergraph is constructed according to the first type of hypergraph nodes and the second type of hypergraph nodes.

3. The method according to claim 1, characterized in that: The step of obtaining the labels of each node in the incremental hypergraph according to the historical hypergraph includes: Comparing each node in the historical hypergraph and the incremental hypergraph according to specified parameters, wherein the specified parameters include interconnection relationships and resource files; Determine nodes in which the incremental hypergraph differs from the historical hypergraph and nodes in which there are no differences according to the comparison result; The labels corresponding to the nodes with differences are determined to be changed, and the labels corresponding to the nodes without differences are determined to be unchanged, wherein the change types include parameter changes and node additions.

4. The method according to claim 1, characterized in that: The step of cutting the hypergraph based on the historical cutting result and referring to the label to obtain an incremental cutting result includes: For the nodes with unchanged labels, determining that the positions of the nodes on the first type of FPGA in the historical cutting results remain unchanged; For the node whose label is change and whose change type is parameter change, determine that the position on the second type FPGA located in the historical cutting result remains unchanged, and mark the second type FPGA as the changed FPGA; The nodes whose labels are changed and whose change types are node addition are segmented according to a specified segmentation algorithm, and the labels of the first type of FPGA are determined according to the distribution positions after segmentation.

5. The method according to claim 4, characterized in that The step of determining the label of the first type of FPGA according to the segmented position includes: When determining whether a node with a label of change and a change type of node addition is segmented onto the first type of FPGA, if so, marking the first type of FPGA as the changed FPGA, Otherwise, the first type of FPGA is marked as the unchanged FPGA.

6. The method according to claim 1, characterized in that After the incremental hypergraph is cut based on the historical cutting result and with reference to the label to obtain the incremental cutting result, the method further includes: Mapping the nodes marked as changed to the changed FPGA, and generating a changed FPGA list according to the changed FPGA; A burning strategy is determined according to the changed FPGA list, and the changed FPGA is re-burned according to the burning strategy.

7. The method according to any one of claims 1 to 6, characterized in that: After the incremental hypergraph corresponding to the current incremental design project is generated by referring to the historical design project and the historical hypergraph, the method further includes: Performing detection on the incremental hypergraph; Generate an alarm when an anomaly is detected in the generated incremental hypergraph.

8. An incremental cutting device, characterized in that: The device comprises: An incremental hypergraph generation module, used to generate an incremental hypergraph corresponding to the current incremental design project by referring to the historical design project and the historical hypergraph; A label marking module, used for obtaining the label of each node in the incremental hypergraph according to the historical hypergraph, and marking the label on the node, wherein the label includes changed and unchanged; A historical cutting result acquisition module, used for acquiring the historical cutting result of the historical design project, wherein the historical cutting result includes a field programmable gate array FPGA and the distribution position of the historical hypergraph nodes on the FPGA; The incremental cutting result acquisition module is used to cut the incremental hypergraph based on the historical cutting results and refer to the labels to obtain incremental cutting results, wherein the incremental cutting results include changed FPGAs and unchanged FPGAs.

9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the method according to any one of claims 1 to 7 when executed.

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