Parasitic resistance parameter extraction method, electronic equipment and storage medium

Abstract

The invention relates to a parasitic resistance parameter extraction method, electronic equipment and a storage medium, and the method comprises the steps: obtaining the parameter information of a layout which comprises multiple layers of sub-layouts; layering grouping is conducted on the layout according to the parameter information, multiple sets of sub-layout sets are obtained, and each sub-layout set comprises at least one layer of sub-layout of the layout; and respectively processing each sub-layout set in the plurality of groups of sub-layout sets based on a plurality of first processes so as to extract parasitic resistance parameters of each sub-layout set in parallel. According to the technical scheme, the layout is hierarchically grouped and then allocated to the multiple processes for parallel processing, the data volume processed in the different processes is reasonably controlled, and therefore the accuracy and efficiency of parasitic resistance parameter extraction in the layout are improved.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a method for extracting parasitic resistance parameters, an electronic device, and a storage medium. Background Art

[0002] Parasitic resistance parameters refer to the non-ideal resistance caused by physical layout and manufacturing process in addition to the intentionally designed resistance in integrated circuit design. Parasitic resistance parameter extraction is the process of calculating the actual resistance value from the physical layout of the integrated circuit. In the process of parasitic resistance parameter extraction, EDA (Electronic Design Automation) tools need to create resistance nodes by processing the graphics of the entire layout. The layout is a planar graphic representation of the layout of transistors, resistors, capacitors and other components in the logic design and their connection relationships according to certain rules and process requirements.

[0003] In the prior art, EDA tools usually divide the layout into multiple physical areas, extract resistors independently in each area, merge these local networks to form a complete resistor network, and finally output the networks one by one to the netlist. However, as the chip scale increases, memory overruns or merging errors may occur during the merging process, which can easily affect the accuracy and efficiency of parasitic resistance parameter extraction. Summary of the invention

[0004] In response to the above technical problems, the present application provides a method for extracting parasitic resistance parameters, an electronic device, and a storage medium. By hierarchically grouping the layout and assigning it to multiple processes for parallel processing, the amount of data processed in different processes can be reasonably controlled, thereby improving the accuracy and efficiency of extracting parasitic resistance parameters in the layout.

[0005] In order to solve the above technical problems, the present application provides a method for extracting parasitic resistance parameters, the method comprising the following steps:

[0006] Acquiring parameter information of a layout, wherein the layout includes multiple layers of sub-layouts;

[0007] Hierarchically grouping the layout according to the parameter information to obtain a plurality of sub-layout sets, each of the sub-layout sets including at least one layer of sub-layouts of the layout;

[0008] Based on the multiple first processes, each sub-layout set in the multiple groups of sub-layout sets is processed respectively to extract the parasitic resistance parameters of each sub-layout set in parallel.

[0009] In some embodiments, the hierarchical grouping of the layout according to the parameter information includes at least one of the following:

[0010] hierarchically grouping the layout according to the number of layers of the layout;

[0011] hierarchically grouping the sub-layouts according to the types of the sub-layouts;

[0012] The sub-layouts are hierarchically grouped according to the complexity of the sub-layouts.

[0013] In some embodiments, the processing of each sub-layout set in the plurality of sub-layout sets based on the plurality of first processes respectively includes:

[0014] Flattening the three-dimensional graphics in each of the sub-layout sets into a two-dimensional space;

[0015] The graphics are processed in the two-dimensional space based on a preset operation, wherein the preset operation includes at least one of graphics scanning, segmentation, and merging.

[0016] In some embodiments, extracting the parasitic resistances in the plurality of sub-layout sets includes:

[0017] Obtaining the number of networks in the sub-layout set, and obtaining the number of graphics and / or the complexity of graphics in each network;

[0018] According to the number of the networks, the number of graphs in each network and / or the complexity of the graphs, the networks are grouped to obtain a plurality of sub-network sets, wherein the sub-network sets include at least one network;

[0019] Each sub-network set in the plurality of sub-network sets is processed separately based on a plurality of second processes to extract parasitic resistance parameters in the plurality of sub-network sets in parallel.

[0020] In some embodiments, grouping the networks according to the number of the networks, the number of graphs in each network and / or the complexity of the graphs comprises at least one of the following:

[0021] The number of graphs between each of the sub-network sets is equal or similar;

[0022] The graph complexity of each sub-network set is similar.

[0023] In some embodiments, the processing of each sub-network set in the plurality of sub-network sets based on the plurality of second processes respectively includes:

[0024] The corresponding sub-network set is allocated to the second process according to the load level of the second process, so that the second process achieves load balancing.

[0025] In some embodiments, extracting parasitic resistance parameters in the plurality of sub-network sets includes:

[0026] Obtaining the graphical connection status of each network in the sub-network set;

[0027] Obtaining a graphic connection pair according to the graphic connection status of the network;

[0028] constructing a resistor network model based on the graphical connection pairs;

[0029] The parasitic resistance parameters are extracted according to the resistance network model.

[0030] In some embodiments, the step of constructing a resistor network model based on the graphic connection pairs includes:

[0031] Determine at least one resistance node according to the graphical connection pair;

[0032] Sort the resistance nodes according to the directions of the graphs where the resistance nodes are located;

[0033] The adjacent resistance nodes are combined into resistance edges, and a resistance network model is constructed according to the resistance nodes and the resistance edges.

[0034] The present application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the parasitic resistance parameter extraction method as described above when executing the computer program.

[0035] The present application also provides a storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method for extracting parasitic resistance parameters as described above are implemented.

[0036] The parasitic resistance parameter extraction method, electronic device, and storage medium of the present application include: obtaining parameter information of a layout, the layout including multiple layers of sub-layouts; hierarchically grouping the layout according to the parameter information to obtain multiple sets of sub-layouts, each sub-layout set including at least one layer of sub-layouts of the layout; and processing each sub-layout set in the multiple sets of sub-layouts based on multiple first processes to extract the parasitic resistance parameters of each sub-layout set in parallel. The technical solution of the present application improves the accuracy and efficiency of parasitic resistance parameter extraction in the layout by hierarchically grouping the layout and assigning it to multiple processes for parallel processing, and reasonably controlling the amount of data processed in different processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 The diagram is a schematic diagram of dividing and merging a layout in the prior art.

[0038] Figure 2 One of the flow charts of the method for extracting parasitic resistance parameters provided in an embodiment of the present application.

[0039] Figure 3 A schematic diagram of the effect of hierarchical grouping and flattening of a layout provided in an embodiment of the present application.

[0040] Figure 4 A schematic diagram of adjacent graphic connections provided in an embodiment of the present application.

[0041] Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0043] It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.

[0044] It should be understood that, although the terms first, second, third, etc. may be used to describe various information in this article, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this article, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein can be interpreted as "at the time of..." or "when..." or "in response to determination". Furthermore, as used in this article, the singular forms "one", "one" and "the" are intended to also include plural forms, unless there is an opposite indication in the context. It should be further understood that the terms "comprising", "including" indicate that there are described features, steps, operations, elements, components, projects, kinds, and / or groups, but do not exclude the existence, occurrence or addition of one or more other features, steps, operations, elements, components, projects, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Thus, “A, B, or C” or “A, B and / or C” means “any of the following: A; B; C; A and B; A and C; B and C; A, B, and C.” An exception to this definition will occur only when a combination of elements, functions, steps, or operations are inherently mutually exclusive in some manner.

[0045] It should be understood that, although the various steps in the flowchart in the embodiment of the present application are displayed in sequence according to the indication of the arrows, these steps are not necessarily performed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and it can be performed in other orders. Moreover, at least a portion of the steps in the figure may include a plurality of sub-steps or a plurality of stages, and these sub-steps or stages are not necessarily performed at the same time, but can be performed at different times, and their execution order is not necessarily performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0046] It should be noted that in this article, step codes such as S1 and S2 are used for the purpose of expressing the corresponding content more clearly and concisely, and do not constitute a substantial limitation on the order. When implementing the step, those skilled in the art may execute S2 first and then S1, etc., but these should all be within the scope of protection of this application.

[0047] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0048] In the subsequent description, the suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present application, and have no specific meanings. Therefore, "module", "component" or "unit" can be used in a mixed manner.

[0049] In the process of extracting parasitic resistance parameters in the prior art, the layout is first divided by grid lines. Figure 1 As shown, the layout 11 is rectangular and is divided into multiple regions of equal size by multiple horizontal grid lines 12 and multiple vertical grid lines 14. Then, the local resistance network is extracted from each region respectively. The EDA tool can analyze the geometry and material properties of the graphics in the region one by one and identify the conductive path. For example, if an area contains a metal line segment, the tool estimates its resistance value based on the length, width and material of the line segment. For each region, a local resistance network is generated, which consists of resistance nodes (representing points in the circuit) and resistance edges (representing resistance) connecting these resistance nodes. Then, the local resistance networks of all regions are merged into the global resistance network of the entire layout 11. Finally, the global resistance network is converted into a netlist file in a standard format one by one.

[0050] It should be noted that a netlist is a text description that lists all resistor nodes and their resistor connection relationships. Each resistor network connection is recorded in a certain format in the netlist for subsequent circuit simulation or other analysis.

[0051] However, after the physical area division of the layout 11, the cross-area graphic 13 is divided into multiple parts. Since the graphics division and merging methods in different areas may be different, the calculated resistance networks between the various parts of the graphics 13 in different areas are very different, which in turn causes errors in the merging stage, such as false alarms of circuit short circuits.

[0052] In addition, as the chip scale increases, the number of physically divided areas on the layout increases, and the number of components and connection complexity in each area may increase, which will lead to a significant increase in the amount of data for a single local resistor network. Therefore, when merging the local resistor networks of all areas into a global resistor network for the entire layout 11, a large amount of memory will be consumed, which is prone to memory limit problems.

[0053] For the above questions, see Figure 2 The embodiment of the present application provides a method for extracting parasitic resistance parameters. The method for extracting parasitic resistance parameters can be implemented in software and / or hardware, for example, it can be specifically a computing device such as a computer or a server. The method for extracting parasitic resistance parameters provided in the embodiment includes:

[0054] S1, obtain parameter information of the layout, the layout includes multiple layers of sub-layouts.

[0055] The parameter information of the layout is used to describe the physical and chemical properties of the chip, such as geometric dimensions, material properties, capacitance parameters, resistance parameters, device parameters, connection relationships of conductors or dielectric patterns, etc. The geometric dimensions can be the dimensions of conductive materials such as metal wires or polysilicon, such as length, width, thickness, spacing between adjacent conductive materials, and the dimensions of electrical connection holes (contact holes or through holes) between different layers.

[0056] It can be understood that in integrated circuit design, the layout is a detailed graphical representation of the physical implementation of the chip. The layout can contain multiple layers of sub-layouts, each of which can reflect different materials or process steps involved in chip manufacturing, and these layers together constitute the physical structure of the chip.

[0057] S2, hierarchically grouping the layout according to the parameter information to obtain multiple groups of sub-layout sets, each of which includes at least one layer of sub-layouts of the layout.

[0058] Among them, hierarchical grouping of the layout according to the layout parameter information means taking one layer of sub-layout as the smallest grouping unit, dividing the multi-layered layout into multiple groups of sub-layout sets according to the layout parameter information, and each group of sub-layout sets includes one or more layers of sub-layouts. In this way, the efficiency of layout grouping can be improved and the large amount of calculation required for gridding the layout can be avoided.

[0059] S3, processing each sub-layout set in the multiple groups of sub-layout sets respectively based on the multiple first processes, so as to extract the parasitic resistance parameters of each sub-layout set in parallel.

[0060] Among them, the process is the basic unit for resource allocation and scheduling of the operating system. Each process has independent memory space, system resources (such as file descriptors, network connections, etc.) and execution environment. In this embodiment, after the layout is hierarchically grouped to obtain multiple groups of sub-layout sets, multiple independent first processes are started to process different sub-layout sets respectively, and the sub-layouts in the same sub-layout set are processed in the same first process to achieve efficient processing. Each first process independently extracts the parasitic resistance parameters of the sub-layout set assigned to it, reads one or more layers of sub-layout data of the corresponding sub-layout set, and calculates the parasitic resistance parameters of each layer of sub-layout in the sub-layout set one by one. In this way, the amount of data that needs to be processed by a single process is reduced, the memory requirement is reduced, and the total processing time of the layout is significantly reduced.

[0061] Through the above method, there is no need to grid the layout, which avoids the segmentation and merging of cross-region graphics after grid division, and improves the accuracy of extracting parasitic resistance parameters. At the same time, the amount of data processed in different processes can be reasonably controlled, thereby improving the efficiency of extracting parasitic resistance parameters in the layout.

[0062] In some embodiments, in step S2, hierarchical grouping of the layout according to the parameter information includes at least one of the following:

[0063] Hierarchical grouping of layouts according to the number of layers in the layout;

[0064] Hierarchical grouping of sub-layouts according to their types;

[0065] Layouts are grouped hierarchically according to the complexity of the sub-layouts.

[0066] As an implementation of this embodiment, the parameter information includes the number of layers of the layout, and the layout can be directly hierarchically grouped according to the number of layers of the layout, which can realize fast grouping of the layout, which is simple and efficient. For example, layout A is composed of 100 layers of sub-layouts, and layout A can be evenly divided into 10 groups, each group including 10 adjacent layers of sub-layouts. Of course, in other embodiments, non-average hierarchical grouping methods can also be used.

[0067] As an implementation method of this embodiment, the parameter information also includes the type of each layer of sub-layouts, and the layouts can be hierarchically grouped according to the type of sub-layouts. Different types of sub-layouts have different functions and characteristics and require different processing methods or models. Specialized processing for different types of sub-layouts can improve the accuracy and efficiency of parasitic parameter extraction.

[0068] The types of each sub-layout layer include but are not limited to a polysilicon layer, a diffusion layer, a metal layer, a contact hole layer, an isolation layer, a passivation layer, a substrate layer, and a buried layer. For example, layout B is composed of a polysilicon layer, a metal layer 1, a metal layer 2, a contact hole layer, and a diffusion layer, and layout B can be divided into four groups. The first sub-layout set includes a polysilicon layer, the second sub-layout set includes a metal layer 1 and a metal layer 2, the third sub-layout set includes a contact hole layer, and the fourth sub-layout set includes a diffusion layer.

[0069] As an implementation method of this embodiment, the complexity of the sub-layout can be calculated according to the parameter information of the layout, and the layout can be hierarchically grouped according to the complexity of the sub-layout. The sub-layout with lower complexity can be processed quickly, while the sub-layout with higher complexity can be allocated more computing resources, thereby optimizing the overall processing time. By dynamically adjusting the number of processes for processing sub-layouts with higher and lower complexity, load balancing is achieved and process utilization is improved.

[0070] The complexity of a sub-layout refers to a quantitative evaluation index extracted or calculated based on the parameter information of the sub-layout, which is used to measure the workload and technical difficulty required to process the sub-layout. In this embodiment, the complexity of the sub-layout can be evaluated in combination with multi-dimensional parameter information. The complexity of the sub-layout includes one or more of geometric complexity, electrical complexity, and functional complexity.

[0071] Optionally, the geometric complexity of the sub-layouts is comprehensively evaluated and ranked according to the number of graphics, image size and graphic complexity of each sub-layout, and the sub-layouts with high geometric complexity and low geometric complexity are staggered and balancedly grouped so that the overall geometric complexity within each group is similar.

[0072] Optionally, the electrical complexity of the sub-layouts is comprehensively evaluated and ranked according to the number of electrical networks, the number of electrical nodes, the length of the connection, the density of the connection, etc. in each sub-layout, and the sub-layouts with low electrical complexity and low electrical complexity are staggered and balancedly grouped so that the overall electrical complexity within each group is similar.

[0073] Optionally, the functional complexity of the sub-layouts is comprehensively evaluated and ranked according to the number of functional modules and the complexity of the functional modules of each sub-layout, and the sub-layouts with low functional complexity and low functional complexity are staggered and balanced to make the overall functional complexity in each grouping similar. Functional module refers to an independent part with a specific function in a chip. The functional module is usually responsible for performing a specific task and can work with other modules to realize the function of the entire chip. Functional modules include but are not limited to a central processing unit (CPU), a graphics processing unit (GPU), a memory module, an input and output interface, an analog-to-digital converter, a digital-to-analog converter, a power management unit (PMU), a communication module, a sensor interface, a timer, a counter, a display controller, and an audio processing module.

[0074] Optionally, based on the aforementioned indicators such as geometric complexity, electrical complexity, and functional complexity, a comprehensive complexity score is calculated for each layer of sub-layout as the complexity of the sub-layout. The weighted average method can be used to integrate the various indicators, assign weights to each indicator, and then calculate the weighted average as the final complexity score. According to the calculated complexity score, each layer of sub-layout is divided into different complexity levels or groups. For example, the layers with higher complexity scores can be independently grouped together, and the layers with lower complexity can be grouped together, so that the complexity scores within each group are generally similar.

[0075] In some embodiments, in step S3, processing each sub-layout set in the plurality of sub-layout sets respectively based on the plurality of first processes includes:

[0076] Flatten the three-dimensional graphics in each sub-board set into a two-dimensional space;

[0077] The graphics are processed in a two-dimensional space based on a preset operation, where the preset operation includes at least one of graphics scanning, segmentation, and merging.

[0078] Among them, expanding the three-dimensional graphics in the sub-layout set means dividing the three-dimensional graphics in the space into corresponding layers according to the settings in the layout design. Specifically, according to the layout design rules, the graphics in the three-dimensional space are distributed to different two-dimensional layers according to specific levels, so that the stacked or overlapping structures in the three-dimensional space are decomposed and placed on their corresponding two-dimensional layers. Figure 3 It reflects the process of expanding the layer group data (layerDataGroup) and reflecting the top-level design (topdesign). Among them, the layer group data refers to the collection of multi-layer sub-layouts, and the top-level design refers to the connection relationship and overall layout between the sub-layouts of each layer. Figure 3 As shown, Figure 3 The multi-layer stacked sub-layout shown in (a) is flattened to Figure 3 (b) shows a two-dimensional plane, so that the two-dimensional plane contains all the graphics in the multi-layer sub-layout set, and the graphics are in a flattened state. In this way, the graphics in the three-dimensional space are projected onto the two-dimensional plane, and the graphic elements of different heights are placed on the corresponding layers to form a series of two-dimensional planes, so that the graphics of each layer can be processed independently.

[0079] Next, the flattened graphics are further processed, such as scanning, segmentation, merging, etc. Scanning refers to scanning the flattened graphics to identify each graphic element. Segmentation refers to dividing a complex graphics into smaller parts for easy calculation. Merging refers to merging adjacent small parts into a larger graphics as needed to simplify subsequent processing.

[0080] In some embodiments, in step S3, extracting parasitic resistances in multiple sets of sub-layout sets includes:

[0081] Get the number of networks in the sub-layout set, the number of graphics in each network and / or the complexity of the graphics;

[0082] According to the number of networks, the number of graphs in each network and / or the complexity of the graphs, the networks are grouped to obtain a plurality of sub-network sets, each of which includes at least one network;

[0083] Based on the plurality of second processes, each sub-network set in the plurality of sub-network sets is processed respectively, so as to extract the parasitic resistance parameters in the plurality of sub-network sets in parallel.

[0084] Among them, on the basis of hierarchical grouping of the layout, when processing each group of sub-layout sets, the sub-layout sets can continue to be grouped to further improve the processing efficiency. First, extract the number of networks in the sub-layout, and count the number of graphics on each network and / or evaluate the complexity of the graphics. The graphics represent the actual physical structure, such as polygons, line segments, etc. After statistics, you can know the number of graphics that each sub-network set can accommodate. For example, there are 100,000 graphics in total and 10 sub-network sets, then each sub-network set can accommodate about 10,000 graphics, so that the number of graphics in the network combination will not differ too much. For the evaluation of graphic complexity, it can be comprehensively measured by a variety of indicators, such as the number of polygons, area, perimeter, spacing, regular symmetry, etc.

[0085] It should be noted that a network refers to an electrical network with specific functions that has been defined in the layout design. The network is usually defined by the designer during the circuit design stage and implemented in the layout. Each network can contain multiple graphics (such as polygons, line segments, etc.), which represent the actual physical structure, such as metal wires, polysilicon layers, etc.

[0086] Next, the network is divided into multiple sub-network sets, each of which contains at least one network. The networks can be grouped according to the number of graphs and / or the complexity of the graphs contained in each network to ensure that the load of each sub-network set is relatively balanced, thereby improving the efficiency of parallel processing.

[0087] After the networks in the sub-layout are grouped to obtain multiple groups of sub-network sets, multiple independent second processes are started to process different sub-network sets respectively. The networks in the same network set are processed in the same second process, and the graphics in the same network are also centrally processed in the second process to achieve efficient processing. Each second process extracts the parasitic resistance parameters of each network in the sub-network set assigned to it. In this way, efficient parallel computing is achieved through network grouping and multi-process processing, further reducing the amount of data that needs to be processed by a single process.

[0088] In this embodiment, one or more networks on one or more layers of sub-layouts in a sub-layout set are processed as a whole, which can maintain the integrity and coherence of the network and avoid data segmentation and reorganization problems caused by regional division. At the same time, multiple networks are grouped to form a network combination. Each network combination contains a group of related networks, which can be processed independently, and each network combination is processed by an independent process, thereby realizing parallel computing.

[0089] In some embodiments, the networks are grouped according to the number of networks, the number of graphs in each network, and the complexity of the graphs, including at least one of the following:

[0090] The number of graphs between each set of subnetworks is equal or similar;

[0091] The graph complexity among each set of subnetworks is similar.

[0092] As an implementation method of this embodiment, the number of graphics between each sub-network set is made equal or close. For example, there are three networks on the sub-layout C. According to statistics, there are 50 graphics in the E network, 100 graphics in the F network, and 60 graphics in the G network. If load balancing is not considered, the E network and the F network can be divided into Group A, and the G network can be divided into Group B. In this way, the difference in the number of graphics between the two groups is large, resulting in an unbalanced load on the computer. Considering the situation of load balancing, the E network and the G network can be divided into Group A, and the F network can be divided into Group B. In this way, the number of graphics in Groups A and B is close, so that the load of the computer is balanced.

[0093] As an implementation method of this embodiment, the graphic complexity of each sub-network set is made similar. The graphic complexity of each network can be calculated by quantitatively calculating the number of polygons, area, perimeter, spacing, regular symmetry and other indicators, and assigning weights to each indicator to calculate a comprehensive complexity score. Then, multiple networks in the sub-layout are grouped according to the graphic complexity to reasonably control the data processing volume of the second process of each processing sub-network set.

[0094] As an implementation method of this embodiment, the number of graphics between each sub-network set is equal or similar, and the complexity of graphics between each sub-network set is similar. The multiple networks in the sub-layout are grouped based on the number of graphics and the complexity of graphics to ensure that the number of graphics between each sub-network set is equal or similar, and the complexity of graphics is similar.

[0095] In some embodiments, processing each sub-network set in the plurality of sub-network sets respectively based on the plurality of second processes includes:

[0096] A corresponding sub-network set is allocated to the second process according to the load level of the second process, so that the second process achieves load balancing.

[0097] Among them, when the second process processes a sub-network set, the sub-network set processed in each process can be adjusted in real time. During the operation, the sub-network set is dynamically allocated according to the current load of each process. If a process is lightly loaded, more sub-network sets can be allocated to it; conversely, if a process is heavily loaded, the amount of tasks allocated to it can be reduced. Ensure that the workload of each process is roughly equal to avoid the situation where some processes are overloaded while other processes are idle. It helps to maximize the use of computing resources and improve overall processing efficiency.

[0098] In some embodiments, extracting parasitic resistance parameters from multiple groups of sub-network sets includes:

[0099] Get the graph connection status of each network in the sub-network collection;

[0100] Obtaining a graphic connection pair according to the graphic connection status of the network;

[0101] Construct resistor network models based on graphical connection pairs;

[0102] Extract parasitic resistance parameters based on the resistor network model.

[0103] In each sub-network set, the EDA tool creates a resistor network model by network. The resistor network model is an abstract model generated by scanning and processing the graphics in the known network during the parasitic parameter extraction process. The abstract model is a representation method generated by simplifying and transforming the graphical connection of the circuit, which is used to efficiently extract and analyze parameters such as parasitic resistance. The resistor network model is used to represent the resistor elements in the network and their connection relationships.

[0104] The process of creating a resistor network first scans the graphics in the network to obtain multiple graphics used to form a network and the connection between the graphics. If there is a connection between two graphics, a connection pair is constructed to represent the connection relationship between the graphics. After the entire network is scanned, the connection pairs are recorded and resistor nodes are constructed at the connection between the graphics. Figure 4 As shown, there is a connection edge 20 between the graph I and the graph J, and a resistance node can be set on the connection edge 20. Preferably, the resistance node is set at the center point of the connection edge 20. Adjacent resistance nodes are connected in sequence to form a resistance edge, and the value of the resistance edge is the resistance value.

[0105] As a result, the EDA tool can create resistor nodes based on the graphics of the entire layout, connect each resistor node to build a resistor network model, and then calculate the parasitic resistance parameters in the resistor network model. In the entire process of creating the resistor network, the traditional physical area division method is not used, but the resistor network is directly created for the entire network. The complexity and potential problems caused by area division and subsequent merging are avoided. By directly processing the entire network, a complete resistor network model can be built at one time to ensure its consistency and integrity. Therefore, no merging steps are required in the entire process, which simplifies the processing flow and improves the calculation efficiency and accuracy of the results.

[0106] In some embodiments, constructing a resistor network model based on the graphical connection pairs includes:

[0107] Determine at least one resistance node according to the graphical connection pair;

[0108] Sort the resistor nodes according to the direction of the graph where they are located;

[0109] Adjacent resistance nodes are combined into resistance edges, and a resistance network model is constructed based on the resistance nodes and resistance edges.

[0110] Among them, after determining at least one resistance node according to the connection pair of the graph, the resistance nodes are sorted according to the horizontal coordinate value or the vertical coordinate value according to the direction of the graph where the resistance node is located, and the resistance node sequence of the graph is obtained. For example, if the graph is distributed horizontally, a coordinate system is established on the graph, and the coordinate values ​​of each resistance node on the graph can be obtained. The resistance nodes are sorted according to the size of the horizontal coordinate of the resistance node, which can be in ascending or descending order. Similarly, if the graph is distributed vertically, a coordinate system is established on the graph, and the coordinate values ​​of each resistance node on the graph can be obtained. The resistance nodes are sorted according to the size of the vertical coordinate of the resistance node, which can be in ascending or descending order. Then, the adjacent resistance nodes in the resistance node sequence are connected to form resistance edges, and each resistance edge represents a section of conductor with a certain resistance value. A resistance network model is constructed by resistance nodes and resistance edges.

[0111] In some embodiments, after the resistor network model is constructed, the resistance formula can be used to calculate the resistance value of each resistor edge, and the calculated resistance value can be updated to the resistor network model and stored on the corresponding resistor edge. Then, the resistor network model is converted into a netlist output for easy reading and processing by EDA tools. The netlist usually contains information such as node number, resistance value, connection relationship, etc. Next, the EDA tool is used to output the resistance value of each network, that is, the value stored on the resistor edge.

[0112] In some embodiments, after processing the graph to obtain connection pairs, the process effects (such as temperature effects, material property changes, etc.) are calculated. According to the processed graph connection pairs and the calculated process effects, resistor nodes and resistor edges are created to form a resistor network model. Before creating the resistor network model, a more accurate resistance value is obtained based on the calculation results of the process effects, thereby improving the accuracy and consistency of the resistor network.

[0113] The method for extracting parasitic resistance parameters of the present application includes: obtaining parameter information of a layout, the layout including multiple layers of sub-layouts; hierarchically grouping the layout according to the parameter information to obtain multiple sets of sub-layouts, each of which includes at least one layer of sub-layouts of the layout; and processing each sub-layout set in the multiple sets of sub-layouts based on multiple first processes to extract the parasitic resistance parameters of each sub-layout set in parallel. The technical solution of the present application improves the accuracy and efficiency of extracting parasitic resistance parameters in the layout by hierarchically grouping the layout and assigning it to multiple processes for parallel processing, and reasonably controlling the amount of data processed in different processes.

[0114] Based on the same inventive concept as the above embodiments, an embodiment of the present invention provides an electronic device, such as Figure 5As shown, the electronic device includes: a processor 310 and a memory 311 storing a computer program; wherein, Figure 5 The processor 310 shown in the figure is not used to indicate that the number of the processor 310 is one, but is only used to indicate the positional relationship of the processor 310 relative to other devices. In actual applications, the number of the processor 310 may be one or more; similarly, Figure 5 The memory 311 shown in the figure has the same meaning, that is, it is only used to refer to the position relationship of the memory 311 relative to other devices. In practical applications, the number of memories 311 can be one or more. When the processor 310 runs the computer program, the parasitic resistance parameter extraction method applied to the above electronic device is implemented.

[0115] The electronic device may also include: at least one network interface 312. The various components in the electronic device are coupled together via a bus system 313. It is understood that the bus system 313 is used to achieve connection and communication between these components. In addition to the data bus, the bus system 313 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, the bus system 313 is not used in the following examples. Figure 5 Various buses are labeled as bus system 313.

[0116] The memory 311 may be a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memories. The nonvolatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory, a magnetic surface memory, an optical disk, or a compact disc read-only memory (CD-ROM); the magnetic surface memory may be a disk memory or a tape memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SDRAM), and so on.

[0117] (SLDRAM, SyncLink Dynamic Random Access Memory), Direct Rambus Random Access Memory (DRRAM, Direct Rambus Random Access Memory). The memory 311 described in the embodiment of the present invention is intended to include but is not limited to these and any other suitable types of memory.

[0118] The memory 311 in the embodiment of the present invention is used to store various types of data to support the operation of the electronic device. Examples of these data include: any computer program used to operate on the electronic device, such as an operating system and an application; contact data; phone book data; messages; pictures; videos, etc. Among them, the operating system includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., which are used to implement various basic services and process hardware-based tasks. The application program may include various applications, such as a media player (Media Player), a browser (Browser), etc., which are used to implement various application services. Here, the program that implements the method of the embodiment of the present invention may be included in the application program.

[0119] Based on the same inventive concept as the above-mentioned embodiment, this embodiment further provides a storage medium, in which a computer program is stored. The storage medium may be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM); it may also be various devices including one or any combination of the above-mentioned memories, such as a mobile phone, a computer, a tablet device, a personal digital assistant, etc. When the computer program stored in the storage medium is executed by the processor, the above-mentioned method for extracting parasitic resistance parameters is implemented. For the specific steps implemented when the computer program is executed by the processor, please refer to Figure 2 The description of the illustrated embodiment will not be repeated here.

[0120] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0121] In this document, the terms "comprises," "comprising," or any other variations thereof, are intended to cover a non-exclusive inclusion of elements other than those listed and may also include additional elements not expressly listed.

[0122] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for extracting parasitic resistance parameters, characterized in that: The method comprises the following steps: Acquiring parameter information of a layout, wherein the layout includes multiple layers of sub-layouts; Hierarchically grouping the layout according to the parameter information to obtain a plurality of sub-layout sets, each of the sub-layout sets including at least one layer of sub-layout of the layout; Based on the multiple first processes, each sub-layout set in the multiple groups of sub-layout sets is processed respectively to extract the parasitic resistance parameters of each sub-layout set in parallel.

2. The method according to claim 1, characterized in that The hierarchical grouping of the layout according to the parameter information includes at least one of the following: hierarchically grouping the layout according to the number of layers of the layout; hierarchically grouping the sub-layouts according to the types of the sub-layouts; The sub-layouts are hierarchically grouped according to the complexity of the sub-layouts.

3. The method according to claim 1, characterized in that: The method of processing each sub-layout set in the plurality of sub-layout sets based on the plurality of first processes respectively includes: Flattening the three-dimensional graphics in each of the sub-layout sets into a two-dimensional space; The graphics are processed in the two-dimensional space based on a preset operation, wherein the preset operation includes at least one of graphics scanning, segmentation, and merging.

4. The method according to claim 1, characterized in that The extracting the parasitic resistances in the plurality of sets of sub-layouts includes: Obtaining the number of networks in the sub-layout set, and obtaining the number of graphics and / or the complexity of graphics in each network; According to the number of the networks, the number of graphs in each network and / or the complexity of the graphs, the networks are grouped to obtain a plurality of sub-network sets, wherein the sub-network sets include at least one network; Each sub-network set in the plurality of sub-network sets is processed separately based on a plurality of second processes to extract parasitic resistance parameters in the plurality of sub-network sets in parallel.

5. The method according to claim 4, characterized in that The grouping of the networks according to the number of the networks, the number of graphs in each network and / or the complexity of the graphs comprises at least one of the following: The number of graphs between each of the sub-network sets is equal or similar; The graph complexity of each sub-network set is similar.

6. The method according to claim 4, characterized in that The processing of each sub-network set in the plurality of sub-network sets based on the plurality of second processes respectively includes: The corresponding sub-network set is allocated to the second process according to the load level of the second process, so that the second process achieves load balancing.

7. The method according to claim 4, characterized in that The extracting of parasitic resistance parameters from the plurality of sub-network sets comprises: Obtaining the graphical connection status of each network in the sub-network set; Obtaining a graphic connection pair according to the graphic connection status of the network; constructing a resistor network model based on the graphical connection pairs; The parasitic resistance parameters are extracted according to the resistance network model.

8. The method according to claim 7, characterized in that The step of constructing a resistor network model based on the graphic connection pairs includes: Determine at least one resistance node according to the graphical connection pair; Sort the resistance nodes according to the directions of the graphs where the resistance nodes are located; The adjacent resistance nodes are combined into resistance edges, and a resistance network model is constructed according to the resistance nodes and the resistance edges.

9. An electronic device, characterized in that: The method comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 1 to 8 when executing the computer program.

10. A storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 8 is implemented.

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