Radiation-resistant standard cell library layout design method, device and equipment

Abstract

In order to overcome the problems of long time consumption, long cycle, low efficiency and high cost in layout design in the prior art, the present invention proposes a method, device and equipment for designing a radiation-resistant standard cell library layout. The design method generates layout process transplantation rules by obtaining the design rule files of the original process and the target process commercial library, and further generates radiation-resistant layout process transplantation rules in combination with the target process radiation-resistant design rules. The original process radiation-resistant standard cell library layout is transplanted according to the radiation-resistant layout process transplantation rules to generate the target process radiation-resistant standard cell library layout. The design method ensures that the radiation-resistant standard cell library layout has the characteristics of short design cycle, high efficiency, low cost and flexible configuration. The radiation-resistant standard cell library layout designed based on the present invention is suitable for the design of aerospace-grade integrated circuits, which greatly reduces the process manufacturing cost.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, in particular to the field of layout design of radiation-resistant integrated circuits, and specifically to a method, device and equipment for designing the layout of a radiation-resistant standard cell library. Background Art

[0002] With the rapid development of the country's aerospace industry and the rapid progress of integrated circuit process technology, the design requirements for aerospace-grade integrated circuits are getting higher and higher. They need to have strong radiation resistance to resist various charged particles such as galactic cosmic rays, solar cosmic rays, and earth radiation belt particles in the space environment and other radiation sources. Special design processes and materials need to be used during design to enhance the integrated circuit chip's resistance to radiation and effectively reduce radiation damage to the chip.

[0003] At present, in the prior art, the design of radiation-resistant integrated circuits can adopt a full-custom design method, including but not limited to the following steps: in accordance with the requirements of design compromises and design specifications, in accordance with the specific technical requirements involved in the method, the circuit design of radiation-resistant standard cells is carried out one by one, and the designed radiation-resistant standard cells are laid out according to a specific cell height and a specific arrangement. After the layout is drawn, the radiation-resistant performance of each unit is iteratively verified. However, due to the large number of standard cells mentioned above, the layout drawing and design in the process are very time-consuming, and the workload of radiation-resistant performance verification is huge, resulting in a long design cycle and high cost, and it is impossible to complete the delivery of the fully customized design of radiation-resistant integrated circuits in a short period of time.

[0004] The standard cell layout in the standard cell library is carefully designed and iteratively verified, and can be stored in the database for design. It can be seen that the importance of standard cell library design as a bridge from digital logic design to chip physical implementation is self-evident. At the same time, in order to accelerate the development of aerospace-grade integrated circuit design, it is necessary to establish a set of radiation-resistant standard cell libraries suitable for space integrated circuits.

[0005] The layout design of the radiation-resistant standard cell library is an important part of the semi-custom design process of radiation-resistant integrated circuits. If the time consumption of the layout design of the radiation-resistant standard cell library can be reduced, the design time of the corresponding integrated circuit semi-custom design method can be greatly reduced, and the integrated circuit process efficiency can be improved by shortening the design cycle, thereby achieving the goal of reducing the design and process production costs.

[0006] Process migration in the field of integrated circuit design is the process of optimizing the integrated circuit designed under the original process conditions into the integrated circuit under the target process through a series of migration processes. The commercial library layouts of different processes are designed according to specific rules, and the radiation-resistant standard cell library is obtained by radiation-resistant reinforcement on the basis of the commercial library. Therefore, it is possible to similarly consider the migration operation of the radiation-resistant standard cell library layout based on the existing process to generate the radiation-resistant standard cell library layout of the target process. Summary of the invention

[0007] In view of this, in order to solve the problems of long design time, long cycle, low efficiency and high cost in the prior art, the present invention provides a radiation-resistant standard cell library layout design method, device and equipment. The radiation-resistant standard cell library layout design method has the characteristics of short cycle, high efficiency and low design cost.

[0008] A method for designing a layout of a radiation-resistant standard cell library is disclosed. The method performs standard cell layout design based on a process transplantation method, and comprises the following steps:

[0009] Step S110: obtaining a first design rule file of an original process commercial library and a second design rule file of a target process commercial library, wherein both the first design rule file and the second design rule file contain multiple pieces of process information, and the process information is used as input data for computer processing;

[0010] Step S120: Compare the process information described in the first design rule file and the second design rule file for similarities and differences; use the data results of the similarities and differences comparison to design a commercial library layout process transplantation rule for transplanting the layout of the target process commercial library in a high-level programming language; combine the commercial library layout process transplantation rule with the target process radiation-resistant design rule to generate a radiation-resistant layout process transplantation rule;

[0011] Step S130: performing a process transplantation operation on the original process radiation-resistant standard cell library layout according to the radiation-resistant layout process transplantation rule obtained in step S120, generating a target process radiation-resistant standard cell library layout, and recording it in a file “all.gds”;

[0012] Step S140: verifying whether the radiation resistance performance of the target process radiation resistance standard cell library layout meets the target process design requirements. If the verification fails, optimizing the radiation resistance reinforcement until the design requirements are met.

[0013] Step S150: outputting design data of a target process radiation-resistant standard cell library layout that meets the target process design requirements.

[0014] Specifically, the process information includes:

[0015] The layer name, GDS number and data type defined in the first layer information file in the original process program and the second layer information file in the target process program; each of the three types of information, namely, the layer name, GDS number and data type, is not completely the same in the first layer information file and the second layer information file;

[0016] In the original process commercial library and the target process commercial library, the respective standard cell layouts adopt a unified design height, and the design height is an integer multiple of the width of the metal wiring track in the corresponding standard cell layout;

[0017] The standard cell layout structure follows the minimum width, minimum height and minimum area principles;

[0018] The centerline position of the standard cell layout structure;

[0019] NMOS and PMOS area division in the standard cell layout structure;

[0020] The gate length and source-drain region length of the process node;

[0021] The location of the boundary layer, the size of the via, and the distance from the via to the active area boundary.

[0022] Preferably, the commercial library layout process transplantation rules include rules for transplanting and converting all the process information in the original process and the target process, and the rules for transplanting and converting all the process information include scaling by a proportional factor and offsetting the setting position.

[0023] Preferably, the target process radiation resistance design rules include the distance design rules from the well contact to the transistor in the standard cell layout structure, the minimum distance design rules from the active area of ​​the PMOS tube to the N well, the minimum distance design rules from the active area of ​​the NMOS tube to the N well and the width design rules of the well contact.

[0024] Further, suppose is the total number of standard cells in the target process radiation-resistant standard cell library layout, and the variable Mark the first Radiation-resistant standard units, , The initial value of is set to 1, then the process of generating the target process radiation-resistant standard cell library layout in step S130 specifically includes:

[0025] Step S131: extract the first A radiation-resistant standard cell layout;

[0026] Step S132: The radiation-resistant standard cell layout is subjected to a process transplantation operation according to the radiation-resistant layout process transplantation rule to generate the target process radiation-resistant standard cell library layout. The process transplantation operation includes performing the first The relative position layout of transistors and consistent metal wiring of a radiation-resistant standard cell layout;

[0027] Step S133: The radiation-resistant standard cell layout is checked for DRC and LVS to check whether the layout design meets the manufacturing reliability requirements and whether new errors are introduced after the process migration operation; if the above check fails, the layout is manually modified and the above check is performed again until the check passes; if the above check passes, the first step in the current target process is saved. The radiation-resistant standard cell layout data is used as the first A radiation-resistant standard cell layout is saved in the file "all.gds";

[0028] Step S134: When When , return to step S131 until , ending the loop.

[0029] Preferably, the process of manually modifying the layout in step S133 includes manually adjusting the positions of the metal lines and the positions of the through holes.

[0030] The present invention protects a radiation-resistant standard cell library layout design device, which uses the steps of the above method to design a radiation-resistant standard cell library layout based on process transplantation, and the device includes the following modules:

[0031] A data input module, used to obtain a first design rule file of an original process commercial library and a second design rule file of a target process commercial library, and use the multiple pieces of process information contained in the first design rule file and the second design rule file as input data for computer processing;

[0032] A process transplantation rule design module is used to compare the process information described in the first design rule file and the second design rule file for similarities and differences; using the data results of the similarities and differences comparison, a commercial library layout process transplantation rule for performing a transplantation operation on the layout of the target process commercial library is designed in a high-level programming language; the commercial library layout process transplantation rule is combined with the target process radiation-resistant design rule to generate a radiation-resistant layout process transplantation rule;

[0033] A radiation-resistant standard cell library layout generation module, used to generate a target process radiation-resistant standard cell library layout using the radiation-resistant layout process migration rule obtained by the process migration rule design module, and record it in a file "all.gds";

[0034] The radiation resistance performance verification and reinforcement module is used to verify whether the radiation resistance performance of the target process radiation resistance standard cell library layout meets the target process design requirements. If the verification fails, the radiation resistance reinforcement optimization is performed until the design requirements are met.

[0035] The data output module is used to output the design data of the target process radiation-resistant standard cell library layout that meets the target process design requirements.

[0036] In addition, the present invention also protects a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the aforementioned radiation-resistant standard cell library layout design method when executing the computer program.

[0037] In summary, the present invention provides a method, device and equipment for designing a radiation-resistant standard cell library layout. Compared with the prior art, the method, device and equipment form a commercial library layout process transplantation rule by acquiring the commercial library layout design rules of the original process and the target process, and form the radiation-resistant layout process transplantation rule after combining the radiation-resistant design rules of the target process. The radiation-resistant standard cell library layout of the original process is transplanted according to the radiation-resistant layout process transplantation rule to form the radiation-resistant standard cell library layout of the target process. Since the design method is based on the existing radiation-resistant standard cell library layout process, the standard cell layout of the original process is adjusted and transplanted according to the unified transplantation rule to obtain the corresponding standard cell layout in the target process, without the need to redesign a single standard cell layout, and is easy to implement computer program-aided design, ensuring the characteristics of low cost, short cycle, high efficiency and flexible configuration of the radiation-resistant standard cell library layout design. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a flow chart of a method for designing a layout of a radiation-resistant standard cell library in the first embodiment of the present invention;

[0039] Figure 2 Schematic diagram of transistor layout of radiation-resistant standard cell layout design in the original process and the target process in the first embodiment of the present invention, wherein: (a) is a schematic diagram of transistor layout of radiation-resistant standard cell layout design in the original process, specifically is the unit layout design height, is the distance from the well contact to the transistor, It is the minimum distance from the active area of ​​the PMOS tube to the N well. It is the minimum distance from the active area of ​​the NMOS tube to the N well. is the width of the well contact; (b) is a schematic diagram of the transistor layout designed for the radiation-resistant standard cell layout in the target process, specifically is the unit layout design height, is the distance from the well contact to the transistor, It is the minimum distance from the active area of ​​the PMOS tube to the N well. It is the minimum distance from the active area of ​​the NMOS tube to the N well. is the width of the well contact;

[0040] Figure 3 This is a full flow chart of the steps and procedures for implementing a method for designing a layout of a radiation-resistant standard cell library in the second embodiment of the present invention. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0042] In a first embodiment, the present invention proposes a method for designing a layout of a radiation-resistant standard cell library, such as Figure 1 As shown, the method performs standard cell layout design based on process transplantation, and the specific steps include:

[0043] Step S110: obtaining a first design rule file of an original process commercial library and a second design rule file of a target process commercial library, wherein both the first design rule file and the second design rule file contain multiple pieces of process information, and the process information is used as input data for computer processing;

[0044] Step S120: Compare the process information described in the first design rule file and the second design rule file for similarities and differences; use the data results of the similarities and differences comparison to design a commercial library layout process transplantation rule for transplanting the layout of the target process commercial library in a high-level programming language; combine the commercial library layout process transplantation rule with the target process radiation-resistant design rule to generate a radiation-resistant layout process transplantation rule;

[0045] Step S130: performing a process transplantation operation on the original process radiation-resistant standard cell library layout according to the radiation-resistant layout process transplantation rule obtained in step S120, generating a target process radiation-resistant standard cell library layout, and recording it in a file “all.gds”;

[0046] Step S140: verifying whether the radiation resistance performance of the target process radiation resistance standard cell library layout meets the target process design requirements. If the verification fails, optimizing the radiation resistance reinforcement until the design requirements are met.

[0047] Step S150: outputting design data of a target process radiation-resistant standard cell library layout that meets the target process design requirements.

[0048] The original process commercial library refers to a commercial integrated circuit standard cell database (commercial library) under existing process conditions provided by semiconductor manufacturers on the market, including existing process technology parameter information (hereinafter referred to as process information) and design rule files. For example, the original process commercial library can be a commercial library for 55nm CMOS process.

[0049] The target process commercial library refers to a commercial library of another process whose process information and design rule files match the target requirements based on the design requirements of the target integrated circuit unit library, so as to adapt to the new target process flow and equipment, such as the commercial library of 40nm CMOS process or other node CMOS process.

[0050] Specifically, in step S110, both the first design rule file and the second design rule file involve manufacturing processes and process information thereof, and the process information includes:

[0051] The layer name, GDS number and data type defined in the first layer information file in the original process program and the second layer information file in the target process program; each of the three types of information, namely, the layer name, GDS number and data type, is not completely the same in the first layer information file and the second layer information file;

[0052] In the original process commercial library and the target process commercial library, the respective standard cell layouts adopt a unified design height, and the design height is an integer multiple of the width of the metal wiring track in the corresponding standard cell layout;

[0053] The standard cell layout structure follows the minimum width, minimum height and minimum area principles;

[0054] The centerline position of the standard cell layout structure;

[0055] NMOS and PMOS area division in the standard cell layout structure;

[0056] The gate length and source-drain region length of the process node;

[0057] The location of the boundary layer, the size of the via, and the distance from the via to the active area boundary.

[0058] Specifically, the commercial library layout process migration rules in step S120 include:

[0059] Rules for migration and conversion of layer names, GDS numbers and data types defined in the layer information files of the original process and the target process;

[0060] Rules for converting the unit height, minimum width, minimum height and minimum area principles in the original process and the target process;

[0061] Rules for transplanting and converting the centerline positions of the cell layout structures of the original process and the target process;

[0062] The rules for transplanting and converting the gate length and source / drain length of the original process and the target process;

[0063] The rules for transplanting and converting the position of the boundary layer between the original process and the target process, the size of the through hole, the distance from the through hole to the active area boundary, etc.

[0064] Preferably, the rules for transplanting and converting all the aforementioned process information include scaling by a proportional factor and offsetting the setting position.

[0065] The target process radiation resistance design rules include:

[0066] Design rules for the distance from the well contact to the transistor in the target process standard cell layout structure;

[0067] The minimum distance design rule from the active area of ​​the PMOS tube to the N-well in the target process standard cell layout structure;

[0068] The minimum distance design rule from the NMOS tube active area to the N well in the target process standard cell layout structure;

[0069] Width design rules for well contacts in target process standard cell layout structure.

[0070] In this embodiment, if Figure 2 As shown in (a), in the original process standard unit layout structure: the unit layout design height is , the distance from the well contact to the transistor is , the minimum distance from the active area of ​​the PMOS tube to the N well is , the minimum distance from the NMOS tube active area to the N well is , the width of the well contact is .like Figure 2 As shown in (b), in the target process standard unit layout structure: the unit layout design height is , the distance from the well contact to the transistor is , the minimum distance from the active area of ​​the PMOS tube to the N well is , the minimum distance from the NMOS tube active area to the N well is , the width of the well contact is The design parameter values ​​in the target process standard cell layout and , is the design parameter value in the original process standard cell layout and The result is obtained after transplantation and conversion according to the radiation-resistant layout process transplantation rules.

[0071] In the second embodiment of the present invention, is the total number of standard cells in the target process radiation-resistant standard cell library layout, and the variable Mark the first Radiation-resistant standard units, , The initial value of is set to 1, then the process of generating the target process radiation-resistant standard cell library layout in step S130 specifically includes:

[0072] Step S131: extract the first A radiation-resistant standard cell layout;

[0073] Step S132: The radiation-resistant standard cell layout is subjected to a process transplantation operation according to the radiation-resistant layout process transplantation rule described in step S120 to generate the target process radiation-resistant standard cell library layout. The process transplantation operation includes performing the first The relative position layout of transistors and consistent metal wiring of a radiation-resistant standard cell layout;

[0074] Step S133: The radiation-resistant standard cell layout is subjected to a design rule check (DRC) and a layout versus schematic (LVS) check to check whether the layout design meets the manufacturing reliability requirements and whether new errors are introduced after the process migration operation. If the check fails, the layout is manually modified and the above check is performed again until the check passes. If the check passes, the first step in the current target process is saved. The radiation-resistant standard cell layout data is used as the first A radiation-resistant standard cell layout is saved in the file "all.gds";

[0075] Step S134: When When , return to step S131 until , ending the loop.

[0076] Specifically, in step S132, the transistor layout diagram of the cell layout in the radiation-resistant standard cell library in the original process is as follows: Figure 2 As shown in (a), according to the radiation-resistant layout process migration rule, the target process generated by process migration is The relative positions of transistors in the radiation-resistant standard cell layout are as follows: Figure 2 As shown in (b), directly refer to the radiation-resistant layout process migration rules to transfer the original process The metal wiring pattern of the radiation-hardened standard cell layout is transplanted to the target process The target process is generated on the radiation-resistant standard cell layout. A radiation-resistant standard cell layout.

[0077] Specifically, the design rule check (DRC) is a very important step in the integrated circuit design process. The main inspection contents include: minimum size feature check, minimum spacing check, inter-layer alignment check, through-hole and conductor spacing check, wiring width and spacing check, etc. The DRC check is implemented by using industry standard or commonly used automated DRC inspection tools, such as Calibre software, to ensure that each standard cell layout in the target process radiation-resistant cell library layout design meets the capabilities and limitations of the integrated circuit design and manufacturing process, avoiding defects or design failures caused by improper design in the actual production process.

[0078] The layout and schematic comparison check (LVS) is a tool and inspection process used in integrated circuit design to verify the consistency between the layout and the corresponding circuit principle. The inspection content mainly includes: verifying whether the layout accurately realizes the design intent of the circuit schematic; identifying possible design errors in the layout, such as unconnected lines, short circuits, missing or incorrectly placed devices, etc.; ensuring that the designed layout is consistent with the corresponding circuit schematic, and improving the reliability and performance of the layout design.

[0079] In addition, due to the metal wiring transplantation process, the positions of metal lines and through holes may not meet the design requirements. The process of manually modifying the layout in step S133 includes manually adjusting the positions of metal lines and through holes.

[0080] The steps and procedures of a radiation-resistant standard cell library layout design method in this embodiment are as follows: Figure 3 shown.

[0081] The radiation-resistant standard cell library layout design methods described in the first embodiment and the second embodiment are based on the existing radiation-resistant standard cell library layout process, and all standard cell layouts of the original process are adjusted and transplanted according to the unified radiation-resistant layout process transplantation rules, generating all cell layouts of the radiation-resistant standard cell library of the entire target process, reducing the circuit design and layout drawing process of the radiation-resistant standard cells one by one, and facilitating the implementation of computer program-aided design, greatly saving labor costs and time costs, shortening the design cycle, and improving design efficiency, and the corresponding standard cell library obtained has the characteristics of flexible configuration. The radiation-resistant standard cell library designed based on the present invention can be suitable for space integrated circuits, greatly speeding up the design of aerospace-grade integrated circuits, and also greatly reducing research and development costs.

[0082] In another embodiment of the present invention, a radiation-resistant standard cell library layout design device is provided, wherein the device is used to design a radiation-resistant standard cell library layout using the above method, wherein the method performs standard cell layout design based on process transplantation, and the device specifically includes the following modules:

[0083] A data input module, used to obtain a first design rule file of an original process commercial library and a second design rule file of a target process commercial library, and use the multiple pieces of process information contained in the first design rule file and the second design rule file as input data for computer processing;

[0084] A process transplantation rule design module is used to compare the process information described in the first design rule file and the second design rule file for similarities and differences; using the data results of the similarities and differences comparison, a commercial library layout process transplantation rule for performing a transplantation operation on the layout of the target process commercial library is designed in a high-level programming language; the commercial library layout process transplantation rule is combined with the target process radiation-resistant design rule to generate a radiation-resistant layout process transplantation rule;

[0085] A radiation-resistant standard cell library layout generation module, used to generate a target process radiation-resistant standard cell library layout using the radiation-resistant layout process migration rule obtained by the process migration rule design module, and record it in a file "all.gds";

[0086] The radiation resistance performance verification and reinforcement module is used to verify whether the radiation resistance performance of the target process radiation resistance standard cell library layout meets the target process design requirements. If the verification fails, the radiation resistance reinforcement optimization is performed until the design requirements are met.

[0087] The data output module is used to output the design data of the target process radiation-resistant standard cell library layout that meets the target process design requirements.

[0088] In one embodiment, the present invention also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the aforementioned radiation-resistant standard cell library layout design method when executing the computer program.

[0089] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0090] The above-mentioned embodiments only express several implementation modes of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the invention. It should be pointed out that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the attached claims.

Claims

1. A method for designing a layout of a radiation-resistant standard cell library, characterized in that: The method performs standard cell layout design based on process transplantation, and includes the following steps: Step S110: obtaining a first design rule file of an original process commercial library and a second design rule file of a target process commercial library, wherein both the first design rule file and the second design rule file contain multiple pieces of process information, and the process information is used as input data for computer processing; The process information includes: The layer name, GDS number and data type defined in the first layer information file in the original process program and the second layer information file in the target process program; each of the three types of process information, namely, the layer name, GDS number and data type, is not completely the same in the first layer information file and the second layer information file; In the original process commercial library and the target process commercial library, the respective standard cell layouts adopt a unified design height, and the design height is an integer multiple of the width of the metal wiring track in the corresponding standard cell layout; The standard cell layout structure follows the minimum width, minimum height and minimum area principles; The centerline position of the standard cell layout structure; NMOS and PMOS area division in the standard cell layout structure; The gate length and source-drain region length of the process node; The location of the boundary layer, the size of the via, and the distance from the via to the active area boundary; Step S120: Compare the process information described in the first design rule file and the second design rule file for similarities and differences; use the data results of the similarities and differences comparison to design a commercial library layout process transplantation rule for transplanting the layout of the target process commercial library in a high-level programming language; combine the commercial library layout process transplantation rule with the target process radiation-resistant design rule to generate a radiation-resistant layout process transplantation rule; Step S130: performing a process transplantation operation on the original process radiation-resistant standard cell library layout according to the radiation-resistant layout process transplantation rule obtained in step S120, generating a target process radiation-resistant standard cell library layout, and recording it in a file "all.gds"; Step S140: verifying whether the radiation resistance performance of the target process radiation resistance standard cell library layout meets the target process design requirements. If the verification fails, optimizing the radiation resistance reinforcement until the design requirements are met. Step S150: outputting design data of a target process radiation-resistant standard cell library layout that meets the target process design requirements.

2. The method for designing a layout of a radiation-resistant standard cell library according to claim 1, characterized in that: The commercial library layout process transplantation rules include rules for transplanting and converting all the process information in the original process and the target process, and the rules for transplanting and converting all the process information include scaling by a proportional factor and offsetting a setting position.

3. The method for designing a layout of a radiation-resistant standard cell library according to claim 2, characterized in that: The target process radiation resistance design rules include the distance design rules from the well contact to the transistor in the standard cell layout structure, the minimum distance design rules from the active area of ​​the PMOS tube to the N well, the minimum distance design rules from the active area of ​​the NMOS tube to the N well, and the width design rules of the well contact.

4. The method for designing a layout of a radiation-resistant standard cell library according to claim 3, characterized in that: set up is the total number of standard cells in the target process radiation-resistant standard cell library layout, and the variable Mark the first Radiation-resistant standard units, , The initial value of is set to 1, then the process of generating the target process radiation-resistant standard cell library layout in step S130 specifically includes: Step S131: extract the first A radiation-resistant standard cell layout; Step S132: The radiation-resistant standard cell layout is subjected to a process transplantation operation according to the radiation-resistant layout process transplantation rule to generate the target process radiation-resistant standard cell library layout. The process transplantation operation includes performing the first The relative position layout of transistors and consistent metal wiring of a radiation-resistant standard cell layout; Step S133: The radiation-resistant standard cell layout is checked for DRC and LVS to check whether the layout design meets the manufacturing reliability requirements and whether new errors are introduced after the process migration operation; if the above check fails, the layout is manually modified and the above check is performed again until the check passes; if the above check passes, the first step in the current target process is saved. The radiation-resistant standard cell layout data is used as the first A radiation-resistant standard cell layout is saved in the file "all.gds"; Step S134: When When , return to step S131 until , ending the loop.

5. The method for designing a layout of a radiation-resistant standard cell library according to claim 4, characterized in that: The process of manually modifying the layout in step S133 includes manually adjusting the positions of the metal lines and the positions of the through holes.

6. A radiation-resistant standard cell library layout design device, characterized in that: The device uses the steps of the method according to any one of claims 1 to 5 to design a radiation-resistant standard cell library layout, and the device includes the following modules: A data input module, used to obtain a first design rule file of an original process commercial library and a second design rule file of a target process commercial library, and use the multiple pieces of process information contained in the first design rule file and the second design rule file as input data for computer processing; A process migration rule design module, used for comparing the process information described in the first design rule file and the second design rule file for similarities and differences; Using the data results of the similarities and differences comparison, a commercial library layout process transplantation rule for performing a transplantation operation on the layout of the target process commercial library is designed in a high-level programming language; the commercial library layout process transplantation rule is combined with the target process radiation-resistant design rule to generate a radiation-resistant layout process transplantation rule; A radiation-resistant standard cell library layout generation module, used to generate a target process radiation-resistant standard cell library layout using the radiation-resistant layout process migration rule obtained by the process migration rule design module, and record it in a file "all.gds"; The radiation resistance performance verification and reinforcement module is used to verify whether the radiation resistance performance of the target process radiation resistance standard cell library layout meets the target process design requirements. If the verification fails, the radiation resistance reinforcement optimization is performed until the design requirements are met. The data output module is used to output the design data of the target process radiation-resistant standard cell library layout that meets the target process design requirements.

7. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 5 are implemented.

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