Graph rendering method and device, electronic equipment and storage medium

Abstract

The invention relates to a graph rendering method and device, electronic equipment and a storage medium, and the method comprises the steps: receiving a first drawing instruction sent by an application program, and the first drawing instruction comprises at least one first identifier used for indicating a rendering target; and if the first identifier also exists in the second drawing instruction and a second identifier except the first identifier in the second drawing instruction is set as a null value in the first drawing instruction, keeping a rendering target applied to be bound to the GPU by the first drawing instruction to be the same as the second drawing instruction, the GPU is instructed not to execute write-in operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction; and submitting an instruction set at least comprising the first drawing instruction and the second drawing instruction to a GPU at one time, so that the GPU performs a graphic rendering operation. The embodiment of the invention can improve the graphic rendering efficiency.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a graphics rendering method, device, electronic device and storage medium. Background Art

[0002] Tile-Based Deferred Rendering (TBDR) is an efficient graphics rendering technology for graphics processing units (GPUs). It breaks down the rendering process into multiple small tiles (tiles) and significantly improves rendering efficiency by processing multiple tiles in parallel. In TBDR, the drawing instructions sent by the application are first collected and stored in the command buffer. After a frame of commands is collected, the rendering commands are assigned to tiles, and then the GPU processes these tiles in parallel. Each tile is responsible for processing all commands within it by a high-speed renderer and writing the results back to the frame buffer. Tiles have a specific data storage structure layout. If multiple drawing instructions share the same data storage structure and have no dependencies, they can be assigned to the same tile for batch processing, further improving efficiency and reducing state changes and memory access overhead.

[0003] However, when multiple consecutive drawing instructions (draw) in a frame of graphics frequently switch render targets (rendertarget, RT), the complexity of rendering will increase, resulting in a decrease in rendering performance. Summary of the invention

[0004] The present disclosure proposes a graphics rendering technology solution.

[0005] According to one aspect of the present disclosure, a graphics rendering method is provided, which is applied to a graphics processor (GPU) driver, and includes:

[0006] receiving a first drawing instruction sent by an application, wherein the first drawing instruction includes at least one first identifier for indicating a rendering target, and the rendering target is used to cache a rendering result obtained by executing the drawing instruction;

[0007] If the first identifier also exists in the second drawing instruction, and the second identifier other than the first identifier in the second drawing instruction is set to a null value in the first drawing instruction, the rendering target to which the first drawing instruction is applied to be bound to the GPU is kept the same as that of the second drawing instruction, and the GPU is instructed not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction;

[0008] Submitting an instruction set including at least the first drawing instruction and the second drawing instruction to the GPU at one time so that the GPU performs a graphics rendering operation.

[0009] In a possible implementation, instructing the GPU not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction includes:

[0010] The write mask of the first rendering target in the first drawing instruction is set to a first indication flag, where the first indication flag is used to instruct the GPU not to perform a write operation on the first rendering target when executing the first drawing instruction.

[0011] In a possible implementation, the GPU driver receives multiple drawing instructions in sequence and continuously, the second drawing instruction is a drawing instruction received before the first drawing instruction, and after instructing the GPU not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction, the method further includes:

[0012] The first drawing instruction is added to the instruction set where the second drawing instruction is located.

[0013] In a possible implementation manner, after instructing the GPU not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction, the method further includes:

[0014] receiving a third drawing instruction sent by the application;

[0015] Submitting the instruction set including at least the first drawing instruction and the second drawing instruction to the GPU at one time includes:

[0016] In a case where the third identifier in the third drawing instruction does not exist in the first drawing instruction, the instruction set is submitted to the GPU at one time.

[0017] In a possible implementation, the GPU driver receives a plurality of drawing instructions in sequence and continuously, the plurality of drawing instructions including the first drawing instruction and the second drawing instruction; and submitting the instruction set including at least the first drawing instruction and the second drawing instruction to the GPU at one time includes:

[0018] In any two drawing instructions that are adjacent in time sequence among the multiple drawing instructions, if the previous drawing instruction includes all the identifiers in the next drawing instruction, the multiple drawing instructions are submitted to the GPU at one time.

[0019] In a possible implementation manner, after instructing the GPU not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction, the method further includes:

[0020] The state flag corresponding to the first rendering target is set to a first state value, where the first state value is used to indicate that the first rendering target is in a state where it is not written.

[0021] In a possible implementation, the method further includes:

[0022] When the state flag corresponding to the first rendering target is a first state value, if the third identifier in the third drawing instruction does not exist in the first drawing instruction, setting a write mask of the corresponding rendering target according to the identifier in the third drawing instruction.

[0023] According to one aspect of the present disclosure, a graphics rendering device is provided, which is applied to a graphics processor (GPU) driver, and includes:

[0024] An instruction receiving unit, configured to receive a first drawing instruction sent by an application, wherein the first drawing instruction includes at least one first identifier for indicating a rendering target, and the rendering target is used to cache a rendering result obtained by executing the drawing instruction;

[0025] an instructing unit, configured to keep the rendering target of the GPU to which the first drawing instruction is applied to be bound the same as that of the second drawing instruction, and instruct the GPU not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction, if the first identifier also exists in the second drawing instruction and the second identifier in the second drawing instruction other than the first identifier is set to a null value in the first drawing instruction;

[0026] The submitting unit is used to submit an instruction set including at least the first drawing instruction and the second drawing instruction to the GPU at one time, so that the GPU performs a graphics rendering operation.

[0027] In a possible implementation, the indication unit is used to set the write mask of the first rendering target in the first drawing instruction to a first indication flag, and the first indication flag is used to instruct the GPU not to perform a write operation on the first rendering target when executing the first drawing instruction.

[0028] In a possible implementation, the GPU driver receives multiple drawing instructions in sequence and continuously, the second drawing instruction is a drawing instruction received before the first drawing instruction, and the device further includes:

[0029] The collection unit is used to add the first drawing instruction to the instruction collection where the second drawing instruction is located.

[0030] In a possible implementation manner, after instructing the GPU not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction, the device further includes:

[0031] A third instruction receiving unit, used for receiving a third drawing instruction sent by the application;

[0032] The submitting unit is configured to submit the instruction set to the GPU at one time when the third identifier in the third drawing instruction does not exist in the first drawing instruction.

[0033] In a possible implementation, the GPU driver receives multiple drawing instructions in sequence and continuously, and the multiple drawing instructions include the first drawing instruction and the second drawing instruction; the submitting unit is used to submit the multiple drawing instructions to the GPU at one time if the previous drawing instruction contains all the identifiers in the next drawing instruction among any two drawing instructions that are adjacent in time sequence among the multiple drawing instructions.

[0034] In a possible implementation, the device further includes: a state setting unit, configured to set a state flag corresponding to the first rendering target to a first state value, wherein the first state value is used to indicate that the first rendering target is in a state where it is not written.

[0035] In a possible implementation, the device further includes: a write mask setting unit, configured to, when the state flag corresponding to the first rendering target is a first state value, set a write mask of the corresponding rendering target according to the identifier in the third drawing instruction if the third identifier in the third drawing instruction does not exist in the first drawing instruction.

[0036] According to one aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to call the instructions stored in the memory to execute the above method.

[0037] According to one aspect of the present disclosure, a computer-readable storage medium is provided, on which computer program instructions are stored, and the computer program instructions implement the above method when executed by a processor.

[0038] In the embodiment of the present disclosure, after receiving the first drawing instruction sent by the application; if the first identifier in the first drawing instruction also exists in the second drawing instruction, and the second identifier in the second drawing instruction other than the first identifier is set to a null value in the first drawing instruction, the first drawing instruction is applied to be bound to the rendering target of the GPU to keep it the same as the second drawing instruction, and the GPU is instructed not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction, thereby, the rendering target corresponding to the first drawing instruction is not actually set to a null value, but is kept the same as the second drawing instruction, then the first drawing instruction and the second drawing instruction can share the same data storage structure (layout), can be placed in the same instruction set, and then by submitting the instruction set containing at least the first drawing instruction and the second drawing instruction to the GPU at one time, compared with submitting in multiple times, it can reduce the additional overhead caused by the interaction between the GPU driver and the operating system, and improve the efficiency of graphics rendering. In addition, the GPU can batch the instruction set, further improving the processing efficiency.

[0039] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

[0041] Figure 1 A flowchart of a graphics rendering method according to an embodiment of the present disclosure is shown.

[0042] Figure 2 A flowchart of a graphics rendering method in an actual application scenario according to an embodiment of the present disclosure is shown.

[0043] Figure 3 A flowchart of a graphics rendering method in an actual application scenario according to an embodiment of the present disclosure is shown.

[0044] Figure 4 A block diagram of a graphics rendering device according to an embodiment of the present disclosure is shown.

[0045] Figure 5 A block diagram of an electronic device 1900 according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0046] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0047] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0048] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0049] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0050] When the continuous drawing instructions (draw) of a frame of image frequently switch render targets (render target, RT), it will destroy the efficiency optimization in the TBDR architecture. Each render target may require a different layout (layout) or state setting, which makes it impossible to simply merge these drawing commands into the same tile for rendering. In this case, the user mode driver (User Mode Driver, UMD) needs to interrupt the continuous drawing commands and submit them to the hardware for execution in multiple times.

[0051] Because the GPU driver needs to interact with the operating system (such as Windows) every time it submits instructions to the hardware, this adds additional overhead. Especially in a virtual environment built by a virtual machine, this interaction may be affected by greater latency, because the virtual environment usually has additional overhead and synchronization requirements, and the time interval between two rendering commands may be as high as 0.2ms.

[0052] In the embodiment of the present disclosure, after receiving the first drawing instruction sent by the application; if the first identifier in the first drawing instruction also exists in the second drawing instruction, and the second identifier in the second drawing instruction other than the first identifier is set to a null value in the first drawing instruction, the first drawing instruction is applied to be bound to the rendering target of the GPU to keep it the same as the second drawing instruction, and the GPU is instructed not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction, thereby, the rendering target corresponding to the first drawing instruction is not actually set to a null value, but is kept the same as the second drawing instruction, then the first drawing instruction and the second drawing instruction can share the same data storage structure (layout), can be placed in the same instruction set, and then by submitting the instruction set containing at least the first drawing instruction and the second drawing instruction to the GPU at one time, compared with submitting in multiple times, it can reduce the additional overhead caused by the interaction between the GPU driver and the operating system, and improve the efficiency of graphics rendering. In addition, the GPU can batch the instruction set, further improving the processing efficiency.

[0053] Figure 1 A flowchart of a graphics rendering method according to an embodiment of the present disclosure is shown, which is applied to a graphics processor GPU driver, such as Figure 1 As shown, the method includes:

[0054] In step S11, a first drawing instruction sent by an application is received, wherein the first drawing instruction includes at least one first identifier for indicating a rendering target, and the rendering target is used to cache a rendering result obtained by executing the drawing instruction;

[0055] The application here can be software that requires GPU for graphics rendering, such as games, image processing software, etc. These applications will generate drawing instructions, such as drawing a shape (such as a triangle or rectangle), rendering a texture, etc., and send these instructions to the driver through the graphics interface. The driver receives these instructions and performs subsequent processing based on the information in the instructions, generates rendering commands that can be executed by the GPU, and finally sends them to the GPU for graphics rendering.

[0056] A render target (RT) is a memory area used to cache the rendering results obtained after executing a drawing instruction. It is usually one or more buffers, such as color, depth, and other possible buffers, used to store pixel-level rendering results. When a drawing instruction is executed, the rendering result will be stored in the RT bound to the drawing instruction.

[0057] The identifier of the render target is used to identify different render targets. In one example, the identifier of the render target can be a name or a string. These names can be defined by the programmer for the render target, or they can be automatically generated by the system. By specifying these names, the application can tell the driver or GPU which render target it wants to use. In addition, the identifier of the render target can also be a resource handle, a memory location, etc., which is not limited by the present disclosure.

[0058] After receiving the first drawing instruction sent by the application, the parameters in the drawing instruction will be parsed to obtain the identifier contained in the first drawing instruction. For ease of description, the identifier contained in the first drawing instruction is recorded as the first identifier. It can be understood that the "first" and "second" in the embodiment of the present disclosure are used to distinguish the objects described, and should not be understood as other limitations such as the order of the objects described, indication or implication of relative importance.

[0059] In step S12, if the first identifier also exists in the second drawing instruction, and the second identifier other than the first identifier in the second drawing instruction is set to a null value in the first drawing instruction, the first drawing instruction is applied to be bound to the same rendering target of the GPU as the second drawing instruction, and the GPU is instructed not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction;

[0060] The second drawing instruction may be an instruction that has been received before the first drawing instruction. When rendering an image frame, the application may decompose the image frame into multiple small blocks, each of which may contain multiple drawing instructions. Each tile has a high-speed renderer that is responsible for processing all rendering commands within the tile. During the graphics rendering process, the renderer in the GPU divides the frame buffer into small blocks, each of which corresponds to a tile. Then, the renderer executes all rendering commands within the tile and writes the results back to the frame buffer.

[0061] Each tile has a specific data storage structure (layout), which is used to describe how data is organized in memory, determined by the rendering objects it contains. If multiple drawing commands can share the same layout and there is no dependency between them, then these drawing commands can be submitted at once and rendered on the same tile. This batching technology can further improve rendering efficiency.

[0062] Then, after the driver receives the first drawing instruction, if the driver has received the second drawing instruction before, the driver will check whether the newly received first drawing instruction can share the same data storage structure with the second drawing instruction.

[0063] Specifically, if the rendering targets of the first drawing instruction and the second drawing instruction are the same, it can be considered that the two can share the same data storage structure. In the absence of a mutual dependency relationship (for example, the first drawing instruction does not need to use the rendering result of the second drawing instruction), an instruction set including at least the first drawing instruction and the second drawing instruction can be submitted to the GPU at one time so that the GPU can perform graphics rendering operations.

[0064] The first identifier also exists in the second drawing instruction, and the second identifiers other than the first identifier in the second drawing instruction are set to null values ​​in the first drawing instruction. Specifically, all identifiers in the second drawing instruction include all identifiers in the first drawing instruction, and the identifiers other than the first identifier in the second drawing instruction (referred to as second identifiers for ease of description) are set to null values ​​in the first drawing instruction. Exemplarily, the identifiers in the first drawing instruction draw1 are (RT0, nullptr, RT2, RT3), and the identifiers in the second drawing instruction draw0 are (RT0, RT1, RT2, RT3). Then draw0 contains 4 identifiers, namely RT0, RT1, RT2, and RT3, and draw1 contains 3 identifiers, namely RT0, RT2, and RT3, wherein nullptr represents a null value. Then, RT1 is recorded as the second identifier in the above text, which is set to a null value in draw1.

[0065] In this case, the rendering target bound to the GPU by the first drawing instruction can be kept the same as that of the second drawing instruction, without setting the RT of the second identifier to a null value in the driver. In this way, the rendering target bound to the first drawing instruction is kept the same as that of the second drawing instruction, that is, the first drawing instruction can share the same data storage structure with the second drawing instruction, that is, the rendering results obtained by rendering the first drawing instruction and the second drawing instruction are organized in the same way in the memory. Continuing with the above example, the rendering target applied for by the first drawing instruction is also (RT0, RT1, RT2, RT3), and RT1 is not set to a null value.

[0066] Furthermore, the GPU is instructed not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction, so that the GPU does not perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction, thereby achieving the effect of setting the second identifier to a null value.

[0067] In step S13, an instruction set including at least the first drawing instruction and the second drawing instruction is submitted to the GPU at one time, so that the GPU performs a graphics rendering operation.

[0068] An instruction set may contain multiple drawing instructions that can share the same data storage structure. An instruction set may be sent to the GPU as a whole to reduce the number of communications between the GPU and the driver and improve rendering efficiency.

[0069] The user mode driver (UMD) in the driver program converts drawing instructions (draw) into rendering commands (command) that the GPU can efficiently execute. The rendering commands are packaged into submission data (submission) and sent to the GPU through the kernel mode driver (KMD).

[0070] After receiving the command, the GPU starts to execute the rendering process and caches the rendering results in the bound rendering target. When executing the first drawing instruction, the first rendering target corresponding to the second identifier is not written. After all the data of a frame is rendered, the data of the frame is displayed on the screen.

[0071] In the embodiment of the present disclosure, after receiving the first drawing instruction sent by the application; if the first identifier in the first drawing instruction also exists in the second drawing instruction, and the second identifier in the second drawing instruction other than the first identifier is set to a null value in the first drawing instruction, the first drawing instruction is applied to be bound to the rendering target of the GPU to keep it the same as the second drawing instruction, and the GPU is instructed not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction, thereby, the rendering target corresponding to the first drawing instruction is not actually set to a null value, but is kept the same as the second drawing instruction, then the first drawing instruction and the second drawing instruction can share the same data storage structure (layout), can be placed in the same instruction set, and then by submitting the instruction set containing at least the first drawing instruction and the second drawing instruction to the GPU at one time, compared with submitting in multiple times, it can reduce the additional overhead caused by the interaction between the GPU driver and the operating system, and improve the efficiency of graphics rendering. In addition, the GPU can batch the instruction set, further improving the processing efficiency.

[0072] In one possible implementation, instructing the GPU not to perform a write operation on the rendering target corresponding to the second identifier when executing the first drawing instruction includes: setting a write mask of the first rendering target in the first drawing instruction to a first indicator, wherein the first indicator is used to instruct the GPU not to perform a write operation on the first rendering target when executing the first drawing instruction.

[0073] The write mask (rtwritemask) is a mask used to control the GPU to write rendering results, and is used to specify which rendering targets should be updated by the rendering results. Each rendering target is usually represented by one bit. If this bit is set to the first indicator (for example, set to 0), the corresponding rendering target will not be written; if it is set to the second indicator (for example, set to 1), the corresponding rendering target will be written. If the driver sets the write mask of the first rendering target to the first indicator, it means that during the GPU's execution of the first drawing instruction, the first rendering target will not be written, and can be executed on the same tile as the second drawing instruction without changing the rendering target, thereby improving the efficiency of graphics rendering.

[0074] In the disclosed embodiment, by setting the write mask of the first rendering target in the first drawing instruction to the first indication mark, the first indication mark is used to instruct the GPU not to perform a write operation on the first rendering target when executing the first drawing instruction. Therefore, when the second mark is requested to be set to a null value in the first drawing instruction, the GPU is instructed not to perform a write operation on the first rendering target corresponding to the second mark when executing the first drawing instruction by changing the write mask, so that it is not necessary to set the first rendering target bound to the GPU by the first drawing instruction to a null value, so that the rendering target bound to the GPU by the first drawing instruction is kept the same as the second drawing instruction, so that the first drawing instruction and the second drawing instruction can share the same data storage structure (layout) and can be placed in the same instruction set, and then by submitting the instruction set containing at least the first drawing instruction and the second drawing instruction to the GPU at one time, compared with submitting in multiple times, the additional overhead caused by the interaction between the GPU driver and the operating system can be reduced, and the graphics rendering efficiency is improved.

[0075] The application side does not need to make any improvements. Even if the application sets the RT to a null value, the driver will not actually set the RT to a null value. In this way, the driver can avoid the actual RT switching overhead and reuse the previous rendering state. In addition, in order to ensure that the RT does not affect the final rendering output, the driver will prohibit the writing of drawing process data by setting rtwritemask to 0. In this way, developers can keep the logic of the application unchanged without introducing additional performance overhead, which is more friendly to application developers.

[0076] In a possible implementation, the GPU driver continuously receives multiple drawing instructions, the second drawing instruction is a drawing instruction received before the first drawing instruction, and after instructing the GPU not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction, the method also includes: adding the first drawing instruction to the instruction set where the second drawing instruction is located.

[0077] The GPU driver receives drawing instructions from the operating system or application program continuously. For two drawing instructions received continuously, if the latter can share the same data storage structure with the former, the latter can be added to the instruction set where the former is located. For example, the four instructions received continuously are: draw0(RT0,RT1,RT2,RT3), draw1(RT0,nullptr,RT2,RT3), draw2(RT0,nullptr,nullptr,RT3), draw3(RT0,nullptr,nullptr,nullptr). Among these instructions, two adjacent instructions can share the same data storage structure. Then, after receiving draw1, draw1 can be added to the instruction set where draw0 is located. At this time, the instruction set is {draw0,draw1}; after receiving draw2, draw2 can be added to the instruction set where draw1 is located. At this time, the instruction set is {draw0,draw1,draw2}; after receiving draw3, draw3 can be added to the instruction set where draw2 is located. At this time, the instruction set is {draw0,draw1,draw2,draw3}.

[0078] In an embodiment of the present disclosure, the GPU driver receives multiple drawing instructions continuously, the second drawing instruction is a drawing instruction received before the first drawing instruction, and after instructing the GPU not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction, the method further includes: adding the first drawing instruction to the instruction set where the second drawing instruction is located. Thus, the continuously received drawing instructions that can share the same data storage structure can be put into one instruction set so as to be submitted to the GPU at one time. Compared with submitting them in multiple times, the additional overhead caused by the interaction between the GPU driver and the operating system can be reduced, and the efficiency of graphics rendering is improved.

[0079] In a possible implementation, after instructing the GPU not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction, the method further includes: receiving a third drawing instruction sent by an application; submitting an instruction set including at least the first drawing instruction and the second drawing instruction to the GPU at one time, including: submitting the instruction set to the GPU at one time when the third identifier in the third drawing instruction does not exist in the first drawing instruction.

[0080] The third identifier is an identifier used to indicate a rendering target in the third drawing instruction. If the third identifier does not exist in the first drawing instruction, then relative to the first drawing instruction, the third drawing instruction needs to apply for a new rendering target, and the third drawing instruction cannot share the same data storage structure with the first drawing instruction, and the third drawing instruction cannot be added to the instruction set where the first drawing instruction is located. Then, at this time, the instruction set where the first drawing instruction is located can be submitted to the GPU at one time to avoid submitting drawing instructions with different data storage structures together.

[0081] In a possible implementation, the GPU driver receives multiple drawing instructions in sequence and continuously, and the multiple drawing instructions include the first drawing instruction and the second drawing instruction; submitting the instruction set including at least the first drawing instruction and the second drawing instruction to the GPU at one time includes: among any two drawing instructions adjacent in time sequence among the multiple drawing instructions, if the previous drawing instruction includes all the identifiers in the latter drawing instruction, submitting the multiple drawing instructions to the GPU at one time.

[0082] The GPU driver program will receive multiple drawing instructions in a time sequence, which may include a first drawing instruction and a second drawing instruction, or may include more drawing instructions.

[0083] When the GPU driver needs to submit these multiple drawing instructions received continuously to the GPU for execution, it will determine whether any two adjacent drawing instructions in time sequence among the multiple drawing instructions meet the condition that the previous drawing instruction contains all the identifiers of the next drawing instruction. If so, the previous drawing instruction of the two adjacent drawing instructions can be regarded as the second drawing instruction, and the next drawing instruction can be regarded as the first drawing instruction. According to the above processing of the first drawing instruction and the second drawing instruction, the rendering target applied to bind the first drawing instruction to the GPU will be kept the same as that of the second drawing instruction, that is, the rendering target applied to bind the next drawing instruction to the GPU will be kept the same as that of the previous drawing instruction. Then, the two adjacent instructions can share the same data storage structure, and the multiple drawing instructions can be submitted to the GPU at one time.

[0084] For example, the four instructions received consecutively are: draw0(RT0,RT1,RT2,RT3), draw1(RT0,nullptr,RT2,RT3), draw2(RT0,nullptr,nullptr,RT3), draw3(RT0,nullptr,nullptr,nullptr), where nullptr is empty. Obviously, in this example, among any two adjacent drawing instructions, the previous drawing instruction will contain all the identifiers of the next drawing instruction, so these four instructions can be submitted to the CPU at one time.

[0085] In the disclosed embodiment, for receiving multiple drawing instructions in sequence, when the previous drawing instruction of any two adjacent drawing instructions contains all the identifiers of the next drawing instruction, the multiple drawing instructions are submitted to the GPU at one time. Thus, the rendering target of the next drawing instruction can be bound to the GPU to keep the same as that of the previous drawing instruction. Then, the two adjacent instructions can share the same data storage structure, and the multiple drawing instructions can be submitted to the GPU at one time. Since the number of instruction submissions is reduced, the communication overhead between the CPU and the GPU is also reduced accordingly, which helps to improve rendering performance, reduce rendering delay, and increase frame rate, thereby providing users with a smoother visual experience.

[0086] In one possible implementation, after instructing the GPU not to perform a write operation on the first rendering target corresponding to the second identifier when executing a first drawing instruction, the method further includes: setting a status flag corresponding to the first rendering target to a first status value, wherein the first status value is used to characterize that the first rendering target is in a state where it is not written.

[0087] In order to mark the current state of the first rendering target so that the subsequently received drawing instructions can be accurately written into the corresponding rendering target, this can be achieved by setting a state flag in the driver. When the first rendering target is in a state where it is not written, the state flag corresponding to the first rendering target can be set to a first state value (such as 0 or a specific character), and the GPU driver or other related components can quickly identify that the rendering target is currently in a state where it is not written.

[0088] In a possible implementation, the method further includes: when the state flag corresponding to the first rendering target is a first state value, if the third identifier in the third drawing instruction does not exist in the first drawing instruction, setting a write mask of the corresponding rendering target according to the identifier in the third drawing instruction.

[0089] When the first rendering target is marked as not to be written, the GPU driver will check whether the subsequent drawing instruction (such as the third drawing instruction) involves this rendering target. If the third identifier (an identifier different from the first identifier) ​​in the third drawing instruction does not exist in the first drawing instruction, it means that this new rendering target (the rendering target indicated by the third identifier) ​​needs to be written. At this time, according to the third identifier in the third drawing instruction, the GPU driver will set the write mask of the corresponding rendering target to ensure that the correct write operation occurs.

[0090] In the disclosed embodiments, by setting status flags and dynamically adjusting the write mask according to drawing instructions, the GPU driver can more finely control the write operation of each rendering target, thereby adapting to more complex rendering scenarios. By precisely controlling the write operation of each rendering target, the possibility of data overwrite and rendering errors can be reduced, thereby ensuring rendering quality and stability while improving rendering efficiency.

[0091] In a possible implementation, the state flag corresponding to the first rendering target is set to a second state value, where the second state value is used to indicate that the first rendering target is currently in a write-allowed state.

[0092] After setting the write mask of the corresponding rendering target according to the third identifier in the third drawing instruction, the state of the first rendering target in the driver can be changed from not allowing writing to allowing writing, so as to accurately control the writing operation of subsequent rendering targets.

[0093] See also Figure 2 , Figure 2A flowchart of a graphics rendering method in an actual application scenario according to an embodiment of the present disclosure is shown. For example, four consecutively received instructions are: draw0(RT0, RT1, RT2, RT3), draw1(RT0, nullptr, RT2, RT3), draw2(RT0, nullptr, nullptr, RT3), draw3(RT0, nullptr, nullptr, nullptr). After receiving draw3(RT0, nullptr, nullptr, nullptr), these four instructions can be put into the same set. Therefore, the status flags of RT1, RT2, and RT3 are all set to 0 to indicate that they are currently in a state where writing is not allowed. If a new drawing instruction draw4 (RT0, RT1, RT2, RT3) is received later, and RT1, RT2, and RT3 in draw4 are not in draw3, then draw0, draw1, draw2, and draw3 need to be submitted at one time, and the write masks corresponding to RT1, RT2, and RT3 are reset to the values ​​indicated in draw4, and the status flags of draw4 are all set to 1 to indicate that they are currently in a state where writing is not allowed.

[0094] See also Figure 3 , Figure 3 A flowchart of a graphics rendering method in an actual application scenario according to an embodiment of the present disclosure is shown. When drawing a frame of an image, multiple drawing instructions will be received. For a received drawing instruction, it will be determined whether the instruction is the same as the previous instruction. If the same, the instruction will be placed in the instruction set of the previous instruction, and subsequent instructions will continue to be received; if the instruction is different from the previous instruction, it will be determined whether the second RT that appeared in the previous instruction is set to a null value in the current instruction, and other first RTs are the same. If not, the instruction set where the previous instruction is located is submitted to the GPU, and the write mask and status flag are reset; if yes, the instruction is placed in the instruction set of the previous instruction, and the second RT of the instruction is not set to a null value to keep the RT bound to the GPU the same as the previous instruction, and the write mask of the second RT of the instruction is set to 0, and the status flag of the second RT is set to 0, and subsequent instructions are continued to be received.

[0095] In one possible implementation, the graphics rendering method can be executed by electronic devices such as terminal devices and servers. The terminal device can be a user equipment (UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (PDA), a handheld device, a computing device, a vehicle-mounted device, a wearable device, etc. The method can be implemented by a processor calling computer-readable instructions stored in a memory.

[0096] In addition, the present disclosure also provides a graphics rendering device, an electronic device, a computer-readable storage medium, and a program, all of which can be used to implement any graphics rendering method provided by the present disclosure. The corresponding technical solutions and descriptions are referred to the corresponding records in the method part and will not be repeated here.

[0097] Figure 4 A block diagram of a graphics rendering device according to an embodiment of the present disclosure is shown, which is applied to a graphics processor GPU driver, such as Figure 4 As shown, the device 20 comprises:

[0098] The instruction receiving unit 21 is used to receive a first drawing instruction sent by an application, wherein the first drawing instruction includes at least one first identifier for indicating a rendering target, and the rendering target is used to cache a rendering result obtained by executing the drawing instruction;

[0099] an instruction unit 22, configured to keep the rendering target of the GPU to which the first drawing instruction is applied to be bound the same as that of the second drawing instruction, and to instruct the GPU not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction, if the first identifier also exists in the second drawing instruction and the second identifier other than the first identifier in the second drawing instruction is set to a null value in the first drawing instruction;

[0100] The submitting unit 23 is used to submit an instruction set including at least the first drawing instruction and the second drawing instruction to the GPU at one time, so that the GPU performs a graphics rendering operation.

[0101] In a possible implementation, the indication unit is used to set the write mask of the first rendering target in the first drawing instruction to a first indication flag, and the first indication flag is used to instruct the GPU not to perform a write operation on the first rendering target when executing the first drawing instruction.

[0102] In a possible implementation, the GPU driver receives multiple drawing instructions in sequence and continuously, the second drawing instruction is a drawing instruction received before the first drawing instruction, and the device further includes:

[0103] The collection unit is used to add the first drawing instruction to the instruction collection where the second drawing instruction is located.

[0104] In a possible implementation manner, after instructing the GPU not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction, the device further includes:

[0105] A third instruction receiving unit, used for receiving a third drawing instruction sent by the application;

[0106] The submitting unit is configured to submit the instruction set to the GPU at one time when the third identifier in the third drawing instruction does not exist in the first drawing instruction.

[0107] In a possible implementation, the GPU driver receives multiple drawing instructions in sequence and continuously, and the multiple drawing instructions include the first drawing instruction and the second drawing instruction; the submitting unit is used to submit the multiple drawing instructions to the GPU at one time if the previous drawing instruction contains all the identifiers in the next drawing instruction among any two drawing instructions that are adjacent in time sequence among the multiple drawing instructions.

[0108] In a possible implementation, the device further includes: a state setting unit, configured to set a state flag corresponding to the first rendering target to a first state value, wherein the first state value is used to indicate that the first rendering target is in a state where it is not written.

[0109] In a possible implementation, the device further includes: a write mask setting unit, configured to, when the state flag corresponding to the first rendering target is a first state value, set a write mask of the corresponding rendering target according to the identifier in the third drawing instruction if the third identifier in the third drawing instruction does not exist in the first drawing instruction.

[0110] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0111] The embodiment of the present disclosure also provides a computer-readable storage medium on which computer program instructions are stored, and the computer program instructions implement the above method when executed by a processor. The computer-readable storage medium can be a volatile or non-volatile computer-readable storage medium.

[0112] An embodiment of the present disclosure further proposes an electronic device, comprising: a processor; and a memory for storing instructions executable by the processor; wherein the processor is configured to call the instructions stored in the memory to execute the above method.

[0113] The embodiments of the present disclosure also provide a computer program product, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

[0114] The electronic device may be provided as a terminal, a server, or a device in other forms.

[0115] Figure 5 1 is a block diagram of an electronic device 1900 according to an embodiment of the present disclosure. For example, the electronic device 1900 may be provided as a server or a terminal device. Figure 5 , the electronic device 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions executable by the processing component 1922, such as an application. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to perform the above method.

[0116] The electronic device 1900 may also include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output (I / O) interface 1958. The electronic device 1900 may operate based on an operating system stored in the memory 1932, such as a Microsoft Server operating system (Windows Server 2003). TM ), a graphical user interface operating system launched by Apple (Mac OSX TM ), a multi-user, multi-process computer operating system (Unix TM ), a free and open source Unix-like operating system (Linux TM ), an open source Unix-like operating system (FreeBSD TM ) or similar.

[0117] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions, which can be executed by the processing component 1922 of the electronic device 1900 to perform the above method.

[0118] The present disclosure may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0119] Computer readable storage medium can be a tangible device that can hold and store instructions used by an instruction execution device. Computer readable storage medium can be, for example, (but not limited to) an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (non-exhaustive list) of computer readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, for example, a punch card or a convex structure in a groove on which instructions are stored, and any suitable combination thereof. The computer readable storage medium used here is not interpreted as a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated by a waveguide or other transmission medium (for example, a light pulse by an optical fiber cable), or an electrical signal transmitted by a wire.

[0120] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0121] The computer program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed completely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be customized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0122] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0123] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0124] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0125] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0126] The computer program product may be implemented in hardware, software or a combination thereof. In one optional embodiment, the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK) and the like.

[0127] The above description of various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced to each other, and for the sake of brevity, they will not be repeated herein.

[0128] Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0129] If the technical solution of this application involves personal information, the product using the technical solution of this application has clearly informed the personal information processing rules and obtained the individual's voluntary consent before processing the personal information. If the technical solution of this application involves sensitive personal information, the product using the technical solution of this application has obtained the individual's separate consent before processing the sensitive personal information, and at the same time meets the "explicit consent" requirement. For example, on personal information collection devices such as cameras, clear and prominent signs are set to inform that the personal information collection scope has been entered and personal information will be collected. If the individual voluntarily enters the collection scope, it is deemed that he or she agrees to the collection of his or her personal information; or on the device that processes personal information, the personal information processing rules are notified by obvious signs / information, and the individual's authorization is obtained through pop-up information or by asking the individual to upload his or her personal information; among them, the personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the type of personal information processed.

[0130] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A graphics rendering method, characterized in that: Applicable to GPU drivers, including: receiving a first drawing instruction sent by an application, wherein the first drawing instruction includes at least one first identifier for indicating a rendering target, and the rendering target is used to cache a rendering result obtained by executing the drawing instruction; If the first identifier also exists in the second drawing instruction, and the second identifier other than the first identifier in the second drawing instruction is set to a null value in the first drawing instruction, the rendering target to which the first drawing instruction is applied to be bound to the GPU is kept the same as that of the second drawing instruction, and the GPU is instructed not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction; Submitting an instruction set including at least the first drawing instruction and the second drawing instruction to the GPU at one time so that the GPU performs a graphics rendering operation.

2. The method according to claim 1, characterized in that The instructing the GPU not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction includes: The write mask of the first rendering target in the first drawing instruction is set to a first indication flag, where the first indication flag is used to instruct the GPU not to perform a write operation on the first rendering target when executing the first drawing instruction.

3. The method according to claim 1, characterized in that The GPU driver receives a plurality of drawing instructions in sequence and continuously, the second drawing instruction is a drawing instruction received before the first drawing instruction, and after instructing the GPU not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction, the method further includes: The first drawing instruction is added to the instruction set where the second drawing instruction is located.

4. The method according to claim 1, characterized in that After instructing the GPU not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction, the method further includes: receiving a third drawing instruction sent by the application; Submitting the instruction set including at least the first drawing instruction and the second drawing instruction to the GPU at one time includes: In a case where the third identifier in the third drawing instruction does not exist in the first drawing instruction, the instruction set is submitted to the GPU at one time.

5. The method according to claim 1, characterized in that The GPU driver receives a plurality of drawing instructions in sequence and continuously, wherein the plurality of drawing instructions include the first drawing instruction and the second drawing instruction; and submitting the instruction set including at least the first drawing instruction and the second drawing instruction to the GPU at one time, comprises: In any two drawing instructions that are adjacent in time sequence among the multiple drawing instructions, if the previous drawing instruction includes all the identifiers in the next drawing instruction, the multiple drawing instructions are submitted to the GPU at one time.

6. The method according to claim 1, characterized in that After instructing the GPU not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction, the method further includes: The state flag corresponding to the first rendering target is set to a first state value, where the first state value is used to indicate that the first rendering target is in a state where it is not written.

7. The method according to claim 4, characterized in that The method further comprises: When the state flag corresponding to the first rendering target is a first state value, if the third identifier in the third drawing instruction does not exist in the first drawing instruction, setting a write mask of the corresponding rendering target according to the identifier in the third drawing instruction.

8. A graphics rendering device, characterized in that: Applicable to GPU drivers, including: An instruction receiving unit, configured to receive a first drawing instruction sent by an application, wherein the first drawing instruction includes at least one first identifier for indicating a rendering target, and the rendering target is used to cache a rendering result obtained by executing the drawing instruction; an instructing unit, configured to keep the rendering target of the GPU to which the first drawing instruction is applied to be bound the same as that of the second drawing instruction, and instruct the GPU not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction, if the first identifier also exists in the second drawing instruction and the second identifier in the second drawing instruction other than the first identifier is set to a null value in the first drawing instruction; The submitting unit is used to submit an instruction set including at least the first drawing instruction and the second drawing instruction to the GPU at one time, so that the GPU performs a graphics rendering operation.

9. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to call the instructions stored in the memory to implement the method described in any one of claims 1 to 7.

10. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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