Driving circuit of display device

Abstract

The driving circuit of the display device comprises a first driving circuit, a second driving circuit and a third driving circuit which are used for receiving a first clock signal, a second clock signal and a third clock signal respectively, in a first period in which data is supplied to a pixel in a frame period, a first gate signal having a gate on-voltage synchronized with a rising edge timing of a corresponding clock signal is output, respectively. Outputting a second gate signal having a gate on-voltage synchronized with the rising edge timing of the corresponding clock signal in a second period for initializing the transistor of the pixel in the frame period, and outputs a third gate signal having a gate on-voltage synchronized with a rising edge timing of the corresponding clock signal in a third period for compensating a threshold voltage of the transistor in the frame period. A rising edge timing of the second clock signal is different from a rising edge timing of the third clock signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the priority of Korean Patent Application No. 10-2023-0128495 filed in the Korean Intellectual Property Office on September 25, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a driving circuit of a display device, and more particularly, to a gate driving circuit for outputting a gate signal to a pixel and a display device including the gate driving circuit. Background Art

[0004] The display device generally includes a display panel including a plurality of pixels for displaying an image, a gate drive circuit for driving the gate lines of the display panel, a data drive circuit for driving the data lines of the display panel, and a controller for controlling the gate drive circuit and the data drive circuit. The gate drive circuit may include a stage connected to the gate line, and the stage may supply a gate signal to the gate line connected to the stage in response to a signal from the controller. However, there may be a brightness deviation between the even and odd rows of pixels, which reduces the image quality perceived by the viewer. Summary of the invention

[0005] At least one embodiment of the present disclosure includes a display device having improved display quality by minimizing its brightness deviation. The technical solution to be implemented by the present disclosure is not limited to the above technical solution, and ordinary technicians in this field can clearly understand other technical solutions not mentioned above based on the description of the present disclosure.

[0006] According to an embodiment, a driving circuit for outputting at least one gate signal to a pixel of a display panel includes a first driving circuit, a second driving circuit, and a third driving circuit. The first driving circuit is configured to receive a first clock signal, and in a first period in a frame period in which data is supplied to a pixel, outputs a first gate signal having a gate-on voltage synchronized with the rising edge timing of the first clock signal. The second driving circuit is configured to receive a second clock signal, and in a second period in a frame period for initializing a driving transistor of a pixel, outputs a second gate signal having a gate-on voltage synchronized with the rising edge timing of the second clock signal. The third driving circuit is configured to receive a third clock signal, and in a third period in a frame period for compensating for a threshold voltage of a driving transistor of a pixel, outputs a third gate signal having a gate-on voltage synchronized with the rising edge timing of the third clock signal. The rising edge timing of the second clock signal is different from the rising edge timing of the third clock signal.

[0007] In an embodiment, the first driving circuit may include multiple first stages each configured to output a first gate signal to a corresponding pixel row of the display panel, the second driving circuit may include multiple second stages each configured to simultaneously output a second gate signal to a corresponding pair of pixel rows of the display panel, and the third driving circuit may include multiple third stages each configured to simultaneously output a third gate signal to a corresponding pair of pixel rows of the display panel.

[0008] In an embodiment, the second period may be before the first period, and the third period may be between the first period and the second period.

[0009] In an embodiment, the driving circuit may further include: a fourth driving circuit configured to receive a fourth clock signal and output a fourth gate signal having a gate-on voltage synchronized with the rising edge timing of the fourth clock signal in at least a portion of the second time period and the emission period of the pixel, wherein the light-emitting device of the pixel may be initialized in the second time period, and the rising edge timing of the fourth clock signal may be the same as the rising edge timing of the second clock signal or the rising edge timing of the third clock signal.

[0010] In an embodiment, the fourth driving circuit may include a plurality of fourth stages each configured to simultaneously output a fourth gate signal to a corresponding pair of pixel rows of the display panel.

[0011] In an embodiment, the driving circuit may further include: a fifth driving circuit, configured to receive a fifth clock signal, and in a third period and an emission period of the pixel, output a fifth gate signal having a gate-on voltage synchronized with the rising edge timing of the fifth clock signal, wherein the rising edge timing of the fifth clock signal may be the same as the rising edge timing of the second clock signal or the rising edge timing of the third clock signal.

[0012] In an embodiment, the fifth driving circuit may include a plurality of fifth stages each configured to simultaneously output a fifth gate signal to a corresponding pair of pixel rows of the display panel.

[0013] In an embodiment, a rising edge timing of the second clock signal may be later than a rising edge timing of the third clock signal.

[0014] In an embodiment, the rising edge timing of the third clock signal may be 0.5 μs with respect to the horizontal synchronization signal, and the rising edge timing of the second clock signal may be 1.5 μs with respect to the horizontal synchronization signal.

[0015] In an embodiment, a rising edge timing of the third clock signal may be later than a rising edge timing of the second clock signal.

[0016] In an embodiment, the rising edge timing of the second clock signal may be 0.5 μs with respect to the horizontal synchronization signal, and the rising edge timing of the third clock signal may be 1.5 μs with respect to the horizontal synchronization signal.

[0017] In an embodiment, a signal width of a first gate signal output to odd-numbered pixel rows of a display panel may be equal to a signal width of a first gate signal output to even-numbered pixel rows of the display panel.

[0018] In an embodiment, the rising edge timing of the first clock signal may be before the rising edge timing of the second clock signal and before the rising edge timing of the third clock signal.

[0019] According to an embodiment, a driving circuit for outputting at least one gate signal to a pixel of a display panel includes a first driving circuit, a second driving circuit, and a third driving circuit. The first driving circuit is configured to receive a first clock signal, and in a first period in a frame period in which data is supplied to a pixel, outputs a first gate signal having a gate-on voltage synchronized with the rising edge timing of the first clock signal. The second driving circuit is configured to receive a second clock signal, and in a second period in a frame period for initializing a driving transistor of a pixel, outputs a second gate signal having a gate-on voltage synchronized with the rising edge timing of the second clock signal. The third driving circuit is configured to receive a third clock signal, and in a third period in a frame period for compensating for a threshold voltage of a driving transistor of a pixel, outputs a third gate signal having a gate-on voltage synchronized with the rising edge timing of the third clock signal. In the first period, the signal width of the first gate signal output to the odd pixel rows of the display panel is different from the signal width of the first gate signal output to the even pixel rows of the display panel.

[0020] In an embodiment, the rising edge timing of the second clock signal and the rising edge timing of the third clock signal may be identical to each other, and the rising edge timing of the first clock signal may be before the rising edge timing of the second clock signal and the rising edge timing of the third clock signal.

[0021] In an embodiment, the first driving circuit may include multiple first stages each configured to output a first gate signal to a corresponding pixel row of the display panel, the second driving circuit may include multiple second stages each configured to simultaneously output a second gate signal to a corresponding pair of pixel rows of the display panel, and the third driving circuit may include multiple third stages each configured to simultaneously output a third gate signal to a corresponding pair of pixel rows of the display panel.

[0022] In an embodiment, the driving circuit may further include: a fourth driving circuit configured to receive a fourth clock signal and output a fourth gate signal having a gate-on voltage synchronized with the rising edge timing of the fourth clock signal in at least a portion of the second time period and the emission period of the pixel, wherein the light-emitting device of the pixel may be initialized in the second time period, and the rising edge timing of the fourth clock signal may be the same as the rising edge timing of the second clock signal.

[0023] In an embodiment, the fourth driving circuit may include a plurality of fourth stages each configured to simultaneously output a fourth gate signal to a corresponding pair of pixel rows of the display panel.

[0024] In an embodiment, the driving circuit may further include: a fifth driving circuit, configured to receive a fifth clock signal, and in a third period and an emission period of the pixel, output a fifth gate signal having a gate-on voltage synchronized with the rising edge timing of the fifth clock signal, wherein the rising edge timing of the fifth clock signal may be the same as the rising edge timing of the second clock signal.

[0025] In an embodiment, the fifth driving circuit may include a plurality of fifth stages each configured to simultaneously output a fifth gate signal to a corresponding pair of pixel rows of the display panel.

[0026] According to an embodiment, a display device may include the driving circuit according to an embodiment of the present disclosure.

[0027] In an embodiment, a display device includes a display panel and a driving circuit according to an embodiment of the present disclosure. The display device includes a controller configured to provide at least a first clock signal, a second clock signal, and a third clock signal to the driving circuit, wherein a rising edge timing of the second clock signal is different from a rising edge timing of the third clock signal, or wherein, in a first period, a signal width of a first gate signal output to an odd pixel row of the display panel is different from a signal width of a first gate signal output to an even pixel row of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Aspects and features of certain embodiments of the present disclosure will become more apparent through the following description in conjunction with the accompanying drawings, in which:

[0029] Figure 1A and Figure 1B is a diagram schematically illustrating a display device according to an embodiment;

[0030] Figure 2 is a diagram schematically illustrating a display device according to an embodiment;

[0031] Figure 3 is an equivalent circuit diagram of a pixel according to an embodiment;

[0032] Figure 4A and Figure 4B Is used to describe Figure 3 A diagram of signals illustrating the operation of a pixel;

[0033] Figure 5 and Figure 6 It is a schematic diagram Figure 2 A diagram of a gate drive circuit;

[0034] Figure 7 is a diagram schematically illustrating a display device according to an embodiment;

[0035] Figure 8 It is a schematic diagram Figure 7 A diagram of a gate drive circuit;

[0036] Fig. 9 It is a schematic diagram Figure 7 A diagram of a portion of a pixel and a gate driving circuit;

[0037] FIG. 10A to FIG. 10E Is the graphic input to Figure 7 A diagram of a start signal and a clock signal of a gate drive circuit;

[0038] Fig.11 The diagram is from Figure 7 A diagram of a gate signal and a carry signal output by a gate drive circuit;

[0039] Fig.12 and Fig.13 is a diagram schematically illustrating changes in a clock signal, a gate signal, and a driving voltage;

[0040] Fig.14 is a diagram illustrating a clock signal according to an embodiment;

[0041] Figures 15 to 17 is a diagram illustrating a clock signal and a first gate signal according to an embodiment;

[0042] Fig.18 is a diagram illustrating a timing of a first gate signal according to an embodiment;

[0043] Fig.19 is a cross-sectional view illustrating a structure of a display element according to an embodiment;

[0044] Figure 20 to Figure 25 is a cross-sectional view illustrating a structure of a display element according to an embodiment; and

[0045] Fig.26 is a cross-sectional view illustrating a structure of a pixel of a display device according to an embodiment. DETAILED DESCRIPTION

[0046] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein.

[0047] It will be understood that although terms such as “first” and “second” may be used herein to describe various elements, these elements should not be limited by these terms and these terms are only used to distinguish one element from another.

[0048] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise; and the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0049] It will be understood that when a layer, region, area, component or element is referred to as being “on” another layer, region, area, component or element, it can be “directly on” another layer, region, area, component or element or can be “indirectly on” another layer, region, area, component or element with one or more intervening layers, regions, areas, components or elements therebetween.

[0050] In the following embodiments, when X and Y are connected to each other, with or without at least one intervening element, X and Y may be electrically connected to each other, X and Y may be functionally connected to each other, or X and Y may be physically connected to each other. Here, X and Y may be target objects (e.g., devices, equipment, circuits, wires, electrodes, terminals, conductive layers or layers). Therefore, the present disclosure is not limited to a specific connection relationship.

[0051] For example, when X and Y are electrically connected to each other, X and Y may be directly connected to each other, or one or more devices (e.g., switches, transistors, capacitors, inductors, resistors, or diodes) that implement electrical connection between X and Y may be connected between X and Y.

[0052] In the following embodiments, the term "ON" used in conjunction with the device state may refer to the activated state of the device, and the term "OFF" may refer to the deactivated state of the device. "ON" used in conjunction with the signal received by the device may refer to the signal that activates the device, and "OFF" may refer to the signal that deactivates the device. The device can be activated by a high level voltage or a low level voltage. For example, a P-channel transistor (P-type transistor) can be activated by a low level voltage, and an N-channel transistor (N-type transistor) can be activated by a high level voltage. Therefore, it should be understood that the "ON" voltage of the P-type transistor and the N-type transistor is an opposite (low to high) voltage level.

[0053] In addition, in this article, the x direction, y direction and z direction are not limited to the directions along the three axes of the rectangular coordinate system, and can be interpreted in a broad sense. For example, the x direction, y direction and z direction can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0054] The display device according to the embodiment of the present disclosure may be a device for displaying a moving image or a still image, and may be used as a display screen of various products such as televisions, notebook computers, monitors, billboards, and the Internet of Things (IoT), and portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs). In addition, the display device according to the embodiment may be used in wearable devices such as smart watches, watch phones, glasses-type displays, and head-mounted displays (HMDs). In addition, the display device according to the embodiment may be used as a central information display (CID) arranged at the dashboard of a vehicle or the central control panel or dashboard of a vehicle, an interior mirror display replacing the side mirrors of a vehicle, or a display arranged at the rear side of the front seat of a vehicle as an entertainment facility for the rear seat of the vehicle. Moreover, the display device may be a flexible device.

[0055] Figure 1A and Figure 1B is a diagram schematically illustrating a display device according to an embodiment. Figure 2 is a diagram schematically illustrating a display device according to an embodiment.

[0056] refer to Figure 1A and Figure 1B , the display device 10 may include a display area DA for displaying an image and a peripheral area PA located outside the display area DA. The display area DA may be completely surrounded by the peripheral area PA.

[0057] In a plan view, the display area DA may have a rectangular shape. In other embodiments, the display area DA may have a polygonal shape such as a triangular, pentagonal, or hexagonal shape, a circular shape, an elliptical shape, or an atypical shape. The corners of the edges of the display area DA may be rounded. In an embodiment, as shown in FIG. Figure 1A As shown in , the display device 10 may include a display area DA having a shape in which the length in the x direction is greater than the length in the y direction. Figure 1B As shown in , the display device 10 may include a display area DA having a shape in which a length in the y direction is greater than a length in the x direction.

[0058] refer to Figure 2The display device 10 according to the embodiment may include a pixel region 110 (eg, a display panel), a gate driving circuit 130, a data driving circuit 150, a power supply circuit 170, and a controller 190 (eg, a control circuit).

[0059] The pixel area 110 may be located in the display area DA. Figure 2 As shown in FIG. 1 , a plurality of pixels PX may be arranged in a pixel region 110. A plurality of gate lines GL, a plurality of data lines DL, and a plurality of pixels PX connected to the plurality of gate lines GL and the plurality of data lines DL may be arranged in the pixel region 110. The plurality of pixels PX may be arranged in various forms such as stripe arrangement, pentile arrangement, diamond arrangement, and mosaic arrangement to display an image. Each pixel PX may include an organic light emitting diode OLED (see FIG. 1 ) as a display element (light emitting element). Figure 3 ) and a pixel circuit connected to an organic light emitting diode OLED. The pixel circuit may include a plurality of transistors and at least one capacitor. The pixel PX may emit, for example, red light, green light, blue light or white light through the organic light emitting diode OLED. Each pixel PX may be connected to at least one corresponding gate line among a plurality of gate lines GL and a corresponding data line among a plurality of data lines DL.

[0060] Each of the gate lines GL may extend in the x direction (pixel row direction) to be connected to the pixels PX located in the same pixel row. Each of the gate lines GL may be configured to transmit the gate signal GS to the pixels PX in the same pixel row. Each of the data lines DL may extend in the y direction (pixel column direction) to be connected to the pixels PX in the same pixel column. Each of the data lines DL may be configured to transmit the data signal DATA to each of the pixels PX in the same pixel column in synchronization with the gate signal GS. Each pixel PX may be connected to a drive voltage line PL (see Figure 3 ) to receive the driving voltage ELVDD. Each of the driving voltage lines PL may extend in the y direction to be connected to the pixels PX located in the same column. Hereinafter, for ease of description, a pixel row may be referred to as a row, and a pixel column may be referred to as a column.

[0061] Each of the pixel circuits of the pixel PX may be electrically connected to a peripheral circuit arranged in the peripheral area PA. Various wires for transmitting electrical signals to be applied to the display area DA, peripheral circuits electrically connected to the pixel circuits, and / or pads attached to a printed circuit board or a driver IC chip may be located in the peripheral area PA. For example, the gate drive circuit 130, the data drive circuit 150, the power supply circuit 170, and the controller 190 may be located in the peripheral area PA.

[0062] In an embodiment, the peripheral area PA is a non-display area in which the pixels PX are not arranged. In another embodiment, a portion of the peripheral area PA is implemented as a display area DA. For example, a plurality of pixels PX may be arranged in at least one corner of the peripheral area PA to overlap with the peripheral circuit. Accordingly, the dead zone may be reduced and the display area DA may be expanded.

[0063] The gate driving circuit 130 may be connected to a plurality of gate lines GL, may generate a gate signal GS in response to a control signal GCS from the controller 190, and may sequentially supply the gate signal GS to the gate lines GL. The gate line GL may be connected to the gate of a transistor included in the pixel PX. The gate signal GS may be a gate control signal for controlling the conduction and cutoff of a transistor whose gate is connected to the gate line GL. The gate signal GS may be a signal including a gate-on voltage for turning on the transistor and a gate-off voltage for turning off the transistor. The gate-on voltage may be a high level voltage (a first level voltage) or a low level voltage (a second level voltage).

[0064] Figure 2 The illustrated pixel PX is connected to one gate line GL. However, this is only an example, as Figure 3 As shown in , the pixel PX may be connected to two or more gate lines, and the gate driving circuit 130 may supply two or more gate signals GS to which the gate-on voltage is applied at different timings to the corresponding gate lines.

[0065] The data driving circuit 150 may be connected to a plurality of data lines DL, and may supply data signals DATA to the data lines DL in response to control signals DCS from the controller 190. The data signals DATA supplied to the data lines DL may be supplied to the pixels PX supplied with the gate signals GS. The data driving circuit 150 may convert input image data having grayscale input from the controller 190 into data signals DATA in the form of voltage or current.

[0066] In response to the control signal PCS from the controller 190, the power supply circuit 170 may generate a voltage for driving the pixel PX and a signal and voltage required to drive the gate driving circuit 130. The power supply circuit 170 may generate a driving voltage ELVDD and a common voltage ELVSS, and supply them to the pixel PX. The driving voltage ELVDD may be a high-level voltage provided to a terminal of a driving transistor connected to a first electrode (pixel electrode or anode) of a display element included in the pixel PX. The common voltage ELVSS may be a low-level voltage provided to a second electrode (counter electrode or cathode) of a display element included in the pixel PX. The power supply circuit 170 may generate at least one start signal FLM, at least one clock signal CLK, and at least one voltage signal (e.g., voltage VGH or VGL), and supply them to the gate driving circuit 130. Although not shown, the power supply circuit 170 may generate a signal and voltage for driving the data driving circuit 150, and supply them to the data driving circuit 150. For example, the power supply circuit 170 may generate at least one start signal, at least one clock signal, and at least one voltage signal, and supply them to the data driving circuit 150.

[0067] Figure 2 The power supply circuit 170 is illustrated as generating a voltage for driving the pixel PX and a signal and a voltage for driving the gate driving circuit 130 and the data driving circuit 150. However, the embodiment is not limited thereto. For example, a circuit for generating a clock signal may be provided separately from the power supply circuit 170 to generate and supply a clock signal for driving the gate driving circuit 130 and the data driving circuit 150.

[0068] The controller 190 may generate control signals GCS, DCS, and PCS based on signals input from the outside, and supply them to the gate driving circuit 130 , the data driving circuit 150 , and the power supply circuit 170 , respectively.

[0069] The display device 10 may include a display panel, and the display panel may include a substrate. The pixel PX may be arranged in a display area DA of the substrate. In the process of forming the transistors constituting the pixel circuit in the display area DA of the substrate, some or all of the gate drive circuit 130 may be directly formed in the peripheral area PA of the substrate. The data drive circuit 150, the power supply circuit 170, and the controller 190 may be formed as separate integrated circuit chips or as a single integrated circuit chip and arranged above a flexible printed circuit board (FPCB) electrically connected to a terminal unit arranged on one side of the substrate. In other embodiments, the data drive circuit 150, the power supply circuit 170, and the controller 190 may be directly arranged above the substrate by using a chip on glass (COG) or a chip on plastic (COP) method.

[0070] In an embodiment, a plurality of transistors included in a pixel circuit of the display area DA and a plurality of transistors included in a peripheral circuit of the peripheral area PA (for example, a plurality of transistors included in the gate driving circuit 130) may be N-type oxide thin film transistors. The plurality of transistors included in the peripheral circuit of the peripheral area PA may be formed by the same process as the plurality of transistors included in the pixel circuit of the display area DA. In another embodiment, the plurality of transistors included in the pixel circuit of the display area DA and the plurality of transistors included in the peripheral circuit of the peripheral area PA may be P-type silicon thin film transistors. In another embodiment, the plurality of transistors included in the pixel circuit of the display area DA may be N-type oxide thin film transistors, and the plurality of transistors included in the peripheral circuit of the peripheral area PA may be P-type silicon thin film transistors.

[0071] In an oxide thin film transistor, the semiconductor layer may include an oxide. The oxide semiconductor may include a Zn oxide-based material such as Zn oxide, In-Zn oxide, or Ga-In-Zn oxide. In some embodiments, the oxide semiconductor may be an In-Ga-Zn-O (IGZO) semiconductor including metals such as indium (In) and gallium (Ga) in ZnO. In some embodiments, the oxide semiconductor may be an In-Sn-Ga-Zn-O (ITGZO) semiconductor. In an embodiment, the oxide thin film transistor may be a low temperature polycrystalline oxide (LTPO) thin film transistor. The silicon thin film transistor may be a low temperature polycrystalline silicon (LTPS) thin film transistor in which the semiconductor layer includes amorphous silicon or polycrystalline silicon.

[0072] Figure 3 is an equivalent circuit diagram of a pixel according to an embodiment. However, the present disclosure is not limited to Figure 3 Instead of using pixels, other circuits of the pixels can be used. Figure 4A and Figure 4B Is used to describe Figure 3 FIG. 4 is a diagram of signals illustrating the operation of a pixel.

[0073] refer to Figure 3 , the pixel PX may include a pixel circuit PC and an organic light emitting diode OLED as a display element connected to the pixel circuit PC.

[0074] The pixel PX may be connected to a first gate line GWL configured to transmit a first gate signal GW, a second gate line GIL configured to transmit a second gate signal GI, and a third gate line GRL configured to transmit a third gate signal GR. In an embodiment, the pixel PX may be connected to a fourth gate line EML configured to transmit a fourth gate signal EM and / or a fifth gate line EMBL configured to transmit a fifth gate signal EMB, and a data line DL configured to transmit a data signal DATA. Because the light emission of the pixel PX is controlled by the fourth gate signal EM and the fifth gate signal EMB, the fourth gate signal EM and the fifth gate signal EMB may be referred to as emission control signals, and the fourth gate line EML and the fifth gate line EMBL may be referred to as emission control lines. In addition, the pixel PX may be connected to a driving voltage line PL configured to transmit a driving voltage ELVDD, a reference voltage line VRL configured to transmit a reference voltage Vref, and an initialization voltage line VL configured to transmit an initialization voltage Vint.

[0075] In an embodiment, a plurality of transistors included in the pixel circuit PC may be N-type oxide thin film transistors. The oxide thin film transistor may be a low temperature polycrystalline oxide (LTPO) thin film transistor in which the semiconductor layer includes an oxide. However, this is merely an example, and the N-type transistor is not limited thereto. For example, the semiconductor layer included in the N-type transistor may include an inorganic semiconductor (e.g., amorphous silicon or polycrystalline silicon) or an organic semiconductor.

[0076] The pixel circuit PC may include a first transistor T1 to a sixth transistor T6 and a first capacitor C1 and a second capacitor C2. The first transistor T1 may be a driving transistor that outputs a driving current corresponding to the data signal DATA, and the second transistor T2 to the sixth transistor T6 may be a switching transistor configured to transmit a signal. The first terminal (first electrode) and the second terminal (second electrode) of each of the first transistor T1 to the sixth transistor T6 may be a source or a drain depending on the voltage of the first terminal and the second terminal. For example, depending on the voltage of the first terminal and the second terminal, the first terminal may be a drain and the second terminal may be a source, or the first terminal may be a source and the second terminal may be a drain. The node to which the first gate of the first transistor T1 is connected may be referred to as a first node N1, and the node to which the second terminal of the first transistor T1 is connected may be referred to as a second node N2.

[0077] The first transistor T1 may be connected between the driving voltage line PL and the second node N2. The first transistor T1 may include a gate, a first terminal, and a second terminal connected to the second node N2. The first transistor T1 may include a first gate connected to the first node N1. The first transistor T1 may further include a second gate connected to its second terminal. The first gate and the second gate may be arranged in different layers to face each other. For example, the first gate and the second gate of the first transistor T1 may face each other, with a semiconductor layer therebetween.

[0078] The first gate of the first transistor T1 may be connected to the second terminal of the second transistor T2, the first terminal of the third transistor T3, and the first capacitor C1. The second gate of the first transistor T1 may be connected to the first terminal of the sixth transistor T6, the first capacitor C1, and the second capacitor C2. The first terminal of the first transistor T1 may be connected to the driving voltage line PL via the fifth transistor T5, and the second terminal thereof may be connected to the pixel electrode of the organic light emitting diode OLED via the sixth transistor T6. The first terminal of the first transistor T1 may be connected to the second terminal of the fifth transistor T5. The second terminal of the first transistor T1 may be connected to the first terminal of the sixth transistor T6, the first capacitor C1, and the second capacitor C2. The first transistor T1 may receive the data signal DATA according to the switching operation of the second transistor T2 to control the amount of driving current flowing through the organic light emitting diode OLED.

[0079] The second transistor T2 (data write transistor) may be connected between the data line DL and the first gate of the first transistor T1. The second transistor T2 may include a gate connected to the first gate line GWL, a first terminal connected to the data line DL, and a second terminal connected to the first node N1. The second terminal of the second transistor T2 may be connected to the first gate of the first transistor T1, the first terminal of the third transistor T3, and the first capacitor C1. The second transistor T2 may be turned on by the first gate signal GW received via the first gate line GWL to electrically connect the data line DL to the first node N1 and transmit the data signal DATA received via the data line DL to the first node N1.

[0080] The third transistor T3 (first initialization transistor) may be connected between the first gate of the first transistor T1 and the reference voltage line VRL. The third transistor T3 may include a gate connected to the third gate line GRL, a first terminal connected to the first node N1, and a second terminal connected to the reference voltage line VRL. The first terminal of the third transistor T3 may be connected to the first gate of the first transistor T1, the second terminal of the second transistor T2, and the first capacitor C1. The third transistor T3 may be turned on by the third gate signal GR received via the third gate line GRL to transfer the reference voltage Vref received by the reference voltage line VRL to the first node N1. For example, the third gate signal GR may be applied to the gate of the third transistor T3.

[0081] The fourth transistor T4 (second initialization transistor or reset transistor) may be connected between the sixth transistor T6 and the initialization voltage line VL. The fourth transistor T4 may be connected between the organic light emitting diode OLED and the initialization voltage line VL. The fourth transistor T4 may include a gate connected to the second gate line GIL, a first terminal connected to the third node N3, and a second terminal connected to the initialization voltage line VL. The first terminal of the fourth transistor T4 may be connected to the second terminal of the sixth transistor T6 and the organic light emitting diode OLED. The fourth transistor T4 may be turned on by the second gate signal GI received via the second gate line GIL to transfer the initialization voltage Vint received by the initialization voltage line VL to the third node N3. For example, the second gate signal GI may be applied to the gate of the fourth transistor T4.

[0082] The fifth transistor T5 (first emission control transistor) may be connected between the driving voltage line PL and the first transistor T1. The fifth transistor T5 may include a gate connected to the fourth gate line EML, a first terminal connected to the driving voltage line PL, and a second terminal connected to the first terminal of the first transistor T1. The fifth transistor T5 may be turned on or off according to a fourth gate signal EM received through the fourth gate line EML. For example, the fourth gate signal EM may be applied to the gate of the fifth transistor T5.

[0083] The sixth transistor T6 (second emission control transistor) may be connected between the first transistor T1 and the organic light emitting diode OLED. The sixth transistor T6 may be connected between the second node N2 and the third node N3. The sixth transistor T6 may include a gate connected to the fifth gate line EMBL, a first terminal connected to the second node N2, and a second terminal connected to the third node N3. The first terminal of the sixth transistor T6 may be connected to the second terminal of the first transistor T1, the first capacitor C1, and the second capacitor C2. The second terminal of the sixth transistor T6 may be connected to the first terminal of the fourth transistor T4 and the pixel electrode of the organic light emitting diode OLED. The sixth transistor T6 may be turned on or off according to the fifth gate signal EMB received by the fifth gate line EMBL. For example, the fifth gate signal EMB may be applied to the gate of the sixth transistor T6.

[0084] The first capacitor C1 may be connected between the first gate of the first transistor T1 and the second terminal of the first transistor T1. The first electrode of the first capacitor C1 may be connected to the first node N1, and the second electrode of the first capacitor C1 may be connected to the second node N2. The first electrode of the first capacitor C1 may be connected to the first gate of the first transistor T1, the second terminal of the second transistor T2, and the first terminal of the third transistor T3. The second electrode of the first capacitor C1 may be connected to the second terminal and the second gate of the first transistor T1, the second electrode of the second capacitor C2, and the first terminal of the sixth transistor T6. The first capacitor C1 may be a storage capacitor, and may store a threshold voltage of the first transistor T1 and a voltage corresponding to the data signal DATA.

[0085] The second capacitor C2 may be connected between the driving voltage line PL and the second node N2. The first electrode of the second capacitor C2 may be connected to the driving voltage line PL. The second electrode of the second capacitor C2 may be connected to the second terminal and the second gate of the first transistor T1, the second electrode of the first capacitor C1, and the first terminal of the sixth transistor T6. In an embodiment, the capacitance of the first capacitor C1 is greater than the capacitance of the second capacitor C2.

[0086] The organic light emitting diode OLED may be connected to the first transistor T1 through the sixth transistor T6. The organic light emitting diode OLED may include a pixel electrode (anode) connected to the third node N3 and an opposing electrode (cathode) facing the pixel electrode, and the opposing electrode may receive a common voltage ELVSS. The opposing electrode may be a common electrode common to a plurality of pixels PX.

[0087] The pixel PX may display an image in units of frames or frame periods. Figure 4A, a frame may include a non-emission period NEP in which the pixel PX does not emit light and an emission period EP in which the pixel PX emits light. The non-emission period NEP may include a first period P1, a second period P2, and a third period P3. In an embodiment, the non-emission period NEP may include a fourth period P4.

[0088] Each of the first gate signal GW, the second gate signal GI, the third gate signal GR, the fourth gate signal EM, and the fifth gate signal EMB may have a high level voltage (first level voltage) in some periods, and may have a low level voltage (second level voltage) in some periods. Here, the high level voltage may be a gate-on voltage for turning on the transistor, and the low level voltage may be a gate-off voltage for turning off the transistor.

[0089] The first period P1 may be a first initialization period for initializing the first node N1 connected to the first gate electrode of the first transistor T1 and the third node N3 connected to the pixel electrode of the organic light emitting diode OLED. In the first period P1, the second gate signal GI having a gate-on voltage is supplied to (applied to) the second gate line GIL, and the third gate signal GR having a gate-on voltage may be supplied to the third gate line GRL. In the first period P1, the first gate signal GW, the fourth gate signal EM, and the fifth gate signal EMB may be supplied with a gate-off voltage.

[0090] The fourth transistor T4 may be turned on by the second gate signal GI, and the third transistor T3 may be turned on by the third gate signal GR. The first node N1 (i.e., the first gate of the first transistor T1) may be initialized to the reference voltage Vref by the turned-on third transistor T3. The third node N3 (i.e., the pixel electrode of the organic light emitting diode OLED) may be initialized to the initialization voltage Vint by the turned-on fourth transistor T4. Since the pixel electrode of the organic light emitting diode OLED is reset to the initialization voltage Vint in the first period P1, the first period P1 may be referred to as a reset period.

[0091] The second period P2 may be a compensation period for compensating for the threshold voltage of the first transistor T1. In the second period P2, the third gate signal GR having a gate-on voltage may be supplied to the third gate line GRL, and the fourth gate signal EM having a gate-on voltage may be supplied to the fourth gate line EML. During the second period P2, the first gate signal GW, the second gate signal GI, and the fifth gate signal EMB may be supplied with a gate-off voltage.

[0092] The third transistor T3 may be turned on by the third gate signal GR, and the fifth transistor T5 may be turned on by the fourth gate signal EM. Accordingly, the reference voltage Vref may be supplied to the first node N1 and the first drive voltage ELVDD may be supplied to the first terminal of the first transistor T1, and thus the first transistor T1 may be turned on. When the voltage of the second terminal of the first transistor T1 reaches the difference (Vref-Vth) between the reference voltage Vref and the threshold voltage (Vth) of the first transistor T1, the first transistor T1 may be turned off. A voltage corresponding to the threshold voltage (Vth) of the first transistor T1 may be stored in the first capacitor C1 to compensate for the threshold voltage (Vth) of the first transistor T1.

[0093] The third period P3 may be a writing period in which the data signal DATA is supplied to the pixel PX. In the third period P3, the first gate signal GW having a gate-on voltage may be supplied to the first gate line GWL. During the third period P3, the second gate signal GI, the third gate signal GR, the fourth gate signal EM, and the fifth gate signal EMB may be supplied with a gate-off voltage.

[0094] The second transistor T2 can be turned on by the first gate signal GW, and the turned-on second transistor T2 can be configured to transmit the data signal DATA from the data line DL to the first node N1 (i.e., the first gate of the first transistor T1). Accordingly, the voltage of the first node N1 can be changed from the reference voltage Vref to a voltage corresponding to the data signal DATA. In this case, the voltage of the second node N2 can also change corresponding to the amount of change in the voltage of the first node N1. The voltage of the second node N2 can be a voltage (Vref-Vth+α×(DATA-Vref)) that changes according to the capacitance ratio (α=C1 / (C1+C2)) of the first capacitor C1 and the second capacitor C2. Accordingly, the first capacitor C1 can be charged with a voltage corresponding to the data signal DATA and the threshold voltage (Vth) of the first transistor T1.

[0095] The fourth period P4 may be a second initialization period for initializing the third node N3 of the pixel electrode connected to the organic light emitting diode OLED after data writing and before the emission period EP. The second gate signal GI having a gate-on voltage may be supplied to the second gate line GIL. During the fourth period P4, the first gate signal GW, the third gate signal GR, the fourth gate signal EM, and the fifth gate signal EMB may be supplied with a gate-off voltage.

[0096] The fourth transistor T4 may be turned on by the second gate signal GI, and the initialization voltage Vint may be transmitted to the pixel electrode of the organic light emitting diode OLED through the turned-on fourth transistor T4. In an embodiment, the fourth period P4 may be omitted.

[0097] The emission period EP may be a period in which the organic light emitting diode OLED emits light. In the emission period EP, a fourth gate signal EM having a gate-on voltage may be supplied to the fourth gate line EML, and a fifth gate signal EMB having a gate-on voltage may be supplied to the fifth gate line EMBL. During the emission period EP, the first gate signal GW, the second gate signal GI, and the third gate signal GR may be gate-off voltages.

[0098] The fifth transistor T5 may be turned on by the fourth gate signal EM, and the driving voltage ELVDD may be supplied to the first terminal of the first transistor T1 through the turned-on fifth transistor T5. The first transistor T1 may output a driving current (Id∝(Vgs-Vth)) corresponding to a voltage corresponding to the data signal DATA stored in the first capacitor C1 (i.e., a voltage (Vgs-Vth) obtained by subtracting a threshold voltage (Vth) of the first transistor T1 from a gate-source voltage (Vgs) of the first transistor T1). 2 )). The driving current may flow through the organic light emitting diode OLED via the sixth transistor T6 turned on by the fifth gate signal EMB, and the organic light emitting diode OLED may emit light having brightness corresponding to the driving current.

[0099] In another embodiment, if Figure 4B As shown in, a fifth gate signal EMB having a gate-on voltage may be applied to the fifth gate line EMBL in at least a portion of the first period P1 and the fourth period P4. Therefore, in the first period P1 and the fourth period P4, the fourth transistor T4 and the sixth transistor T6 may be turned on, and the second node N2 and the third node N3 may be initialized to the initialization voltage Vint.

[0100] Figure 5 and Figure 6 is a schematic diagram illustrating a Figure 2 Diagram of the gate drive circuit.

[0101] refer to Figure 5 , the gate driving circuit 130 may include a plurality of stages ST1 to STn. The plurality of stages ST1 to STn may sequentially output the output signal OUT. The output signal OUT may be a gate signal. The number of stages present in the gate driving circuit 130 may vary according to the number of rows provided in the pixel region 110. In an embodiment, the number of stages may be equal to the number of rows, or may be less than the number of rows.

[0102] Each of the stages ST1 to STn may be connected to the gate line GL of at least one row corresponding thereto. Each of the stages ST1 to STn may receive at least one clock signal and at least one voltage signal, and may supply an output signal OUT to at least one gate line GL. In an embodiment, each of the stages ST1 to STn may supply an output signal OUT to a gate line GL included in a row corresponding thereto. In another embodiment, each of the stages ST1 to STn may supply an output signal OUT to two gate lines GL included in two rows corresponding thereto.

[0103] Each of the plurality of stages ST1 to STn may output an output signal OUT in response to a start signal. A start signal FLM for controlling the timing of the first output signal OUT may be supplied to the first stage ST1. A carry signal CR may be supplied as a start signal to each of the second stage ST2 to the nth stage STn. In an embodiment, the carry signal CR is an output signal OUT output from a preceding stage. The preceding stage may be a stage located before another stage. Figure 5 The example in which the previous stage is the stage immediately before is illustrated. For example, the third output signal OUT output from the third stage ST3 (previous stage) can be input to the fourth stage ST4 (current stage) as the carry signal CR. In another embodiment, as Figure 6 As shown in , the carry signal CR may be a signal generated and output separately from the output signal OUT outputted from the previous stage.

[0104] A first voltage VGH, a second voltage VGL1, and a third voltage VGL2 may be input to each of the stages ST1 to STn. The first voltage VGH may be a first level voltage, and the second voltage VGL1 and the third voltage VGL2 may be second level voltages. In an embodiment, the second voltage VGL1 has a voltage level lower than that of the first voltage VGH, and the third voltage VGL2 has a voltage level lower than that of the second voltage VGL1.

[0105] The first clock signal CLK1 and the second clock signal CLK2 may be input to each of the stages ST1 to STn. Figure 6 As shown in , when the carry signal CR is a signal generated and output separately from the output signal OUT from the previous stage, the first carry clock signal CR_CLK1 or the second carry clock signal CR_CLK2 may be further input to each of the stages ST1 to STn.

[0106] Figure 7 is a diagram schematically illustrating a display device according to an embodiment. Figure 8 It is a schematic diagram Figure 7Diagram of the gate drive circuit. Fig. 9 It is a schematic diagram Figure 7 FIG. 1 is a diagram of a portion of a pixel and a gate drive circuit. FIG. 10A to FIG. 10E Is the graphic input to Figure 7 Diagram of the start signal and clock signal of the gate drive circuit. Fig.11 The diagram is from Figure 7 Diagram of the gate signal and carry signal output by the gate drive circuit. Fig.11 Gate signals supplied to the m-th row and the m+1-th row are illustrated.

[0107] like Figure 7 As shown in FIG. 1 , the display device 10 may include a pixel region 110 (eg, a display panel), a gate driving circuit 130, a data driving circuit 150, a power supply circuit 170, and a controller 190. In the following, for the sake of simplicity, the above reference will be omitted. Figure 1A , Figure 1B and Figure 2 The description given is a duplicate of the description.

[0108] In the pixel region 110, a plurality of gate lines may be arranged at specific intervals in the y direction (eg, the column direction). The gate lines may extend in the x direction (eg, the row direction) to be connected to pixels PX located in the same row (row line). For example, the pixels PX may be Figure 3 , and the gate lines connected to the pixel PX may include a first gate line GWL, a second gate line GIL, a third gate line GRL, a fourth gate line EML, and a fifth gate line EMBL. The first gate line GWL, the second gate line GIL, the third gate line GRL, the fourth gate line EML, and the fifth gate line EMBL may be arranged in each row.

[0109] A plurality of data lines DL may be arranged at certain intervals in the x direction in the pixel region 110. The data lines DL may extend in the y direction to be connected to pixels PX located in the same column (column line).

[0110] The gate drive circuit 130 may be connected to the gate line and may sequentially apply a gate signal to the gate line. The gate drive circuit 130 may include a first gate drive circuit 130L arranged on the left side of the pixel area 110 and a second gate drive circuit 130R arranged on the right side of the pixel area 110. In other embodiments, the gate drive circuit 130 may include only the first gate drive circuit 130L arranged on the left side of the pixel area 110 or the second gate drive circuit 130R arranged on the right side of the pixel area 110. Each of the first gate drive circuit 130L and the second gate drive circuit 130R may include a first drive circuit 131, a second drive circuit 133, a third drive circuit 135, a fourth drive circuit 137, and a fifth drive circuit 139.

[0111] The first driving circuit 131 may be connected to a plurality of first gate lines GWL, and may sequentially supply a first gate signal GW to the first gate lines GWL according to or in response to a first control signal GCS1. The second driving circuit 133 may be connected to a plurality of fourth gate lines EML, and may sequentially supply a fourth gate signal EM to the fourth gate line EML according to or in response to a second control signal GCS2. The third driving circuit 135 may be connected to a plurality of third gate lines GRL, and may sequentially supply a third gate signal GR to the third gate line GRL according to or in response to a third control signal GCS3. The fourth driving circuit 137 may be connected to a plurality of second gate lines GIL, and may sequentially supply a second gate signal GI to the second gate line GIL according to or in response to a fourth control signal GCS4. The fifth driving circuit 139 may be connected to a plurality of fifth gate lines EMBL, and may sequentially supply a fifth gate signal EMB to the fifth gate line EMBL according to or in response to a fifth control signal GCS5.

[0112] The data driving circuit 150 may be connected to the plurality of data lines DL, and may apply a data signal DATA representing a grayscale to the data line DL according to a sixth control signal DCS.

[0113] The power supply circuit 170 may generate a voltage for driving the pixel PX according to the seventh control signal PCS. For example, the power supply circuit 170 may generate a driving voltage ELVDD and a common voltage ELVSS, and supply them to the pixel PX. The power supply circuit 170 may generate a reference voltage Vref and an initialization voltage Vint, and supply them to the pixel PX. In an embodiment, the voltage level of the driving voltage ELVDD is higher than the voltage level of the common voltage ELVSS. In an embodiment, the voltage level of the reference voltage Vref is lower than the voltage level of the driving voltage ELVDD. In an embodiment, the voltage level of the initialization voltage Vint is lower than the voltage level of the common voltage ELVSS.

[0114] The power supply circuit 170 may generate voltages VGH and VGL for driving the gate driving circuit 130 and transmit them to the gate driving circuit 130. The voltage VGL may include a second voltage VGL1 (see Figure 5 and Figure 6 ) and the third voltage VGL2 (see Figure 5 and Figure 6 ).

[0115] refer to Figure 8 Each of the first driving circuit 131, the second driving circuit 133, the third driving circuit 135, the fourth driving circuit 137, and the fifth driving circuit 139 may include a plurality of stages. Each stage may receive at least one clock signal and at least one voltage signal and generate a gate signal corresponding thereto.

[0116] like FIG. 10A to FIG. 10E As shown in , at least one clock signal may be a square wave signal that repeats a high level voltage (first level voltage) and a low level voltage (second level voltage). The high level voltage may be a gate-on voltage for turning on an N-type transistor, and the low level voltage may be a gate-off voltage for turning off an N-type transistor. The timing of the rising edge of the clock signal (hereinafter, referred to as "rising edge timing") may be based on the horizontal synchronization signal Hsync (see Fig.15 ) to determine.

[0117] Under the control of the controller 190, the power supply circuit 170 can adjust the rising edge timing of the clock signal supplied to each of the first drive circuit 131, the second drive circuit 133, the third drive circuit 135, the fourth drive circuit 137 and the fifth drive circuit 139 and the timing of the start of the falling edge of the clock signal (hereinafter referred to as "falling edge timing").

[0118] Each of the first driving circuit 131 , the second driving circuit 133 , the third driving circuit 135 , the fourth driving circuit 137 and the fifth driving circuit 139 may output a gate signal having a specific signal width at a specific timing according to the rising edge timing and the falling edge timing of the clock signal.

[0119] The clock signal supplied to each of the first drive circuit 131, the second drive circuit 133, the third drive circuit 135, the fourth drive circuit 137, and the fifth drive circuit 139 may be a signal having the same waveform but phase-shifted (phase-delayed) at certain intervals. Fig. 10D As shown in , the second gate clock signal GI_CLK2 has the same waveform as that of the second gate clock signal GI_CLK1 but is phase-shifted (phase delayed) at a certain interval, and is then supplied to the fourth driving circuit 137 .

[0120] like Figure 8 As shown in , the first driving circuit 131 may include a plurality of stages WST1, WST2, WST3, WST4, ..., WST2m-1, WST2m connected in cascade, and each of the plurality of stages WST1, WST2, WST3, WST4, ..., WST2m-1, WST2m may correspond to each row of the pixel area 110. Fig. 10A and Fig.11, a plurality of stages WST1, WST2, WST3, WST4, ..., WST2m-1, WST2m may generate a first gate signal GW and a carry signal GW_CR based on a first start signal GW_FLM, first gate clock signals GW_CLK1, GW_CLK2, GW_CLK3, and GW_CLK4, and carry clock signals CR_CLK1, CR_CLK2, CR_CLK3, and CR_CLK4. The first gate signal GW may be output to a first gate line GWL of a corresponding row, and the carry signal GW_CR may be output to a next stage.

[0121] The odd-numbered stages among the plurality of stages WST1, WST2, WST3, WST4, ..., WST2m-1, WST2m may output the first gate signal GW having the first level voltage in synchronization with the rising edge of the first gate clock signal GW_CLK1 or the first gate clock signal GW_CLK3 among the first gate clock signals GW_CLK1, GW_CLK2, GW_CLK3, and GW_CLK4 at a specific timing. The first gate clock signal GW_CLK1 and the first gate clock signal GW_CLK3 may be alternately input to the odd-numbered stages. The even-numbered stages among the plurality of stages WST1, WST2, WST3, WST4, ..., WST2m-1, WST2m may output the first gate signal GW having the first level voltage in synchronization with the rising edge of the first gate clock signal GW_CLK2 or the first gate clock signal GW_CLK4 among the first gate clock signals GW_CLK1, GW_CLK2, GW_CLK3, and GW_CLK4 at a specific timing. The first gate clock signal GW_CLK2 and the first gate clock signal GW_CLK4 may be alternately input to the even-numbered stages.

[0122] The first gate signal GW output from a plurality of stages WST1, WST2, WST3, WST4, ..., WST2m-1, WST2m may be shifted in sequence. For example, the first gate signal GW may be shifted and output in sequence at intervals of 1 horizontal period (H). Here, 1H may be 1 / (driving frequency × vertical resolution). The number of stages of the first drive circuit 131 may be equal to the number of rows or the number of first gate lines GWL.

[0123] refer to Figure 8 , the second driving circuit 133 may include a plurality of stages EST1, EST2, . . . , ESTm connected in cascade, and each of the plurality of stages EST1, EST2, . . . , ESTm may correspond to two rows (a pair of rows) of the pixel area 110. Fig. 10B and Fig.11, a plurality of stages EST1, EST2, ..., ESTm may generate a fourth gate signal EM based on a fourth start signal EM_FLM and fourth gate clock signals EM_CLK1 and EM_CLK2. In an embodiment, the fourth gate signal EM is simultaneously output to fourth gate lines EML arranged in two rows, and may be output to the next stage as a carry signal EM_CR.

[0124] The odd-numbered stages among the plurality of stages EST1, EST2, ..., ESTm may output the fourth gate signal EM having a first level voltage in synchronization with a rising edge of one (e.g., the fourth gate clock signal EM_CLK1) of the fourth gate clock signals EM_CLK1 and EM_CLK2 at a specific timing. The even-numbered stages among the plurality of stages EST1, EST2, ..., ESTm may output the fourth gate signal EM having a first level voltage in synchronization with a rising edge of the other (e.g., the fourth gate clock signal EM_CLK2) of the fourth gate clock signals EM_CLK1 and EM_CLK2 at a specific timing.

[0125] The fourth gate signal EM output from the plurality of stages EST1, EST2, ..., ESTm may be shifted sequentially. For example, the fourth gate signal EM may be shifted and sequentially output at intervals of 2 horizontal periods (H). The number of stages of the second driving circuit 133 may be 1 / 2 of the number of rows or 1 / 2 of the number of the fourth gate line EML.

[0126] like Figure 8 As shown in , the third driving circuit 135 may include a plurality of stages RST1, RST2, . . . , RSTm connected in cascade, and each of the plurality of stages RST1, RST2, . . . , RSTm may correspond to two rows (a pair of rows) of the pixel area 110. Fig. 10C and Fig.11 , a plurality of stages RST1, RST2, ... RSTm may generate a third gate signal GR based on the third start signal GR_FLM and the third gate clock signals GR_CLK1 and GR_CLK2. In an embodiment, the third gate signal GR is simultaneously output to the third gate lines GRL arranged in two rows, and may be output to the next stage as a carry signal GR_CR.

[0127] The odd-numbered stages among the plurality of stages RST1, RST2, ..., RSTm may output the third gate signal GR having the first level voltage in synchronization with a rising edge of one (e.g., the third gate clock signal GR_CLK1) of the third gate clock signals GR_CLK1 and GR_CLK2 at a specific timing. The even-numbered stages among the plurality of stages RST1, RST2, ..., RSTm may output the third gate signal GR having the first level voltage in synchronization with a rising edge of the other (e.g., the third gate clock signal GR_CLK2) of the third gate clock signals GR_CLK1 and GR_CLK2 at a specific timing.

[0128] The third gate signal GR outputted from the plurality of stages RST1, RST2, ..., RSTm may be shifted sequentially. For example, the third gate signal GR may be shifted and sequentially outputted at intervals of 2 horizontal periods (H). The number of stages of the third driving circuit 135 may be 1 / 2 of the number of rows or 1 / 2 of the number of the third gate lines GRL.

[0129] like Figure 8 As shown in , the fourth driving circuit 137 may include a plurality of stages IST1, IST2, . . . , ISTm connected in cascade, and each of the plurality of stages IST1, IST2, . . . , ISTm may correspond to two rows (a pair of rows) of the pixel area 110. Fig. 10D and Fig.11 , a plurality of stages IST1, IST2, ..., ISTm may generate a second gate signal GI based on a second start signal GI_FLM and second gate clock signals GI_CLK1 and GI_CLK2. In an embodiment, the second gate signal GI is simultaneously output to second gate lines GIL arranged in two rows, and may be output to the next stage as a carry signal GI_CR.

[0130] The odd-numbered stages among the plurality of stages IST1, IST2, ..., ISTm may output the second gate signal GI having a first level voltage in synchronization with a rising edge of one of the second gate clock signals GI_CLK1 and GI_CLK2 (e.g., the second gate clock signal GI_CLK1) at a specific timing. The even-numbered stages among the plurality of stages IST1, IST2, ..., ISTm may output the second gate signal GI having a first level voltage in synchronization with a rising edge of the other of the second gate clock signals GI_CLK1 and GI_CLK2 (e.g., the second gate clock signal GI_CLK2) at a specific timing.

[0131] The second gate signal GI output from the plurality of stages IST1, IST2, ..., ISTm may be shifted sequentially. For example, the second gate signal GI may be shifted and sequentially output at intervals of 2 horizontal periods (H). The number of stages of the fourth driving circuit 137 may be 1 / 2 of the number of rows or 1 / 2 of the number of second gate lines GIL.

[0132] like Figure 8 As shown in , the fifth driving circuit 139 may include a plurality of stages BST1, BST2, . . . , BSTm connected in cascade, and each of the plurality of stages BST1, BST2, . . . , BSTm may correspond to two rows (a pair of rows) of the pixel region 110. Fig. 10E and Fig.11 , the plurality of stages BST1, BST2, . . . , BSTm may generate a fifth gate signal EMB based on the fifth start signal EMB_FLM and the fifth gate clock signals EMB_CLK1 and EMB_CLK2. The fifth gate signal EMB may be simultaneously output to the fifth gate lines EMBL arranged in two rows, and may be output to the next stage as a carry signal EMB_CR.

[0133] The odd-numbered stages among the plurality of stages BST1, BST2, ..., BSTm may output the fifth gate signal EMB having a first level voltage in synchronization with a rising edge of one (e.g., the fifth gate clock signal EMB_CLK1) of the fifth gate clock signals EMB_CLK1 and EMB_CLK2 at a specific timing. The even-numbered stages among the plurality of stages BST1, BST2, ..., BSTm may output the fifth gate signal EMB having a first level voltage in synchronization with a rising edge of the other (e.g., the fifth gate clock signal EMB_CLK2) of the fifth gate clock signals EMB_CLK1 and EMB_CLK2 at a specific timing.

[0134] The fifth gate signal EMB output from the plurality of stages BST1, BST2, ..., BSTm may be shifted sequentially. For example, the fifth gate signal EMB may be shifted and sequentially output at intervals of 2 horizontal periods (H). The number of stages of the fifth driving circuit 139 may be 1 / 2 of the number of rows or 1 / 2 of the number of the fifth gate line EMBL.

[0135] like Fig. 9As shown in, the first stage WST1 of the first driving circuit 131 can output the first first gate signal GW1 to the first gate line GWL1 connected to the first pixel PX1 arranged in the first row, the second stage WST2 of the first driving circuit 131 can output the second first gate signal GW2 to the first gate line GWL2 connected to the second pixel PX2 arranged in the second row, the third stage WST3 of the first driving circuit 131 can output the third first gate signal GW3 to the first gate line GWL3 connected to the third pixel PX3 arranged in the third row, and the fourth stage WST4 of the first driving circuit 131 can output the fourth first gate signal GW4 to the first gate line GWL4 connected to the fourth pixel PX4 arranged in the fourth row.

[0136] In an embodiment, the fourth gate signal EM output from the first stage EST1 of the second driving circuit 133 is simultaneously supplied as the first fourth gate signal EM1 to the fourth gate line EML1 connected to the first pixel PX1 and as the second fourth gate signal EM2 to the fourth gate line EML2 connected to the second pixel PX2. In an embodiment, the fourth gate signal EM output from the second stage EST2 of the second driving circuit 133 is simultaneously supplied as the third fourth gate signal EM3 to the fourth gate line EML3 connected to the third pixel PX3 arranged in the third row and as the fourth fourth gate signal EM4 to the fourth gate line EML4 connected to the fourth pixel PX4 arranged in the fourth row.

[0137] In an embodiment, the third gate signal GR output from the first stage RST1 of the third driving circuit 135 is simultaneously supplied as the first third gate signal GR1 to the third gate line GRL1 connected to the first pixel PX1 and as the second third gate signal GR2 to the third gate line GRL2 connected to the second pixel PX2. In an embodiment, the third gate signal GR output from the second stage RST2 of the third driving circuit 135 is simultaneously supplied as the third third gate signal GR3 to the third gate line GRL3 connected to the third pixel PX3 and as the fourth third gate signal GR4 to the third gate line GRL4 connected to the fourth pixel PX4.

[0138] In an embodiment, the second gate signal GI output from the first stage IST1 of the fourth driving circuit 137 is simultaneously supplied as the first second gate signal GI1 to the second gate line GIL1 connected to the first pixel PX1 and as the second second gate signal GI2 to the second gate line GIL2 connected to the second pixel PX2. In an embodiment, the second gate signal GI output from the second stage IST2 of the fourth driving circuit 137 is simultaneously supplied as the third second gate signal GI3 to the second gate line GIL3 connected to the third pixel PX3 and as the fourth second gate signal GI4 to the second gate line GIL4 connected to the fourth pixel PX4.

[0139] In an embodiment, the fifth gate signal EMB output from the first stage BST1 of the fifth driving circuit 139 is simultaneously supplied as the first fifth gate signal EMB1 to the fifth gate line EMBL1 connected to the first pixel PX1 and as the second fifth gate signal EMB2 to the fifth gate line EMBL2 connected to the second pixel PX2. In an embodiment, the fifth gate signal EMB output from the second stage BST2 of the fifth driving circuit 139 is simultaneously supplied as the third fifth gate signal EMB3 to the fifth gate line EMBL3 connected to the third pixel PX3 and as the fourth fifth gate signal EMB4 to the fifth gate line EMBL4 connected to the fourth pixel PX4.

[0140] In this way, if Fig.11 As shown in the figure, each of the second gate signal GI, the third gate signal GR, the fourth gate signal EM and the fifth gate signal EMB can be similarly supplied to the mth pixel arranged in the mth row and the m+1th pixel arranged in the m+1th row, and the first gate signal GW[m] and the first gate signal GW[m+1] can be sequentially supplied to the mth pixel and the m+1th pixel.

[0141] Fig.12 and Fig.13 is a diagram schematically illustrating changes in a clock signal, a gate signal, and a driving voltage. Fig.14 is a diagram illustrating a clock signal according to an embodiment. Figures 15 to 17 is a diagram illustrating a clock signal and a first gate signal according to an embodiment.

[0142] refer to Fig.12 In an embodiment, the rising edge timing of the second gate clock signal GI_CLK1, the rising edge timing of the third gate clock signal GR_CLK1, the rising edge timing of the fourth gate clock signal EM_CLK1 and the rising edge timing of the fifth gate clock signal EMB_CLK1 are identical to each other.

[0143] The second driving circuit 133, the third driving circuit 135, the fourth driving circuit 137, and the fifth driving circuit 139, which are common to the pixels in two rows (i.e., common to two stages), can output gate signals at intervals of 2H by operating as shift registers. Accordingly, in the third gate signal GR, the fourth gate signal EM, and the fifth gate signal EMB, signal ripples may appear at intervals of 2H, and therefore, ripples of the driving voltage ELVDD may appear at intervals of 2H. In addition, as Figure 4BAs shown in , when the sixth transistor T6 and the fourth transistor T4 are turned on in the first period P1 in which the second gate signal GI and the fifth gate signal EMB are supplied to the pixel PX and thus the second terminal of the first transistor T1 and the pixel electrode are initialized, a large ripple of the driving voltage ELVDD may occur. Because the first gate signal GW is output at intervals of 1H, the degree of ripple of the driving voltage ELVDD when the first gate signal GW is supplied to the pixels PX arranged in odd rows may be different from the degree of ripple of the driving voltage ELVDD when the first gate signal GW is supplied to the pixels PX arranged in even rows, as shown in FIG. Fig.13 Accordingly, in response to the same data signal, the brightness due to the light emission from the pixels PX in the odd-numbered rows may be different from the brightness due to the light emission from the pixels PX in the even-numbered rows.

[0144] In an embodiment, the generation time of the ripple of the driving voltage ELVDD can be adjusted by adjusting the rising edge timing of the gate clock signal to minimize the brightness deviation between the odd rows and the even rows. At least one of the rising edge timings of the second gate clock signals GI_CLK1 and GI_CLK2, the rising edge timing of the third gate clock signals GR_CLK1 and GR_CLK2, the rising edge timing of the fourth gate clock signals EM_CLK1 and EM_CLK2, and the rising edge timing of the fifth gate clock signals EMB_CLK1 and EMB_CLK2 can be shifted, for example, different from each other. For example, the rising edge timing of the second gate clock signal GI_CLK can be different from the rising edge timing of the third gate clock signal GR_CLK. Accordingly, the brightness deviation between the brightness caused by the pixels PX in the odd rows and the brightness caused by the pixels PX in the even rows can be minimized by adjusting the generation time of the ripple of the driving voltage ELVDD.

[0145] For example, Fig.14 As shown in, the rising edges of the third gate clock signal GR_CLK1, the fourth gate clock signal EM_CLK1, and the fifth gate clock signal EMB_CLK1 may be identical to each other, and the rising edge of the second gate clock signal GI_CLK1 may be shifted by a specific time SG from their rising edges, i.e., have different rising edge timings. The rising edge timing of the second gate clock signal GI_CLK1 may be later than the rising edge timings of the third gate clock signal GR_CLK1, the fourth gate clock signal EM_CLK1, and the fifth gate clock signal EMB_CLK1.

[0146] refer to Fig.14, the fourth driving circuit 137 may output a first second gate signal GI[1] having a first level voltage synchronized with the rising edge timing of the second gate clock signal GI_CLK1. The third driving circuit 135 may output a first third gate signal GR[1] having a first level voltage synchronized with the rising edge timing of the third gate clock signal GR_CLK1. The second driving circuit 133 may output a first fourth gate signal EM[1] having a first level voltage synchronized with the rising edge timing of the fourth gate clock signal EM_CLK1. The fifth driving circuit 139 may output a first fifth gate signal EMB[1] having a first level voltage synchronized with the rising edge timing of the fifth gate clock signal EMB_CLK1.

[0147] In an embodiment, the rising edge timing of the third gate clock signal GR_CLK1, the rising edge timing of the fourth gate clock signal EM_CLK1, and the rising edge timing of the fifth gate clock signal EMB_CLK1 are the same as each other. Similarly, the rising edge timing of the third gate clock signal GR_CLK2, the rising edge timing of the fourth gate clock signal EM_CLK2, and the rising edge timing of the fifth gate clock signal EMB_CLK2 can be the same as each other.

[0148] In an embodiment, the rising edge timing of the second gate clock signal GI_CLK1 is shifted by a specific time SG from the rising edge timing of the third gate clock signal GR_CLK1, the rising edge timing of the fourth gate clock signal EM_CLK1, and the rising edge timing of the fifth gate clock signal EMB_CLK1. Similarly, the rising edge timing of the second gate clock signal GI_CLK2 can be shifted by a specific time SG from the rising edge timing of the third gate clock signal GR_CLK2, the rising edge timing of the fourth gate clock signal EM_CLK2, and the rising edge timing of the fifth gate clock signal EMB_CLK2. Accordingly, the brightness deviation between the brightness caused by the pixels PX in the odd rows and the brightness caused by the pixels PX in the even rows can be minimized by adjusting the generation time of the ripple of the driving voltage ELVDD.

[0149] Table 1 below illustrates the brightness deviation between odd-numbered lines and even-numbered lines according to the rising edge timing SCTE of the horizontal synchronization signal Hsync depending on the second gate clock signal GI_CLK (GI_CLK1 and GI_CLK2), as shown in FIG. Fig.15 The brightness deviation between the odd-numbered rows and the even-numbered rows may vary depending on the rising edge timing SCTE of the second gate clock signal GI_CLK1.

[0150] Referring to Table 1, when the rising edge timing SCTE of the second gate clock signal GI_CLK is 0.5μs, the brightness deviation between the odd rows and the even rows can be 3.99%, when the rising edge timing SCTE of the second gate clock signal GI_CLK is 1.0μs, the brightness deviation between the odd rows and the even rows can be 1.21%, and when the rising edge timing SCTE of the second gate clock signal GI_CLK is 1.5μs, the brightness deviation between the odd rows and the even rows can be 0.38%. In this case, the rising edge timing of the third gate clock signal GR_CLK (GR_CLK1 and GR_CLK2), the rising edge timing of the fourth gate clock signal EM_CLK (EM_CLK1 and EM_CLK2), and the rising edge timing of the fifth gate clock signal EMB_CLK (EMB_CLK1 and EMB_CLK2) can be 0.5μs, and the rising edge timing of the first gate clock signal GW_CLK (GW_CLK1, GW_CLK2, GW_CLK3, and GW_CLK4) can be 0μs.

[0151] SCTE(μs) Brightness deviation (%) 0.5 3.99 1.0 1.21 1.5 0.38

[0152] Table 1

[0153] In an embodiment, Fig.16 As shown in , the rising edge timing SCTE2 of the second gate clock signal GI_CLK may be later than the rising edge timing SCTE1 of each of the third gate clock signal GR_CLK, the fourth gate clock signal EM_CLK, and the fifth gate clock signal EMB_CLK. The rising edge timing of the first gate clock signal GW_CLK may be before the rising edge timing SCTE2 of the second gate clock signal GI_CLK and the rising edge timing SCTE1 of each of the third gate clock signal GR_CLK, the fourth gate clock signal EM_CLK, and the fifth gate clock signal EMB_CLK. For example, the rising edge timing of the first gate clock signal GW_CLK may be 0 μs, the rising edge timing SCTE1 of each of the third gate clock signal GR_CLK, the fourth gate clock signal EM_CLK, and the fifth gate clock signal EMB_CLK may be 0.5 μs (or greater), and the rising edge timing SCTE2 of the second gate clock signal GI_CLK may be 1.5 μs (or greater). Accordingly, a brightness deviation between brightness due to the pixels PX in the odd-numbered rows and brightness due to the pixels PX in the even-numbered rows may be minimized by adjusting the generation time of the ripple of the driving voltage ELVDD.

[0154] In an embodiment, Fig.17As shown in , the rising edge timing SCTE2 of the third gate clock signal GR_CLK may be later than the rising edge timing SCTE1 of each of the second gate clock signal GI_CLK, the fourth gate clock signal EM_CLK, and the fifth gate clock signal EMB_CLK. The rising edge timing of the first gate clock signal GW_CLK may be before the rising edge timing SCTE2 of the third gate clock signal GR_CLK and the rising edge timing SCTE1 of each of the second gate clock signal GI_CLK, the fourth gate clock signal EM_CLK, and the fifth gate clock signal EMB_CLK. For example, the rising edge timing of the first gate clock signal GW_CLK may be 0 μs, the rising edge timing SCTE1 of each of the second gate clock signal GI_CLK, the fourth gate clock signal EM_CLK, and the fifth gate clock signal EMB_CLK may be 0.5 μs (or greater), and the rising edge timing SCTE2 of the third gate clock signal GR_CLK may be 1.5 μs (or greater). Accordingly, a brightness deviation between brightness due to the pixels PX in the odd-numbered rows and brightness due to the pixels PX in the even-numbered rows may be minimized by adjusting the generation time of the ripple of the driving voltage ELVDD.

[0155] However, the embodiments of the present disclosure are not limited to Fig.16 and Fig.17 . In an embodiment, the rising edge timing of the first gate clock signal GW_CLK may be 0 μs, the rising edge timing of each of the second gate clock signal GI_CLK, the third gate clock signal GR_CLK, and the fifth gate clock signal EMB_CLK may be 0.5 μs, and the rising edge timing of the fourth gate clock signal EM_CLK may be 1.5 μs. Alternatively, in an embodiment, the rising edge timing of the first gate clock signal GW_CLK may be 0 μs, the rising edge timing of each of the second gate clock signal GI_CLK, the third gate clock signal GR_CLK, and the fourth gate clock signal EM_CLK may be 0.5 μs, and the rising edge timing of the fifth gate clock signal EMB_CLK may be 1.5 μs.

[0156] Fig.18 is a diagram illustrating the timing of a first gate signal according to an embodiment.

[0157] In an embodiment, the signal width of the first gate signal GW can be adjusted without changing the rising edge timing of the gate clock signal to minimize the Fig.12 and Fig.13The luminance deviation between the luminance of the pixels PX in the odd rows and the luminance of the pixels PX in the even rows caused by the ripple of the driving voltage ELVDD illustrated in FIG. The signal width of the first gate signal GW may correspond to the period (duration) in which the gate-on voltage of the first gate signal GW is maintained in the third period P3. The signal width of the first gate signal GW may be adjusted by adjusting the signal width of the first gate clock signal GW_CLK supplied to the first driving circuit 131. Under the control of the controller 190, the power supply circuit 170 may adjust the signal width of the first gate clock signal GW_CLK supplied to the first driving circuit 131.

[0158] The third period P3 (see Figure 4A and Figure 4B ). When the signal width of the first gate signal GW increases, the time for writing the data signal increases, and thus the brightness of the pixel PX increases. Therefore, the brightness deviation between the odd rows and the even rows can be minimized by adjusting the signal width of the first gate signal GW supplied to the pixels PX in the odd rows and the signal width of the first gate signal GW supplied to the pixels PX in the even rows, thereby adjusting the brightness of the pixels PX in the odd rows and the brightness of the pixels PX in the even rows. In this case, the rising edge timing of each of the second gate clock signal GI_CLK, the third gate clock signal GR_CLK, the fourth gate clock signal EM_CLK, and the fifth gate clock signal EMB_CLK may be the same as each other. For example, the rising edge timing of the first gate clock signal GW_CLK may be 0 μs, and the rising edge timing of each of the second gate clock signal GI_CLK, the third gate clock signal GR_CLK, the fourth gate clock signal EM_CLK, and the fifth gate clock signal EMB_CLK may be 0.5 μs.

[0159] In an embodiment where the brightness of the pixels PX in the odd rows is higher than the brightness of the pixels PX in the even rows, the second signal width SW2 of the first gate signals (GW[2], GW[4], ...) supplied to the pixels PX in the even rows is greater than the first signal width SW1 of the first gate signals (GW[1], GW[3], ...) supplied to the pixels PX in the odd rows, such as Fig.18 As shown in . In an embodiment, the first signal width SW1 is greater than 1 horizontal period (1H) and less than 2 horizontal periods (2H). In an embodiment, the second signal width SW2 is greater than the first signal width SW1 and less than 2 horizontal periods (2H).

[0160] Similarly, when the brightness of the pixels PX in the even rows is higher than the brightness of the pixels PX in the odd rows, the second signal width SW2 of the first gate signals (GW[2], GW[4], ...) supplied to the pixels PX in the even rows may be smaller than the first signal width SW1 of the first gate signals (GW[1], GW[3], ...) supplied to the pixels PX in the odd rows.

[0161] In the above-described embodiments, outputting (or supplying) a specific signal may mean outputting (or supplying) a first level voltage, and not outputting (or supplying) the specific signal may mean outputting (or supplying) a second level voltage.

[0162] In the gate driving circuit according to the embodiment, the driving circuit outputting the gate signal for writing the data signal (for example, the first driving circuit outputting the first gate signal GW) may include a plurality of stages in units of rows, and at least one driving circuit outputting the gate signal for initialization and compensation (for example, the fourth driving circuit, the third driving circuit, the second driving circuit, and the fifth driving circuit outputting the second gate signal GI, the third gate signal GR, the fourth gate signal EM, and the fifth gate signal EMB, respectively) may include a plurality of stages of a two-stage common structure common to two rows. According to the embodiment, the brightness deviation between the odd rows and the even rows can be minimized by adjusting the rising edge timing of the clock signal supplied for outputting at least one of the second gate signal GI, the third gate signal GR, the fourth gate signal EM, and the fifth gate signal EMB, or by adjusting the signal width of the gate signal for writing the data signal.

[0163] Fig.19 is a cross-sectional view illustrating the structure of a display element according to the embodiment. Figure 20 to Figure 25 is a cross-sectional view illustrating the structure of a display element according to the embodiment.

[0164] refer to Fig.19 The organic light emitting diode OLED as a display element according to the embodiment may include a pixel electrode 211, an opposing electrode 215, and an intermediate layer 213 located between the pixel electrode 211 (first electrode or anode) and the opposing electrode 215 (second electrode or cathode).

[0165] The pixel electrode 211 may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3), indium gallium oxide (IGO) or aluminum zinc oxide (AZO). The pixel electrode 211 may include a reflective layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or any compound thereof. For example, the pixel electrode 211 may have a three-layer structure of ITO / Ag / ITO.

[0166] The counter electrode 215 may be disposed above the intermediate layer 213. The counter electrode 215 may include a metal, an alloy, a conductive compound, or any combination thereof having a low work function. For example, the counter electrode 215 may include lithium (Li), silver (Ag), magnesium (Mg), aluminum (Al), aluminum-lithium (Al-Li), calcium (Ca), magnesium-indium (Mg-In), magnesium-silver (Mg-Ag), ytterbium (Yb), silver-ytterbium (Ag-Yb), ITO, IZO, or any combination thereof. The counter electrode 215 may be a transparent electrode, a semi-transparent electrode, or a reflective electrode.

[0167] The intermediate layer 213 may include a high molecular weight or low molecular weight organic material for emitting light of a specific color. In addition to various organic materials, the intermediate layer 213 may further include a metal-containing compound such as an organic metal compound or an inorganic material such as a quantum dot.

[0168] In an embodiment, the intermediate layer 213 includes an emission layer and a first functional layer and a second functional layer respectively disposed below and above the emission layer. For example, the first functional layer may include a hole transport layer (HTL) or may include an HTL and a hole injection layer (HIL). The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The first functional layer or the second functional layer may be omitted. Each of the first functional layer and the second functional layer may be integrally formed to correspond to a plurality of organic light emitting diodes OLED included in the display area DA.

[0169] In an embodiment, the intermediate layer 213 may include two or more emission units sequentially stacked between the pixel electrode 211 and the counter electrode 213 and a charge generation layer arranged between the two emission units. When the intermediate layer 213 includes an emission unit and a charge generation layer, the organic light emitting diode OLED may be a tandem light emitting device. Because the organic light emitting diode OLED has a stacked structure of multiple emission units, its color purity and luminous efficiency may be improved.

[0170] An emission unit may include an emission layer and a first functional layer and a second functional layer below and above the emission layer, respectively. The charge generation layer may include a negative charge generation layer and a positive charge generation layer. The luminous efficiency of an organic light emitting diode OLED, which is a tandem light emitting device including multiple emission layers, can be further improved by a negative charge generation layer and a positive charge generation layer.

[0171] The negative charge generation layer may be an n-type charge generation layer. The negative charge generation layer may supply electrons. The negative charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material. The positive charge generation layer may be a p-type charge generation layer. The positive charge generation layer may supply holes. The positive charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material.

[0172] In an embodiment, Fig. 20 As shown in , the organic light emitting diode OLED may include a first emission unit EU1 including a first emission layer EML1 and a second emission unit EU2 including a second emission layer EML2 stacked in sequence. A charge generation layer CGL may be provided between the first emission unit EU1 and the second emission unit EU2. For example, the organic light emitting diode OLED may include a pixel electrode 211, a first emission layer EML1, a charge generation layer CGL, a second emission layer EML2, and a counter electrode 215 stacked in sequence. The first functional layer and the second functional layer may be included below and above the first emission layer EML1, respectively. The first functional layer and the second functional layer may be included below and above the second emission layer EML2, respectively. The first emission layer EML1 may be a blue emission layer, and the second emission layer EML2 may be a yellow emission layer.

[0173] In an embodiment, Fig.21 As shown in , the organic light emitting diode OLED may include a first emission unit EU1 and a third emission unit EU3 each including a first emission layer EML1, and a second emission unit EU2 including a second emission layer EML2. The first charge generation layer CGL1 may be located between the first emission unit EU1 and the second emission unit EU2, and the second charge generation layer CGL2 may be located between the second emission unit EU2 and the third emission unit EU3. For example, the organic light emitting diode OLED may include a pixel electrode 211, a first emission layer EML1, a first charge generation layer CGL1, a second emission layer EML2, a second charge generation layer CGL2, a first emission layer EML1, and a counter electrode 215 stacked in sequence. The first functional layer and the second functional layer may be disposed below and above the first emission layer EML1, respectively. The first functional layer and the second functional layer may be disposed below and above the second emission layer EML2, respectively. The first emission layer EML1 may be a blue emission layer, and the second emission layer EML2 may be a yellow emission layer.

[0174] In an embodiment, in the organic light emitting diode OLED, in addition to the second emission layer EML2, the second emission unit EU2 may further include a third emission layer EML3 and / or a fourth emission layer EML4 directly contacting the second emission layer EML2 below and / or above the second emission layer EML2. Here, direct contact may mean that no other layers are arranged between the second emission layer EML2 and the third emission layer EML3 and / or between the second emission layer EML2 and the fourth emission layer EML4. The third emission layer EML3 may be a red emission layer, and the fourth emission layer EML4 may be a green emission layer.

[0175] For example, Fig. 22 As shown in , the organic light emitting diode OLED may include a pixel electrode 211, a first emission layer EML1, a first charge generation layer CGL1, a third emission layer EML3, a second emission layer EML2, a second charge generation layer CGL2, a first emission layer EML1 and a counter electrode 215 stacked sequentially. Alternatively, as Fig.23 As shown in the figure, the organic light emitting diode OLED may include a pixel electrode 211, a first emission layer EML1, a first charge generation layer CGL1, a third emission layer EML3, a second emission layer EML2, a fourth emission layer EML4, a second charge generation layer CGL2, a first emission layer EML1 and a counter electrode 215 stacked sequentially.

[0176] Fig.24 It is a graphic Fig. 22 A cross-sectional view of an example of an organic light emitting diode, and Fig.25 It is a graphic Fig.23 A cross-sectional view of an example of an organic light emitting diode.

[0177] refer to Fig.24 , the organic light emitting diode OLED may include a first emission unit EU1, a second emission unit EU2, and a third emission unit EU3 stacked sequentially. A first charge generation layer CGL1 may be provided between the first emission unit EU1 and the second emission unit EU2, and a second charge generation layer CGL2 may be provided between the second emission unit EU2 and the third emission unit EU3. Each of the first charge generation layer CGL1 and the second charge generation layer CGL2 may include a negative charge generation layer nCGL and a positive charge generation layer pCGL.

[0178] The first emission unit EU1 may include a blue emission layer BEML. The first emission unit EU1 may further include a hole injection layer HIL and a hole transport layer HTL located between the pixel electrode 211 and the blue emission layer BEML. In an embodiment, a p-doped layer may be further included between the hole injection layer HIL and the hole transport layer HTL. The p-doped layer may be formed by doping the hole injection layer HIL with a p-type dopant. In an embodiment, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may be further included between the blue emission layer BEML and the hole transport layer HTL. The blue light auxiliary layer may improve the light output efficiency of the blue emission layer BEML. The blue light auxiliary layer may adjust the hole charge balance to improve the light output efficiency of the blue emission layer BEML. The electron blocking layer may prevent electrons from being injected into the hole transport layer HTL. The buffer layer may compensate for the resonance distance depending on the wavelength of light emitted from the blue emission layer BEML.

[0179] The second emission unit EU2 may include a yellow emission layer YEML and a red emission layer REML directly contacting the yellow emission layer YEML below the yellow emission layer YEML. The second emission unit EU2 may further include a hole transport layer HTL located between the red emission layer REML and the positive charge generation layer pCGL of the first charge generation layer CGL1, and may further include an electron transport layer ETL located between the yellow emission layer YEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0180] The third emission unit EU3 may include a blue emission layer BEML. The third emission unit EU3 may further include a hole transport layer HTL located between the blue emission layer BEML and the positive charge generation layer pCGL of the second charge generation layer CGL2. The third emission unit EU3 may further include an electron transport layer ETL and an electron injection layer EIL located between the blue emission layer BEML and the counter electrode 215. The electron transport layer ETL may include a single layer or multiple layers. In an embodiment, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may be further included between the blue emission layer BEML and the hole transport layer HTL. At least one of a hole blocking layer and a buffer layer may be further included between the blue emission layer BEML and the electron transport layer ETL. The hole blocking layer may prevent holes from being injected into the electron transport layer ETL.

[0181] As for the stacking structure of the second emission unit EU2, Fig.25 The organic light emitting diode OLED shown in the figure can be different from Fig.24 The organic light emitting diode OLED shown in the figure, and its other configurations can be Fig.24 The structure is the same as shown in the figure. Fig.25, the second emission unit EU2 may include a yellow emission layer YEML, a red emission layer REML directly contacting the yellow emission layer YEML below the yellow emission layer YEML, and a green emission layer GEML directly contacting the yellow emission layer YEML above the yellow emission layer YEML. The second emission unit EU2 may further include a hole transport layer HTL located between the red emission layer REML and the positive charge generation layer pCGL of the first charge generation layer CGL1, and may further include an electron transport layer ETL located between the green emission layer GEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0182] Fig.26 is a cross-sectional view illustrating a structure of a pixel of a display device according to an embodiment.

[0183] refer to Fig.26 , the display device may include a plurality of pixels. The plurality of pixels may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. Each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a pixel electrode 211, a counter electrode 215, and an intermediate layer 213. In an embodiment, the first pixel PX1 may be a red pixel, the second pixel PX2 may be a green pixel, and the third pixel PX3 may be a blue pixel. Here, each pixel may include an organic light emitting diode OLED as a display element, and the organic light emitting diode OLED of each pixel may be electrically connected to the pixel circuit.

[0184] The pixel electrode 211 may be independently provided in each of the first pixel PX1 , the second pixel PX2 , and the third pixel PX3 .

[0185] The intermediate layer 213 of the organic light emitting diode OLED of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a first emission unit EU1 and a second emission unit EU2 stacked sequentially and a charge generation layer CGL located between the first emission unit EU1 and the second emission unit EU2. The charge generation layer CGL may include a negative charge generation layer nCGL and a positive charge generation layer pCGL. The charge generation layer CGL may be a common layer continuously formed in the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0186] The first emission unit EU1 of the first pixel PX1 may include a hole injection layer HIL, a hole transport layer HTL, a red emission layer REML, and an electron transport layer ETL sequentially stacked above the pixel electrode 211. The first emission unit EU1 of the second pixel PX2 may include a hole injection layer HIL, a hole transport layer HTL, a green emission layer GEML, and an electron transport layer ETL sequentially stacked above the pixel electrode 211. The first emission unit EU1 of the third pixel PX3 may include a hole injection layer HIL, a hole transport layer HTL, a blue emission layer BEML, and an electron transport layer ETL sequentially stacked above the pixel electrode 211. Each of the hole injection layer HIL, the hole transport layer HTL, and the electron transport layer ETL of the first emission unit EU1 may be a common layer continuously formed in the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0187] The second emission unit EU2 of the first pixel PX1 may include a hole transport layer HTL, an auxiliary layer AXL, a red emission layer REML, and an electron transport layer ETL sequentially stacked above the charge generation layer CGL. The second emission unit EU2 of the second pixel PX2 may include a hole transport layer HTL, a green emission layer GEML, and an electron transport layer ETL sequentially stacked above the charge generation layer CGL. The second emission unit EU2 of the third pixel PX3 may include a hole transport layer HTL, a blue emission layer BEML, and an electron transport layer ETL sequentially stacked above the charge generation layer CGL. Each of the hole transport layer HTL and the electron transport layer ETL of the second emission unit EU2 may be a common layer continuously formed in the first pixel PX1, the second pixel PX2, and the third pixel PX3. In an embodiment, at least one of a hole blocking layer and a buffer layer may be further included between the emission layer and the electron transport layer ETL in the second emission unit EU2 of the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0188] The thickness H1 of the red emission layer REML, the thickness H2 of the green emission layer GEML, and the thickness H3 of the blue emission layer BEML may be determined according to the resonance distance. The auxiliary layer AXL may be a layer added to adjust the resonance distance and may include a resonance auxiliary material. For example, the auxiliary layer AXL may include the same material as the hole transport layer HTL.

[0189] exist Fig.26 , the auxiliary layer AXL is included only in the first pixel PX1. However, the embodiments of the present disclosure are not limited thereto. For example, the auxiliary layer AXL may be included in at least one of the first pixel PX1, the second pixel PX2, and the third pixel PX3 to adjust the resonance distance of the corresponding pixel among the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0190] The display device may further include a capping layer 217 disposed outside the counter electrode 215. According to the principle of constructive interference, the capping layer 217 may improve the light emitting efficiency. Accordingly, the light extraction efficiency of the organic light emitting diode OLED may be improved, and thus, the light emitting efficiency of the organic light emitting diode OLED may be improved.

[0191] Embodiments of the present disclosure may provide a display device having improved display quality by minimizing its brightness deviation. However, the effects of the present disclosure are not limited to the above effects, and various extensions may be made without departing from the spirit of the present disclosure.

[0192] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes may be made in form and detail without departing from the spirit and scope of the present disclosure.

Claims

1. A driving circuit for outputting at least one gate signal to a pixel of a display panel, the driving circuit comprising: a first driving circuit configured to receive a first clock signal and, in a first period in a frame period in which data is supplied to the pixel, output a first gate signal having a gate-on voltage synchronized with a rising edge timing of the first clock signal, a second driving circuit configured to receive a second clock signal and, in a second period in the frame period for initializing the driving transistor of the pixel, output a second gate signal having a gate-on voltage synchronized with a rising edge timing of the second clock signal; as well as a third driving circuit configured to receive a third clock signal and, in a third period in the frame period for compensating the threshold voltage of the driving transistor of the pixel, output a third gate signal having a gate-on voltage synchronized with a rising edge timing of the third clock signal, The rising edge timing of the second clock signal is different from the rising edge timing of the third clock signal.

2. The driving circuit according to claim 1, wherein: The first driving circuit includes a plurality of first stages each configured to output the first gate signal to a corresponding pixel row of the display panel, The second driving circuit includes a plurality of second stages each configured to simultaneously output the second gate signal to a corresponding pair of pixel rows of the display panel, and The third driving circuit includes a plurality of third stages each configured to simultaneously output the third gate signal to a corresponding pair of pixel rows of the display panel.

3. The driving circuit according to claim 1, wherein: The second time period is before the first time period, and the third time period is between the first time period and the second time period.

4. The driving circuit according to claim 1, further comprising: a fourth driving circuit configured to receive a fourth clock signal and output a fourth gate signal having a gate-on voltage synchronized with a rising edge timing of the fourth clock signal in at least a portion of the second period and an emission period of the pixel, wherein the light emitting device of the pixel is initialized in the second period, and The rising edge timing of the fourth clock signal is the same as the rising edge timing of the second clock signal or the rising edge timing of the third clock signal.

5. The driving circuit according to claim 4, wherein: The fourth driving circuit includes a plurality of fourth stages each configured to simultaneously output the fourth gate signal to a corresponding pair of pixel rows of the display panel.

6. The driving circuit according to claim 4, further comprising: a fifth driving circuit configured to receive a fifth clock signal and, in the third period and the emission period of the pixel, output a fifth gate signal having a gate-on voltage synchronized with the rising edge timing of the fifth clock signal, The rising edge timing of the fifth clock signal is the same as the rising edge timing of the second clock signal or the rising edge timing of the third clock signal.

7. The driving circuit according to claim 6, wherein: The fifth driving circuit includes a plurality of fifth stages each configured to simultaneously output the fifth gate signal to a corresponding pair of pixel rows of the display panel.

8. The driving circuit according to claim 1, wherein: The rising edge timing of the second clock signal is later than the rising edge timing of the third clock signal.

9. The driving circuit according to claim 8, wherein: The rising edge timing of the third clock signal is 0.5 microseconds with respect to a horizontal synchronization signal, and the rising edge timing of the second clock signal is 1.5 microseconds with respect to the horizontal synchronization signal.

10. The driving circuit according to claim 1, wherein: The rising edge timing of the third clock signal is later than the rising edge timing of the second clock signal.

11. The driving circuit according to claim 10, wherein: The rising edge timing of the second clock signal is 0.5 microseconds with respect to a horizontal synchronization signal, and the rising edge timing of the third clock signal is 1.5 microseconds with respect to the horizontal synchronization signal.

12. The driving circuit according to claim 1, wherein: A signal width of the first gate signal output to odd-numbered pixel rows of the display panel is equal to a signal width of the first gate signal output to even-numbered pixel rows of the display panel.

13. The driving circuit according to any one of claims 1 to 12, wherein: The rising edge timing of the first clock signal is before the rising edge timing of the second clock signal and the rising edge timing of the third clock signal.

14. A driving circuit for outputting at least one gate signal to a pixel of a display panel, the driving circuit comprising: a first driving circuit configured to receive a first clock signal and, in a first period in a frame period in which data is supplied to the pixel, output a first gate signal having a gate-on voltage synchronized with a rising edge timing of the first clock signal, a second driving circuit configured to receive a second clock signal and, in a second period in the frame period for initializing the driving transistor of the pixel, output a second gate signal having a gate-on voltage synchronized with a rising edge timing of the second clock signal; as well as a third driving circuit configured to receive a third clock signal and, in a third period in the frame period for compensating the threshold voltage of the driving transistor of the pixel, output a third gate signal having a gate-on voltage synchronized with a rising edge timing of the third clock signal, In the first period, a signal width of the first gate signal output to the odd pixel rows of the display panel is different from a signal width of the first gate signal output to the even pixel rows of the display panel.

15. The driving circuit according to claim 14, wherein: The rising edge timing of the second clock signal and the rising edge timing of the third clock signal are identical to each other, and The rising edge timing of the first clock signal is before the rising edge timing of the second clock signal and the rising edge timing of the third clock signal.

16. The driving circuit according to claim 14, wherein: The first driving circuit includes a plurality of first stages each configured to output the first gate signal to a corresponding pixel row of the display panel, The second driving circuit includes a plurality of second stages each configured to simultaneously output the second gate signal to a corresponding pair of pixel rows of the display panel, and The third driving circuit includes a plurality of third stages each configured to simultaneously output the third gate signal to a corresponding pair of pixel rows of the display panel.

17. The driving circuit according to claim 15, further comprising: a fourth driving circuit configured to receive a fourth clock signal and output a fourth gate signal having a gate-on voltage synchronized with a rising edge timing of the fourth clock signal in at least a portion of the second period and an emission period of the pixel, wherein the light emitting device of the pixel is initialized in the second period, and The rising edge timing of the fourth clock signal is the same as the rising edge timing of the second clock signal.

18. The driving circuit according to claim 17, wherein: The fourth driving circuit includes a plurality of fourth stages each configured to simultaneously output the fourth gate signal to a corresponding pair of pixel rows of the display panel.

19. The driving circuit according to claim 17, further comprising: a fifth driving circuit configured to receive a fifth clock signal and, in the third period and the emission period of the pixel, output a fifth gate signal having a gate-on voltage synchronized with the rising edge timing of the fifth clock signal, The rising edge timing of the fifth clock signal is the same as the rising edge timing of the second clock signal.

20. The driving circuit according to claim 19, wherein: The fifth driving circuit includes a plurality of fifth stages each configured to simultaneously output the fifth gate signal to a corresponding pair of pixel rows of the display panel.

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