Array substrate, display panel, control method of display panel and projection equipment

Abstract

The invention provides an array substrate, a display panel, a control method of the display panel and projection equipment. A driving circuit layer of the array substrate comprises a first transistor, an output circuit, a control circuit, a data signal line, a first signal line, a second signal line and an output signal line. The first transistor is located in the central region. The output circuit and the control circuit are located in the peripheral area. The first electrode of the first transistor and the input end of the output circuit are connected with a data signal line. The control end of the output circuit is electrically connected with the first signal line, and the output end is connected with the output signal line. The output end of the control circuit is connected with the signal input end of the data signal line, the input end receives an input signal, and the control end is electrically connected with the second signal line. The first signal line and the second signal line are configured to turn off the control circuit when the output circuit is turned on, and the leakage current of the first transistor is output through the output signal line; when the output circuit is turned off, the control circuit is turned on, and the data signal line receives an input signal and transmits the input signal to the first transistor.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a display panel and a control method thereof, and a projection device. Background Art

[0002] A projector generally includes a light source, a liquid crystal display panel, a lens, etc. The light emitted by the light source is incident on the liquid crystal display panel so that the liquid crystal display panel displays an image, and the lens projects the image displayed on the display panel.

[0003] The image quality of the images projected by the existing projectors is poor, which affects the user experience. Summary of the invention

[0004] The present application provides an array substrate, a display panel and a control method thereof, and a projection device.

[0005] According to a first aspect of an embodiment of the present application, an array substrate is provided. The array substrate comprises a central area and a peripheral area located at at least one side of the central area; the array substrate comprises a substrate and a driving circuit layer located on the substrate;

[0006] The driving circuit layer includes a first transistor, an output circuit, a control circuit, a data signal line, a first signal line, a second signal line and an output signal line; the first transistor is located in the central area; the output circuit and the control circuit are located in the peripheral area; the first transistor includes a first electrode, a second electrode and a gate;

[0007] The first electrode of the first transistor and the input end of the output circuit are respectively connected to the data signal line; the control end of the output circuit is electrically connected to the first signal line, and the output end of the output circuit is connected to the output signal line; the output end of the control circuit is connected to the signal input end of the data signal line, the input end of the control circuit receives an input signal, and the control end of the control circuit is electrically connected to the second signal line;

[0008] The first signal line and the second signal line are configured as follows: when the output circuit is turned on, the control circuit is turned off, and the leakage current of the first transistor is output through the output signal line; when the output circuit is turned off, the control circuit is turned on, and the data signal line receives an input signal and transmits it to the first transistor.

[0009] In one embodiment, the driving circuit layer includes a plurality of pixel driving circuits located in the central area, and at least one of the pixel driving circuits includes the first transistor.

[0010] In one embodiment, the driving circuit layer includes a plurality of pixel driving circuits located in the central area, each of the pixel driving circuits includes one first transistor; the first transistors in the display area are arranged in a plurality of columns, and the first transistors in the same column are connected to the same data signal line;

[0011] The driving circuit layer includes a plurality of output circuits and a plurality of control circuits. One data signal line is connected to one output circuit; and one data signal line is connected to one control circuit.

[0012] In one embodiment, the output circuit includes at least one second transistor, and the control circuit includes at least one third transistor.

[0013] In one embodiment, the output circuit comprises two or more second transistors, and the second transistors of the same output circuit are connected in series; and / or,

[0014] The control circuit includes two or more third transistors, and the third transistors of the same control circuit are connected in series.

[0015] In one embodiment, the second transistor and the third transistor are both N-type transistors, and the first signal line and the second signal line are specifically configured as follows: during a frame display period, the first signal line provides a low-level signal to the second transistor, and the second signal line provides a high-level signal to the third transistor, so that the second transistor is turned off and the third transistor is turned on; during a black frame period between two frames, the first signal line provides a high-level signal to the second transistor, and the second signal line provides a low-level signal to the third transistor, so that the second transistor is turned on and the third transistor is turned off; or,

[0016] The second transistor and the third transistor are both P-type transistors, and the first signal line and the second signal line are specifically configured as follows: during the display of a frame of picture, the first signal line provides a high-level signal to the second transistor, and the second signal line provides a low-level signal to the third transistor, so that the second transistor is turned off and the third transistor is turned on; during the black picture period between two frames of pictures, the first signal line provides a low-level signal to the second transistor, and the second signal line provides a high-level signal to the third transistor, so that the second transistor is turned on and the third transistor is turned off.

[0017] In one embodiment, the first signal line and the second signal line are further configured to provide a signal to a gate driving circuit.

[0018] In one embodiment, the first signal line is configured to provide an initial input signal to the gate driving circuit during a frame display period, and the second signal line is configured to provide a reset signal to the gate driving circuit during a black frame period between two frames.

[0019] In one embodiment, the extension direction of the first signal line and the extension direction of the second signal line are respectively parallel to the extension direction of the data signal line, the driving circuit layer further includes a first lead and a second lead, and the extension direction of the first lead and the extension direction of the second lead intersect with the extension direction of the data signal line;

[0020] One end of the first lead is connected to the first signal line, and the first lead is connected to the control end of the output circuit; one end of the second lead is connected to the second signal line, and the second lead is connected to the control end of the control circuit.

[0021] In one embodiment, the driving circuit layer further includes at least one third signal line, the third signal line is located between the data signal line and the first signal line, and between the data signal line and the second signal line; the driving circuit layer includes a first conductive layer and a second conductive layer, the third signal line is located in the first conductive layer;

[0022] The first lead includes a connected first section and a second section, the first section is connected to the first signal line, and the second section is connected to the control end of the output circuit; the second lead includes a connected third section and a fourth section, the third section is connected to the second signal line, and the fourth section is connected to the control end of the control circuit; the orthographic projection of the first section on the substrate and the orthographic projection of the third section on the substrate overlap with the orthographic projection of the third signal line on the substrate respectively, the first section and the third section are located in the second conductive layer, and the second section, the fourth section, the control end of the output circuit and the control end of the control circuit are all located in the first conductive layer.

[0023] In one embodiment, the driving circuit layer includes a first conductive layer and a second conductive layer, the first conductive layer includes a fan-out line and an output pin; the output signal line includes a first signal segment, a second signal segment, a third signal segment and a fourth signal segment connected in sequence; an extension direction of the first signal segment and an extension direction of the third signal segment respectively intersect with an extension direction of the data signal line, and an extension direction of the second signal segment and an extension direction of the fourth signal segment are respectively parallel to an extension direction of the data signal line; the first signal segment is connected to an output end of the output circuit; an orthographic projection of at least a portion of the second signal segment on the substrate overlaps with an orthographic projection of the fan-out line on the substrate, and the at least portion of the segment is located in the second conductive layer; the fourth signal segment is located in the second conductive layer, and an orthographic projection of the fourth signal segment on the substrate overlaps with an orthographic projection of the output pin on the substrate.

[0024] In one embodiment, the width of the output signal line ranges from 6 μm to 15 μm.

[0025] In one embodiment, the distance between the output signal line and an adjacent signal line located in the same conductive layer is greater than or equal to 4 μm; and / or,

[0026] A distance between an orthographic projection of the output signal line on the substrate and an orthographic projection of an adjacent signal line located in a different conductive layer on the substrate is greater than or equal to 2 μm.

[0027] According to the second aspect of the embodiment of the present application, a display panel is provided, which includes a driving chip, a control chip, a color filter substrate, a liquid crystal layer and the above-mentioned array substrate; the color filter substrate and the array substrate are arranged opposite to each other, and the liquid crystal layer is located between the color filter substrate and the array substrate; the driving chip is respectively connected to the input end of the control circuit, the first signal line and the second signal line; the control chip is electrically connected to the output end of the output signal line; the display panel includes a display area, and the boundary of the central area coincides with the boundary of the display area.

[0028] In one embodiment, the display panel further includes a circuit board, which is provided with an amplifying circuit; the output end of the output signal line is connected to the amplifying circuit; the control chip is electrically connected to the output end of the amplifying circuit to obtain the signal output by the amplifying circuit.

[0029] According to a third aspect of an embodiment of the present application, a projection device is provided, comprising a light source and the above-mentioned display panel.

[0030] According to a fourth aspect of an embodiment of the present application, a control method for a display panel is provided, which is applied to the control chip of the display panel described above; the control method comprises:

[0031] Acquire a leakage current signal, wherein the leakage current signal indicates the magnitude of the leakage current output by the output signal line;

[0032] Acquire a control signal matching the leakage current signal, wherein the control signal includes at least one of an off voltage of a switch transistor of a pixel circuit and a gamma voltage signal;

[0033] The display panel is controlled according to the control signal matching the leakage current signal.

[0034] In one embodiment, the acquiring a control signal matching the leakage current signal includes:

[0035] Determining whether a current control signal of the display panel matches the leakage current signal;

[0036] If the current control signals all match the leakage current signal, the current control signals are obtained; if the current control signals do not match the leakage current signal, the control signals that match the leakage current signal are obtained based on the correspondence between the control signals that do not match the leakage current signal and the leakage current signal.

[0037] In one embodiment, the output circuit includes at least one second transistor, and the control circuit includes at least one third transistor;

[0038] The second transistor and the third transistor are both N-type transistors, and the obtaining of the leakage current signal includes: during a black screen period between two frames, the first signal line provides a high-level signal to the second transistor, and the second signal line provides a low-level signal to the third transistor, so that the second transistor is turned on and the third transistor is turned off, and the leakage current of the first transistor is output through the second transistor and the output signal line; receiving the leakage current signal; or,

[0039] The second transistor and the third transistor are both P-type transistors, and the method of obtaining the leakage current signal includes: during a black screen period between two frames, the first signal line provides a low-level signal to the second transistor, and the second signal line provides a high-level signal to the third transistor, so that the second transistor is turned on and the third transistor is turned off, and the leakage current of the first transistor is output through the second transistor and the output signal line; receiving the leakage current signal.

[0040] The array substrate, display panel, control method thereof, and projection device provided by the embodiments of the present application are configured such that an output circuit and a control circuit are arranged in a peripheral area of ​​the array substrate, and the signals provided by the first signal line and the second signal line can make the control circuit closed when the output circuit is turned on. Then, the leakage current of the first transistor can be output to the output signal line through the output circuit. At this time, the input signal cannot be input to the first transistor through the control circuit, and will not affect the leakage current of the first transistor, thereby ensuring the accuracy of the leakage current output by the output signal line. The control chip of the display panel where the array substrate is located can obtain a leakage current signal indicating the size of the leakage current output by the output signal line, and obtain the turn-off voltage and gamma voltage of the switching transistor of the pixel circuit in the display panel according to the leakage current signal, so as to improve the image quality of the displayed image. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 is a structural schematic diagram of an array substrate provided by an exemplary embodiment of the present application;

[0042] Figure 2 yes Figure 1 A partial enlarged view of area A of the array substrate shown;

[0043] Figure 3 yes Figure 1 A local enlarged view of area D of the array substrate shown;

[0044] Figure 4 yes Figure 1 A local enlarged view of area B of the array substrate shown;

[0045] Figure 5 yes Figure 1 A local enlarged view of area C of the array substrate shown;

[0046] Figure 6 is a flow chart of a method for controlling a display panel provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0047] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0048] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0049] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0050] The inventors have found that when the projector is in use, the light source releases a large amount of heat while emitting light, and the heat is transferred to the display panel, causing the temperature of the display panel to change.

[0051] When the temperature of the display panel of the projector changes, the leakage current of the switching transistor of the pixel circuit in the display panel will be affected and change. The change of the leakage current of the switching transistor will cause the voltage of the pixel electrode to change, thereby affecting the image quality of some specific display images, such as causing the grayscale of the lower grayscale area in the image to shift. Specifically, when the central area of ​​the display image is white and the edge area surrounding the central area is gray, the change of the voltage of the pixel electrode will cause the brightness of some areas in the edge area to be brighter and the brightness of some areas to be darker. When users watch the projected image of the projector, the image quality problem is more obvious.

[0052] When the display panel of the projector is working, the optimal gamma voltage value is different when the temperature of the display panel is different. If the temperature of the display panel changes, the optimal gamma value of the display panel changes, and there is a deviation between the current gamma voltage of the display panel and the optimal gamma voltage, which will cause the problem of residual image on the display screen. When the user watches the projected image of the projector, the residual image is more obvious.

[0053] The embodiments of the present application provide an array substrate, a display panel and a control method thereof, and a projection device, which can solve at least one of the above problems. The array substrate, the display panel and a control method thereof, and the projection device in the embodiments of the present application are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the features in the following embodiments can complement or combine with each other.

[0054] The present application embodiment provides an array substrate. Figure 1 As shown, the array substrate includes a central area 101 and a peripheral area 102 located at least on one side of the central area 101. The array substrate includes a substrate and a driving circuit layer located on the substrate. The boundary of the central area 101 of the array substrate may coincide with the boundary of the display area of ​​the display panel where the array substrate is located.

[0055] The driving circuit layer includes a first transistor 10, an output circuit 20, a control circuit 30, a data signal line 41, a first signal line 42, a second signal line 43 and an output signal line 44. The first transistor 10 is located in the central area 101. The output circuit 20 and the control circuit 30 are located in the peripheral area 102. The first transistor 10 includes a first electrode 11, a second electrode 12 and a gate 13. The output circuit 20 includes an input terminal 21, an output terminal 22 and a control terminal 23. The control circuit 30 includes an input terminal 31, an output terminal 32 and a control terminal 33.

[0056] The first electrode 11 of the first transistor 10 and the input terminal 21 of the output circuit 20 are respectively connected to the data signal line 41. The control terminal 23 of the output circuit 20 is electrically connected to the first signal line 42, and the output terminal 22 of the output circuit 20 is connected to the output signal line 44. The output terminal 32 of the control circuit 30 is connected to the signal input terminal of the data signal line 41, the input terminal 31 of the control circuit 30 receives an input signal, and the control terminal 33 of the control circuit 30 is electrically connected to the second signal line 43.

[0057] The first signal line 42 and the second signal line 43 are configured as follows: when the output circuit 20 is turned on, the control circuit 30 is turned off, and the leakage current of the first transistor 10 is output through the output signal line 44; when the output circuit 20 is turned off, the control circuit 30 is turned on, and the data signal line 41 receives the input signal and transmits it to the first transistor 10.

[0058] The array substrate provided in the embodiment of the present application is provided with an output circuit and a control circuit in the peripheral area of ​​the array substrate, and the signals provided by the first signal line and the second signal line can make the control circuit closed when the output circuit is turned on, so that the leakage current of the first transistor can be output to the output signal line through the output circuit, and the input signal cannot be input to the first transistor through the control circuit, and will not affect the leakage current of the first transistor, so that the accuracy of the leakage current output by the output signal line can be guaranteed; the control chip of the display panel where the array substrate is located can obtain a leakage current signal indicating the leakage current output by the output signal line, and obtain the turn-off voltage and gamma voltage of the switch transistor of the pixel circuit in the display panel according to the leakage current signal, so as to improve the image quality of the display screen, avoid the problem of gray scale offset in the area with lower gray scale in a specific screen and the problem of afterimage in the display screen, and improve the user experience; the signals provided by the first signal line and the second signal line in the present application can make the output circuit closed when the control circuit is turned on, and the control circuit can transmit the input signal to the first transistor through the data signal line, and the input signal cannot be output through the output signal line, and the output circuit will not affect the transmission of the input signal to the first transistor, so as to ensure the normal operation of the first transistor.

[0059] Specifically, the principle that the control chip of the display panel obtains the off voltage of the switch transistor of the pixel circuit in the display panel according to the obtained leakage current signal and improves the image quality of the display panel is as follows:

[0060] The leakage current of the first transistor can reflect the leakage current of the switching transistor of the pixel circuit in the display panel. For example, when the first transistor is a switching transistor, the leakage current of the first transistor is also the leakage current of the switching transistor; when the first transistor is not a switching transistor and the channel size of the first transistor is the same as the channel size of the switching transistor, the leakage current of the first transistor is equal to the leakage current of the switching transistor; when the first transistor is not a switching transistor and the channel size of the first transistor is different from the channel size of the switching transistor, the ratio of the leakage current of the first transistor to the leakage current of the switching transistor and the ratio of the channel size of the first transistor to the channel size of the switching transistor are constant values. If there is a corresponding relationship between the leakage current of the switching transistor and VGL, then there is a corresponding relationship between the leakage current of the first transistor and VGL, so the control chip can determine the matching VGL according to the leakage current of the first transistor. By adjusting VGL, the leakage current of the switching transistor of the pixel circuit can be changed, thereby improving the grayscale offset problem of the lower grayscale area in a specific picture caused by the change in the leakage current of the switching transistor.

[0061] The principle of the control chip of the display panel obtaining the gamma voltage signal according to the obtained leakage current signal and improving the image quality of the display panel is as follows:

[0062] The leakage current of the first transistor corresponds to the temperature of the display panel, and the temperature of the display panel corresponds to the optimal gamma voltage. Therefore, the optimal gamma voltage of the display panel corresponds to the leakage current of the first transistor, so the control chip of the display panel can determine the gamma voltage signal that matches the current temperature of the display panel according to the acquired leakage current signal. By adjusting the gamma voltage signal, the problem of afterimage caused by mismatch of the gamma voltage signal can be improved.

[0063] In one embodiment, Figure 1 As shown, the peripheral area 102 of the array substrate surrounds the central area 101. The peripheral area 102 includes a first sub-peripheral area 1021, a second sub-peripheral area 1022, a third sub-peripheral area 1023 and a fourth sub-peripheral area 1024. The first sub-peripheral area 1021 is opposite to the second sub-peripheral area 1022, and the third sub-peripheral area 1023 is opposite to the fourth sub-peripheral area 1024. The array substrate may further include a gate driving circuit 50, and the gate driving circuit 50 is located in the third sub-peripheral area 1023. The fourth sub-peripheral area 1024 may also have a gate driving circuit.

[0064] In one embodiment, Figure 1 As shown, the array substrate includes a plurality of first transistors 10 located in a central area 101, the plurality of first transistors 10 are arranged in a plurality of columns, each column includes a plurality of first transistors 10, a column of first transistors 10 is connected to the same data signal line 41, and each data signal line 41 is connected to an output circuit 20. In this arrangement, when the output circuit 20 is turned on, the leakage current of the first transistors 10 in each column is transmitted to the output signal line 44, so that the leakage current output by the output signal line 44 is large, and the leakage current output by the output signal line 44 is small, which can avoid the leakage current from being greatly deviated when being subjected to signal crosstalk during the transmission process, thereby causing the gamma voltage and VGL determined according to the leakage current to match it to have large errors, which is more helpful to improve the display screen.

[0065] In one embodiment, the driving circuit layer includes a plurality of pixel driving circuits located in the central area 101, at least one of the pixel driving circuits includes the first transistor 10, and the first transistor 10 is a switching transistor of the pixel circuit. The pixel driving circuit may include only the first transistor. In this way, by using the transistor in the pixel driving circuit as the first transistor, there is no need to additionally set the first transistor in the central area 101, which helps to simplify the structure of the array substrate. In other embodiments, the display panel where the array substrate is located may include a fingerprint driving circuit, and at least one fingerprint driving circuit includes a first transistor. Alternatively, the display panel where the array substrate is located may include a touch driving circuit, and at least one touch driving circuit includes a first transistor.

[0066] In one embodiment, each of the pixel driving circuits includes a first transistor 10; the first transistors in the display area are arranged in multiple columns, and the first transistors 10 in the same column are connected to the same data signal line 41. The driving circuit layer includes multiple output circuits 20 and multiple control circuits 30. The data signal line 41 extends along the column direction, and one data signal line 41 is connected to one output circuit 20; one data signal line 41 is connected to one control circuit 30. In this way, the leakage current output by the output signal line 44 can be made larger while simplifying the structure of the array substrate, reducing the deviation of the leakage current caused by signal crosstalk during transmission, thereby reducing the error of the gamma voltage and VGL matched with it determined by the control chip according to the leakage current.

[0067] In one embodiment, one of the first electrode 11 and the second electrode 12 of the first transistor 10 is a source electrode, and the other is a drain electrode. When the first transistor 10 is an N-type transistor, the first electrode 11 is a source electrode, and the second electrode 12 is a drain electrode. When the first transistor 10 is a P-type transistor, the first electrode 11 is a drain electrode, and the second electrode 12 is a source electrode.

[0068] In one embodiment, Figure 1 and Figure 2 As shown, the output circuit 20 includes at least one second transistor 201, and the control circuit 30 includes at least one third transistor 301. In this way, the output circuit 20 and the control circuit 30 can be simple in structure and easy to implement.

[0069] In one embodiment, the output circuit 20 includes two or more second transistors 201, and the second transistors 201 of the same output circuit are connected in series. The second transistors 201 connected in series refer to that, among two adjacent second transistors 201, the second electrode of one second transistor 201 is connected to the first electrode of another second transistor 201. In this embodiment, in the same output circuit 20, there is a second transistor 201 whose first electrode is directly connected to the data signal line 41, and there is a second transistor 201 whose second electrode is connected to the output signal line 44. Among the second transistors 201 of the output circuit 20, the first electrode directly connected to the data signal line 41 is the input terminal of the output circuit 20, and the second electrode directly connected to the output signal line 44 is the output terminal of the output circuit 20, and the gate of each second transistor 201 is the control terminal of the output circuit 20. Figure 2 In the illustrated embodiment, the output circuit 20 includes two second transistors 201. In other embodiments, the output circuit 20 may include three or more second transistors 201.

[0070] In one embodiment, the output circuit 20 includes two or more second transistors 201, and the second transistors 201 of all the output circuits 20 can be arranged in multiple rows, and the gates of the second transistors 201 in the same row are connected to the same first signal line 42. Figure 2 As shown, the output circuit 20 includes two second transistors 201 , and the second transistors 201 of all the output circuits 20 are arranged in two rows, and the two second transistors 201 of the same output circuit 20 are located in different rows.

[0071] In one embodiment, one of the first electrode 11 and the second electrode 12 of the first transistor 10 is a source electrode, and the other is a drain electrode. When the first transistor 10 is an N-type transistor, the first electrode 11 is a source electrode, and the second electrode 12 is a drain electrode. When the first transistor 10 is a P-type transistor, the first electrode 11 is a drain electrode, and the second electrode 12 is a source electrode.

[0072] In one embodiment, the control circuit 30 includes two or more third transistors 301, and the third transistors 301 of the same control circuit 30 are connected in series. The third transistors 301 connected in series refer to that, among two adjacent third transistors 301, the second electrode of one third transistor 301 is connected to the first electrode of another third transistor 301. In this embodiment, there is a third transistor 301 in the control circuit 30 with a first electrode directly connected to the data signal line 41, and there is a third transistor 301 with a second electrode connected to the output signal line 44. Among the third transistors 301 of the control circuit 30, the second electrode directly connected to the data signal line 41 is the output terminal of the control circuit 30, and the first electrode not directly connected to the data signal line 41 and not connected to other third transistors 301 is the input terminal of the control circuit 30; the gate of each third transistor 301 is the control terminal of the control circuit 30. Figure 2 In the illustrated embodiment, the control circuit 30 includes only one third transistor 301. In other embodiments, the control circuit 30 may include two or more third transistors 301.

[0073] In one embodiment, the input end of the control circuit 30 is connected to the driver chip. When the control circuit 30 is turned on, the driver chip provides an input signal to the control circuit 30, and then the control circuit 30 transmits the input signal to the data signal line 41. In some embodiments, the input signal provided by the driver chip to the control circuit is a data signal.

[0074] In one embodiment, the second transistor 201 and the third transistor 301 are both N-type transistors, and the first signal line 42 and the second signal line 43 are specifically configured as follows: during a frame display period, the first signal line 42 provides a low-level signal to the second transistor 201, and the second signal line 43 provides a high-level signal to the third transistor 301, so that the second transistor 201 is turned off and the third transistor 301 is turned on; during a black screen period between two frames, the first signal line 42 provides a high-level signal to the second transistor 201, and the second signal line 43 provides a low-level signal to the third transistor, so that the second transistor is turned on and the third transistor is turned off. In this way, the leakage current of the first transistor is detected during the black screen period, and the data signal line provides a data signal to the first transistor during the screen display period, which can ensure that the leakage current detection of the display panel where the array substrate is located and the screen display do not interfere with each other.

[0075] In another embodiment, the second transistor 201 and the third transistor 301 are both P-type transistors, and the first signal line 42 and the second signal line 43 are specifically configured as follows: during a frame display period, the first signal line 42 provides a high-level signal to the second transistor 201, and the second signal line provides a low-level signal to the third transistor 301, so that the second transistor 201 is turned off and the third transistor 301 is turned on; during a black frame period between two frames, the first signal line 42 provides a low-level signal to the second transistor 201, and the second signal line 43 provides a high-level signal to the third transistor 301, so that the second transistor 201 is turned on and the third transistor 301 is turned off. In this way, the leakage current of the first transistor is detected during the black frame period, and the data signal line can provide a data signal to the first transistor during the picture display period, which can ensure that the leakage current detection of the display panel where the array substrate is located and the picture display do not interfere with each other.

[0076] In one embodiment, the material of the output signal line is metal. Compared with the use of transparent metal oxide conductive materials such as indium zinc oxide, the use of metal materials can reduce the resistance of the output signal line and reduce the loss during the transmission of leakage current. In some embodiments, the material of the output signal line may include aluminum and molybdenum. When the line width and line length of the output signal line are the same, when the material of the output signal line includes aluminum and molybdenum, the resistance of the output signal line can be reduced by 64.88Ω compared with the output signal line material being indium zinc oxide.

[0077] In one embodiment, the driving circuit layer includes a first conductive layer and a second conductive layer, and the second conductive layer is located on a side of the first conductive layer away from the substrate. The gate of the first transistor 10, the gate of the second transistor 201, and the gate of the third transistor 301 can all be located in the first conductive layer. The first electrode and the second electrode of the first transistor 10, the second transistor 201, and the third transistor 301 can all be located in the second conductive layer.

[0078] In one embodiment, the array substrate further includes an insulating layer located between the first conductive layer and the second conductive layer. The structure located on the first conductive layer and the structure located on the second conductive layer can be connected via a through hole opened in the insulating layer.

[0079] In one embodiment, the data signal line 41 is located in the second conductive layer, so that the first electrode of the first transistor 10, the first electrode of the second transistor 201, and the second electrode of the third transistor 301 are located in the same layer as the data signal line 41, and the first electrode of the first transistor 10, the first electrode of the second transistor 201, and the second electrode of the third transistor 301 are connected to the data signal line 41.

[0080] In one embodiment, Figure 1 and Figure 2 As shown, the array substrate further includes a plurality of fan-out lines 60 connected to the second sub-peripheral area 1022, and the first signal line 42, the second signal line 43, and the input end of the control circuit 30 can be connected to the fan-out line 60. The fan-out line 60 can be located in the first conductive layer. Each fan-out line 60 can be electrically connected to a driver chip, so that the driver chip can provide a signal to the signal line connected to the fan-out line.

[0081] In one embodiment, Figure 3 As shown, the array substrate further includes an output pin 71 located in the second sub-peripheral area 1022, and the output signal line 44 can be connected to the output pin 71. The output pin 71 is used to connect to the circuit board.

[0082] In one embodiment, the output pin 71 may be located in the first conductive layer.

[0083] In one embodiment, Figure 1 and Figure 2 As shown, the first signal line 42 and the second signal line 43 are also configured to provide signals to the gate drive circuit 50. In this configuration, the output circuit 20 and the gate drive circuit 50 share the first signal line 42, and the control circuit 30 and the gate drive circuit 50 share the second signal line 43, which helps to reduce the number of signal lines in the array substrate and simplify the structure of the array substrate.

[0084] In one embodiment, the first signal line 42 is configured to provide an initial input signal to the gate driving circuit 50 during a frame display period, and the second signal line 43 is configured to provide a reset signal to the gate driving circuit 50 during a black frame period between two frames.

[0085] In one embodiment, Figure 1 and Figure 2 As shown, the extension direction of the first signal line 42 and the extension direction of the second signal line 43 are respectively parallel to the extension direction of the data signal line 41, and all three can extend along the column direction. The extension direction of the signal line refers to the extension direction of the signal line as a whole. The driving circuit layer also includes a first lead 45 and a second lead 46, and the extension direction of the first lead 45 and the extension direction of the second lead 46 intersect with the extension direction of the data signal line 41. For example, the extension direction of the first lead 45 and the extension direction of the second lead 46 can be perpendicular to the extension direction of the data signal line 41. One end of the first lead 45 is connected to the first signal line 42, and the first lead 45 is connected to the control end of the output circuit 20; one end of the second lead 46 is connected to the second signal line 43, and the second lead 46 is connected to the control end of the control circuit 30. The arrangement of the first lead 45 facilitates the connection of the control end of the output circuit 20 with the first signal line 42, and the arrangement of the second lead 46 facilitates the connection of the control end of the control circuit 30 with the second signal line 43.

[0086] In one embodiment, Figure 1 and Figure 2 As shown, the driving circuit layer further includes at least one third signal line 47, the third signal line 47 is located between the data signal line 41 and the first signal line 42, and between the data signal line 41 and the second signal line 43; the third signal line 47 is located in the first conductive layer. The third signal line 47 can provide a signal to the gate driving circuit, and the third signal line 47 can be a clock signal line.

[0087] In one embodiment, Figure 2As shown, the first lead 45 includes a first section 451 and a second section 452 connected to each other, the first section 451 is connected to the first signal line 42, and the second section 452 is connected to the control end of the output circuit 20; the orthographic projection of the first section 451 on the substrate overlaps with the orthographic projection of the third signal line 47 on the substrate, the first section 451 is located in the second conductive layer, and the second section 452 and the control end 23 of the output circuit 20 are located in the first conductive layer. By arranging the first section 451 and the third signal line 47 to be located in different conductive layers, the first section 451 and the first signal line 42 can be connected while avoiding the first section 451 and the third signal line 47 from crossing and causing a short circuit; by arranging the second section 452 and the control end 23 of the output circuit 20 to be located in the same conductive layer, it is convenient to connect the control end 23 of the output circuit 20 with the second section 452.

[0088] In one embodiment, Figure 2 As shown, the second lead 46 includes a third section 461 and a fourth section 462 connected to each other, the third section 461 is connected to the second signal line 43, and the fourth section 462 is connected to the control end of the control circuit; the orthographic projection of the third section 461 on the substrate overlaps with the orthographic projection of the third signal line 47 on the substrate, the third section 461 is located in the second conductive layer, and the fourth section 462 is located in the first conductive layer. By arranging the third section 461 of the second lead 46 and the third signal line 47 to be located in different conductive layers, the third section 461 can be connected to the second signal line 43 while avoiding the third section 461 and the third signal line 47 from crossing and causing a short circuit; by arranging the fourth section 462 and the control end 33 of the control circuit 30 to be located in the same conductive layer, it is convenient to connect the control end 33 of the control circuit 30 with the fourth section 462.

[0089] In one embodiment, Figure 1 , Figures 3 to 5As shown, the output signal line 44 includes a first signal segment 441, a second signal segment 442, a third signal segment 443 and a fourth signal segment 444 connected in sequence; the extension direction of the first signal segment 441 and the extension direction of the third signal segment 443 respectively intersect with the extension direction of the data signal line 41, and the extension direction of the second signal segment 442 and the extension direction of the fourth signal segment 444 are respectively parallel to the extension direction of the data signal line 41; the first signal segment 441 is connected to the output end 22 of the output circuit 20, and the first signal segment 441 is located in the first conductive layer; the orthographic projection of at least a portion of the second signal segment 442 on the substrate overlaps with the orthographic projection of the fan-out line 60 on the substrate, and the at least portion of the segment is located in the second conductive layer; the fourth signal segment 444 is located in the second conductive layer, and the orthographic projection of the fourth signal segment 444 on the substrate overlaps with the orthographic projection of the output pin 71 on the substrate. The second signal segment 442 is located in the fourth sub-peripheral area 1024 , and the output pin 71 , the third signal segment 443 , and the fourth signal segment 444 are located in the second sub-peripheral area 1022 .

[0090] By setting the output signal line 44 to include multiple signal segments connected in sequence and the extension directions of the connected signal lines are different, it is convenient to lead the output signal line 44 from the fourth sub-peripheral area of ​​the array substrate to the second sub-peripheral area to connect with the output pin 71; by setting the first signal segment 441 to be located in the first conductive layer, that is, the first signal segment 441 and the output end 22 of the output circuit 20 are located in the same layer, it is convenient to electrically connect the first signal segment 441 with the output end 22 of the output circuit 20; by setting at least a part of the second signal segment 442 and the fan-out line 60 to be located in different layers, the second signal segment 442 and the fan-out line 60 can be avoided from crossing; by setting the fourth signal segment 444 to be located in the second conductive layer, and its orthographic projection on the substrate overlaps with the orthographic projection of the output pin 71 located in the first conductive layer on the substrate, it is convenient to connect the fourth signal segment 444 with the output pin 71.

[0091] In one embodiment, Figure 4 And such as Figure 5 As shown, the second signal segment 442 includes a first sub-segment 445 and a second sub-segment 446. The first sub-segment 445 is connected to the first signal segment 441, and the second sub-segment 446 is connected to the third signal segment 443. The first sub-segment 445 is located in the first conductive layer, and the second sub-segment 446 is located in the second conductive layer.

[0092] In some embodiments, the orthographic projection of the fourth signal segment 444 on the substrate covers the orthographic projection of the output pin 71 on the substrate, which makes it easier to connect the two.

[0093] In some embodiments, the third signal segment 443 is located in the second conductive layer, so as to avoid the third signal segment 443 from crossing the fan-out line 60 .

[0094] In one embodiment, the width of the output signal line 44 ranges from 6 μm to 15 μm. This arrangement can avoid the output signal line 44 being too small in width, resulting in a large resistance of the output signal line, and can also avoid the output signal line 44 being too large in width, resulting in a small distance between the output signal line 44 and adjacent signals, resulting in large signal crosstalk between the output signal line 44 and adjacent signal lines. In some embodiments, the width of the output signal line 44 can be 6 μm, 8 μm, 10 μm, 12 μm, 15 μm, etc.

[0095] In one embodiment, Figure 4 As shown, the array substrate further includes a common voltage signal line 48 located in the fourth sub-peripheral area 1024 , and the common voltage signal line 48 provides a voltage signal to a common electrode of the display panel where the array substrate is located.

[0096] In one embodiment, Figure 4 and Figure 5 As shown, the array substrate also includes a test signal line 49 located in the fourth sub-peripheral area 1024, and the test signal line 49 is connected to the gate drive circuit. The output signal of the gate drive circuit can be connected to the test electrode through the test signal line 49 to test the gate drive circuit.

[0097] In one embodiment, the distance between the output signal line 44 and the adjacent signal line located in the same conductive layer is greater than or equal to 4 μm. This arrangement can ensure that the signal crosstalk between the output signal line 44 and the adjacent signal line located in the same layer is small.

[0098] In some embodiments, the first signal segment 441, the second segment 452, the fourth segment 462, the first sub-segment 445, the test signal line 49 and the common voltage signal line 48 of the output signal line 44 are all located in the first conductive layer, and the distance between the first signal segment 441 and the adjacent second segment 452 is greater than or equal to 4 μm; the distance between the first signal segment 441 and the adjacent fourth segment 462 is greater than or equal to 4 μm; the first sub-segment 445 is connected to the common voltage signal line 48 and the distance between the two is greater than or equal to 4 μm; the first sub-segment 445 is connected to the test signal line 49 and the distance between the two is greater than or equal to 4 μm.

[0099] In one embodiment, the distance between the orthographic projection of the output signal line 44 on the substrate and the orthographic projection of the adjacent signal line located in a different conductive layer on the substrate is greater than or equal to 2μm. This arrangement can ensure that the signal crosstalk between the output signal line 44 and the adjacent signal lines located in different layers is small. In some embodiments, the second sub-section 446 is located in the second conductive layer, and the test signal line 49 and the common voltage signal line 48 are both located in the first conductive layer, then the distance between the orthographic projection of the second sub-section 446 on the substrate and the orthographic projection of the test signal line 49 on the substrate is greater than or equal to 2μm, and the distance between the orthographic projection of the second sub-section 446 on the substrate and the orthographic projection of the common voltage signal line 48 on the substrate is greater than or equal to 2μm.

[0100] The embodiment of the present application also provides a display panel, the display panel includes a driving chip, a control chip, a color filter substrate, a liquid crystal layer and the array substrate described in any of the above embodiments. The color filter substrate is arranged opposite to the array substrate, and the liquid crystal layer is located between the color filter substrate and the array substrate; the driving chip is respectively connected to the input end of the control circuit, the first signal line and the second signal line; the control chip is electrically connected to the output end of the output signal line; the display panel includes a display area, and the boundary of the central area coincides with the boundary of the display area.

[0101] In one embodiment, the color filter substrate includes a light shielding layer, and the orthographic projection of the light shielding layer on the substrate covers the orthographic projection of the channel region of the first transistor on the substrate. This arrangement can prevent light from entering the channel region of the first transistor and causing the leakage current of the first transistor to change, thereby causing the leakage current output by the output signal line to be unable to accurately indicate the current temperature of the display panel.

[0102] In one embodiment, the display panel further comprises a circuit board, the circuit board is bound to the output pin, the control chip can be connected to the circuit board, and after the leakage current output by the output signal line is transmitted to the circuit board, the control chip obtains the leakage current signal from the circuit board. In some embodiments, the circuit board is a flexible circuit board.

[0103] In one embodiment, the circuit board is provided with an amplifier circuit, and the output end of the output signal line is connected to the amplifier circuit; the control chip is electrically connected to the output end of the amplifier circuit to obtain the signal output by the amplifier circuit.

[0104] In one embodiment, the circuit board is further provided with an analog-to-digital conversion circuit, the analog-to-digital conversion circuit is connected to the output end of the amplifier circuit, and the control chip is connected to the output end of the analog-to-digital conversion circuit. The analog-to-digital converter converts the analog signal output by the amplifier circuit into a digital signal and provides it to the control chip.

[0105] The embodiment of the present application further provides a projection device, the projection device comprising a light source and a display panel as described in any one of the above embodiments. The light source is opposite to the display panel, and the light emitted by the light source is incident on the display panel.

[0106] The present application also provides a method for controlling a display panel, and the method is applied to the control chip of the display panel. Figure 6 As shown, the control method includes the following steps 110 to 130.

[0107] In step 110, a leakage current signal is acquired, where the leakage current signal indicates the magnitude of the leakage current output by the output signal line.

[0108] In one embodiment, the acquired leakage current signal may be a signal of the leakage current output by the output signal line after being amplified and analog-to-digital converted.

[0109] In one embodiment, the output circuit includes at least one second transistor, and the control circuit includes at least one third transistor; when the second transistor and the third transistor are both N-type transistors, before obtaining the leakage current signal, the control method of the display panel further includes:

[0110] During the black screen period between two frames, the first signal line provides a high-level signal to the second transistor, and the second signal line provides a low-level signal to the third transistor, so that the second transistor is turned on and the third transistor is turned off, and the leakage current of the first transistor is output through the second transistor and the output signal line.

[0111] In one embodiment, the output circuit includes at least one second transistor, and the control circuit includes at least one third transistor; the second transistor and the third transistor are both P-type transistors, and before obtaining the leakage current signal, the control method of the display panel also includes: during a black screen period between two frames, the first signal line provides a low-level signal to the second transistor, and the second signal line provides a high-level signal to the third transistor, so that the second transistor is turned on and the third transistor is turned off, and the leakage current of the first transistor is output through the second transistor and the output signal line.

[0112] In step 120, a control signal matching the leakage current signal is acquired, wherein the control signal includes at least one of a turn-off voltage of a switch transistor of a pixel circuit and a gamma voltage signal.

[0113] In one embodiment, the control chip may store a corresponding relationship between the control signal and the leakage current signal. Specifically, when the control signal includes the off-voltage of the switch transistor of the pixel circuit, the control chip stores the corresponding relationship between the off-voltage of the switch transistor of the pixel circuit and the leakage current signal; when the control signal includes the gamma voltage signal, the control chip stores the corresponding relationship between the gamma voltage signal and the leakage current signal.

[0114] In one embodiment, the step of obtaining a control signal matching the leakage current signal includes the following process:

[0115] Determining whether a current control signal of the display panel matches the leakage current signal;

[0116] If the current control signals all match the leakage current signal, the current control signals are obtained; if the current control signals do not match the leakage current signal, the control signals that match the leakage current signal are obtained based on the correspondence between the control signals that do not match the leakage current signal and the leakage current signal.

[0117] In step 130, the display panel is controlled according to the control signal matching the leakage current signal.

[0118] The control method of the display panel provided in the embodiment of the present application first obtains a leakage current signal indicating the size of the leakage current output by the output signal line, and then obtains a control signal matching the leakage current signal. Since the control signal includes at least one of the turn-off voltage of the switching transistor of the pixel circuit and the gamma voltage signal, when the display panel is controlled to display according to the control signal matching the leakage current signal, the image quality of the displayed picture can be improved. Specifically, when the control signal includes the turn-off voltage of the switching transistor of the pixel circuit, the problem of grayscale offset in a lower grayscale area in a specific picture can be improved. When the control signal includes the gamma voltage signal, the problem of afterimage in the displayed picture can be improved.

[0119] The embodiments of the array substrate, the display panel, and the display panel control method provided in the embodiments of the present application belong to the same inventive concept, and the descriptions of relevant details and beneficial effects can be referred to each other and will not be repeated here.

[0120] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0121] Those skilled in the art will readily appreciate other embodiments of the present application after considering the description and practicing the contents disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common knowledge or customary techniques in the art that are not disclosed in the present application. The description and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0122] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. An array substrate, characterized in that: The array substrate comprises a central area and a peripheral area located at at least one side of the central area; the array substrate comprises a substrate and a driving circuit layer located on the substrate; The driving circuit layer includes a first transistor, an output circuit, a control circuit, a data signal line, a first signal line, a second signal line and an output signal line; the first transistor is located in the central area; the output circuit and the control circuit are located in the peripheral area; the first transistor includes a first electrode, a second electrode and a gate; The first electrode of the first transistor and the input end of the output circuit are respectively connected to the data signal line; the control end of the output circuit is electrically connected to the first signal line, and the output end of the output circuit is connected to the output signal line; the output end of the control circuit is connected to the signal input end of the data signal line, the input end of the control circuit receives an input signal, and the control end of the control circuit is electrically connected to the second signal line; The first signal line and the second signal line are configured as follows: when the output circuit is turned on, the control circuit is turned off, and the leakage current of the first transistor is output through the output signal line; when the output circuit is turned off, the control circuit is turned on, and the data signal line receives an input signal and transmits it to the first transistor.

2. The array substrate according to claim 1, characterized in that: The driving circuit layer includes a plurality of pixel driving circuits located in the central area, and at least one of the pixel driving circuits includes the first transistor.

3. The array substrate according to claim 1, characterized in that: The driving circuit layer includes a plurality of pixel driving circuits located in the central area, each of the pixel driving circuits includes one first transistor; the first transistors in the central area are arranged in a plurality of columns, and the first transistors in the same column are connected to the same data signal line; The driving circuit layer includes a plurality of output circuits and a plurality of control circuits. One data signal line is connected to one output circuit; and one data signal line is connected to one control circuit.

4. The array substrate according to claim 1, characterized in that: The output circuit includes at least one second transistor, and the control circuit includes at least one third transistor.

5. The array substrate according to claim 4, characterized in that: The output circuit comprises two or more second transistors, and the second transistors of the same output circuit are connected in series; and / or, The control circuit includes two or more third transistors, and the third transistors of the same control circuit are connected in series.

6. The array substrate according to claim 4, characterized in that: The second transistor and the third transistor are both N-type transistors, and the first signal line and the second signal line are specifically configured as follows: during a frame display period, the first signal line provides a low-level signal to the second transistor, and the second signal line provides a high-level signal to the third transistor, so that the second transistor is turned off and the third transistor is turned on; during a black frame period between two frames, the first signal line provides a high-level signal to the second transistor, and the second signal line provides a low-level signal to the third transistor, so that the second transistor is turned on and the third transistor is turned off; or, The second transistor and the third transistor are both P-type transistors, and the first signal line and the second signal line are specifically configured as follows: during the display of a frame of picture, the first signal line provides a high-level signal to the second transistor, and the second signal line provides a low-level signal to the third transistor, so that the second transistor is turned off and the third transistor is turned on; during the black picture period between two frames of pictures, the first signal line provides a low-level signal to the second transistor, and the second signal line provides a high-level signal to the third transistor, so that the second transistor is turned on and the third transistor is turned off.

7. The array substrate according to claim 1, characterized in that: The first signal line and the second signal line are also configured to provide signals to a gate driving circuit.

8. The array substrate according to claim 7, characterized in that: The first signal line is configured to provide an initial input signal to the gate driving circuit during a frame display period, and the second signal line is configured to provide a reset signal to the gate driving circuit during a black frame period between two frames.

9. The array substrate according to claim 1, characterized in that: The extension direction of the first signal line and the extension direction of the second signal line are respectively parallel to the extension direction of the data signal line, the driving circuit layer further includes a first lead and a second lead, and the extension direction of the first lead and the extension direction of the second lead intersect with the extension direction of the data signal line respectively; One end of the first lead is connected to the first signal line, and the first lead is connected to the control end of the output circuit; one end of the second lead is connected to the second signal line, and the second lead is connected to the control end of the control circuit.

10. The array substrate according to claim 9, characterized in that: The driving circuit layer further includes at least one third signal line, the third signal line is located between the data signal line and the first signal line, and between the data signal line and the second signal line; the driving circuit layer includes a first conductive layer and a second conductive layer, the third signal line is located in the first conductive layer; The first lead includes a connected first section and a second section, the first section is connected to the first signal line, and the second section is connected to the control end of the output circuit; the second lead includes a connected third section and a fourth section, the third section is connected to the second signal line, and the fourth section is connected to the control end of the control circuit; the orthographic projection of the first section on the substrate and the orthographic projection of the third section on the substrate overlap with the orthographic projection of the third signal line on the substrate respectively, the first section and the third section are located in the second conductive layer, and the second section, the fourth section, the control end of the output circuit and the control end of the control circuit are all located in the first conductive layer.

11. The array substrate according to claim 1, characterized in that: The driving circuit layer includes a first conductive layer and a second conductive layer, the first conductive layer includes a fan-out line and an output pin; the output signal line includes a first signal segment, a second signal segment, a third signal segment and a fourth signal segment connected in sequence; an extension direction of the first signal segment and an extension direction of the third signal segment respectively intersect with an extension direction of the data signal line, and an extension direction of the second signal segment and an extension direction of the fourth signal segment are respectively parallel to an extension direction of the data signal line; The first signal segment is connected to the output end of the output circuit; the orthographic projection of at least part of the second signal segment on the substrate overlaps with the orthographic projection of the fan-out line on the substrate, and the at least part of the segment is located in the second conductive layer; the fourth signal segment is located in the second conductive layer, and the orthographic projection of the fourth signal segment on the substrate overlaps with the orthographic projection of the output pin on the substrate.

12. The array substrate according to claim 1, characterized in that: The width of the output signal line ranges from 6 μm to 15 μm.

13. The array substrate according to claim 1, characterized in that: The distance between the output signal line and the adjacent signal line located in the same conductive layer is greater than or equal to 4 μm; and / or, A distance between an orthographic projection of the output signal line on the substrate and an orthographic projection of an adjacent signal line located in a different conductive layer on the substrate is greater than or equal to 2 μm.

14. A display panel, characterized in that: The display panel includes a driving chip, a control chip, a color filter substrate, a liquid crystal layer and an array substrate according to any one of claims 1 to 12; the color filter substrate and the array substrate are arranged opposite to each other, and the liquid crystal layer is located between the color filter substrate and the array substrate; the driving chip is respectively connected to the input end of the control circuit, the first signal line and the second signal line; the control chip is electrically connected to the output end of the output signal line; the display panel includes a display area, and the boundary of the central area coincides with the boundary of the display area.

15. The display panel according to claim 14, characterized in that: The display panel also includes a circuit board, which is provided with an amplifier circuit; the output end of the output signal line is connected to the amplifier circuit; the control chip is electrically connected to the output end of the amplifier circuit to obtain the signal output by the amplifier circuit.

16. A projection device, characterized in that: The projection device comprises a light source and the display panel according to claim 14 or 15.

17. A method for controlling a display panel, characterized in that: A control chip for a display panel according to claim 14 or 15; the control method comprising: Acquire a leakage current signal, wherein the leakage current signal indicates the magnitude of the leakage current output by the output signal line; Acquire a control signal matching the leakage current signal, wherein the control signal includes at least one of an off voltage of a switch transistor of a pixel circuit and a gamma voltage signal; The display panel is controlled according to the control signal matching the leakage current signal.

18. The control method of the display panel according to claim 17, characterized in that: The obtaining of a control signal matching the leakage current signal comprises: Determining whether a current control signal of the display panel matches the leakage current signal; If the current control signals all match the leakage current signal, the current control signals are obtained; if the current control signals do not match the leakage current signal, the control signals that match the leakage current signal are obtained based on the correspondence between the control signals that do not match the leakage current signal and the leakage current signal.

19. The method for controlling a display panel according to claim 17, wherein: The output circuit includes at least one second transistor, and the control circuit includes at least one third transistor; The second transistor and the third transistor are both N-type transistors, and the obtaining of the leakage current signal includes: during a black screen period between two frames, the first signal line provides a high-level signal to the second transistor, and the second signal line provides a low-level signal to the third transistor, so that the second transistor is turned on and the third transistor is turned off, and the leakage current of the first transistor is output through the second transistor and the output signal line; receiving the leakage current signal; or, The second transistor and the third transistor are both P-type transistors, and the method of obtaining the leakage current signal includes: during a black screen period between two frames, the first signal line provides a low-level signal to the second transistor, and the second signal line provides a high-level signal to the third transistor, so that the second transistor is turned on and the third transistor is turned off, and the leakage current of the first transistor is output through the second transistor and the output signal line; receiving the leakage current signal.

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