Memory clock control method and control device

Abstract

The memory clock control method comprises the following steps of: triggering a basic input / output chip by a starting signal so as to send a starting signal to an auxiliary input / output chip; the auxiliary input / output chip is triggered by an initial signal so as to set the voltage of a pin according to pre-stored voltage control data, the pin is connected to the memory, and the voltage is used for controlling the clock pulse mode of the memory; the basic input / output chip adjusts the voltage control data of the auxiliary input / output chip according to the clock change instruction, a reboot program is executed to send a starting signal to the auxiliary input / output chip again, a first clock mode corresponding to the voltage control data before adjustment is a non-overclocking mode, and a second clock mode corresponding to the voltage control data before adjustment is a non-overclocking mode. And the second clock pulse mode corresponding to the adjusted voltage control data is an overclocking mode.

Description

Technical Field

[0001] The invention relates to a memory clock control method and a control device. Background Art

[0002] In typical computer devices, random-access memory (RAM) is the memory that directly exchanges data with the central processing unit (CPU). Its clock speed represents the rate at which data can be transferred in and out of the memory; a higher clock speed indicates a greater number of transfers per second. To ensure product stability, manufacturers of non-overclockable memory typically pre-set the memory's clock speed at the factory to within a factory-set clock speed range. This factory-set clock speed range is smaller than the memory's inherent operating speed range. Therefore, if users wish to enable their computer's non-overclockable memory to operate at a higher processing speed, they often need to manually adjust the memory's factory settings before they can perform the so-called overclocking operation. This process is complex and prone to problems. Summary of the Invention

[0003] In view of the above, the present invention provides a memory clock control method and control device.

[0004] A memory clock control method according to an embodiment of the present invention includes triggering a basic input / output chip by a power-on signal to send a start signal to an auxiliary input / output chip; triggering the auxiliary input / output chip by the start signal to set a voltage of a pin according to pre-stored voltage control data, wherein the pin is connected to a memory and the voltage is used to control a clock mode of the memory; when the basic input / output chip is controlled to generate a clock change instruction associated with the memory, adjusting the voltage control data of the auxiliary input / output chip according to the clock change instruction, and executing a reboot procedure to re-send the start signal to the auxiliary input / output chip, wherein the first clock mode corresponding to the voltage control data before adjustment is a non-overclocking mode, and the second clock mode corresponding to the voltage control data after adjustment is an overclocking mode.

[0005] According to one embodiment of the present invention, a memory clock control device includes a processor, a memory, an auxiliary input / output chip, and a basic input / output chip. The memory is connected to the processor. The auxiliary input / output chip is connected to the memory and is configured to be triggered by a start signal to set the voltage of a pin of the auxiliary input / output chip according to pre-stored voltage control data, wherein the pin is connected to the memory and the voltage is used to control the clock mode of the memory. The basic input / output chip is connected to the processor and the auxiliary input / output chip and is configured to be triggered by a power-on signal to send a start signal to the auxiliary input / output chip. When a clock change instruction associated with the memory is generated by the control, the voltage control data of the auxiliary input / output chip is adjusted according to the clock change instruction, and a restart procedure is executed to re-send the start signal to the auxiliary input / output chip. The first clock mode corresponding to the voltage control data before adjustment is a non-overclocking mode, and the second clock mode corresponding to the voltage control data after adjustment is an overclocking mode.

[0006] Through the above-described structure, the memory clock control method and control device disclosed in this application can, via a BIOS chip, store corresponding voltage control data in an auxiliary I / O chip based on the last user-set memory overclocking mode. Based on whether the voltage control data in the auxiliary I / O chip has changed, the voltage of a specific pin of the auxiliary I / O chip, connected to the memory, is then determined to be altered, thereby adjusting the memory to operate within a clock frequency range outside the factory default. Computer equipment employing this memory clock control method and control device can automatically detect whether the memory is about to enter overclocking mode and make corresponding adjustments during the process from power-up to the BIOS chip boot process.

[0007] The above description of the content of the present invention and the following description of the embodiments are used to demonstrate and explain the spirit and principle of the present invention, and to provide further explanation of the scope of the patent application of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 FIG. 1 is a block diagram of a memory clock control device according to an embodiment of the present invention.

[0009] Figure 2 FIG. 4 is a flow chart of a memory clock control method according to an embodiment of the present invention.

[0010] Figure 3 FIG. 4 is a flow chart of a memory clock control method according to another embodiment of the present invention. DETAILED DESCRIPTION

[0011] The following detailed description of the features and advantages of the present invention is sufficient to enable any person skilled in the art to understand the technical content of the present invention and implement it accordingly. Furthermore, based on the disclosure of this specification, the claims, and the accompanying drawings, any person skilled in the art can easily understand the relevant objects and advantages of the present invention. The following examples further illustrate the concepts of the present invention but are not intended to limit the scope of the present invention in any way.

[0012] Please refer to Figure 1 , Figure 1 FIG. 1 is a block diagram of a memory clock control device according to an embodiment of the present invention. Figure 1 As shown, the memory clock control device 100 includes a processor 1, a memory 2, an auxiliary input / output chip 3, and a basic input / output chip 4. Memory 2 is connected to processor 1. The auxiliary input / output chip 3 is connected to memory 2 and is configured to be triggered by a start signal to set the voltage of a pin of the auxiliary input / output chip 3 according to pre-stored voltage control data, wherein the pin is connected to memory 2 and the voltage is used to control the clock mode of memory 2. The basic input / output chip 4 is connected to processor 1 and auxiliary input / output chip 3 and is configured to be triggered by a power-on signal to send a start signal to the auxiliary input / output chip 3. When a clock change instruction associated with memory 2 is generated by the control, the voltage control data of the auxiliary input / output chip 3 is adjusted according to the clock change instruction, and a restart procedure is executed to re-send the start signal to the auxiliary input / output chip 3. The first clock mode corresponding to the voltage control data before adjustment is a non-overclocking mode, and the second clock mode corresponding to the voltage control data after adjustment is an overclocking mode.

[0013] In this example, the memory clock control device 100 can be disposed on a motherboard of a computer device, but the present invention is not limited thereto. The processor 1 can be a central processing unit (CPU), a graphics processing unit (GPU), or a computing chip integrating both a CPU and a GPU, and this invention is not limited thereto. The memory 2 can be a synchronous dynamic random-access memory (SDRAM), and in particular, can be a fifth-generation double data rate synchronous dynamic random-access memory (DDR5 SDRAM). The memory 2 is connected to the processor 1 to provide various data required by the processor 1. For different memories, their overclocking mode and non-overclocking mode can correspond to different clock frequencies. Specifically, when the clock frequency of the memory is operated within the factory-preset clock range, it is considered to be in non-overclocking mode. When the clock frequency of the memory is operated beyond the factory-preset clock range, it is considered to be in overclocking mode. The factory-default clock speed range of the aforementioned memories depends on the memory manufacturer and memory specifications. However, generally speaking, newer memories have a higher factory-default clock speed range. Specifically, memory 2 can be a non-overclocked memory with overclocking mode disabled at the factory. Taking a fifth-generation double-data-rate synchronous dynamic random access memory as an example, memory 2 can have a base clock speed of up to 4400 MHz in non-overclocked mode, or 4400 million data transfers per second (MT / s). In overclocked mode, memory 2 can have a clock speed higher than 4400 MHz, or higher than 4400 million data transfers per second (MT / s). It should be noted that the boundary between the base clock speed in non-overclocked mode and the clock speed in overclocked mode can vary for different memories.

[0014] Both the auxiliary input / output chip 3 and the basic input / output chip 4 are related to the operation of other hardware and software in the computer device. The basic input / output chip 4 stores the firmware for the Basic Input / Output System (BIOS), which can be implemented via a read-only memory (ROM) chip. It controls basic computer operations, such as the boot process and the power on self-test (POST). The auxiliary input / output chip 3 can be a chip that integrates multiple communication links, responsible for connecting to other devices such as the keyboard, mouse, and fan, and can be used to manage the power parameters of multiple devices. In this example, the auxiliary input / output chip 3 can be connected to a specific pin of the memory 2 via a general-purpose input / output (GPIO) pin (to provide the VR_Enabled signal). The voltage of this GPIO pin is used to control the clock mode of the memory 2, whether it is in overclocked mode or non-overclocked mode. In this example, the auxiliary input / output chip 3 may be a super I / O chip, and may adjust the voltage of the general purpose input / output pin by a preset value stored at a specific address (e.g., offset) in the chip. For example, a high voltage of the general purpose input / output pin corresponds to the overclocking mode of the memory 2, and a low voltage of the general purpose input / output pin corresponds to the non-overclocking mode of the memory 2. Alternatively, a low voltage of the general purpose input / output pin corresponds to the overclocking mode of the memory 2, and a high voltage of the general purpose input / output pin corresponds to the non-overclocking mode of the memory 2. As previously mentioned, the memory 2 is, in particular, a non-overclocking memory that does not have the overclocking mode enabled by factory default. The memory clock control device 100 of this embodiment can control the memory 2 to enter the non-overclocking mode through the connection between the pins of the auxiliary input / output chip 3 and the memory 2, thereby improving the operating performance of the memory 2.

[0015] The voltage of the pins of the auxiliary input and output chip 3 is determined according to the pre-stored voltage control data of the auxiliary input and output chip 3, and the voltage control data of the auxiliary input and output chip 3 can be adjusted by the basic input and output chip 4, which will be described in detail later. Figure 1As shown, the memory clock control device 100 may further include a platform controller hub (PCH) 5, which serves as a connection interface between the processor 1, the auxiliary input / output chip 3, and the basic input / output chip 4. For example, when the computer device is powered on, the basic input / output chip 4 may transmit a start signal to the processor 1 and the auxiliary input / output chip 3 via the platform controller hub 5. Specifically, data can be transmitted between the basic input / output chip 4 and the platform controller hub 5 of the memory clock control device 100 via a serial peripheral interface (SPI), data can be transmitted between the auxiliary input / output chip 3 and the platform controller hub 5 via a low pin count bus (LPC), and data can be transmitted between the processor 1 and the platform controller hub 5 via a direct media interface (DMI).

[0016] Please refer to Figure 2 , Figure 2 FIG. 1 is a flow chart of a memory clock control method according to an embodiment of the present invention. Figure 2 As shown, the memory clock control method of this embodiment is Figure 1 The memory clock control device 100 shown in FIG. 1 executes the following steps: Step S1: a BIOS chip is triggered by a power-on signal to send a start signal to the auxiliary BIOS chip; Step S3: the auxiliary BIOS chip is triggered by the start signal to set the voltage of the auxiliary BIOS chip pin according to pre-stored voltage control data; and when the BIOS chip is controlled to generate a clock change instruction associated with the memory, Step S5: the BIOS chip adjusts the voltage control data of the auxiliary BIOS chip according to the clock change instruction; and Step S7: the BIOS chip executes a reboot procedure to re-send the start signal to the auxiliary BIOS chip (returning to Step S1). It should be noted that the first clock mode corresponding to the voltage control data before adjustment is the non-overclocking mode, and the second clock mode corresponding to the voltage control data after adjustment is the overclocking mode.

[0017] In step S1, after the computer device is powered on and before the BIOS chip executes the boot sequence and pre-boot self-test, the BIOS chip may be triggered by the power-on signal to send a start signal to the auxiliary I / O chip. In step S3, when the auxiliary I / O chip is triggered by the start signal from the BIOS chip, the voltage of a pin of the auxiliary I / O chip is set, for example, to a high or low level, based on pre-stored voltage control data. The pin is connected to the memory, and the voltage of the pin is used to control the clock mode of the memory. In other words, when the computer device is shut down, the auxiliary I / O chip may store the voltage control data corresponding to the last set clock mode, thereby controlling the clock mode of the memory upon the next startup. In step S5, when the BIOS chip is controlled to generate a clock change command associated with the memory, the voltage control data of the I / O chip may be adjusted according to the clock change command. In step S7, a reboot procedure is executed, including resetting system parameters, after which step S1 is re-executed. In other words, after the memory clock control method of this embodiment returns to step S1 after step S7, the voltage control data in the auxiliary I / O chip has been changed. Therefore, the voltage of the pins of the auxiliary I / O chip connected to the memory has been changed in step S3, thereby controlling the memory to enter overclocking mode.

[0018] Please combine Figure 2 refer to Figure 3 , Figure 3 FIG. 1 is a flow chart of a memory clock control method according to another embodiment of the present invention. Figure 2 and Figure 3 As shown, the memory clock control method of this example can be executed after step S3 in which the auxiliary input-output chip is triggered by the start signal to set the voltage of the pin of the auxiliary input-output chip according to the pre-stored voltage control data. Step S41: receiving the specified clock associated with the memory by the basic input-output chip; step S42: comparing whether the specified clock is the same as the preset clock of the memory, wherein the preset clock corresponds to the pre-stored voltage control data; if the specified clock is the same as the preset clock, executing step S9: obtaining and executing the operation program by the processor; if the specified clock is different from the preset clock, executing step S43: generating a clock change instruction according to the specified clock, and executing the above-mentioned step S5.

[0019] In step S41, during the boot-up process of the computer device, the basic input and output chip can be awakened and connected to a user interface (such as a basic input and output system setting interface), and the user interface can output a designated clock associated with the memory to the basic input and output chip. In step S42, the basic input and output chip can compare whether the designated clock is equal to the preset clock of the memory to determine whether to change the voltage control data of the auxiliary input and output chip. When the designated clock is different from the preset clock, in step S43, the basic input and output chip can generate a clock change instruction according to the designated clock, that is, the clock change instruction includes first data corresponding to the designated clock. In one embodiment, the designated clock in step S42 can refer to the clock corresponding to The information corresponding to the instruction to check the overclocking mode or the instruction not to check the overclocking mode in the user interface. That is, the determination in step S42 that the specified clock is different from the preset clock may refer to the determination that there is an instruction to check the overclocking mode in the user interface. Further, in step S5, the basic input and output chip may adjust the voltage control data of the auxiliary input and output chip according to the first data corresponding to the specified clock in the instruction to change the clock. On the other hand, when the specified clock is the same as the preset clock (for example, when it is determined that there is no instruction to check the overclocking mode in the user interface), the basic input and output chip may control the processor to obtain and execute the operating program, that is, to execute the normal boot program, wherein the operating program refers to running the operating system (Operation System (OS) program. It should be noted that the process of "the BIOS comparing the designated clock and the preset clock to find that they are different" in this case is also equivalent to the process of "the BIOS not being controlled to generate the clock change instruction associated with the memory." That is, in other embodiments, step S9 can also be executed as follows: when the BIOS is not controlled to generate the clock change instruction associated with the memory, the control processor obtains and executes the operating program.

[0020] Through the above-described structure, the memory clock control method and control device disclosed in this application can, via a BIOS chip, store corresponding voltage control data in an auxiliary I / O chip based on the last user-set memory overclocking mode. Based on whether the voltage control data in the auxiliary I / O chip has changed, the voltage of a specific pin of the auxiliary I / O chip, connected to the memory, is then determined to be altered, thereby adjusting the memory to operate within a clock frequency range outside the factory default. Computer equipment employing this memory clock control method and control device can automatically detect whether the memory is about to enter overclocking mode and make corresponding adjustments during the process from power-up to the BIOS chip boot process.

[0021]

Explanation of symbols

[0022] 100:Memory clock control device

[0023] 1: Processor

[0024] 2: Memory

[0025] 3: Auxiliary input and output chip

[0026] 4: Basic input and output chip

[0027] 5: Platform path controller

[0028] S1~S9, S41~S43: steps.

Claims

1. A memory clock control method, characterized in that: Include: The basic input-output chip is triggered by the power-on signal to send a start signal to the auxiliary input-output chip; The auxiliary input-output chip is triggered by the start signal to set the voltage of the pin of the auxiliary input-output chip according to pre-stored voltage control data, wherein the pin is connected to a memory and the voltage is used to control the clock mode of the memory; as well as When the basic input-output chip is controlled to generate a change clock instruction associated with the memory, the basic input-output chip adjusts the voltage control data of the auxiliary input-output chip according to the change clock instruction, and executes a restart procedure to re-send the start signal to the auxiliary input-output chip. The first clock mode corresponding to the voltage control data before adjustment is a non-overclocking mode, and the second clock mode corresponding to the voltage control data after adjustment is an overclocking mode.

2. The memory clock control method according to claim 1, wherein: Also includes: Receiving a designated clock associated with the memory by the basic input and output chip; Comparing the designated clock with a preset clock in the memory, wherein the preset clock corresponds to the pre-stored voltage control data; as well as When the designated clock is different from the preset clock, the clock change instruction is generated according to the designated clock.

3. The memory clock control method according to claim 1, wherein: Also includes: When the basic input and output chip is not controlled to generate the change clock instruction associated with the memory, the control processor obtains and executes the operation program.

4. The memory clock control method according to claim 1, wherein the step of setting the voltage of the pin of the auxiliary input / output chip according to the pre-stored voltage control data by the auxiliary input / output chip comprises: The auxiliary input-output chip is used to set the voltage of the universal input-output pin of the auxiliary input-output chip according to the pre-stored voltage control data. 5 . The memory clock control method according to claim 1 , wherein the memory is a fifth generation double data rate synchronous dynamic random access memory, and the clock frequency of the overclocking mode is greater than 4400 MHz.

6. A memory clock control device, characterized in that: Include: processor; a memory connected to the processor; An auxiliary input-output chip connected to the memory, used to be triggered by a start signal to set the voltage of a pin of the auxiliary input-output chip according to pre-stored voltage control data, wherein the pin is connected to the memory and the voltage is used to control a clock mode of the memory; A basic input-output chip is connected to the processor and the auxiliary input-output chip and is used for: being triggered by a power-on signal to send the start signal to the auxiliary input / output chip; as well as When the controlled device generates a change clock instruction associated with the memory, the voltage control data of the auxiliary input-output chip is adjusted according to the change clock instruction, and a restart procedure is executed to re-send the start signal to the auxiliary input-output chip. The first clock mode corresponding to the voltage control data before adjustment is a non-overclocking mode, and the second clock mode corresponding to the voltage control data after adjustment is an overclocking mode.

7. The memory clock control device according to claim 6, wherein the basic input and output chip is further used for: receiving a designated clock associated with the memory; comparing the designated clock with a preset clock of the memory, wherein the preset clock corresponds to the pre-stored voltage control data; and When the designated clock is different from the preset clock, the clock change instruction is generated according to the designated clock.

8. The memory clock control device according to claim 6, wherein the basic input and output chip is further used for: When the clock change instruction associated with the memory is not received, the processor is controlled to obtain and execute an operation program.

9. The memory clock control device according to claim 6, wherein the pin of the auxiliary input-output chip is a general-purpose input-output pin.

10. The memory clock control device according to claim 6, wherein the memory is a fifth generation double data rate synchronous dynamic random access memory, and the clock frequency of the overclocking mode is greater than 4400 MHz.

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