Repair method of DRAM chip and DRAM chip

Abstract

The invention discloses a method for repairing a DRAM (Dynamic Random Access Memory) chip and the DRAM chip, relates to the technical field of semiconductor storage, and discloses the method for repairing the DRAM chip, which comprises the following steps: acquiring bad area address information of the DRAM chip; shielding a bad region unit of the DRAM chip based on the bad region address information to generate a shielding result; sorting good region units of the DRAM chip based on the shielding result to generate a sorting result; and storing the sorting result to the DRAM chip so as to repair the DRAM chip. By acquiring the bad area address information of the DRAM chip and performing targeted shielding on the bad areas, memory access errors and data loss caused by the bad areas can be reduced. And good area units of the DRAM chip are reordered, so that memory fragments are prevented from being generated, and the access efficiency is improved. According to the method, the DRAM chip can be effectively repaired through simple shielding and sorting operations, and the maintenance complexity and cost are reduced.

Description

Technical Field

[0001] The present application relates to a specific technical field, and in particular to a DRAM chip repair method and a DRAM chip. Background Art

[0002] DRAM chips (Dynamic Random Access Memory) are composed of many storage cells, each of which can store a bit (0 or 1). Each storage cell consists of a capacitor and a transistor. The capacitor is used to store data, while the transistor is used to control the state of the capacitor. When data is written to the DRAM chip, a charge is stored in the capacitor, and this charge represents the bit value of the data. When the stored data needs to be accessed, the DRAM chip will find the corresponding storage cell according to the address and read out the charge.

[0003] However, due to leakage current, parasitic capacitance, manufacturing process deviation, external environmental influences and other reasons, DRAM chips have bad areas, which affect the reliability and stability of their stored data. The existence of these bad areas may cause data reading errors, reduced storage capacity and overall performance impairment, thus causing adverse effects on systems or devices using DRAM chips. Summary of the invention

[0004] The main purpose of this application is to provide a DRAM chip repair method and a DRAM chip, aiming to solve the technical problem that the system chip cannot be accessed due to the existence of bad areas in the DRAM chip.

[0005] To achieve the above-mentioned purpose, the present application proposes a method for repairing a DRAM chip, the method comprising: obtaining bad area address information of the DRAM chip; based on the bad area address information, shielding the bad area units of the DRAM chip to generate a shielding result; based on the shielding result, sorting the good area units of the DRAM chip to generate a sorting result; storing the sorting result to the DRAM chip to repair the DRAM chip.

[0006] In one embodiment, the step of obtaining the bad block address information of the DRAM chip includes: configuring the FGPA test platform required for the DRAM chip test; based on the FGPA test platform, implementing the DRAM chip memory first segment address space test to generate a first test result; based on the FGPA test platform, implementing the DRAM chip memory unit full domain test to generate a second test result; based on the first test result and the second test result, obtaining the bad block address information of the DRAM chip.

[0007] In one embodiment, the step of shielding the bad block unit of the DRAM chip based on the bad block address information to generate a shielding result includes: storing the bad block address information in a shielding area of ​​the address storage area; shielding the bad block address information in the shielding area to generate a feedback result; and generating a shielding result based on the bad block address information and the feedback result.

[0008] In one embodiment, the step of sorting the good block units of the DRAM chip based on the masking result to generate a sorting result includes: obtaining the good block address information of the DRAM chip based on the masking result; obtaining the sorting storage area of ​​the address storage area; sorting the good block address information in sequence, and mapping it from the starting position of the sorting storage area in turn to generate a sorting result.

[0009] In one embodiment, the step of storing the sorting result in a DRAM chip to repair the DRAM chip includes: storing the sorting result in a DRAM chip; establishing a mapping relationship between the sorting result and good block units; and repairing the DRAM chip by accessing the sorting result.

[0010] In addition, to achieve the above-mentioned purpose, the present application also proposes a DRAM chip, which applies the DRAM chip repair method as described above; the DRAM chip includes: a first storage area and a second storage area; the first storage area is used to store data information; the second storage area is a non-volatile storage area, which is used to store the sorting results and masking results of the first storage area.

[0011] In addition, to achieve the above-mentioned purpose, the present application also proposes a DRAM chip repair device, and the DRAM chip repair device includes: an information acquisition module and a sorting and shielding module; the information acquisition module is used to obtain the bad area address information of the DRAM chip; the sorting and shielding module is used to shield the bad area units of the DRAM chip based on the bad area address information to generate a shielding result; it is also used to sort the good area units of the DRAM chip based on the shielding result to generate a sorting result; it is also used to store the sorting result to the DRAM chip to repair the DRAM chip.

[0012] In addition, to achieve the above-mentioned purpose, the present application also proposes a DRAM chip repair device, which includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the DRAM chip repair method as described above.

[0013] In addition, to achieve the above-mentioned purpose, the present application also proposes a storage medium, which is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by the processor, the steps of the DRAM chip repair method described above are implemented.

[0014] In addition, to achieve the above-mentioned purpose, the present application also provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, the steps of the DRAM chip repair method as described above are implemented.

[0015] One or more technical solutions proposed in this application have at least the following technical effects:

[0016] By accurately obtaining the bad block address information of the DRAM chip and shielding these bad blocks in a targeted manner, the memory access errors and data loss problems caused by bad blocks can be significantly reduced. Reordering the good block units of the DRAM chip can not only avoid the generation of memory fragmentation, but also improve the efficiency of memory access. The sorted good block units can form a more continuous memory space, allowing the system to find the required address more quickly when allocating and accessing memory, thereby reducing memory access delays and conflicts. This method can effectively repair DRAM chips through simple shielding and sorting operations, greatly reducing the complexity and cost of maintenance. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0018] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0019] Figure 1 A schematic diagram of a process flow provided for an embodiment of a method for repairing a DRAM chip of the present application;

[0020] Figure 2 A schematic diagram of the structure provided for the DRAM chip embodiment of the present application;

[0021] Figure 3 This is a schematic diagram of the module structure of the DRAM chip repair device of the embodiment of the present application;

[0022] Figure 4 Schematic diagram of the device structure of the hardware operating environment involved in the DRAM chip repair method in the embodiment of the present application.

[0023] Description of Figure Numbers:

[0024] Label illustrate Label illustrate 10 First storage area 20 Second storage area 30 Information acquisition module 40 Sorting mask module

[0025] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0026] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0027] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0028] In actual system applications, the interaction between SOC (System on Chip) and DRAM (Dynamic Random Access Memory) chips is crucial, especially the address continuity requirement when the SOC chip accesses DRAM memory.

[0029] This is because when SOC chips are designed, their memory access logic usually assumes that the addresses of memory cells or blocks are continuous. This continuity ensures efficient and reliable data access. If the addresses are not continuous, the SOC chip may encounter data access errors, performance degradation, or system crashes.

[0030] For example, discontinuous addresses may cause the SOC chip to mistakenly read adjacent but non-target data blocks when trying to access data, thereby causing data errors; in order to handle discontinuous addresses, the SOC may require additional logic to manage memory access, which will increase latency and reduce overall performance; in extreme cases, discontinuous addresses may cause the system to fail to correctly load or execute necessary programs and data, causing the system to crash.

[0031] Based on this, in order to solve the technical problem that the DRAM chip has bad areas and the system chip cannot be accessed, the embodiment of the present application provides a method for repairing the DRAM chip. Figure 1 , Figure 1 This is a flow chart of the first embodiment of the DRAM chip repair method of the present application.

[0032] In this embodiment, the DRAM chip repair method includes steps S10 to S40:

[0033] Step S10, obtaining bad block address information of the DRAM chip.

[0034] It should be noted that bad block address information usually refers to the address information corresponding to the area in the storage device (such as hard disk, SSD, DRAM chip, etc.) that cannot be used normally or has data reading and writing errors due to various reasons such as physical damage, manufacturing defects, wear and tear, etc.

[0035] It should be noted that for DRAM chips, bad block address information includes the following aspects: In DRAM chips, bad blocks usually refer to areas where the block cannot store data normally due to manufacturing defects or physical damage during use. Bad block address information will indicate the specific location of these bad blocks in the DRAM chip, usually expressed in the form of addresses.

[0036] In addition to bad blocks, there may also be bad bits in the DRAM chip, that is, one or more bits cannot store data normally. The bad bit address information will indicate the specific location of these bad bits in the DRAM chip, including information such as block address and bit offset.

[0037] Specifically, the bad block address information may also include information about the type of fault, such as read fault, write fault, check error, etc. This information helps to further understand the nature and possible causes of the bad block. In some cases, the bad block address information may also include information about the fault frequency, i.e., the frequency or number of times the bad block fails. This helps to assess the impact of the bad block on the performance and reliability of the storage device.

[0038] It is understandable that obtaining the bad block address information of the DRAM chip is the process of identifying the bad block of the DRAM chip and parsing the address. Generally speaking, obtaining the bad block address information of the DRAM chip requires the use of professional testing tools and methods, such as memory testing software, hardware testing platforms, etc. These tools can perform comprehensive testing and analysis on DRAM chips and generate detailed test reports, including bad block address information and other related content.

[0039] It should be noted that the bad area address information of DRAM chips may vary depending on factors such as chip model, manufacturer, batch, etc. Therefore, in actual operation, specific analysis is required and corresponding processing is performed based on the information in the test report.

[0040] Furthermore, this embodiment provides a feasible implementation method for obtaining bad block address information: configuring the FGPA test platform required for the DRAM chip test; based on the FGPA test platform, implementing the DRAM chip memory first segment address space test to generate a first test result; based on the FGPA test platform, implementing the DRAM chip memory unit full domain test to generate a second test result; based on the first test result and the second test result, obtaining the bad block address information of the DRAM chip.

[0041] It should be noted that the test platform needs to be built first. The FPGA test platform has high flexibility and scalability. Through programming and configuration, FPGA can adapt to different types of DRAM chip test requirements, including different storage capacity, timing requirements and failure modes. Therefore, the FPGA (field programmable gate array) test platform was selected. The platform has sufficient IO resources and processing power to support the test requirements of DRAM chips. The FPGA test platform can simulate the working environment and timing of DRAM chips for accurate testing.

[0042] It is understood that on the FPGA test platform, the memory first address space of the DRAM chip is tested. This usually involves reading and writing the first address space and checking whether any errors or failures occur. After the test is completed, a first test result is generated, which should contain information about the status of the first address space, including whether there are bad blocks.

[0043] It is understandable that on the FPGA test platform, the entire memory unit of the DRAM chip is tested. This usually involves reading and writing the entire memory address space and checking the status of each address unit. After the test is completed, a second test result is generated, which should contain information about the status of the entire memory address space, including the specific location of the bad area.

[0044] It is understandable that in DRAM chip testing, the practice of testing the head end first and then the entire domain is mainly based on the ability to quickly identify potential problems. The head end address space is usually a more critical and sensitive area in the DRAM chip, and its stability and reliability have an important impact on the performance of the entire chip; the test process from the head end to the entire domain is actually a step-by-step in-depth and step-by-step troubleshooting process. By testing the head end first, we can get a preliminary understanding of the overall performance and stability of the DRAM chip, and provide more accurate test parameters and conditions for subsequent global tests.

[0045] It is understandable that the bad area address information of the DRAM chip is extracted and analyzed in combination with the first test result and the second test result. The test results are further processed, such as data analysis, error location, etc. Finally, a report containing the bad area address information of the DRAM chip is generated for subsequent processing and management.

[0046] It should be noted that this embodiment uses an FPGA test platform to achieve high-speed and high-precision testing of DRAM chips. Through comprehensive memory testing, bad areas in DRAM chips can be accurately identified and their address information can be obtained. This solution is versatile and scalable and is suitable for different types of DRAM chip testing requirements.

[0047] Step S20: Based on the bad block address information, the bad block units of the DRAM chip are shielded to generate a shielding result.

[0048] It can be understood that shielding the bad block units of the DRAM chip means that when the SOC accesses the DRAM, it directly skips the corresponding physical addresses of all bad blocks and bad blocks and does not perform read and write operations.

[0049] Specifically, some redundant storage units or address lines can be reserved in the hardware design of the DRAM chip so as to be replaced when a bad area is found. The address of the bad area unit is mapped to the redundant storage unit by modifying the control logic of the DRAM chip, thereby achieving shielding.

[0050] Or use software shielding, in the operating system or memory management software, mark the bad block unit as unavailable based on the bad block address information. When the system tries to access these units, the software will intercept the access request and return an error code or perform other processing. Or use hybrid shielding, combining hardware and software methods, performing address mapping at the hardware level and access control at the software level to achieve a more comprehensive shielding effect.

[0051] It should be noted that generating shielding results may include recording shielding information, verifying shielding effects, and generating shielding reports. The shielded bad block unit address, shielding method, shielding time and other information are recorded for subsequent tracking and management; read and write tests are performed on the shielded DRAM chip to ensure that the bad block unit has been effectively shielded and has no impact on other normal units; based on the test results and shielding information, a detailed shielding report is generated, including the number of shielded bad block units, locations, shielding methods, and test results.

[0052] Furthermore, this embodiment provides a feasible implementation method for shielding the bad block unit of the DRAM chip based on the bad block address information to generate a shielding result: storing the bad block address information in a shielding area of ​​the address storage area; shielding the bad block address information in the shielding area to generate a feedback result; generating a shielding result based on the bad block address information and the feedback result.

[0053] It should be noted that the core of this embodiment is the introduction of an address storage area, which is a specially designed storage area for storing address information of bad blocks detected in a DRAM chip. This area can be located inside the DRAM chip or can be an independent memory connected to the DRAM chip.

[0054] It can be understood that the address storage area provides a centralized location to store bad block address information, making this information easy to access and manage. When the system needs to access the DRAM chip, it can first check the address storage area to determine whether there are any bad block addresses. If so, the system can immediately take appropriate measures (such as skipping these addresses or using redundant addresses) to avoid accessing the bad blocks.

[0055] It is understandable that as DRAM chips are used and tested, new bad block addresses may be detected. The address storage area needs to be able to dynamically update this information to ensure that it always contains the latest bad block addresses. In order to ensure the accuracy and integrity of the address storage area, the bad block address information therein needs to be verified regularly. This can be done through direct communication with the DRAM chip or using specialized test tools.

[0056] It should be noted that shielding the bad block address information stored in the shielded area involves modifying the internal logic of the DRAM chip to ensure that these shielded bad block addresses are not accessed in subsequent memory accesses. Shielding may include mapping the bad block address to a redundant address, adding shielding rules in the access control logic, etc.

[0057] It is understood that after the shielding process is completed, a feedback result is generated. This feedback result should contain information about whether the shielding operation is successful, how many bad block addresses are shielded, whether there are any anomalies or errors, etc. The feedback result can be used to verify the correctness and completeness of the shielding operation.

[0058] Finally, based on the stored bad block address information and the generated feedback results, a final shielding result is generated. This shielding result should be a comprehensive and accurate record that contains all the shielded bad block address information and the results of the shielding operation. It can be used for subsequent memory management, fault tracking, and quality analysis of DRAM chips.

[0059] In this embodiment, a structured method is used to manage and track the bad block units of the DRAM chip, which helps to improve the reliability and stability of the DRAM chip. By generating feedback results and final shielding results, the correctness and integrity of the shielding operation can be easily verified, providing strong support for subsequent maintenance and optimization.

[0060] Step S30: sorting the good block cells of the DRAM chip based on the masking result to generate a sorting result.

[0061] It should be noted that by sorting the good block units, the system can find and access continuous memory areas faster when accessing the DRAM chip, thereby improving the efficiency of memory access. The sorted good block units can be more easily allocated and recycled, which helps to reduce memory fragmentation and improve memory utilization. The final sorting result can be used to guide the system's memory management strategy to avoid system crashes or instability caused by frequent access to bad block units.

[0062] It should be noted that the address continuity of the good block units needs to be considered during sorting, and the good block units with similar addresses are placed together so that the system can access these areas more efficiently.

[0063] It should be noted that in addition to address continuity, the good block units can also be sorted according to performance parameters (such as read and write speed, delay, etc.). Placing good block units with better performance at higher priority positions can further improve system performance.

[0064] It is understandable that before sorting, it is necessary to ensure the accuracy and completeness of the masked results. If there are errors or omissions in the masked results, the sorting results may be inaccurate. The addresses included in the masked results should also be excluded during the sorting process.

[0065] Specifically, this embodiment provides a feasible implementation method for sorting the good block units of the DRAM chip based on the shielding result to generate a sorting result: based on the shielding result, obtaining the good block address information of the DRAM chip; obtaining the sorting storage area of ​​the address storage area; sorting the good block address information in sequence, and mapping it from the starting position of the sorting storage area in turn to generate a sorting result.

[0066] It should be noted that, based on the masking result, all unmasked good block address information is extracted from the test or diagnosis data of the DRAM chip. These good block address information should include the start address, size (or end address) and possible other related attributes (such as performance parameters) of the good block unit.

[0067] It should be noted that an area is reserved in the address storage area for storing the sorted good zone address information, namely the sort storage area. Ensure that the sort storage area has sufficient capacity to store all good zone address information and take into account possible expansion requirements.

[0068] It should be noted that the extracted good area address information is sorted according to preset sorting rules (such as address continuity, performance parameters, etc.). The selection of the sorting algorithm should be comprehensively considered based on factors such as data scale, sorting efficiency and system resources.

[0069] It should be noted that the sorted good area address information is mapped to the starting position of the sorting storage area in sequence. The mapping process should ensure that each good area address information has a unique and continuous position in the sorting storage area. Pointers, indexes or other data structures can be used to track and access the good area address information in the sorting storage area.

[0070] It should be noted that after the sorting is completed, a sorting result including the address information of the sorted good area is generated. The sorting result can be a data structure (such as an array, a linked list, etc.), which contains references or copies of all the good area address information in the sorting storage area. The sorting result can also include metadata related to the sorting, such as sorting rules, sorting time, etc.

[0071] Specifically, the mathematical model of arranging bad memory blocks into continuous good blocks can be abstracted as an interval covering problem, which aims to shield the bad blocks in the memory and arrange the remaining good blocks into a continuous memory address interval. Assume that the memory consists of N units or blocks, and the numbers of all units or blocks are defined as {1, 2, ..., N}; there are M bad blocks, and their number set is B = {b1, b2, ..., bM}, where bi∈{1, 2, ..., N}.

[0072] At this time, the set of good blocks is G = {g1, g2, ..., g(NM)} = {1, 2, ..., N}-B. Each memory block is numbered i, i∈{1, 2, ..., N}. After rearrangement, the good blocks occupy a continuous interval {g1', g2', ..., g(NM)'}, where gi' = g1'+(i-1), that is, the interval formed by the good blocks is [g1', g(NM)'].

[0073] Assuming that we want to place consecutive good blocks starting from number P, the formula can be expressed as: Target: gi'=P+(i-1), i=1, 2, ..., NM, where P is the starting number of the good block interval after rearrangement, i is the number of consecutive good blocks, and gi' is the number of the i-th good block after rearrangement.

[0074] At this time, the constraint is that the bad block cannot be included in the rearranged interval, that is, for all i∈{1, 2, …, NM}, C∩B is an empty set.

[0075] The goal of optimization is usually to minimize the length of the interval after the good blocks are rearranged or to make the good blocks as close to one end of the memory as possible. Specifically, there can be the following objective functions: minimize the starting position P of the good block interval: min P or minimize the total length of the good block interval: min(g(NM)'-g1'+1).

[0076] Step S40, storing the sorting result in the DRAM chip to repair the DRAM chip.

[0077] It is understood that an appropriate storage location is determined in the DRAM chip to store the sorting results. This location can be a specific area in the DRAM chip, such as a reserved memory segment or a portion of the address storage area. Ensure that the storage location has sufficient capacity to store the sorting results and take into account future expansion requirements.

[0078] It is understandable that the memory management information of the DRAM chip is updated according to the sorting results, such as the memory mapping table, address translation table, etc. This information is used to guide the system how to access the memory area in the DRAM chip, ensuring that the system can correctly bypass the bad area and access the good area.

[0079] It is understandable that after storing the sorting results and updating the memory management information, the DRAM chip is subjected to verification testing. The verification test should cover all key functions of the DRAM chip, including read and write operations, address mapping, performance parameters, etc. Ensure that the DRAM chip can work normally after repair and meet the performance requirements of the system.

[0080] Specifically, this embodiment provides a feasible implementation method for storing the sorting result in a DRAM chip to repair the DRAM chip: storing the sorting result in a DRAM chip; establishing a mapping relationship between the sorting result and good block units; and repairing the DRAM chip by accessing the sorting result.

[0081] It can be understood that the sorting result (i.e., the sorting mapping of the good block address information) is first stored in a specific area of ​​the DRAM chip, and then a mapping relationship between the sorting result and the actual good block unit in the DRAM chip is established. When the system needs to access the DRAM chip, it will first check the sorting result, and then access the actual good block unit according to the mapping relationship, thereby bypassing the bad block and realizing the repair and optimization of the DRAM chip.

[0082] This embodiment can significantly reduce the memory access errors and data loss problems caused by bad blocks by accurately obtaining the bad block address information of the DRAM chip and performing targeted shielding on these bad blocks. Reordering the good block units of the DRAM chip can not only avoid the generation of memory fragmentation, but also improve the efficiency of memory access. The sorted good block units can form a more continuous memory space, so that the system can find the required address more quickly when allocating and accessing memory, thereby reducing the delay and conflict of memory access. This method can achieve effective repair of DRAM chips through simple shielding and sorting operations, greatly reducing the complexity and cost of maintenance.

[0083] It should be noted that the above examples are only used to understand the present application and do not constitute a limitation on the repair method of the DRAM chip of the present application. More simple transformations based on this technical concept are all within the scope of protection of the present application.

[0084] Further, based on the above embodiment, the present application also provides a DRAM chip, please refer to Figure 2 , Figure 2 A schematic diagram of the structure of the DRAM chip embodiment of the present application.

[0085] In this embodiment, the DRAM chip includes: a first storage area 10 and a second storage area 20; the first storage area 10 is used to store data information; the second storage area 20 is a non-volatile storage area, used to store the sorting results and masking results of the first storage area.

[0086] It is understood that the first storage area 10 is the main data storage area of ​​the DRAM chip, which is used to store data information that users or systems need to access and process. This area has high-speed access capabilities and is a key part of the DRAM chip to provide high-performance data storage. However, it may also contain some bad areas due to manufacturing defects or long-term use.

[0087] It is understood that the second storage area 20 is a non-volatile storage area for storing key information related to the first storage area 10, including sorting results and masking results. Unlike the first storage area, the second storage area 20 uses non-volatile storage technology, which can keep the stored data unchanged after power failure. This makes it an ideal choice for storing important information with high persistence requirements.

[0088] Meanwhile, the sorting result is mapping information obtained after sorting the address information of the good block cells in the first storage area. It allows the system to efficiently locate the good block cells when accessing the DRAM chip, thereby bypassing the bad block. The shielding result is information about the location and size of the bad block in the DRAM chip. It is used to guide the system on how to avoid accessing these bad blocks to prevent data loss or damage.

[0089] It should be noted that Figure 2 It not only includes the structure of DRAM chips, but also includes the computer hardware schematics, where the various components achieve data storage, processing, and transmission through complex connections and interactions. The computing unit is responsible for performing arithmetic and logical operations; memory components such as ROM and DRAM are used to store data and programs; data transmission components such as DDR and DDR Buffer are responsible for increasing the data transmission rate; the controller is responsible for managing and coordinating the operation of the entire system; and the PMIC is responsible for monitoring and managing the power supply. Non-volatile storage devices are used to keep data unchanged after power failure.

[0090] It is understandable that the second storage area 20 of the DRAM chip can be the address storage area as described above, or can store the program using the sorting masking method as described above, so as to realize an efficient, reliable and durable DRAM chip self-management strategy. This strategy not only improves the reliability and performance of the DRAM chip, but also reduces the risk of system crash and data loss caused by bad blocks.

[0091] This application also provides a DRAM chip repair device, please refer to Figure 3 The DRAM chip repair device includes: an information acquisition module 30 and a sorting and shielding module 40; the information acquisition module 30 is used to obtain the bad area address information of the DRAM chip; the sorting and shielding module 40 is used to shield the bad area units of the DRAM chip based on the bad area address information to generate a shielding result; it is also used to sort the good area units of the DRAM chip based on the shielding result to generate a sorting result; it is also used to store the sorting result to the DRAM chip to repair the DRAM chip.

[0092] The DRAM chip repair device provided by the present application adopts the DRAM chip repair method in the above embodiment, which can solve the technical problem that the DRAM chip has bad areas, resulting in the inaccessibility of the system chip. Compared with the prior art, the beneficial effects of the DRAM chip repair device provided by the present application are the same as the beneficial effects of the DRAM chip repair method provided by the above embodiment, and the other technical features of the DRAM chip repair device are the same as the features disclosed in the above embodiment method, which will not be repeated here.

[0093] The present application provides a DRAM chip repair device, the DRAM chip repair device includes: at least one processor; and a memory connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the DRAM chip repair method in the above-mentioned embodiment one.

[0094] Reference below Figure 4, which shows a schematic diagram of the structure of a DRAM chip repair device suitable for implementing the embodiment of the present application. The DRAM chip repair device in the embodiment of the present application may include but is not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions), PMPs (Portable Media Players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 4 The DRAM chip repair device shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0095] like Figure 4 As shown, the repair device for DRAM chips may include a processing device 1001 (e.g., a central processing unit, a graphics processor, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM: Read Only Memory) 1002 or a program loaded from a storage device 1003 to a random access memory (RAM: Random Access Memory) 1004. In RAM1004, various programs and data required for the operation of the repair device for DRAM chips are also stored. The processing device 1001, ROM1002, and RAM1004 are connected to each other through a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Generally, the following systems can be connected to the I / O interface 1006: an input device 1007 including, for example, a touch screen, a touch pad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD: Liquid Crystal Display), a speaker, a vibrator, etc.; a storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 can allow the repair device of the DRAM chip to communicate with other devices wirelessly or by wire to exchange data. Although the figure shows a repair device of the DRAM chip with various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems can be implemented or have alternatively.

[0096] In particular, according to the embodiments disclosed in the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, the embodiments disclosed in the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device, or installed from a storage device 1003, or installed from a ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are executed.

[0097] The DRAM chip repair device provided by the present application adopts the DRAM chip repair method in the above embodiment, which can solve the technical problem that the DRAM chip has bad areas, resulting in the inaccessibility of the system chip. Compared with the prior art, the beneficial effects of the DRAM chip repair device provided by the present application are the same as the beneficial effects of the DRAM chip repair method provided by the above embodiment, and the other technical features of the DRAM chip repair device are the same as the features disclosed in the method of the previous embodiment, which will not be repeated here.

[0098] It should be understood that the various parts disclosed in this application can be implemented by hardware, software, firmware or a combination thereof. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0099] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0100] The present application provides a computer-readable storage medium having computer-readable program instructions (ie, computer programs) stored thereon, and the computer-readable program instructions are used to execute the DRAM chip repair method in the above-mentioned embodiment.

[0101] The computer-readable storage medium provided in the present application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, systems or devices, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, system or device. The program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination of the above.

[0102] The computer-readable storage medium may be included in the DRAM chip repair device; or may exist independently without being assembled into the DRAM chip repair device.

[0103] The above-mentioned computer-readable storage medium carries one or more programs. When the above-mentioned one or more programs are executed by the DRAM chip repair device, the DRAM chip repair device: obtains the bad area address information of the DRAM chip; based on the bad area address information, masks the bad area units of the DRAM chip to generate a masking result; based on the masking result, sorts the good area units of the DRAM chip to generate a sorting result; and stores the sorting result to the DRAM chip to repair the DRAM chip.

[0104] Computer program code for performing the operations of the present application may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0105] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0106] The modules involved in the embodiments described in this application may be implemented by software or hardware, wherein the name of the module does not constitute a limitation on the unit itself in some cases.

[0107] The readable storage medium provided by the present application is a computer-readable storage medium, which stores computer-readable program instructions (i.e., computer programs) for executing the above-mentioned DRAM chip repair method, and can solve the technical problem that the DRAM chip has bad areas, resulting in the inaccessibility of the system chip. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided by the present application are the same as the beneficial effects of the DRAM chip repair method provided by the above-mentioned embodiment, and will not be repeated here.

[0108] The present application also provides a computer program product, including a computer program, which implements the steps of the above-mentioned DRAM chip repair method when executed by a processor.

[0109] The computer program product provided by the present application can solve the technical problem that the bad area of ​​the DRAM chip causes the system chip to be inaccessible. Compared with the prior art, the beneficial effects of the computer program product provided by the present application are the same as the beneficial effects of the DRAM chip repair method provided by the above embodiment, which will not be described in detail here.

[0110] The above descriptions are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect applications in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A method for repairing a DRAM chip, characterized in that: The method comprises: Get the bad area address information of DRAM chip; Based on the bad block address information, the bad block unit of the DRAM chip is shielded to generate a shielding result; Based on the shielding result, sorting the good area units of the DRAM chip to generate a sorting result; The sorting result is stored in the DRAM chip to repair the DRAM chip.

2. The method for repairing a DRAM chip according to claim 1, wherein: The step of obtaining the bad block address information of the DRAM chip includes: Configure the FGPA test platform required for the DRAM chip test; Based on the FGPA test platform, a DRAM chip memory first segment address space test is performed to generate a first test result; Based on the FGPA test platform, perform a global test of the DRAM chip memory unit to generate a second test result; Based on the first test result and the second test result, bad area address information of the DRAM chip is obtained.

3. The method for repairing a DRAM chip as claimed in claim 2, characterized in that: The step of shielding the bad block unit of the DRAM chip based on the bad block address information to generate a shielding result includes: Storing bad area address information in a shielded area of ​​the address storage area; Shielding bad area address information in the shielding area and generating a feedback result; A shielding result is generated based on the bad area address information and the feedback result.

4. The method for repairing a DRAM chip as claimed in claim 3, characterized in that: The step of sorting the good block units of the DRAM chip based on the shielding result to generate a sorting result comprises: Based on the shielding result, obtaining good area address information of the DRAM chip; Get the sorted storage area of ​​the address storage area; The good area address information is sorted in order, mapped from the starting position of the sorting storage area in sequence, and a sorting result is generated.

5. The method for repairing a DRAM chip as claimed in claim 4, characterized in that: The step of storing the sorting result in the DRAM chip to repair the DRAM chip includes: Storing the sorting result in a DRAM chip; Establishing a mapping relationship between the sorting result and the good zone unit; The DRAM chip is repaired by accessing the sorting result.

6. A DRAM chip, characterized in that: The DRAM chip is applied to the DRAM chip repair method as described in any one of claims 1 to 5; The DRAM chip comprises: a first storage area and a second storage area; the first storage area is used to store data information; the second storage area is a non-volatile storage area, used to store the sorting result and the shielding result of the first storage area.

7. A DRAM chip repair device, characterized in that: The DRAM chip repair device comprises: an information acquisition module and a sorting shielding module; The information acquisition module is used to obtain bad area address information of the DRAM chip; The sorting and shielding module is used to shield the bad area units of the DRAM chip based on the bad area address information to generate a shielding result; it is also used to sort the good area units of the DRAM chip based on the shielding result to generate a sorting result; it is also used to store the sorting result to the DRAM chip to repair the DRAM chip.

8. A DRAM chip repair device, characterized in that: The DRAM chip repair device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the DRAM chip repair method according to any one of claims 1 to 5.

9. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the DRAM chip repair method according to any one of claims 1 to 5 are implemented.

10. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a processor, the steps of the method for repairing a DRAM chip according to any one of claims 1 to 5 are implemented.

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