Built-in self-test circuit and memory

Abstract

The application relates to a built-in self-test circuit and a memory. The built-in self-test circuit comprises a storage array, a command / address generation module, a processing module and a repair module. After entering a self-test mode, the command / address generation module generates and sends internal test commands and internal test addresses according to a preset test mode. According to the internal test commands, the processing module writes preset data into the storage units corresponding to the internal test addresses in the storage array according to the preset test mode, and reads storage data from the storage units corresponding to the internal test addresses in the storage array; according to the comparison result of the storage data read each time and the preset data corresponding to the writing, a fault flag is generated and output. According to the fault flag, the repair module latches the internal test address corresponding to the current read storage data as an error address, and repairs the storage units corresponding to the error address after the self-test mode is exited. The application can realize internal automatic detection and automatic repair.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a built-in self-test circuit and a memory. Background Art

[0002] In DDR DRAM (double data rate synchronous dynamic random access memory), taking DDR5 as an example, after MRW (Mode Register Write) is enabled and three sets of guard keys are assigned, the DDR DRAM enters Mbist mode. The alert_n pin then automatically goes low. During self-test (tSelftest), the DDR DRAM automatically detects and records single-bit or multi-bit errors in the memory array. While existing DDR DRAM can detect errors, it cannot automatically repair the memory cells corresponding to the error addresses. Summary of the Invention

[0003] Based on this, it is necessary to provide a built-in self-test circuit and memory that can realize internal automatic detection and automatic repair.

[0004] In a first aspect, a built-in self-test circuit is provided, the built-in self-test circuit comprising:

[0005] Storage arrays;

[0006] A command / address generation module is used to generate and send internal test commands and internal test addresses according to a preset test mode after entering the self-test mode;

[0007] a processing module, connected to the command / address generation module and the storage array, respectively, and configured to receive the internal test command and the internal test address; write preset data to the storage unit corresponding to the internal test address in the storage array according to the preset test mode according to the internal test command, and read storage data from the storage unit corresponding to the internal test address in the storage array; and generate and output a fault flag based on a comparison result of the storage data read each time with the corresponding preset data written; the fault flag indicating whether there is a data error in the storage data currently being read;

[0008] A repair module is connected to the command / address generation module and the processing module respectively, and is used to latch the internal test address corresponding to the currently read storage data as an error address according to the fault flag, and repair the storage unit corresponding to the error address after exiting the self-test mode.

[0009] In one embodiment, the storage array includes M memory bank groups, each memory bank group includes N memory banks, where M and N are both positive integers; the preset data includes M*N preset sub-data, which correspond one-to-one to the M*N memory banks, and each preset sub-data includes P bits of target write data; the stored data includes M*N stored sub-data, which correspond one-to-one to the M*N memory banks, and each stored sub-data includes P bits of target read data, where P is a positive integer; and the processing module includes:

[0010] M*N judgment units are connected to the memory banks in the memory array in a one-to-one correspondence, each of the judgment units being configured to read a corresponding piece of storage sub-data from P pieces of storage cells corresponding to the internal test address in a corresponding piece of storage bank, and compare P bits of target read data in the storage sub-data with P bits of target write data in a corresponding piece of preset sub-data, bit by bit, to respectively generate and output P first comparison results corresponding to the P pieces of storage cells; wherein, if the target read data and the target write data are identical, the output first comparison result indicates that no data error exists in the corresponding storage cell; conversely, if the target read data and the target write data are different, the output first comparison result indicates that a data error exists in the corresponding storage cell;

[0011] M*N first compression units are connected to the M*N judgment units in a one-to-one correspondence; each first compression unit is used to obtain P first comparison results of P storage units in the corresponding storage bank and perform compression processing to obtain a second comparison result of the corresponding storage bank, where the second comparison result indicates whether there is a data error in the corresponding storage bank;

[0012] The second compression unit is connected to the M*N first compression units respectively, and is used to obtain and compress the second comparison results corresponding to the M*N storage bodies, generate and output the fault flag and storage body flag, and the storage body flag is used to indicate the storage body with data errors.

[0013] In one embodiment, the determining unit includes:

[0014] P XOR gates correspond one-to-one to the P bits of target read data in the corresponding storage sub-data and the P bits of target write data in the corresponding preset sub-data. The two input ends of each XOR gate are respectively used to receive one bit of the target read data read from the corresponding storage unit and one bit of the target write data written thereto, and the output end is used to output the first comparison result of the corresponding storage unit.

[0015] In one embodiment, the first compression unit comprises:

[0016] a compression engine, connected to the corresponding judgment unit, configured to receive the first comparison result of each storage unit in the corresponding storage bank and adopt a compression mode to obtain multi-bit intermediate data, wherein the multi-bit intermediate data carries information about whether there is a data error in the storage bank;

[0017] The auxiliary compression circuit is connected to the compression engine and is used to compress the multi-bit intermediate data into one-bit output data, and use the output data as the second comparison result of the corresponding storage body.

[0018] In one embodiment, when the compression engine outputs four-bit intermediate data, the auxiliary compression circuit includes:

[0019] two first NOR gates, each input end of which is connected to the compression engine respectively, and is used to receive corresponding one-bit intermediate data;

[0020] The first NAND gate has two input terminals connected one to one with the output terminals of the two first NOR gates, and an output terminal for outputting one bit of output data.

[0021] In one embodiment, the second compression unit comprises:

[0022] M block compression circuits corresponding one-to-one to the M memory bank groups, each block compression circuit being connected to the first compression unit corresponding to each memory bank in the corresponding memory bank group; each block compression circuit being configured to obtain the second comparison result of each memory bank in the corresponding memory bank group, perform compression and logical operations, and generate and output a third comparison result and a memory bank selection flag for the corresponding memory bank group, the memory bank selection flag being configured to indicate a memory bank in the corresponding memory bank group having a data error, and the third comparison result indicating whether a data error exists in the corresponding memory bank group;

[0023] a set compression circuit, connected to each of the M block compression circuits, configured to obtain the third comparison result of each memory bank group, perform compression and logic operations, and generate and output the fault flag and a memory bank group selection flag, wherein the memory bank group selection flag is used to indicate the memory bank group with data errors;

[0024] An output unit is connected to the block compression circuit and the set compression circuit respectively, and is used to determine the memory bank flag according to the memory bank selection flag and the memory bank group selection flag.

[0025] In one embodiment, the block compression circuit comprises:

[0026] a bank selection flag generating circuit, configured to obtain the second comparison result of each of the memory banks in the corresponding memory bank group, and when at least one of the memory banks in the corresponding memory bank group has a data error, select one of the memory banks with the data error in accordance with a preset order, and generate the bank selection flag, wherein the bank selection flag indicates a row address corresponding to the selected memory bank;

[0027] The block fault compression circuit is used to obtain the second comparison result of each memory bank in the corresponding memory bank group, and generate a third comparison result of the corresponding memory bank group according to the second comparison result of each memory bank in the corresponding memory bank group.

[0028] In one embodiment, when there are no data errors in the N storage bodies in the corresponding storage body group, the storage body selection flag indicates that the storage body of the storage row address is the storage body located at the front or the back of the preset order in the corresponding storage body group.

[0029] In one embodiment, when N=4, each of the memory bank groups includes a first memory bank, a second memory bank, a third memory bank, and a fourth memory bank; and the memory bank selection flag generation circuit includes:

[0030] a first NOT gate, an input end of which is used to receive a second comparison result of the first memory bank;

[0031] a second NOT gate, an input end of which is used to receive a second comparison result of the second memory bank;

[0032] a second NAND gate, having two input terminals connected to the output terminal of the first NOT gate and the output terminal of the second NOT gate respectively;

[0033] a third NAND gate, having a first input terminal for receiving the second comparison result of the third memory bank, and a second input terminal connected to the output terminal of the second NAND gate;

[0034] The fourth NAND gate has two input terminals connected to the output terminal of the first NAND gate and the output terminal of the third NAND gate respectively, and the output terminal of the fourth NAND gate cooperates with the output terminal of the second NAND gate to output the memory bank selection flag.

[0035] In one embodiment, the block fault compression circuit includes:

[0036] two second NOR gates, whose input ends are respectively used to receive the second comparison result of a corresponding one of the memory banks;

[0037] a fifth NAND gate, whose input terminals are respectively connected to the output terminals of the two second NOR gates;

[0038] The third NOT gate has an input end connected to the output end of the fifth NAND gate, and an output end for outputting the third comparison result of the memory bank group.

[0039] In one embodiment, the aggregate compression circuit includes:

[0040] a memory bank group selection flag generating circuit, configured to obtain the third comparison result of each of the memory bank groups, and when a data error exists in at least one of the memory bank groups, select one of the memory bank groups having the data error according to a preset order, and generate the memory bank group selection flag;

[0041] The collective fault compression circuit is configured to obtain the third comparison result of each of the memory bank groups and generate the fault flag according to the third comparison result of each of the memory bank groups.

[0042] In one embodiment, when there is no data error in any of the M memory bank groups, the memory bank group selection flag indicates the memory bank group that is located at the front or the back of the preset sequence.

[0043] In one embodiment, when M=8, the M memory bank groups include: a first memory bank group, a second memory bank group, a third memory bank group, a fourth memory bank group, a fifth memory bank group, a sixth memory bank group, a seventh memory bank group, and an eighth memory bank group; the memory bank group selection flag includes: a first memory bank selection flag, a second memory bank selection flag, and a third memory bank selection flag;

[0044] The memory bank group selection flag generating circuit includes: a fourth NOT gate, a fifth NOT gate, a sixth NOT gate, a seventh NOT gate, an eighth NOT gate, a ninth NOT gate, a tenth NOT gate, an eleventh NOT gate, a sixth NAND gate, a seventh NAND gate, an eighth NAND gate, a ninth NAND gate, a tenth NAND gate, an eleventh NAND gate, a twelfth NAND gate, a thirteenth NAND gate, a fourteenth NAND gate, a fifteenth NAND gate, a third NOR gate, a fourth NOR gate, a fifth NOR gate and a sixth NOR gate;

[0045] The input end of the fourth NOT gate is used to receive the third comparison result of the third memory bank group; the input end of the fifth NOT gate is used to receive the third comparison result of the fourth memory bank group; the input end of the sixth NOT gate is used to receive the third comparison result of the fifth memory bank group; the input end of the seventh NOT gate is used to receive the third comparison result of the sixth memory bank group; the input end of the eighth NOT gate is used to receive the third comparison result of the seventh memory bank group; the input end of the ninth NOT gate is used to receive the third comparison result of the eighth memory bank group; the first input end of the sixth NAND gate is connected to the output end of the fourth NAND gate, and the second input end of the sixth NAND gate is used to receive the third comparison result of the second memory bank group; the first input end of the seventh NAND gate is connected to the output end of the sixth NAND gate, and the input end of the seventh NAND gate is connected to the output end of the sixth NAND gate. the second input terminal of the NAND gate being connected to the output terminal of the fifth NOT gate; the first input terminal of the eighth NAND gate being connected to the output terminal of the seventh NAND gate, and the second input terminal of the eighth NAND gate being connected to the output terminal of the sixth NAND gate; the first input terminal of the ninth NAND gate being connected to the output terminal of the eighth NAND gate, and the second input terminal of the ninth NAND gate being connected to the output terminal of the seventh NAND gate; the first input terminal of the tenth NAND gate being connected to the output terminal of the ninth NAND gate, and the second input terminal of the tenth NAND gate being connected to the output terminal of the eighth NAND gate; the first input terminal of the eleventh NAND gate being connected to the output terminal of the tenth NAND gate, and the second input terminal of the eleventh NAND gate being connected to the output terminal of the ninth NAND gate, and the output terminal of the eleventh NAND gate being used to generate the first memory bank group selection flag;

[0046] The first input end of the third NOR gate is used to receive the third comparison result of the fifth memory bank group, and the second input end of the third NOR gate is used to receive the third comparison result of the sixth memory bank group; the input end of the tenth NOR gate is used to receive the third comparison result of the third memory bank group; the input end of the eleventh NOR gate is used to receive the third comparison result of the fourth memory bank group; the first input end of the sixth NOR gate is used to receive the third comparison result of the seventh memory bank group, and the second input end of the sixth NOR gate is used to receive the third comparison result of the eighth memory bank group; the twelfth NAND gate the first input terminal of the NAND gate is connected to the output terminal of the tenth NOT gate, the second input terminal of the twelfth NAND gate is connected to the output terminal of the eleventh NAND gate; the first input terminal of the thirteenth NAND gate is connected to the output terminal of the third NOR gate, the second input terminal of the thirteenth NAND gate is connected to the output terminal of the twelfth NAND gate; the first input terminal of the fourteenth NAND gate is connected to the output terminal of the thirteenth NAND gate, the second input terminal of the fourteenth NAND gate is connected to the output terminal of the sixth NOR gate, and the output terminal of the fourteenth NAND gate is used to generate the second memory bank group selection flag;

[0047] The first input terminal of the fourth NOR gate is used to receive the third comparison result of the fifth memory bank group, and the second input terminal of the fourth NOR gate is used to receive the third comparison result of the sixth memory bank group; the first input terminal of the fifth NOR gate is used to receive the third comparison result of the seventh memory bank group, and the second input terminal of the fifth NOR gate is used to receive the third comparison result of the eighth memory bank group; the first input terminal of the fifteenth NAND gate is connected to the output terminal of the fourth NOR gate, the second input terminal of the fifteenth NAND gate is connected to the output terminal of the fifth NOR gate, and the output terminal of the fifteenth NAND gate is used to generate the third memory bank group selection flag;

[0048] The collective fault compression circuit includes: a seventh NOR gate, an eighth NOR gate, a ninth NOR gate, a tenth NOR gate, an eleventh NOR gate, a sixteenth NAND gate and a seventeenth NAND gate;

[0049] The first input end of the seventh NOR gate is used to receive the third comparison result of the first memory bank group, and the second input end of the seventh NOR gate is used to receive the third comparison result of the second memory bank group; the first input end of the eighth NOR gate is used to receive the third comparison result of the third memory bank group, and the second input end of the eighth NOR gate is used to receive the third comparison result of the fourth memory bank group; the first input end of the ninth NOR gate is used to receive the third comparison result of the fifth memory bank group, and the second input end of the ninth NOR gate is used to receive the third comparison result of the sixth memory bank group; the first input end of the tenth NOR gate is used to receive the third comparison result of the seventh memory bank group, and the second input end of the tenth NOR gate is used to receive the third comparison result of the seventh memory bank group. The second input end of the NOR gate is used to receive the third comparison result of the eighth storage body group; the first input end of the sixteenth NAND gate is connected to the output end of the seventh NOR gate, and the second input end of the sixteenth NAND gate is connected to the output end of the eighth NOR gate; the first input end of the seventeenth NAND gate is connected to the output end of the ninth NOR gate, and the second input end of the seventeenth NAND gate is connected to the output end of the tenth NOR gate; the first input end of the eleventh NOR gate is connected to the output end of the sixteenth NAND gate, and the second input end of the eleventh NOR gate is connected to the output end of the seventeenth NAND gate, and the output end of the eleventh NOR gate is used to generate the fault flag.

[0050] In one embodiment, the repair module is further used to receive the storage body flag, latch the storage body flag when the fault flag indicates that there is a data error in the storage data currently being read, and repair the storage unit corresponding to the error address in the storage body indicated by the storage body flag after exiting the self-test mode.

[0051] In one embodiment, the command / address generation module includes:

[0052] a clock generating unit, configured to receive a self-test enable signal and generate and output a clock signal when the self-test enable signal is at a valid level;

[0053] A command generation unit, connected to the clock generation unit, for sequentially generating an activation command, a write command / read command, and a precharge command that meet the read / write operation timing requirements according to the clock signal;

[0054] The internal test address includes an internal test row address and an internal test column address;

[0055] The address generation unit is connected to the clock generation unit and the address generation unit respectively, and is used to generate an internal test row address according to the activation command and the clock signal, and to generate an internal test column address according to the write command / the read command and the clock signal.

[0056] In one embodiment, the command generation unit is further configured to receive a test mode signal; when the test mode signal is at a first level, indicate that the preset test mode is a row-priority test mode, and generate the internal test command according to a row-priority addressing mode; when the test mode signal is at a second level, indicate that the preset test mode is a column-priority test mode, and generate the internal test command according to a column-priority addressing mode;

[0057] The address generation unit is also used to receive a test mode signal; when the test mode signal is at a first level, it indicates that the preset test mode is a row-priority test mode, and generates the internal test address according to the row-priority addressing method; when the test mode signal is at a second level, it indicates that the preset test mode is a column-priority test mode, and generates the internal test address according to the column-priority addressing method.

[0058] In one embodiment, the repair module is connected to the address generation unit and the processing module to receive the fault flag, and is also connected to the address generation unit to receive the internal test row address or the internal test column address, and when the fault flag indicates that there is a data error in the storage data currently being read, the internal test row address or the internal test column address corresponding to the storage data currently being read is latched as an error address, and the storage cell row or storage cell column corresponding to the error address is repaired after the self-test mode is exited.

[0059] In one embodiment, the built-in self-test circuit further includes:

[0060] An alarm module is used to generate a test alarm signal according to the self-test enable signal and send the test alarm signal to the memory controller.

[0061] In one embodiment, the self-test enable signal switches to a valid level when the storage array enters a self-test mode defined by a protocol or a setup mode.

[0062] In a second aspect, a memory is provided, comprising the built-in self-test circuit provided in the first aspect.

[0063] The aforementioned built-in self-test circuit and memory include a memory array, a command / address generation module, a processing module, and a repair module. After entering self-test mode, the command / address generation module generates and sends internal test commands and internal test addresses according to a preset test pattern. The processing module then writes preset data to the memory cells corresponding to the internal test addresses in the memory array according to the internal test commands and the preset test pattern, and reads stored data from the memory cells corresponding to the internal test addresses in the memory array. Based on the comparison result of each read data with the corresponding written preset data, the processing module generates and outputs a fault flag indicating whether there are data errors in the currently read data, thereby achieving automatic detection within the chip. Based on the fault flag, the repair module latches the internal test address corresponding to the currently read data as an error address and repairs the memory cells corresponding to the error address after exiting self-test mode, thereby achieving automatic repair within the memory chip. This allows for automatic testing and repair during the production testing phase, effectively reducing chip production costs and improving chip yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0065] Figure 1 A schematic structural diagram of a built-in self-test circuit according to an embodiment;

[0066] Figure 2 A schematic structural diagram of a storage array and a processing module in a built-in self-test circuit according to an embodiment;

[0067] Figure 3 A schematic structural diagram of a judgment unit in a built-in self-test circuit according to an embodiment;

[0068] Figure 4 and Figure 5is a schematic structural diagram of a first compression unit in a built-in self-test circuit according to an embodiment;

[0069] Figure 6 is a schematic structural diagram of a second compression unit in a built-in self-test circuit according to an embodiment;

[0070] Figure 7 1. A schematic structural diagram of a block compression circuit in a built-in self-test circuit according to an embodiment;

[0071] Figure 8 A schematic structural diagram of a memory bank selection flag generating circuit in a built-in self-test circuit according to an embodiment;

[0072] Figure 9 1. A schematic structural diagram of a block fault compression circuit in a built-in self-test circuit according to an embodiment;

[0073] Figure 10 A schematic structural diagram of a collective compression circuit in a built-in self-test circuit according to an embodiment;

[0074] Figure 11 A schematic structural diagram of a memory bank group selection flag generating circuit in a built-in self-test circuit according to an embodiment;

[0075] Figure 12 A schematic structural diagram of a collective fault compression circuit in a built-in self-test circuit according to an embodiment;

[0076] Figure 13 A schematic structural diagram of a built-in self-test circuit according to another embodiment;

[0077] Figure 14 A schematic diagram of the structure of a command / address generation module in a built-in self-test circuit according to an embodiment;

[0078] Figure 15 is a structural diagram of a built-in self-test circuit according to another embodiment;

[0079] Figure 16 FIG. 4 is a structural diagram of a built-in self-test circuit according to another embodiment.

[0080] Description of reference numerals:

[0081] 10. Storage array, 20. Command / address generation module, 30. Processing module, 40. Repair module, 50. Alarm module;

[0082] 31. Judgment unit, 311. XOR gate;

[0083] 32. First compression unit, 321. Compression engine, 322. Auxiliary compression circuit, 3221. First NOR gate, 3222. First NAND gate;

[0084] 33. Second compression unit, 331. Block compression circuit, 3311. Bank selection flag generation circuit, 3312. Block fault compression circuit, 332. Aggregate compression circuit, 3321. Bank group selection flag generation circuit, 3322. Aggregate fault compression circuit, 333. Output unit. DETAILED DESCRIPTION

[0085] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0086] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0087] It will be understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor without departing from the scope of this application. The first resistor and the second resistor are both resistors, but they are not the same resistor.

[0088] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if there is transmission of electrical signals or data between the connected circuits, modules, units, etc.

[0089] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Furthermore, the term "and / or" as used in this specification includes any and all combinations of the relevant listed items.

[0090] Figure 1 FIG. 1 is a schematic diagram of a built-in self-test circuit according to an embodiment of the present invention. Figure 1As shown, the built-in self-test circuit includes a storage array 10, a command / address generation module 20, a processing module 30, and a repair module 40. The command / address generation module 20 is used to generate and send internal test commands and internal test addresses according to a preset test mode after entering the self-test mode. The processing module 30 is connected to the command / address generation module 20 and the storage array 10, respectively, and is used to receive the internal test commands and internal test addresses; write preset data to the storage cells corresponding to the internal test addresses in the storage array 10 according to the preset test mode based on the internal test commands, and read the storage data from the storage cells corresponding to the internal test addresses in the storage array 10; and generate and output a fault flag based on the comparison result of each read storage data with the corresponding written preset data. The fault flag indicates whether there is a data error in the currently read storage data. The repair module 40 is connected to the command / address generation module 20 and the processing module 30, respectively, and is used to latch the internal test address corresponding to the currently read storage data as an error address based on the fault flag, and repair the storage cell corresponding to the error address after exiting the self-test mode.

[0091] Memory array 10 includes multiple memory bank groups, each of which includes multiple memory banks, each of which includes multiple memory cells arranged in an array. Self-test mode allows the chip to automatically test the memory cells in memory array 10. Preset test modes include predefined test areas and test methods, such as the memory cells to be tested in memory array 10, the order in which each memory cell is tested, and the order in which operations are performed on each memory cell.

[0092] The internal test commands include an activation command for activating the row address corresponding to the storage cell, a write command for writing preset data into the storage cell, a read command for reading the data stored in the storage cell, and a precharge command, etc. The internal test address includes the row address and column address corresponding to the storage cell for writing preset data and reading the stored data, specifically including an internal test row address and an internal test column address. Since the repair of the storage array includes two repair methods, row repair and column repair, that is, it can be to replace the storage cells of an entire row or to replace the storage cells of an entire column, the address transmitted to the repair module 40 for latching is usually one of the row address or the column address, and it is not necessary to transmit the row address and the column address at the same time. A row address / column address corresponds to multiple storage cells respectively, that is, the error address is also one of the row address or the column address, corresponding to all the storage cells of a storage cell row or a storage cell column. As for whether to perform sampling row repair or column repair, the optimal repair method can be selected based on the statistics and calculation of the storage cells with data errors in the memory.

[0093] In the above embodiment, the built-in self-test circuit includes a memory array 10, a command / address generation module 20, a processing module 30, and a repair module 40. After entering self-test mode, the command / address generation module 20 generates and sends internal test commands and internal test addresses according to a preset test pattern. The processing module 30 then writes preset data to the memory cells corresponding to the internal test addresses in the memory array 10 according to the internal test commands and the preset test pattern, and reads the stored data from the memory cells corresponding to the internal test addresses in the memory array 10. Based on the comparison result of each read data with the corresponding written preset data, the processing module 30 generates and outputs a fault flag indicating whether there are data errors in the currently read data, thereby achieving automatic detection within the chip. Based on the fault flag, the repair module 40 latches the internal test address corresponding to the currently read data as an error address and repairs the memory cells corresponding to the error address after exiting self-test mode, thereby achieving automatic repair within the chip. This allows for automated testing and repair during the production test phase, effectively reducing chip production costs and improving chip yield.

[0094] In one embodiment, the memory array 10 includes M memory bank groups, each memory bank group including N memory banks. M and N are both positive integers. The preset data includes M*N preset sub-data, corresponding one-to-one to the M*N memory banks. Each preset sub-data includes P bits of target write data. The stored data includes M*N stored sub-data, corresponding one-to-one to the M*N memory banks. Each stored sub-data includes P bits of target read data. P is a positive integer.

[0095] Exemplarily, the memory array 10 is a dynamic random access memory (DRAM), in which one memory cell typically stores one bit of data. P bits of target write data are written to P memory cells of the same memory bank, and P bits of target read data are read from the P memory cells. M*N preset sub-data are written to N memory banks of an M memory bank group, i.e., written to M*N memory banks; and M*N stored sub-data are read from the M*N memory banks.

[0096] Figure 2 FIG. 1 is a structural diagram of a processing module according to an embodiment of the present invention. Figure 2As shown, in one embodiment, the processing module 30 includes M*N judgment units 31, M*N first compression units 32, and second compression units 33. The M*N judgment units 31 are connected to the memory banks 11 in the memory array 10 in a one-to-one correspondence. Each judgment unit 31 is configured to read a corresponding piece of storage sub-data from P memory cells corresponding to an internal test address in a corresponding memory bank, and compare the P bits of target read data in the storage sub-data with the P bits of target write data in a corresponding preset sub-data bit by bit, thereby generating and outputting P first comparison results corresponding to the P memory cells. If the target read data and the target write data are the same, the output first comparison result indicates that there is no data error in the corresponding memory cell. Conversely, if the target read data and the target write data are different, the output first comparison result indicates that there is a data error in the corresponding memory cell. The M*N first compression units 32 are connected to the M*N judgment units 31 in a one-to-one correspondence. Each first compression unit 32 is configured to obtain the first comparison result of each storage cell in the corresponding memory bank and perform compression processing to obtain the second comparison result of the corresponding memory bank. The second comparison result indicates whether there is a data error in the corresponding memory bank. The second compression unit 33 is connected to each of the M*N first compression units 32 and is configured to obtain the second comparison results corresponding to the M*N memory banks and perform compression, generating and outputting a fault flag and a memory bank flag. The memory bank flag is used to indicate a memory bank with a data error.

[0097] The internal test address corresponds to multiple memory cells. The internal test address includes an internal test row address and an internal test column address. The internal test row address and the internal test column address jointly select the memory cells to be read / written. First, all memory cells in the target row corresponding to the internal test row address are opened based on an activation command containing the internal test row address. Then, based on the internal test column address in the read / write command, the storage sub-data is read / written to the selected corresponding memory cells in the target row. For example, if an internal test address corresponds to P memory cells in the same memory bank, and each memory cell stores one bit of data, the judgment unit 31 selects the P memory cells corresponding to the internal test address from each memory cell in the corresponding memory bank and obtains the stored data from each of the P memory cells, thereby obtaining P bits of target read data, i.e., one storage sub-data. M*N judgment units 31 obtain M*N storage sub-data. Accordingly, the preset data written to the P memory cells is P bits of target write data, i.e., one preset sub-data. M*N judgment units 31 correspond to M*N storage sub-data.

[0098] The first comparison result for a storage cell indicates whether the storage cell has a data error. If a target readout bit of data in the storage cell is the same as the corresponding target write-in bit of data, the storage cell data is correct, i.e., there is no data error. If a target readout bit of data in the storage cell is different from the corresponding target write-in bit of data, a data error exists in the storage cell.

[0099] The second comparison result of a memory bank indicates whether the memory bank has a data error. If all memory cells have no data error, it means that the memory bank has no data error; if at least one memory cell has a data error, it means that the memory bank has a data error.

[0100] The fault flag indicates whether there are data errors in the storage array 10. If all memory banks 11 have no data errors, then the storage array 10 has no data errors, and the memory bank flag indicates a default memory bank in the storage array 10. If there are data errors in at least one memory bank 11, then the storage array 10 has a data error, and the memory bank flag indicates a memory bank 11 in the storage array 10 that has a data error.

[0101] In the above embodiment, the processing module 30 includes M*N judgment units 31, M*N first compression units 32, and second compression units 33. Each judgment unit 31 reads a corresponding piece of storage sub-data from P storage cells corresponding to an internal test address in a corresponding storage bank, and compares the P-bit target read data in the storage sub-data with the P-bit target write data in a corresponding preset sub-data bit by bit, generating and outputting P first comparison results corresponding to the P storage cells, thereby implementing automatic testing of the storage cells. Each first compression unit 32 first obtains the first comparison result of each storage cell in the corresponding storage bank and performs compression processing to obtain the second comparison result of the corresponding storage bank. The second compression unit 33 then obtains the second comparison results corresponding to the M*N storage banks and compresses them to generate and output a fault flag and a storage bank flag, thereby compressing the results of the automatic storage cell testing and reducing the amount of data.

[0102] Figure 3 FIG. 1 is a structural diagram of a judgment unit according to an embodiment of the present invention. Figure 3 As shown, optionally, the judgment unit 31 includes P XOR gates 311, which correspond one-to-one to the P-bit target read data in the corresponding storage sub-data and the P-bit target write data in the corresponding preset sub-data. The two input ends of each XOR gate 311 are respectively used to receive one bit of target read data read from a corresponding storage unit and one bit of target write data written thereto, and the output end is used to output the first comparison result of the corresponding storage unit.

[0103] For example, if the target read data bit received by an XOR gate 311 is the same as the target write data bit written to it, that is, the data received by the two input terminals of the XOR gate 311 are the same, then the output terminal of the XOR gate 311 outputs a low level representing data "0", indicating that there is no data error in the storage cell corresponding to the XOR gate 311. If the target read data bit received by an XOR gate 311 is different from the target write data bit written to it, that is, the data received by the two input terminals of the XOR gate 311 are different, then the output terminal of the XOR gate 311 outputs a high level representing data "1", indicating that there is a data error in the storage cell corresponding to the XOR gate 311.

[0104] Exemplarily, an internal test address corresponds to P storage cells in the same storage body, and P XOR gates 311 respectively receive one bit of target read data and one bit of corresponding target write data from a storage cell in the storage body corresponding to the judgment unit 31, and obtain the first comparison result of the corresponding storage cell, and a total of the first comparison results of the P storage cells in the storage body corresponding to the judgment unit 31 are obtained.

[0105] In the above embodiment, the judgment unit 31 includes P XOR gates 311, which correspond one-to-one to P bits of target read data and P bits of target write data, respectively. The two input ends of each XOR gate 311 are respectively used to receive one bit of target read data read from a corresponding storage cell and one bit of target write data written thereto, and the output end is used to output the first comparison result of the corresponding storage cell. This allows each judgment unit 31 to read one bit of target read data in each storage cell corresponding to the internal test address from a corresponding storage body and compare it with the corresponding one bit of target read data written thereto, thereby generating and outputting P first comparison results corresponding to the P storage cells.

[0106] Figure 4 FIG. 1 is a structural diagram of a first compression unit according to an embodiment of the present invention. Figure 4 As shown, optionally, the first compression unit 32 includes a compression engine 321 and an auxiliary compression circuit 322. The compression engine 321 is connected to the corresponding judgment unit 31 and is configured to receive the first comparison result of each storage unit in the corresponding storage bank and apply a compression mode to obtain multi-bit intermediate data. The multi-bit intermediate data carries information about whether the storage bank has data errors. The auxiliary compression circuit 322 is connected to the compression engine 321 and is configured to compress the multi-bit intermediate data into one-bit output data, and use the output data as the second comparison result of the corresponding storage bank.

[0107] In actual applications, a test engine for other test circuits is set up inside the chip, such as a circuit for testing and repairing fuse units before leaving the factory. Based on the need for repair, this test engine will use 32 bits as a group of repair units, so it is necessary to split 128 bits into 4 groups for separate compression. The group of units where the error occurs is determined based on the compression results to make corresponding modifications. In the above embodiment, the first compression unit 32 includes a compression engine 321 and an auxiliary compression circuit 322. The compression engine 321 first receives P first comparison results of P storage units in the corresponding storage body and adopts a compression mode to obtain multi-bit intermediate data. The auxiliary compression circuit 322 then compresses the multi-bit intermediate data into one-bit output data and uses the output data as the second comparison result of the corresponding storage body. In this way, the compression engines of other test circuits can be reused to reduce the overall chip space and implementation cost.

[0108] Exemplarily, the auxiliary compression circuit 322 includes at least one compression combination, each compression combination being used to compress 4-bit data into 1-bit data.

[0109] For example, compression engine 321 outputs 16 bits of intermediate data, with each 4 bits of intermediate data corresponding to a compression combination. In this case, auxiliary compression circuit 322 includes four compression combinations, each of which compresses 4 bits of data into 1 bit. Finally, a logical OR operation is performed on the outputs of the four compression combinations to obtain the second comparison result for the memory bank corresponding to first compression unit 32.

[0110] Figure 5 FIG. 1 is a schematic structural diagram of an auxiliary compression circuit according to an embodiment of the present invention. Figure 5 As shown, illustratively, when the compression engine 321 outputs four bits of intermediate data, the auxiliary compression circuit 322 includes two first NOR gates 3221 and a first NAND gate 3222. Each input of the two first NOR gates 3221 is connected to the compression engine 321, and the two first NOR gates 3221 are used to receive the corresponding one-bit of intermediate data. The two inputs of the first NAND gates 3222 are connected one-to-one to the outputs of the two first NOR gates 3221, and the outputs of the first NAND gates 3222 are used to output one bit of output data.

[0111] In the above embodiment, when the compression engine 321 outputs four-bit intermediate data, the auxiliary compression circuit 322 includes two first NOR gates 3221 and a first NAND gate 3222, which can compress the multi-bit intermediate data into one-bit output data and use the output data as the second comparison result of the corresponding storage body.

[0112] For details, please refer to Figure 3 ,if Figure 3If the first comparison result outputted from the output terminal of the XOR gate 311 is a high level indicating data "1", it indicates that a data error exists in the storage unit corresponding to the XOR gate 311; Figure 5 , the P first comparison results corresponding to the P storage units output by the P XOR gates 311 corresponding to a memory bank are input to the compression engine 321. When the first comparison result output by any XOR gate 311 is "1", the corresponding 1-bit intermediate data in the 4-bit intermediate data output by the compression engine 321 is output as "1". After the logic operation of the auxiliary compression circuit 322 (two NOR gates 3221 and one NAND gate 3222), the corresponding second comparison result output is also a high level "1", indicating that there is a data error in the corresponding memory bank; conversely, if the P first comparison results are all "0", the 4-bit intermediate data output by the compression engine 321 are also all "0". After the logic operation of the auxiliary compression circuit 322, the corresponding second comparison result output is a low level "0", indicating that there is no data error in the corresponding memory bank.

[0113] Figure 6 FIG. 1 is a schematic structural diagram of a second compression unit according to an embodiment of the present invention. Figure 6 As shown, optionally, the second compression unit 33 includes M block compression circuits 331, a collective compression circuit 332, and an output unit 333. The M block compression circuits 331 correspond one-to-one to the M memory bank groups, and each block compression circuit 331 is connected to the first compression unit 32 corresponding to each memory bank in the corresponding memory bank group. Each block compression circuit 331 is configured to obtain the second comparison result of each memory bank in the corresponding memory bank group, perform compression and logical operations, and generate and output a third comparison result and a memory bank selection flag for the corresponding memory bank group. The memory bank selection flag is used to indicate a memory bank in the corresponding memory bank group that has a data error, and the third comparison result indicates whether a data error exists in the corresponding memory bank group. The collective compression circuit 332 is connected to each of the M block compression circuits 331, and is configured to obtain the third comparison result of each memory bank group, perform compression and logical operations, and generate and output a fault flag and a memory bank group selection flag. The memory bank group selection flag is used to indicate a memory bank group that has a data error. The output unit 333 is connected to the block compression circuit 331 and the set compression circuit 332 respectively, and is used to determine the memory bank flag according to the memory bank selection flag and the memory bank group selection flag.

[0114] In the above embodiment, the second compression unit 33 includes M block compression circuits 331, a collective compression circuit 332, and an output unit 333. Each block compression circuit 331 first obtains the second comparison result of each memory bank in the corresponding memory bank group and performs compression and logical operations to generate and output the third comparison result and memory bank selection flag of the corresponding memory bank group. The collective compression circuit 332 then obtains the third comparison result of each memory bank group and performs compression and logical operations to generate and output a fault flag and a memory bank group selection flag. The output unit 333 finally determines the memory bank flag based on the memory bank selection flag and the memory bank group selection flag. By performing multi-level compression on the second comparison result of each memory bank, the amount of data is reduced, and the memory bank with data errors can be identified (the memory bank flag can be used to determine which memory bank in the specific memory bank group has the data error). In combination with the internal test address, a memory cell row or a memory cell column with data errors can be identified for repair.

[0115] Figure 7 FIG. 1 is a block compression circuit diagram according to an embodiment of the present invention. Figure 7 As shown, the block compression circuit 331 optionally includes a bank selection flag generation circuit 3311 and a block fault compression circuit 3312. The bank selection flag generation circuit 3311 is configured to obtain the second comparison result for each bank in the corresponding bank group and, when at least one bank in the corresponding bank group has a data error, select one of the banks with the data error in a preset order to generate a bank selection flag. The block fault compression circuit 3312 is configured to obtain the second comparison result for each bank in the corresponding bank group and, based on the second comparison results of each bank in the corresponding bank group, generate a third comparison result for the corresponding bank group.

[0116] In the above embodiment, the block compression circuit 331 includes a bank selection flag generation circuit 3311 and a block fault compression circuit 3312. The bank selection flag generation circuit 3311 obtains the second comparison result for each bank in the corresponding bank group. When at least one bank in the corresponding bank group has a data error, the block fault compression circuit 3312 selects one of the banks with the data error in a preset order and generates a bank selection flag. Based on the second comparison results for each bank in the corresponding bank group, the block fault compression circuit 3312 generates a third comparison result for the corresponding bank group to indicate whether a data error exists in the corresponding bank group. By combining the bank selection flag and the third comparison result, it is possible to determine whether a data error exists in the corresponding bank group. When at least one bank in the bank group has a data error, the bank with the data error in the bank group is identified and repaired.

[0117] Optionally, when there is no data error in N memory banks in the corresponding memory bank group, the memory bank selection flag indicates a memory bank that is located at the front or the back of a preset order in the corresponding memory bank group.

[0118] Since the third comparison result indicates whether there is a data error in the corresponding memory bank group, the memory bank selection flag indicates a memory bank without data error in the corresponding memory bank group, and the memory bank without data error will not be repaired.

[0119] Figure 8 FIG. 1 is a schematic structural diagram of a memory bank selection flag generating circuit in a built-in self-test circuit according to an embodiment of the present invention. Figure 8 As shown, illustratively, when N=4, each memory bank group includes a first memory bank, a second memory bank, a third memory bank, and a fourth memory bank. A memory bank selection flag generation circuit 3311 includes a first NOT gate 33111, a second NOT gate 33112, a second NAND gate 33113, a third NAND gate 33114, and a fourth NAND gate 33115. The input of the first NOT gate 33111 is used to receive the second comparison result of the first memory bank. The input of the second NOT gate 33112 is used to receive the second comparison result of the second memory bank. The two inputs of the second NAND gate 33113 are respectively connected to the output of the first NOT gate 33111 and the output of the second NOT gate 33112. The first input of the third NAND gate 33114 is used to receive the second comparison result of the third memory bank, and the second input of the third NAND gate 33114 is connected to the output of the first NOT gate 33111. Two input terminals of the fourth NAND gate 33115 are respectively connected to the output terminals of the first NOT gate 33111 and the third NAND gate 33114. The output terminals of the fourth NAND gate 33115 and the second NAND gate 33113 are used to output the bank selection flag Bank<1:0>.

[0120] When the second comparison result of the first memory bank indicates that there is a data error in the first memory bank, the input end of the first NOT gate 33111 receives a high-level signal indicating "1", and the output end of the first NOT gate 33111 outputs a low-level signal indicating "0". At this time, regardless of whether the second comparison result of the second memory bank, the second comparison result of the third memory bank, and the second comparison result of the fourth memory bank are high-level signals or low-level signals (i.e., whether there is a data error in the second memory bank, the third memory bank, and the fourth memory bank), the output end of the second NAND gate 33113 and the output end of the fourth NAND gate 33115 both output a high-level signal indicating "1". Bank <1> and Bank <0> The bank selection flag Bank<1:0> is 11, indicating that the data error in the first bank in the corresponding bank group is to be repaired. Therefore, when a data error exists in the first bank, the bank selection flag Bank<1:0> indicating the first bank is set to 11, regardless of whether other banks in the same bank group have data errors. Therefore, the first bank in the same bank group can be repaired first based on the bank selection flag Bank<1:0>=11, that is, the preset order (repair order) of the first bank is higher than that of the other three banks.

[0121] When the second comparison result for the first memory bank indicates that there is no data error in the first memory bank, the input of the first NOT gate 33111 receives a low-level signal representing "0," and the output of the first NOT gate 33111 outputs a high-level signal representing "1." At this time, the output of the second NAND gate 33113 and the output of the fourth NAND gate 33115 are both determined by the input value of the other input. If the second comparison result for the second memory bank indicates that there is a data error in the second memory bank, the input of the second NOT gate 33112 receives a high-level signal representing "1," and the output of the second NOT gate 33112 outputs a low-level signal representing "0." The two inputs of the second NAND gate 33113 receive a high-level signal representing "1" and a low-level signal representing "0," respectively, and the output of the second NAND gate 33113 outputs a high-level signal representing "1."

[0122] The second input end of the third NAND gate 33114 is connected to the output end of the second NOT gate 33112, and receives a low-level signal indicating "0". At this time, regardless of whether the second comparison result of the third memory bank and the second comparison result of the fourth memory bank are high-level signals or low-level signals (i.e., whether there is a data error in the third memory bank and the fourth memory bank), the output end of the third NAND gate 33114 outputs a high-level signal indicating "1". The two input ends of the fourth NAND gate 33115 receive the high-level signal indicating "1" and the high-level signal indicating "1" respectively, and the output end of the fourth NAND gate 33115 outputs a low-level signal indicating "0". Bank <1> and Bank <0> 1 and 0 respectively, and the bank selection flag Bank<1:0> is 10, indicating that the data error in the second bank in the corresponding bank group is to be repaired. Therefore, it can be seen that when there is no data error in the first bank and there is a data error in the second bank, regardless of whether there is a data error in the third and fourth banks in the same bank group, the bank selection flag Bank<1:0>=10 indicating the second bank is output. Therefore, based on the bank selection flag Bank<1:0>=10, when the first bank does not need to be repaired, the second bank in the same bank group is repaired first, that is, the preset order (repair order) of the second bank is higher than that of the other two banks.

[0123] When the second comparison result of the first memory bank indicates that there is no data error in the first memory bank and the second comparison result of the second memory bank indicates that there is no data error in the second memory bank, the input end of the first NOT gate 33111 and the input end of the second NOT gate 33112 both receive a low-level signal indicating "0", and the output end of the first NOT gate 33111 and the output end of the second NOT gate 33112 both output a high-level signal indicating "1". At this time, the output end of the second NAND gate 33113 outputs a low-level signal indicating "0", that is, Bank <1> is 0, and the output of the fourth NAND gate 33115 is determined by the input value of the other input terminal (the output of the third NAND gate 33114). The second input terminal of the third NAND gate 33114 is connected to the output terminal of the second NOT gate 33112 and receives a high-level signal indicating "1". At this time, the output of the third NAND gate 33114 is determined by the input value of the first input terminal, that is, the second comparison result of the third memory bank. At this time, if the first comparison result of the third memory bank indicates that there is a data error in the third memory bank, the first input terminal of the third NAND gate 33114 receives a high-level signal indicating "1", and the third NAND gate 33114 outputs a low-level signal indicating "0". The two input terminals of the fourth NAND gate 33115 receive a high-level signal indicating "1" and a low-level signal indicating "0", respectively, and the output terminal of the fourth NAND gate 33115 outputs a high-level signal indicating "1". Bank <0> =1, and the bank selection flag Bank<1:0> is 01, indicating that the data error in the third bank in the corresponding bank group is to be repaired. Therefore, it can be seen that when there are no data errors in the first and second banks and there is a data error in the third bank, regardless of whether there is a data error in the fourth bank in the same bank group, the bank selection flag Bank<1:0> indicating the third bank is output as 01. Therefore, based on the bank selection flag Bank<1:0>=01, when neither the first nor the second bank needs to be repaired, the third bank in the same bank group is repaired first, i.e., the preset order (repair order) of the third bank is higher than that of the fourth bank.

[0124] When the second comparison result of the first memory bank, the second comparison result of the second memory bank, and the second comparison result of the third memory bank respectively indicate that there is no data error in the first memory bank, the second memory bank, and the third memory bank, the input end of the first NOT gate 33111 and the input end of the second NOT gate 33112 both receive a low-level signal indicating "0", the first input end of the third NAND gate 33114 receives a low-level signal indicating "0", the output end of the first NOT gate 33111 and the output end of the second NOT gate 33112 both output a high-level signal indicating "1", and the output end of the third NAND gate 33114 outputs a high-level signal indicating "1". At this time, the output end of the second NAND gate 33113 and the output end of the fourth NAND gate 33115 both output a low-level signal indicating "0", i.e., Bank <1> and Bank <0> are all 0, the bank selection flag Bank<1:0> is 00, indicating that the data error in the fourth bank in the corresponding bank group is to be repaired. Therefore, it can be seen that when there is no data error in the first bank, the second bank, and the third bank, regardless of whether there is a data error in the fourth bank in the same bank group, the bank selection flag Bank<1:0>=00 indicating the fourth bank is output, so that according to the bank selection flag Bank<1:0>=00, when no other banks need to be repaired, the fourth bank in the same bank group is repaired, that is, the repair order of the fourth bank is the lowest. When there is no data error in all banks (that is, when the second comparison results corresponding to several banks are all low-level signals), the bank selection flag Bank<1:0>=00 defaults to indicating that the last bank in the preset order (the fourth bank) is to be repaired.

[0125] In the above embodiment, when N=4, the memory bank selection flag generating circuit 3311 includes a first NOT gate 33111, a second NOT gate 33112, a second NAND gate 33113, a third NAND gate 33114 and a fourth NAND gate 33115, which can be used to select one of the memory banks with data errors in a preset order when there is a data error in at least one memory bank in the corresponding memory bank group.

[0126] Figure 9 FIG. 1 is a schematic diagram showing the structure of a block fault compression circuit in a built-in self-test circuit according to an embodiment of the present invention. Figure 9As shown, block fault compression circuit 3312 exemplarily includes two second NOR gates 33121, a fifth NAND gate 33122, and a third NOT gate 33123. The inputs of the two second NOR gates 33121 are each configured to receive the second comparison result of a corresponding memory bank. The input of the fifth NAND gate 33122 is connected to the outputs of the two second NOR gates 33121. The input of the third NOT gate 33123 is connected to the output of the fifth NAND gate 33122, and the output of the third NOT gate 33123 is configured to output the third comparison result of the memory bank group.

[0127] In the above embodiment, the block fault compression circuit 3312 includes two second NOR gates 33121, a fifth NAND gate 33122 and a third NOT gate 33123, which can generate a third comparison result of the corresponding storage body group based on the second comparison results of each storage body in the corresponding storage body group to indicate whether there is a data error in the corresponding storage body group.

[0128] Figure 10 FIG. 1 is a schematic diagram showing the structure of a collective compression circuit in a built-in self-test circuit according to an embodiment of the present invention. Figure 10 As shown, the aggregate compression circuit 332 optionally includes a bank group selection flag generation circuit 3321 and an aggregate fault compression circuit 3322. The bank group selection flag generation circuit 3321 is configured to obtain the third comparison result of each bank group and, when at least one bank group has a data error, select one of the bank groups with the data error in a preset order to generate a bank group selection flag. The aggregate fault compression circuit 3322 is configured to obtain the third comparison result of each bank group and generate a fault flag based on the third comparison result of each bank group.

[0129] In the above embodiment, the aggregate compression circuit 332 includes a bank group selection flag generation circuit 3321 and a aggregate fault compression circuit 3322. When data errors occur in at least one bank group, the bank group selection flag generation circuit 3321 selects one of the bank groups with data errors according to a preset order and generates a bank group selection flag to indicate which of the M bank groups has the data error. The aggregate fault compression circuit 3322 generates a fault flag based on the third comparison results for each bank group to indicate whether data errors exist in the currently read storage data. By combining the bank group selection flag and the fault flag, it is possible to determine whether data errors exist in all the storage data currently being read from the storage array. Furthermore, when data errors occur in at least one bank group, a bank group in the storage array 10 with data errors can be identified for repair.

[0130] Optionally, when no data error exists in any of the M memory bank groups, the memory bank group selection flag indicates a memory bank group that is located at the front or the back of the preset sequence.

[0131] Since the fault flag indicates whether there is a data error in the currently read storage data, when there is no storage bank with data error in the storage array 10, the storage bank without data error will not be repaired.

[0132] As an example, when M=8, the M memory bank groups include: a first memory bank group, a second memory bank group, a third memory bank group, a fourth memory bank group, a fifth memory bank group, a sixth memory bank group, a seventh memory bank group, and an eighth memory bank group. The memory bank group selection flag includes: a first memory bank selection flag, a second memory bank selection flag, and a third memory bank selection flag.

[0133] Figure 11 FIG. 1 is a schematic structural diagram of a memory bank selection flag generating circuit in a built-in self-test circuit according to an embodiment of the present invention. Figure 11As shown, illustratively, the memory bank group selection flag generation circuit 3321 includes: a fourth NOT gate 33211a, a fifth NOT gate 33211b, a sixth NOT gate 33211c, a seventh NOT gate 33211d, an eighth NOT gate 33211e, a ninth NOT gate 33211f, a tenth NOT gate 33211g, an eleventh NOT gate 33211h, a sixth NAND gate 33212a, a seventh NAND gate 33212b, an eighth NAND gate 33212c, a ninth NAND gate 33212d, a tenth NAND gate 33212e, an eleventh NAND gate 33212f, a twelfth NAND gate 33212g, a thirteenth NAND gate 33212h, a fourteenth NAND gate 33212i, a fifteenth NAND gate 33212j, a third NOR gate 33213a, a seventh NAND gate 33213b, an eighth NAND gate 33213c, a ninth NAND gate 33213d, a tenth NAND gate 33213e, an eleventh NAND gate 33213f, a twelfth NAND gate 33213g, a thirteenth NAND gate 33213h, a fourteenth NAND gate 33213i, a fifteenth NAND gate 33213j, and a third NOR gate 33213 The fourth NOT gate 33213a, the fourth NOR gate 33213b, the fifth NOR gate 33213c and the sixth NOR gate 33213d; the input end of the fourth NOT gate 33211a is used to receive the third comparison result of the third memory bank group; the input end of the fifth NOT gate 33211b is used to receive the third comparison result of the fourth memory bank group; the input end of the sixth NOT gate 33211c is used to receive the third comparison result of the fifth memory bank group; the input end of the seventh NOT gate 33211d is used to receive the third comparison result of the sixth memory bank group; the input end of the eighth NOT gate 33211e is used to receive the third comparison result of the seventh memory bank group; the input end of the ninth NOT gate 33211f is used to receive the third comparison result of the seventh memory bank group. The third comparison result of the eighth memory bank group; the first input end of the sixth NAND gate 33212a is connected to the output end of the fourth NOT gate 33211a, and the second input end of the sixth NAND gate 33212a is used to receive the third comparison result of the second memory bank group; the first input end of the seventh NAND gate 33212b is connected to the output end of the sixth NAND gate, and the second input end of the seventh NAND gate 33212b is connected to the output end of the fifth NOT gate 33211b; the first input end of the eighth NAND gate 33212c is connected to the output end of the seventh NAND gate, and the second input end of the eighth NAND gate 33212c is connected to the output end of the sixth NOT gate; the ninth NAND gate 33 The first input terminal of the NAND gate 33212d is connected to the output terminal of the eighth NAND gate, and the second input terminal of the ninth NAND gate 33212d is connected to the output terminal of the seventh NAND gate; the first input terminal of the tenth NAND gate 33212e is connected to the output terminal of the ninth NAND gate 33212d, and the second input terminal of the tenth NAND gate 33212e is connected to the output terminal of the eighth NAND gate; the first input terminal of the eleventh NAND gate 33212f is connected to the output terminal of the tenth NAND gate 33212e, and the second input terminal of the eleventh NAND gate 33212f is connected to the output terminal of the ninth NAND gate, and the output terminal of the eleventh NAND gate 33212f is used to generate a first memory bank group selection flag BG <0> ;The first input end of the third NOR gate 33213a is used to receive the third comparison result of the fifth memory bank group, and the second input end of the third NOR gate 33213a is used to receive the third comparison result of the sixth memory bank group; the input end of the tenth NOR gate 33211g is used to receive the third comparison result of the third memory bank group; the input end of the eleventh NOR gate 33211h is used to receive the third comparison result of the fourth memory bank group; the first input end of the sixth NOR gate 33213d is used to receive the third comparison result of the seventh memory bank group, and the second input end of the sixth NOR gate 33213d is used to receive the third comparison result of the eighth memory bank group; the first input end of the twelfth NAND gate 33212g is connected to the tenth NOR gate 33 211g, the second input terminal of the twelfth NAND gate 33212g is connected to the output terminal of the eleventh NAND gate 33211h; the first input terminal of the thirteenth NAND gate 33212h is connected to the output terminal of the third NOR gate 33213a, the second input terminal of the thirteenth NAND gate 33212h is connected to the output terminal of the twelfth NAND gate 33212g; the first input terminal of the fourteenth NAND gate 33212i is connected to the output terminal of the thirteenth NAND gate 33212h, the second input terminal of the fourteenth NAND gate 33212i is connected to the output terminal of the sixth NOR gate 33213d, and the output terminal of the fourteenth NAND gate 33212i is used to generate a second memory bank group selection flag BG <1> ;

[0134] The first input end of the fourth NOR gate 33213b is used to receive the third comparison result of the fifth memory bank group, and the second input end of the fourth NOR gate 33213b is used to receive the third comparison result of the sixth memory bank group; the first input end of the fifth NOR gate 33213c is used to receive the third comparison result of the seventh memory bank group, and the second input end of the fifth NOR gate 33213c is used to receive the third comparison result of the eighth memory bank group; the first input end of the fifteenth NAND gate 33212j is connected to the output end of the fourth NOR gate 33213b, the second input end of the fifteenth NAND gate 33212j is connected to the output end of the fifth NOR gate 33213c, and the output end of the fifteenth NAND gate 33212j is used to generate a third memory bank group selection flag BG <2> .

[0135] Figure 12 FIG. 1 is a schematic diagram showing the structure of a collective fault compression circuit in a built-in self-test circuit according to an embodiment of the present invention. Figure 12As shown, for example, the collective fault compression circuit 3322 includes: a seventh NOR gate 33213e, an eighth NOR gate 33213f, a ninth NOR gate 33213g, a tenth NOR gate 33213h, an eleventh NOR gate 33213i, a sixteenth NAND gate 33212k, and a seventeenth NAND gate 33212l; a first input end of the seventh NOR gate 33213e is used to receive the third comparison result of the first memory bank group, and a second input end of the seventh NOR gate 33213e is used to receive the second memory bank group. the third comparison result of the group; the first input end of the eighth NOR gate 33213f is used to receive the third comparison result of the third memory bank group, and the second input end of the eighth NOR gate 33213f is used to receive the third comparison result of the fourth memory bank group; the first input end of the ninth NOR gate 33213g is used to receive the third comparison result of the fifth memory bank group, and the second input end of the ninth NOR gate 33213g is used to receive the third comparison result of the sixth memory bank group; the first input end of the tenth NOR gate 33213h is used to receive the third comparison result of the seventh memory bank group, and the second input end of the tenth NOR gate 33213h is used to receive the third comparison result of the eighth memory bank group; the first input end of the sixteenth NAND gate 33212k is connected to the output end of the seventh NOR gate 33213e, and the second input end of the sixteenth NAND gate 33212k is connected to the output end of the eighth NOR gate 33213f; the first input end of the seventeenth NAND gate 33212l is connected to the ninth NOR gate 33 213g is connected to the output end of the 17th NAND gate 33212l, the second input end of the 17th NAND gate 33212l is connected to the output end of the 10th NOR gate 33213h; the first input end of the 11th NOR gate 33213i is connected to the output end of the 16th NAND gate 33212k, the second input end of the 11th NOR gate 33213i is connected to the output end of the 17th NAND gate 33212l, and the output end of the 11th NOR gate 33213i is used to generate the fault flag FAIL_BG_EN.

[0136] Figure 13 FIG. 1 is a structural diagram of a built-in self-test circuit according to another embodiment of the present invention. Figure 13 As shown, exemplarily, the repair module is further used to receive a storage body flag (for example: BG<2:0> and Bank<1:0>), latch the storage body flag when the fault flag indicates that there is a data error in the storage data currently being read, and repair the storage unit corresponding to the error address in the storage body indicated by the storage body flag (for example: BG<2:0> is 111, Bank<1:0> is 10, indicating the second storage body in the first storage body group) after exiting the self-test mode.

[0137] Figure 14FIG. 1 is a schematic diagram of a command / address generation module in a built-in self-test circuit according to an embodiment of the present invention. Figure 14 As shown, in one embodiment, the command / address generation module 20 includes a clock generation unit 21, a command generation unit 22, and an address generation unit 23. The clock generation unit 21 is used to receive a self-test enable signal and generate and output a clock signal when the self-test enable signal is at a valid level. The command generation unit 22 is connected to the clock generation unit 21 and is used to sequentially generate an activation command, a write command / read command, and a precharge command that meet the read / write operation timing requirements according to the clock signal. The internal test address includes an internal test row address and an internal test column address; the address generation unit 23 is connected to the clock generation unit 21 and the address generation unit 22, respectively, and is used to generate an internal test row address according to the activation command and the clock signal, and to generate an internal test column address according to the write command / read command and the clock signal.

[0138] In the above embodiment, the command / address generation module 20 includes a clock generation unit 21, a command generation unit 22 and an address generation unit 23. The clock generation unit 21 first generates and outputs a clock signal when the self-test enable signal is at a valid level. The command generation unit 22 then generates an activation command, a write command / read command and a precharge command that meet the read / write operation timing requirements in sequence according to the clock signal. The address generation unit 23 finally generates an internal test row address according to the activation command and the clock signal, and generates an internal test column address according to the write command / read command and the clock signal, thereby achieving the generation and sending of internal test commands and internal test addresses (including internal test row addresses and internal test column addresses) according to the preset test mode after entering the self-test mode.

[0139] Optionally, the command generation unit 22 is also used to receive a test mode signal; when the test mode signal is at a first level, it indicates that the preset test mode is a row-priority test mode, and generates an internal test command according to a row-priority addressing method; when the test mode signal is at a second level, it indicates that the preset test mode is a column-priority test mode, and generates an internal test command according to a column-priority addressing method.

[0140] The address generation unit 23 is also used to receive a test mode signal; when the test mode signal is at a first level, it indicates that the preset test mode is a row-priority test mode, and generates an internal test address according to a row-priority addressing method; when the test mode signal is at a second level, it indicates that the preset test mode is a column-priority test mode, and generates an internal test address according to a column-priority addressing method.

[0141] In row-first test mode, the command generation unit 22 generates the following internal test commands: an activate command, a write command / read command, and a precharge command for the first row and first column; an activate command, a write command / read command, and a precharge command for the first row and first column; and an activate command, a write command / read command, and a precharge command for the first row and first column. The time required to test the entire memory chip in row-first test mode is shown in Table 1 below.

[0142] Table 1. Row-first test mode

[0143]

[0144] Referring to Table 1, after entering the test mode (Load test mode), first, determine a column address (i.e., determine a column of the memory array), and test the memory cells corresponding to each row address (each row) in this column in sequence (first perform a write data operation), until all memory cells in this column are tested (see sequence number 2 in Table 1). Secondly, test the next column according to the process of the previous step until all columns are tested (see sequence number 3 in Table 1). Then, determine a column address (determine a column of the memory array), and test the memory cells corresponding to each row address (each row) in this column in sequence (perform a read data operation), until all memory cells in this column are tested (see sequence number 4 in Table 1). Finally, test the next column according to the process of the previous step until all columns are read.

[0145] In the test sequence corresponding to Table 1, the clock cycle corresponding to a column address in each row of the memory array is: tRCD+tWR+tRP; where tRCD (RAS to CASDelay) is the delay time for the memory row address to be transferred to the column address; tWR (Write Recovery Time) is the write recovery delay, that is, the delay between writing data and the precharge command; tRP (Row Precharge Time) is the row address precharge time. Table 1 takes tRCD of 5, tRP of 5, and tWR of 6 as an example. For a row number of 2 16 For a storage array with 64 columns, after the operation of sequence number 2 in Table 1, the number of columns in the storage array can be obtained. 16 The clock cycle corresponding to a column address of a row can be (5+6+5)*2 16 =1048576; according to the operation of sequence number 3 in Table 1, all columns are tested and 2 in the storage array are 16 The clock cycle corresponding to the 64 column addresses of a row is 1048576*64=67108864, and the corresponding time consumed is 335.54432ms. After the operation of No. 4 in Table 1, the number of columns in the storage array can be obtained. 16The clock cycle corresponding to one column address of each row is (5+6+5)*216=1048576. After all columns are tested according to the operation of sequence number 5 in Table 1, the clock cycle corresponding to the 64 column addresses of the 216 rows in the storage array is 1048576*64=67108864, and the corresponding time consumed is 335.54432 ms.

[0146] In column-first test mode, command generation unit 22 generates the following internal test commands: an activate command, a write / read command, and a precharge command for the first row; an activate command, a write / read command, and a precharge command for the second row; and an activate command, a write / read command, and a precharge command for the third row. The time required to test an entire memory chip in column-first test mode is shown in Table 2 below.

[0147] Table 2. Column-first test mode

[0148]

[0149] Referring to Table 2, after entering the test mode (Load test mode), first, determine a row address (determine a row of the storage array), and test the storage cells corresponding to each column address (each column) in this row in turn (first perform a write data operation) until all storage cells in this row are tested (see sequence number 2 in Table 2). Secondly, test the next row according to the process of the previous step until all rows are written (see sequence number 3 in Table 2). Thirdly, determine a row address (determine a row of the storage array), and test the storage cells corresponding to each column address (each column) in this row in turn (perform a read data operation) until all storage cells in this row are tested (see sequence number 4 in Table 2). Then, test the next row according to the process of the previous step until all rows are read (see sequence number 5 in Table 2). Finally, repeat all the above steps to complete the read of all rows in another storage cell (see sequence number 6 in Table 2).

[0150] Under the test sequence corresponding to Table 2, the clock cycle corresponding to reading consecutive column addresses in each row of the memory array is: tRCD + tCCD * number of columns + tWR + tRP; among them, tRCD (RAS to CASDelay) is the delay time for transferring the memory row address to the column address; tCCD is an important event in DRAM architecture and bandwidth, which is the delay time for transferring between adjacent memory column addresses; tWR (Write Recovery Time) is the write recovery delay, that is, the delay write recovery time after writing data to the precharge command; tRP (Row Precharge Time) is the row address precharge time.

[0151] Table 2 takes tRCD of 5, tRP of 5, tWR of 6, and tCCD of 4 as an example. 15 For a memory array with 63 columns, after the operation of sequence number 2 in Table 2, the clock cycles corresponding to all column addresses corresponding to each row in the memory array can be 5+4*63+6+5=268, and the corresponding consumption time is 0.0013ms; after the operation of sequence number 3 in Table 2, all rows are written, and the memory array has 2 15 The clock cycle corresponding to the 63 column addresses of a row is 267*2 15 =8781824, the corresponding time consumed is 43.75ms; after the operation of No. 4 in Table 2, it can be obtained that the clock cycle corresponding to all column addresses corresponding to each row in the storage array is 5+4*63+6+5=268; after the operation of No. 5 in Table 2, all rows are read, and 2 in the storage array are 15 The clock cycles corresponding to the 63 column addresses of a row are 268*215=8781824, and the corresponding time consumed is 43.75. Operation No. 6 in Table 2: Repeat all the above steps to complete the reading of all rows of another storage unit, which consumes about 87.50ms.

[0152] Exemplarily, the command generation unit 22 and the address generation unit 23 are both further configured to receive a self-test enable signal, and are in a working state when the self-test enable signal is at a valid level, and are in a non-working state when the self-test enable signal is at an invalid level.

[0153] Figure 15 FIG. 1 is a structural diagram of a built-in self-test circuit according to another embodiment of the present invention. Figure 15 As shown, in one embodiment, the repair module 40 is connected to the processing module 30 for receiving a fault flag. The repair module 40 is also connected to the address generation unit 23 for receiving an internal test row address or an internal test column address, and when the fault flag indicates that there is a data error in the currently read storage data, the internal test row address or the internal test column address corresponding to the currently read storage data is latched as an error address, and the storage cell row or storage cell column corresponding to the error address is repaired after the self-test mode is exited.

[0154] Figure 16 FIG. 1 is a structural diagram of a built-in self-test circuit according to another embodiment of the present invention. Figure 16 As shown, in one embodiment, the built-in self-test circuit further includes an alarm module 50. The alarm module 50 is configured to generate a test alarm signal according to the self-test enable signal and send the test alarm signal to the memory controller.

[0155] In one embodiment, the self-test enable signal switches to a valid level when the memory array enters a self-test mode defined by a protocol or a setup mode.

[0156] Based on the same inventive concept, a memory is also provided, which includes the built-in self-test circuit provided by any of the above embodiments.

[0157] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0158] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0159] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A built-in self-test circuit, characterized in that: The built-in self-test circuit comprises: Storage arrays; A command / address generation module is used to generate and send internal test commands and internal test addresses according to a preset test mode after entering the self-test mode; a processing module, connected to the command / address generation module and the storage array, respectively, and configured to receive the internal test command and the internal test address; write preset data to the storage unit corresponding to the internal test address in the storage array according to the preset test mode according to the internal test command, and read storage data from the storage unit corresponding to the internal test address in the storage array; and generate and output a fault flag based on a comparison result of the storage data read each time with the corresponding preset data written; the fault flag indicating whether there is a data error in the storage data currently being read; a repair module, connected to the command / address generation module and the processing module respectively, for latching the internal test address corresponding to the currently read storage data as an error address according to the fault flag, and repairing the storage unit corresponding to the error address after exiting the self-test mode; The storage array includes M memory bank groups, each of which includes N memory banks, where M and N are both positive integers; the preset data includes M*N preset sub-data, which correspond one-to-one to the M*N memory banks, and each preset sub-data includes P-bit target write data; the stored data includes M*N stored sub-data, which correspond one-to-one to the M*N memory banks, and each stored sub-data includes P-bit target read data, where P is a positive integer; and the processing module includes: M*N judgment units are connected to the memory banks in the memory array in a one-to-one correspondence, each of the judgment units being configured to read a corresponding piece of storage sub-data from P pieces of storage cells corresponding to the internal test address in a corresponding piece of storage bank, and compare P bits of target read data in the storage sub-data with P bits of target write data in a corresponding piece of preset sub-data, bit by bit, to respectively generate and output P first comparison results corresponding to the P pieces of storage cells; wherein, if the target read data and the target write data are identical, the output first comparison result indicates that no data error exists in the corresponding storage cell; conversely, if the target read data and the target write data are different, the output first comparison result indicates that a data error exists in the corresponding storage cell; M*N first compression units are connected to the M*N judgment units in a one-to-one correspondence; each first compression unit is used to obtain P first comparison results of P storage units in the corresponding storage bank and perform compression processing to obtain a second comparison result of the corresponding storage bank, where the second comparison result indicates whether there is a data error in the corresponding storage bank; The second compression unit is connected to the M*N first compression units respectively, and is used to obtain and compress the second comparison results corresponding to the M*N storage bodies, generate and output the fault flag and storage body flag, and the storage body flag is used to indicate the storage body with data errors.

2. The built-in self-test circuit according to claim 1, wherein: The judging unit includes: P XOR gates correspond one-to-one to the P bits of target read data in the corresponding storage sub-data and the P bits of target write data in the corresponding preset sub-data. The two input ends of each XOR gate are respectively used to receive one bit of the target read data read from the corresponding storage unit and one bit of the target write data written thereto, and the output end is used to output the first comparison result of the corresponding storage unit.

3. The built-in self-test circuit according to claim 1, wherein: The first compression unit comprises: a compression engine, connected to the corresponding judgment unit, configured to receive the first comparison result of each storage unit in the corresponding storage bank and adopt a compression mode to obtain multi-bit intermediate data, wherein the multi-bit intermediate data carries information about whether there is a data error in the storage bank; The auxiliary compression circuit is connected to the compression engine and is used to compress the multi-bit intermediate data into one-bit output data, and use the output data as the second comparison result of the corresponding storage body.

4. The built-in self-test circuit according to claim 3, wherein: When the compression engine outputs four-bit intermediate data, the auxiliary compression circuit includes: two first NOR gates, each input end of which is connected to the compression engine respectively, and is used to receive corresponding one-bit intermediate data; The first NAND gate has two input terminals connected one to one with the output terminals of the two first NOR gates, and an output terminal for outputting one bit of output data.

5. The built-in self-test circuit according to claim 1, wherein: The second compression unit comprises: M block compression circuits corresponding one-to-one to the M memory bank groups, each block compression circuit being connected to the first compression unit corresponding to each memory bank in the corresponding memory bank group; each block compression circuit being configured to obtain the second comparison result of each memory bank in the corresponding memory bank group, perform compression and logical operations, and generate and output a third comparison result and a memory bank selection flag for the corresponding memory bank group, the memory bank selection flag being configured to indicate a memory bank in the corresponding memory bank group having a data error, and the third comparison result indicating whether a data error exists in the corresponding memory bank group; a set compression circuit, connected to each of the M block compression circuits, configured to obtain the third comparison results of the M memory bank groups, perform compression and logic operations, and generate and output the fault flag and a memory bank group selection flag, wherein the memory bank group selection flag is used to indicate the memory bank group with data errors; An output unit is connected to the block compression circuit and the set compression circuit respectively, and is used to determine the memory bank flag according to the memory bank selection flag and the memory bank group selection flag.

6. The built-in self-test circuit according to claim 5, wherein: The block compression circuit comprises: a bank selection flag generating circuit, configured to obtain the second comparison result of each of the memory banks in the corresponding memory bank group, and when at least one of the memory banks in the corresponding memory bank group has a data error, select one of the memory banks having the data error in accordance with a preset order to generate the bank selection flag; The block fault compression circuit is used to obtain the second comparison result of each memory bank in the corresponding memory bank group, and generate a third comparison result of the corresponding memory bank group according to the second comparison result of each memory bank in the corresponding memory bank group.

7. The built-in self-test circuit according to claim 6, wherein: When there is no data error in any of the N memory banks in the corresponding memory bank group, the memory bank selection flag indicates the memory bank that is located at the front or the back of the preset order in the memory bank group.

8. The built-in self-test circuit according to claim 7, wherein: When N=4, each of the memory bank groups includes a first memory bank, a second memory bank, a third memory bank, and a fourth memory bank; The memory bank selection flag generation circuit includes: a first NOT gate, an input end of which is used to receive a second comparison result of the first memory bank; a second NOT gate, an input end of which is used to receive a second comparison result of the second memory bank; a second NAND gate, having two input terminals connected to the output terminal of the first NOT gate and the output terminal of the second NOT gate respectively; a third NAND gate, having a first input terminal for receiving the second comparison result of the third memory bank, and a second input terminal connected to the output terminal of the second NAND gate; The fourth NAND gate has two input terminals connected to the output terminal of the first NAND gate and the output terminal of the third NAND gate respectively, and the output terminal of the fourth NAND gate cooperates with the output terminal of the second NAND gate to output the memory bank selection flag.

9. The built-in self-test circuit according to claim 8, wherein: The block fault compression circuit comprises: two second NOR gates, whose input ends are respectively used to receive the second comparison result of a corresponding one of the memory banks; a fifth NAND gate, whose input terminals are respectively connected to the output terminals of the two second NOR gates; The third NOT gate has an input end connected to the output end of the fifth NAND gate, and an output end for outputting the third comparison result of the memory bank group.

10. The built-in self-test circuit according to claim 5, wherein: The collective compression circuit comprises: a memory bank group selection flag generating circuit, configured to obtain the third comparison result of each of the memory bank groups, and when a data error exists in at least one of the memory bank groups, select one of the memory bank groups having the data error according to a preset order, and generate the memory bank group selection flag; The collective fault compression circuit is configured to obtain the third comparison result of each of the memory bank groups and generate the fault flag according to the third comparison result of each of the memory bank groups.

11. The built-in self-test circuit according to claim 10, wherein: When there is no data error in any of the M memory bank groups, the memory bank group selection flag indicates the memory bank group that is located at the front or the back of the preset sequence.

12. The built-in self-test circuit according to claim 11, wherein: When M=8, the M memory bank groups include: a first memory bank group, a second memory bank group, a third memory bank group, a fourth memory bank group, a fifth memory bank group, a sixth memory bank group, a seventh memory bank group, and an eighth memory bank group; the memory bank group selection flag includes: a first memory bank selection flag, a second memory bank selection flag, and a third memory bank selection flag; The memory bank group selection flag generating circuit includes: a fourth NOT gate, a fifth NOT gate, a sixth NOT gate, a seventh NOT gate, an eighth NOT gate, a ninth NOT gate, a tenth NOT gate, an eleventh NOT gate, a sixth NAND gate, a seventh NAND gate, an eighth NAND gate, a ninth NAND gate, a tenth NAND gate, an eleventh NAND gate, a twelfth NAND gate, a thirteenth NAND gate, a fourteenth NAND gate, a fifteenth NAND gate, a third NOR gate, a fourth NOR gate, a fifth NOR gate and a sixth NOR gate; The input end of the fourth NOT gate is used to receive the third comparison result of the third memory bank group; the input end of the fifth NOT gate is used to receive the third comparison result of the fourth memory bank group; the input end of the sixth NOT gate is used to receive the third comparison result of the fifth memory bank group; the input end of the seventh NOT gate is used to receive the third comparison result of the sixth memory bank group; the input end of the eighth NOT gate is used to receive the third comparison result of the seventh memory bank group; the input end of the ninth NOT gate is used to receive the third comparison result of the eighth memory bank group; the first input end of the sixth NAND gate is connected to the output end of the fourth NAND gate, and the second input end of the sixth NAND gate is used to receive the third comparison result of the second memory bank group; the first input end of the seventh NAND gate is connected to the output end of the sixth NAND gate, and the input end of the seventh NAND gate is connected to the output end of the sixth NAND gate. the second input terminal of the NAND gate being connected to the output terminal of the fifth NOT gate; the first input terminal of the eighth NAND gate being connected to the output terminal of the seventh NAND gate, and the second input terminal of the eighth NAND gate being connected to the output terminal of the sixth NAND gate; the first input terminal of the ninth NAND gate being connected to the output terminal of the eighth NAND gate, and the second input terminal of the ninth NAND gate being connected to the output terminal of the seventh NAND gate; the first input terminal of the tenth NAND gate being connected to the output terminal of the ninth NAND gate, and the second input terminal of the tenth NAND gate being connected to the output terminal of the eighth NAND gate; the first input terminal of the eleventh NAND gate being connected to the output terminal of the tenth NAND gate, and the second input terminal of the eleventh NAND gate being connected to the output terminal of the ninth NAND gate, and the output terminal of the eleventh NAND gate being used to generate the first memory bank group selection flag; The first input end of the third NOR gate is used to receive the third comparison result of the fifth memory bank group, and the second input end of the third NOR gate is used to receive the third comparison result of the sixth memory bank group; the input end of the tenth NOR gate is used to receive the third comparison result of the third memory bank group; the input end of the eleventh NOR gate is used to receive the third comparison result of the fourth memory bank group; the first input end of the sixth NOR gate is used to receive the third comparison result of the seventh memory bank group, and the second input end of the sixth NOR gate is used to receive the third comparison result of the eighth memory bank group; the twelfth NAND gate the first input terminal of the NAND gate is connected to the output terminal of the tenth NOT gate, the second input terminal of the twelfth NAND gate is connected to the output terminal of the eleventh NAND gate; the first input terminal of the thirteenth NAND gate is connected to the output terminal of the third NOR gate, the second input terminal of the thirteenth NAND gate is connected to the output terminal of the twelfth NAND gate; the first input terminal of the fourteenth NAND gate is connected to the output terminal of the thirteenth NAND gate, the second input terminal of the fourteenth NAND gate is connected to the output terminal of the sixth NOR gate, and the output terminal of the fourteenth NAND gate is used to generate the second memory bank group selection flag; The first input terminal of the fourth NOR gate is used to receive the third comparison result of the fifth memory bank group, and the second input terminal of the fourth NOR gate is used to receive the third comparison result of the sixth memory bank group; the first input terminal of the fifth NOR gate is used to receive the third comparison result of the seventh memory bank group, and the second input terminal of the fifth NOR gate is used to receive the third comparison result of the eighth memory bank group; the first input terminal of the fifteenth NAND gate is connected to the output terminal of the fourth NOR gate, the second input terminal of the fifteenth NAND gate is connected to the output terminal of the fifth NOR gate, and the output terminal of the fifteenth NAND gate is used to generate the third memory bank group selection flag; The collective fault compression circuit includes: a seventh NOR gate, an eighth NOR gate, a ninth NOR gate, a tenth NOR gate, an eleventh NOR gate, a sixteenth NAND gate and a seventeenth NAND gate; The first input end of the seventh NOR gate is used to receive the third comparison result of the first memory bank group, and the second input end of the seventh NOR gate is used to receive the third comparison result of the second memory bank group; the first input end of the eighth NOR gate is used to receive the third comparison result of the third memory bank group, and the second input end of the eighth NOR gate is used to receive the third comparison result of the fourth memory bank group; the first input end of the ninth NOR gate is used to receive the third comparison result of the fifth memory bank group, and the second input end of the ninth NOR gate is used to receive the third comparison result of the sixth memory bank group; the first input end of the tenth NOR gate is used to receive the third comparison result of the seventh memory bank group, and the second input end of the tenth NOR gate is used to receive the third comparison result of the seventh memory bank group. The second input end of the NOR gate is used to receive the third comparison result of the eighth storage body group; the first input end of the sixteenth NAND gate is connected to the output end of the seventh NOR gate, and the second input end of the sixteenth NAND gate is connected to the output end of the eighth NOR gate; the first input end of the seventeenth NAND gate is connected to the output end of the ninth NOR gate, and the second input end of the seventeenth NAND gate is connected to the output end of the tenth NOR gate; the first input end of the eleventh NOR gate is connected to the output end of the sixteenth NAND gate, and the second input end of the eleventh NOR gate is connected to the output end of the seventeenth NAND gate, and the output end of the eleventh NOR gate is used to generate the fault flag.

13. The built-in self-test circuit according to claim 1, wherein: The repair module is also used to receive the storage body flag, latch the storage body flag when the fault flag indicates that there is a data error in the storage data currently being read, and repair the storage unit corresponding to the error address in the storage body indicated by the storage body flag after exiting the self-test mode.

14. The built-in self-test circuit according to any one of claims 1 to 13, characterized in that: The command / address generation module includes: a clock generating unit, configured to receive a self-test enable signal and generate and output a clock signal when the self-test enable signal is at a valid level; A command generation unit, connected to the clock generation unit, for sequentially generating an activation command, a write command / read command, and a precharge command that meet the read / write operation timing requirements according to the clock signal; The internal test address includes an internal test row address and an internal test column address; The address generation unit is connected to the clock generation unit and the command generation unit respectively, and is used to generate an internal test row address according to the activation command and the clock signal, and to generate an internal test column address according to the write command / the read command and the clock signal.

15. The built-in self-test circuit according to claim 14, wherein: The command generation unit is further configured to receive a test mode signal; when the test mode signal is at a first level, indicate that the preset test mode is a row-priority test mode, and generate the internal test command in a row-priority addressing manner; When the test mode signal is at the second level, indicating that the preset test mode is a column priority test mode, and generating the internal test command according to a column priority addressing mode; The address generation unit is also used to receive a test mode signal; when the test mode signal is at a first level, it indicates that the preset test mode is a row-priority test mode, and generates the internal test address according to the row-priority addressing method; when the test mode signal is at a second level, it indicates that the preset test mode is a column-priority test mode, and generates the internal test address according to the column-priority addressing method.

16. The built-in self-test circuit according to claim 14, wherein: The repair module is connected to the processing module and is used to receive the fault flag. It is also connected to the address generation unit and is used to receive the internal test row address or the internal test column address. When the fault flag indicates that there is a data error in the storage data currently being read, the internal test row address or the internal test column address corresponding to the storage data currently being read is latched as an error address, and the storage cell row or storage cell column corresponding to the error address is repaired after the self-test mode is exited.

17. The built-in self-test circuit according to claim 14, wherein: The built-in self-test circuit further includes: An alarm module is used to generate a test alarm signal according to the self-test enable signal and send the test alarm signal to the memory controller.

18. The built-in self-test circuit according to claim 14, wherein: The self-test enable signal switches to a valid level when the storage array enters a self-test mode defined by a protocol or a setting mode.

19. A memory, characterized in that: The memory comprises a built-in self-test circuit as claimed in any one of claims 1 to 18.

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