Laminated chip inductor and preparation method thereof

Abstract

The invention belongs to the field of electronic components, and particularly discloses a laminated chip inductor and a preparation method thereof.The laminated chip inductor comprises a laminated body and an external electrode; the laminated body comprises a coil conductor area and a medium insulation area which are arranged in a laminated manner; the dielectric insulation region comprises a dielectric layer; the coil conductor area comprises a dielectric layer and a coil conductor which are stacked; the number of the dielectric layers in the coil conductor area is not less than two; the dielectric layer of at least one coil conductor area contains bubbles. According to the laminated chip inductor, the bubbles are introduced into the dielectric layer in the coil conductor area, so that the quality factor Q of the laminated chip inductor is larger than 13, and the self-harmonic frequency SRF is larger than 3800 MHz; furthermore, the mechanical strength and the dielectric property of the laminated chip inductor can be controlled by adjusting the diameter and the porosity of the bubbles in the dielectric insulation area and the coil conductor area.

Description

Technical Field

[0001] The invention belongs to the field of electronic components, and in particular relates to a laminated chip inductor and a preparation method thereof. Background Art

[0002] In recent years, with the widespread application of wireless communication technology (5G), the demand for miniaturized, low-loss, and high-performance multilayer chip inductors has increased dramatically.

[0003] At present, the dielectric layer (or ceramic body) widely used in chip inductors is mainly a "glass + ceramic" system, and the dielectric constant is generally around 5 to 6. Generally, when the dielectric constant of the "glass + ceramic" system is low, it can effectively reduce the parasitic capacitance of the inductor in the high-frequency working circuit, reduce impedance delay and power loss. Miniaturized multilayer chip inductor products are prone to low quality factor Q value and low self-resonant frequency SRF value due to the large dielectric constant. The current common solution is to adjust the formula of the "glass + ceramic" system to reduce the dielectric constant. However, the test cycle for adjusting the formula is long and has great limitations. It is easy to cause a sharp increase in the production defect rate and a significant decrease in the strength value due to the boron element. There are also attempts to reduce the dielectric constant by introducing epoxy resin to fill the pores in the ceramic components. However, the epoxy resin filling process is relatively complicated, and the sintering porosity is too high (>30%). For the "glass + ceramic" system, its strength value is also significantly reduced. Summary of the invention

[0004] In order to overcome the technical problems of low quality factor Q value and low self-resonant frequency SRF value of the multilayer chip inductor in the above-mentioned prior art, one of the objectives of the present invention is to provide a multilayer chip inductor, which introduces bubbles into the dielectric layer of the coil conductor area to improve the quality factor Q value and self-resonant frequency SRF value of the multilayer chip inductor.

[0005] A second object of the present invention is to provide a method for preparing a multilayer chip inductor.

[0006] A third object of the present invention is to provide an electronic product.

[0007] In order to achieve the above object, the technical solution adopted by the present invention is:

[0008] The first aspect of the present invention provides a laminated chip inductor, comprising a laminate and an external electrode; the laminate comprises a coil conductor area and a dielectric insulation area arranged in a laminated manner; the dielectric insulation area comprises a dielectric layer; the coil conductor area comprises a dielectric layer and a coil conductor arranged in a laminated manner; the number of dielectric layers in the coil conductor area is not less than two; and at least one dielectric layer in the coil conductor area contains bubbles.

[0009] The principle of the laminated chip inductor in the present invention to improve the quality factor Q value and the self-resonant frequency SRF value by introducing bubbles into the dielectric layer of the coil conductor area is as follows:

[0010] The quality factor Q is determined by the following formula:

[0011]

[0012] Where: w: power frequency when the circuit resonates;

[0013] R: circuit equivalent resistance;

[0014] C: circuit parasitic capacitance;

[0015] The self-resonant frequency SRF is determined by the following formula:

[0016]

[0017] Where: L: inductance value;

[0018] C: circuit parasitic capacitance;

[0019] Due to the coil conductor, a large amount of parasitic capacitance will be generated during use. The parasitic capacitance is affected by the coil conductor design and the dielectric constant of the dielectric layer.

[0020]

[0021] Where: C: circuit parasitic capacitance;

[0022] ε: dielectric constant of dielectric layer;

[0023] k: electrostatic force constant;

[0024] S: area directly opposite to the coil conductor;

[0025] d: thickness of dielectric layer;

[0026] When bubbles exist in the dielectric layer, the dielectric constant of the bubbles is 1. According to the mixing rule of dielectric constants of different materials, the dielectric constant ε of the interlayer dielectric layer decreases, thereby reducing the parasitic capacitance of the multilayer chip inductor design. When the parasitic capacitance decreases, the quality factor Q and the self-resonant frequency SRF are improved. Therefore, the present invention can improve the quality factor Q value and the self-resonant frequency SRF value of the multilayer chip inductor by introducing bubbles into the dielectric layer of the coil conductor area.

[0027] In some embodiments of the present invention, the dielectric layer of the dielectric insulating region does not contain any bubbles.

[0028] In some embodiments of the present invention, the number of the dielectric layers in the dielectric insulating region is not less than two, and at least one dielectric layer in the dielectric insulating region contains bubbles.

[0029] Unless otherwise specified, the "bubble-containing dielectric layer" in the present invention refers to all dielectric layers containing bubbles in the laminate (including the coil conductor area and the dielectric insulation area). The "bubble-free dielectric layer" in the present invention refers to all dielectric layers without bubbles in the laminate (including the coil conductor area and the dielectric insulation area).

[0030] In some embodiments of the present invention, in the coil conductor area, the dielectric layer containing bubbles is located in the middle area of ​​the stack. The present invention provides a dielectric layer containing bubbles in the middle area of ​​the stack, and the magnetic flux lines all pass through the coil conductor area, and the dielectric constant reduction effect can be maximized.

[0031] In some embodiments of the present invention, in all the dielectric layers containing bubbles in the coil conductor region, the bubble diameter and porosity of each dielectric layer are the same.

[0032] In some embodiments of the present invention, among all the dielectric layers containing bubbles in the coil conductor region, the bubble diameter and porosity of each dielectric layer are different.

[0033] In some embodiments of the present invention, the bubbles are regular closed spheres. In some embodiments of the present invention, the bubbles contain air. The dielectric constant of air is 1. The bubbles in the dielectric layer can reduce the overall dielectric constant of the dielectric layer, reduce the parasitic capacitance of the coil conductor design, and improve the Q value and self-resonant frequency. The bubbles are actually formed by the gas between the gaps between the ceramic particles during the sintering of the laminate, which is difficult to escape, and form closed pores. In order to maintain the minimum surface area of ​​the bubbles, the bubbles should be closed and close to a spherical shape.

[0034] In some embodiments of the present invention, the coil conductor is a spiral coil conductor.

[0035] In some embodiments of the present invention, the medium layer containing bubbles includes at least two thin medium layers; at least one of the thin medium layers contains bubbles. In some embodiments of the present invention, when the number of the thin medium layers containing bubbles is at least two, the porosity and bubble diameter of the at least two thin medium layers containing bubbles may be the same or different.

[0036] In some embodiments of the present invention, the diameter of the bubble is 2 to 25 μm. In some preferred embodiments of the present invention, the diameter of the bubble is 2 to 20 μm. In some specific embodiments of the present invention, the diameter of the bubble can be 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, 18 μm, 19 μm or 20 μm. When the bubble diameter is less than 2 μm, the bubbles are very likely to form new large bubbles due to surface tension and other effects during the sintering process, and it is impossible to stably prepare products with a bubble diameter of less than 2 μm. This results in uncontrollable porosity, and the Q value performance will be more dispersed. When the bubble diameter is too large, on the one hand, it will cause a sharp deterioration in the bending resistance of the laminated chip inductor product. When conducting a bending test, larger bubbles are prone to form stress concentration here and form a fracture source. On the other hand, a larger bubble diameter may cause the upper and lower layers of the conductor coil to be connected and fail.

[0037] In some embodiments of the present invention, the porosity of the dielectric layer containing bubbles is 0.5-35%. In some preferred embodiments of the present invention, the porosity of the dielectric layer containing bubbles is 0.5-30%. In some specific embodiments of the present invention, the porosity of the dielectric layer containing bubbles can be 0.5%, 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19%, 20%, 21%, 22%, 23%, 24%, 25%, 26%, 27%, 28%, 29% or 30%. When the porosity is too low, the dielectric constant between the dielectric layers is not significantly reduced, and the effect on the parasitic capacitance value is small. When the porosity is too high, there are more holes inside the coil, and it is very easy to form bubbles through or form larger bubbles during the sintering process. The production process is difficult to control, and there is also a risk of failure of the bending resistance.

[0038] In some embodiments of the present invention, the average porosity of the dielectric layer in the coil conductor area is not lower than the average porosity of the dielectric layer in the dielectric insulation area. When the average porosity of each dielectric layer in the coil conductor area and the dielectric insulation area meets this condition, it is beneficial to improve the bending strength of the obtained laminated chip inductor. The improvement of the quality factor Q value and the self-resonant frequency SRF value is mainly affected by the parasitic capacitance of the coil conductor area. When the porosity of the dielectric layer of the laminate is relatively high, the volume of air accounts for a high proportion, and the dielectric constant value decreases more significantly. If the average porosity of the dielectric layer in the coil conductor area is higher than that in the dielectric insulation area, there are more magnetic flux lines passing through the coil conductor area. At this time, it is believed that most of the bubbles in the laminate are involved in reducing the dielectric parameters; and if the average porosity of the dielectric layer in the dielectric insulation area is higher than that in the coil conductor area, on the one hand, the magnetic flux lines are not all passed through, wasting part of the bubbles, and on the other hand, most of the bubbles exist in the dielectric insulation area, close to the surface of the laminate, and when the inductor is subjected to stress, the stress is preferentially concentrated on the surface of the laminated chip inductor product, and it is more likely to break the product.

[0039] In some embodiments of the present invention, the dielectric layer containing bubbles contains 60-95% SiO2 by mass; in some specific embodiments of the present invention, the mass percentage of SiO2 in the dielectric layer containing bubbles can be selected from 60%, 61%, 62%, 63%, 64%, 65%, 66%, 67%, 68%, 69%, 70%, 71%, 72%, 73%, 74%, 75%, 76%, 77%, 78%, 79%, 80%, 81%, 82%, 83%, 84%, 85%, 86%, 87%, 88%, 89%, 90%, 91%, 92%, 93%, 94% or 95%.

[0040] In some embodiments of the present invention, the medium layer containing bubbles contains SiO2 with a particle size of x, 2μm<x≤20μm; in some embodiments of the present invention, the medium layer containing bubbles contains SiO2 with a particle size of x, 2μm<x≤10μm; in some specific embodiments of the present invention, the particle size of SiO2 in the medium layer containing bubbles is 2.01μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm or 20μm.

[0041] In the dielectric layer containing bubbles, different SiO2 particle sizes and contents will result in pores of different sizes and different porosities after sintering. When the SiO2 content exceeds 60%, a molten state with a higher viscosity will be formed during the sintering process, and bubbles will be difficult to escape.

[0042] In some embodiments of the present invention, the dielectric constant of the dielectric layer containing bubbles is 4-6; in some specific embodiments of the present invention, the dielectric constant of the dielectric layer containing bubbles is 4, 4.5, 5, 5.5 or 6.

[0043] In some embodiments of the present invention, the medium layer containing bubbles contains 5-40% by mass of a sintering aid; in some specific embodiments of the present invention, the mass percentage of the sintering aid in the medium layer containing bubbles can be 5%, 6%, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19%, 20%, 21%, 22%, 23%, 24%, 25%, 26%, 27%, 28%, 29%, 30%, 31%, 32%, 33%, 34%, 35%, 36%, 37%, 38%, 39% or 40%.

[0044] The present invention does not limit the sintering aid in the dielectric layer containing bubbles. A commercially available sintering aid or a sintering aid commonly used in the art can be used. In some embodiments of the present invention, the sintering aid in the dielectric layer containing bubbles is a compound of at least one element selected from K, Na, Ca, Mg, B, Al, Fe, and Zr. In some preferred embodiments of the present invention, the sintering aid in the dielectric layer containing bubbles is an oxide of at least one element selected from K, Na, Ca, Mg, B, Al, Fe, and Zr. In some embodiments of the present invention, the sintering aid in the dielectric layer containing bubbles includes B2O3, K2O, and Al2O3; in some embodiments of the present invention, the sintering aid in the dielectric layer containing bubbles is a mixture of B2O3, K2O, and Al2O3 in a mass ratio of 1: (0.8-1.2): (2-3).

[0045] In some embodiments of the present invention, the medium layer without bubbles has at least one of the following characteristics:

[0046] (b1) the dielectric layer contains SiO2 in a mass percentage of y, 20%≤y<60%;

[0047] (b2) the dielectric layer contains SiO2 with a particle size of 0.1 to 5 μm;

[0048] (b3) the dielectric constant of the dielectric layer is 4 to 10;

[0049] (b4) the dielectric layer contains a sintering aid in a mass percentage of z, 40%<z≤80%; the sintering aid is a compound of at least one element selected from K, Na, Ca, Mg, B, Al, Fe, and Zr;

[0050] In some specific embodiments of the present invention, the mass percentage of SiO2 in the dielectric layer without bubbles can be 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55% or 59.9%. The particle size of SiO2 in the dielectric layer without bubbles can be 0.1μm, 0.2μm, 0.3μm, 0.4μm, 0.5μm, 1μm, 1.5μm, 1.6μm, 1.7μm, 1.8μm, 1.9μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm or 5μm. The mass percentage of the sintering aid in the dielectric layer without bubbles can be 40.01%, 45%, 50%, 55%, 60%, 65%, 70%, 75% or 80%.

[0051] In some embodiments of the present invention, the medium layer without bubbles has at least one of the following characteristics:

[0052] (c1) the dielectric layer contains 60-95% by mass of SiO2;

[0053] (c2) the dielectric layer contains SiO2 with a particle size of 0.1 to 2 μm;

[0054] (c3) the dielectric constant of the dielectric layer is 4 to 10;

[0055] (c4) The dielectric layer contains a sintering aid in an amount of 5 to 40% by mass; the sintering aid is a compound of at least one element selected from K, Na, Ca, Mg, B, Al, Fe, and Zr.

[0056] In some specific embodiments of the present invention, the mass percentage of SiO2 in the dielectric layer without bubbles can be 60%, 65%, 70%, 75%, 80%, 85%, 90% or 95%. The particle size of SiO2 in the dielectric layer without bubbles can be 0.1μm, 0.2μm, 0.3μm, 0.4μm, 0.5μm, 1μm, 1.5μm, 1.6μm, 1.7μm, 1.8μm, 1.9μm or 2μm. The mass percentage of the sintering aid in the dielectric layer without bubbles can be 5%, 10%, 15%, 20%, 25%, 30%, 35% or 40%.

[0057] The present invention does not limit the sintering aid in the dielectric layer without bubbles. A commercially available sintering aid or a sintering aid commonly used in the art can be used. In some embodiments of the present invention, the sintering aid in the dielectric layer without bubbles is a compound of at least one element selected from K, Na, Ca, Mg, B, Al, Fe, and Zr. In some preferred embodiments of the present invention, the sintering aid in the dielectric layer without bubbles is an oxide of at least one element selected from K, Na, Ca, Mg, B, Al, Fe, and Zr. In some embodiments of the present invention, the sintering aid in the dielectric layer without bubbles includes B2O3, K2O, and Al2O3; in some embodiments of the present invention, the sintering aid in the dielectric layer without bubbles is a mixture of B2O3, K2O, and Al2O3 in a mass ratio of 1: (0.8-1.2): (2-3). The sintering aid in the dielectric layer without bubbles of the present invention can be the same as or different from the sintering aid in the dielectric layer containing bubbles.

[0058] In some embodiments of the present invention, the dielectric constant of the dielectric layer without bubbles is 4 to 10; in some embodiments of the present invention, the dielectric constant of the dielectric layer without bubbles can be 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, 8.5, 9, 9.5 or 10.

[0059] In the present invention, the types of raw materials (silicon dioxide, sintering aid, etc.) for preparing the dielectric layer containing bubbles and the dielectric layer without bubbles can be the same or different. Whether the dielectric layer contains bubbles is mainly controlled by the content and particle size of silicon dioxide in the preparation raw materials.

[0060] The second aspect of the present invention provides a method for preparing the multilayer chip inductor provided in the first aspect of the present invention, comprising the following steps:

[0061] S1: grinding the raw materials for preparing the dielectric layer containing bubbles and the raw materials for preparing the dielectric layer without bubbles separately to form films, thereby obtaining a membrane sheet;

[0062] S2: preparing a coil conductor on a membrane used in a coil conductor area;

[0063] S3: stacking and sintering to obtain the stacked body;

[0064] S4: forming external electrodes at both ends of the stacked body to obtain the stacked chip inductor.

[0065] In some embodiments of the present invention, raw materials for preparing the medium layer containing bubbles include glass ceramic powder A, a dispersant, a binder, and a solvent.

[0066] In some embodiments of the present invention, the glass ceramic powder A includes silicon dioxide and a sintering aid. The mass percentage of silicon dioxide in the glass ceramic powder A is 60% to 95%, and the mass percentage of the sintering aid is 5% to 40%.

[0067] In some embodiments of the present invention, raw materials for preparing the bubble-free dielectric layer include glass ceramic powder B, a dispersant, a binder, and a solvent.

[0068] In some embodiments of the present invention, the glass ceramic powder B includes silicon dioxide and a sintering aid. The mass percentage of silicon dioxide in the glass ceramic powder is 20-60%, but not 60%; the mass percentage of the sintering aid is 40-80%, but not 40%.

[0069] In some embodiments of the present invention, the glass ceramic powder B includes silicon dioxide and a sintering aid. The mass percentage of silicon dioxide in the glass ceramic powder is 60-95%, and the mass percentage of the sintering aid is 5-40%.

[0070] In some embodiments of the present invention, the sintering temperature is 800-900°C; in some specific embodiments of the present invention, the sintering temperature can be 800°C, 810°C, 820°C, 830°C, 840°C, 850°C, 860°C, 870°C, 880°C, 890°C or 900°C.

[0071] In some embodiments of the present invention, the sintering time is 10 to 200 min; in some specific embodiments of the present invention, the sintering time can be 10 min, 20 min, 30 min, 40 min, 50 min, 60 min, 70 min, 80 min, 90 min, 100 min, 110 min, 120 min, 130 min, 140 min, 150 min, 160 min, 170 min, 180 min, 190 min or 200 min.

[0072] A third aspect of the present invention provides an electronic product comprising the multilayer chip inductor according to the first aspect of the present invention.

[0073] The beneficial effects of the present invention are as follows: the laminated chip inductor of the present invention can simultaneously improve the quality factor Q and the self-resonant frequency SRF of the laminated chip inductor by introducing bubbles into the dielectric layer in the coil conductor area to improve the dielectric properties of the dielectric layer, so that the quality factor Q is greater than 13 and the self-resonant frequency SRF is greater than 3800 MHz; and the diameter and porosity of the bubbles in the dielectric insulation area and the coil conductor area are further adjusted to achieve controllable mechanical strength and dielectric properties of the laminated chip inductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] Figure 1 Schematic diagram of the structure of the multilayer chip inductor in Example 1 of the present invention.

[0075] Figure 2 Schematic diagram of the structure of the multilayer chip inductor in Example 2 of the present invention.

[0076] Figure 3 Schematic diagram of the structure of the multilayer chip inductor in Example 3 of the present invention.

[0077] Figure 4 Schematic diagram of the structure of the multilayer chip inductor in Example 4 of the present invention.

[0078] Figure 5 Schematic diagram of the structure of the multilayer chip inductor in Example 5 of the present invention.

[0079] Figure 6 Schematic diagram of the structure of the multilayer chip inductor in Example 6 of the present invention.

[0080] Figure 7 Schematic diagram of the structure of the multilayer chip inductor in Example 7 of the present invention.

[0081] Figure 8 Schematic diagram of the structure of the multilayer chip inductor in Example 8 of the present invention.

[0082] Fig. 9 Schematic diagram of the structure of the multilayer chip inductor in Example 9 of the present invention.

[0083] Fig.10 Schematic diagram of the structure of the multilayer chip inductor in comparative example 1 of the present invention.

[0084] Fig.11 Schematic diagram of the structure of the multilayer chip inductor in comparative example 2 of the present invention.

[0085] Fig.12 This is a schematic diagram of the test structure when testing the bending strength of the present invention. DETAILED DESCRIPTION

[0086] The specific implementation of the present invention is further described in detail below in conjunction with the accompanying drawings and examples, but the implementation and protection of the present invention are not limited thereto. It should be noted that if there are processes that are not particularly described in detail below, they can be implemented or understood by those skilled in the art with reference to the prior art. The reagents or instruments used that do not indicate the manufacturer are all conventional products that can be purchased commercially.

[0087] The sintering aid used in the examples and comparative examples of the present invention is a mixture of B2O3, K2O, and Al2O3 in a mass ratio of 2:2:5.

[0088] Example 1

[0089] like Figure 1 As shown, this example provides a multilayer chip inductor, including a laminate and external electrodes, the number of the external electrodes is two, and the two external electrodes are respectively arranged at two opposite ends of the laminate; the laminate includes a coil conductor area and a dielectric insulation area; the coil conductor area is arranged between the two dielectric insulation areas.

[0090] The coil conductor area in this example is composed of a spiral coil conductor and a dielectric layer stacked together; the spiral coil conductor is electrically connected to the external electrode; only one dielectric layer in the coil conductor area contains bubbles, the bubble diameter is 8μm, and the porosity of the dielectric layer containing bubbles is 7%; the remaining dielectric layers in the coil conductor area do not contain bubbles.

[0091] The dielectric insulating region in this example is formed by laminating dielectric layers that do not contain bubbles.

[0092] The multilayer chip inductor in this example is manufactured by a manufacturing method comprising the following steps:

[0093] S1: glass ceramic powder 1 is prepared according to the formula in Table 1 (wherein the mass percentage of SiO2 is 75%, the mass percentage of the sintering aid is 25%, and the particle size of SiO2 is 5 μm), the mass percentage of glass ceramic powder 1 is 52%, the mass percentage of PVB is 23%, the mass percentage of toluene is 20%, the mass percentage of dioctyl phthalate is 3.8%, and the balance is dispersant NK2000 to weigh the raw materials, and the dielectric layer membrane 1 containing bubbles for molding is obtained by ball milling dispersion and casting;

[0094] S2: glass ceramic powder 5 is prepared according to the formula in Table 1 (wherein the mass percentage of SiO2 is 60%, the mass percentage of the sintering aid is 40%, and the particle size of SiO2 is 1.5 μm), and the raw materials are weighed according to the mass percentage of glass ceramic powder 5 being 52%, the mass percentage of PVB being 23%, the mass percentage of toluene being 20%, the mass percentage of dioctyl phthalate being 3.8%, and the remainder being dispersant NK2000, and a dielectric layer diaphragm 2 free of bubbles for molding is obtained by ball milling dispersion and casting;

[0095] S3: Printing Ag internal electrode paste on the surface of the film required for the coil conductor area to form a spiral coil conductor, and then stacking the coil conductor area and the dielectric insulation area according to the structure of the laminate to obtain the required laminate;

[0096] S4: sintering the laminate in an air atmosphere at a temperature of 850° C. for a holding time of 30 min to obtain a ceramic body;

[0097] S5: External silver electrodes are provided at both ends of the ceramic body to obtain the multilayer chip inductor in this example.

[0098] Table 1 Formula of glass ceramic powder used in Examples 1 to 10 and Comparative Examples 1 to 2

[0099]

[0100]

[0101] Example 2

[0102] like Figure 2 As shown, the structure of the multilayer chip inductor in this example is different from that of Example 1 only in that: all the dielectric layers in the coil conductor area of ​​this example contain bubbles, the bubble diameter is 8μm, and the porosity of the dielectric layer containing bubbles is 7%; the dielectric layer in the coil conductor area adopts the formula of glass ceramic powder 1 in Table 1.

[0103] Example 3

[0104] like Figure 3 As shown, the structure of the multilayer chip inductor in this example is different from that of Example 1 only in that: all dielectric layers in the laminated body of this example contain bubbles, the bubble diameter is 8μm, and the porosity of the dielectric layer containing bubbles is 7%; the dielectric layer adopts the formula of glass ceramic powder 1 in Table 1.

[0105] Example 4

[0106] like Figure 4 As shown, the structure of the multilayer chip inductor in this example is different from that of Example 1 only in that: each dielectric layer in the coil conductor area of ​​this example is formed by stacking a dielectric thin layer A and a dielectric thin layer B, and both the dielectric thin layer A and the dielectric thin layer B contain bubbles. The bubble diameter in the dielectric thin layer A is 8μm, the porosity is 7%, and the formula of the glass ceramic powder 1 in Table 1 is adopted; the bubble diameter in the dielectric thin layer B is 3μm, the porosity is 2%, and the formula of the glass ceramic powder 2 in Table 1 is adopted.

[0107] Example 5

[0108] like Figure 5 As shown, the structure of the multilayer chip inductor in this example is different from that in Example 1 only in that: each dielectric layer in the coil conductor region of this example is formed by laminating dielectric thin layer A, dielectric thin layer B, and dielectric thin layer C; dielectric thin layer A and dielectric thin layer C both contain bubbles, and the diameter of the bubbles in dielectric thin layer A and dielectric thin layer C are both 8 μm, the porosity is both 7%, and the formula of glass ceramic powder 1 in Table 1 is adopted. Dielectric thin layer B does not contain bubbles, and the formula of glass ceramic powder 5 in Table 1 is adopted.

[0109] Example 6

[0110] like Figure 6 As shown, the structure of the multilayer chip inductor in this example is different from that in Example 1 only in that the bubble diameter of the bubble-containing dielectric layer in the coil conductor area of ​​this example is 12 μm, the porosity is 15%, and the formula of the glass ceramic powder 3 in Table 1 is adopted.

[0111] Example 7

[0112] like Figure 7 As shown, the structure of the multilayer chip inductor in this example is different from that in Example 1 only in that:

[0113] (1) In this example, all dielectric layers in the coil conductor region contain bubbles. The diameter of the bubbles in the dielectric layers in the coil conductor region is 12 μm, the porosity is 15%, and the formula of glass ceramic powder 3 in Table 1 is used.

[0114] (2) In this example, all dielectric layers in the dielectric insulating region contain bubbles. The diameter of the bubbles in the dielectric layers in the dielectric insulating region is 8 μm, the porosity is 7%, and the formula of glass ceramic powder 1 in Table 1 is used.

[0115] In this example, the average porosity of the dielectric layer in the coil conductor region is higher than the average porosity of the dielectric layer in the dielectric insulation region.

[0116] Example 8

[0117] like Figure 8 As shown, the structure of the multilayer chip inductor in this example is different from that in Example 1 only in that:

[0118] (1) In this example, all dielectric layers in the coil conductor region contain bubbles. The diameter of the bubbles in the dielectric layers in the coil conductor region is 8 μm, the porosity is 7%, and the formula of glass ceramic powder 1 in Table 1 is used.

[0119] (2) In this example, all dielectric layers in the dielectric insulating region contain bubbles. The diameter of the bubbles in the dielectric layers in the dielectric insulating region is 12 μm, and the porosity is 15%. The formula of glass ceramic powder 3 in Table 1 is used.

[0120] In this example, the average porosity of the dielectric layer in the coil conductor region is lower than the average porosity of the dielectric layer in the dielectric insulation region.

[0121] Example 9

[0122] like Fig. 9 As shown, the structure of the multilayer chip inductor in this example is different from that in Example 1 only in that the bubble diameter of the bubble-containing dielectric layer in the coil conductor area of ​​this example is 25 μm, the porosity is 35%, and the formula of the glass ceramic powder 4 in Table 1 is adopted.

[0123] Example 10

[0124] The structure of the multilayer chip inductor in this example is different from that of Example 1 only in that the bubble diameter of the dielectric layer containing bubbles in the coil conductor area of ​​this example is 8μm, the porosity of the dielectric layer containing bubbles is 7%, and it adopts the formula of glass ceramic powder 1 in Table 1, and the dielectric layer without bubbles adopts the formula of glass ceramic powder 6 in Table 1.

[0125] Comparative Example 1

[0126] like Fig.10 As shown, the structure of the multilayer chip inductor in this example is different from that of Example 1 only in that all dielectric layers in the laminated body of this example do not contain bubbles, and the dielectric layers all adopt the formula of glass ceramic powder 5 in Table 1.

[0127] Comparative Example 2

[0128] like Fig.11 As shown, the structure of the multilayer chip inductor in this example is different from that in Example 1 only in that:

[0129] (1) In this example, all dielectric layers in the coil conductor region do not contain bubbles and all use the formula of glass ceramic powder 5 in Table 1.

[0130] (2) In this example, only one dielectric layer in the dielectric insulation zone contains bubbles, and the remaining dielectric layers do not contain bubbles; the bubble diameter of the dielectric layer containing bubbles in the dielectric insulation zone is 8 μm, the porosity is 7%, and the formula of glass ceramic powder 1 in Table 1 is adopted, and the dielectric layer without bubbles adopts the formula of glass ceramic powder 5 in Table 1.

[0131] Performance Testing

[0132] The quality factor Q, self-resonant frequency SRF and bending strength of the multilayer chip inductors in Examples 1 to 10 and Comparative Examples 1 to 2 were tested respectively. The specific test methods are recorded in Table 2 below, and the test results are recorded in Table 3 below.

[0133] Table 2 Test methods for quality factor Q, self-resonant frequency SRF and bending strength

[0134]

[0135] Table 3 Performance test results of multilayer chip inductors

[0136]

[0137]

[0138] As can be seen from Table 3, the laminated chip inductor of the present invention can simultaneously improve the quality factor Q and the self-resonant frequency SRF of the laminated chip inductor by providing a dielectric layer containing bubbles in the coil conductor area, so that the quality factor Q is greater than 13 and the self-resonant frequency SRF is greater than 3800 MHz. The specific analysis is as follows:

[0139] By comparing Examples 1 to 3 and Comparative Example 1, it can be seen that the increase in porosity in the laminate has a direct impact on the dielectric constant of the laminate. When the laminate does not contain bubbles, its quality factor and self-resonant frequency do not meet the requirements. When the distribution of bubbles in the coil conductor area gradually increases, the dielectric constant value also gradually decreases, further leading to an increase in the quality factor Q and the self-resonant frequency SRF. When the porosity in the laminate gradually increases, the three-point bending strength value decreases slightly; when the entire porcelain body adopts a bubble design, the strength value decreases by 20% to 2.8mm, but it is still within the qualified range.

[0140] By comparing Examples 1-2 and Examples 4-5, it can be seen that a variety of bubbles with different pore sizes can be used in the coil conductor area. After the combination, the performance of the laminate is mainly related to the average porosity of the laminate, and there is no direct correlation with the combination of bubbles. When the average porosity of the dielectric layer in the coil conductor area is higher, the quality factor and self-resonant frequency of the product are improved.

[0141] By comparing Example 1 and Comparative Examples 1-2, it can be seen that when the bubbles are distributed in the coil conductor area, the improvement of the dielectric performance is more obvious, and the quality factor Q is increased from 12.7 to 13.1, which is significantly improved compared to 12.8 in Comparative Example 2. The main reason is that the main generation position of the parasitic capacitance in the coil conductor area is directly opposite to the electrode of the coil conductor. When the dielectric constant of the dielectric layer in the coil conductor area decreases, the reduction of the parasitic capacitance is more obvious. In addition, the dielectric layer containing bubbles is not in the coil conductor area, but closer to the surface of the laminated body, and the strength value of the laminated chip inductor tested in the three-point bending test is reduced.

[0142] By comparing Example 7 and Example 8, it can be seen that when the average porosity of the dielectric layer in the coil conductor area is less than the average porosity in the dielectric insulation area, the surface of the laminate will be extremely loose and the strength value will drop sharply. In addition, when the porosity of the dielectric layer in the coil conductor area is higher, the parasitic capacitance value will be lower, and the quality factor Q and self-resonant frequency SRF values ​​will be better improved.

[0143] By comparing Examples 1, 6, 9, and 10, it can be seen that when the bubble diameter and porosity in the laminate are at the preferred values, the quality factor Q and the self-resonant frequency SRF values ​​are improved, and the strength value does not decrease significantly. However, when the bubble diameter and porosity are significantly larger, not only will the risk of failure in the upper and lower layers of the coil conductor area be increased, but also a failure point will be formed at the three-point bending, and the bending strength value will be sharply reduced.

[0144] In summary, the laminated chip inductor of the present invention introduces bubbles into the dielectric layer in the coil conductor area, and the dielectric constant of the air in the bubbles is 1, which can reduce the overall dielectric constant of the dielectric layer, reduce the parasitic capacitance of the spiral coil conductor design, and improve the Q value and self-resonant frequency. The dielectric properties of the dielectric layer are improved, and the quality factor Q is greater than 13, and the self-resonant frequency SRF is greater than 3800MHz; further, by adjusting the diameter and porosity of the bubbles in the dielectric insulation area and the coil conductor area, the mechanical strength and dielectric properties of the laminated chip inductor can be controlled, and the bending strength is greater than 2mm.

[0145] The above is a detailed description of the embodiments of the present invention, but the present invention is not limited to the above embodiments. Various changes can be made within the knowledge of ordinary technicians in the relevant technical field without departing from the purpose of the present invention. In addition, the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

Claims

1. A multilayer chip inductor, comprising a laminate and an external electrode; characterized in that: The stacked body includes a coil conductor area and a dielectric insulation area arranged in stacked form; the dielectric insulation area includes a dielectric layer; the coil conductor area includes a dielectric layer and a coil conductor arranged in stacked form; the number of dielectric layers in the coil conductor area is not less than two; and at least one dielectric layer in the coil conductor area contains bubbles.

2. The multilayer chip inductor according to claim 1, characterized in that: The number of the dielectric layers in the dielectric insulating region is not less than two, and at least one dielectric layer in the dielectric insulating region contains bubbles.

3. The multilayer chip inductor according to claim 1, characterized in that: In the coil conductor area, the dielectric layer containing bubbles is located in the middle area of ​​the stacked body.

4. The multilayer chip inductor according to claim 1, characterized in that: The medium layer containing bubbles comprises at least two thin medium layers; at least one of the thin medium layers contains bubbles.

5. The multilayer chip inductor according to any one of claims 1 to 4, characterized in that: The diameter of the bubbles is 2-20 μm; the porosity of the medium layer containing the bubbles is 0.5-30%.

6. The multilayer chip inductor according to claim 5, characterized in that: The average porosity of the dielectric layer in the coil conductor region is not lower than the average porosity of the dielectric layer in the dielectric insulation region.

7. The multilayer chip inductor according to claim 1, characterized in that: The medium layer containing bubbles has at least one of the following characteristics: (a1) the dielectric layer contains 60-95% by mass of SiO2; (a2) the dielectric layer contains SiO2 with a particle size of x, 2 μm<x≤20 μm; (a3) the dielectric constant of the dielectric layer is 4 to 6; (a4) The dielectric layer contains a sintering aid in an amount of 5 to 40% by mass; the sintering aid is a compound of at least one element selected from K, Na, Ca, Mg, B, Al, Fe, and Zr.

8. The multilayer chip inductor according to claim 1, characterized in that: The medium layer without bubbles has at least one of the following characteristics: (b1) the dielectric layer contains SiO2 in a mass percentage of y, 20%≤y<60%; (b2) the dielectric layer contains SiO2 with a particle size of 0.1 to 5 μm; (b3) the dielectric constant of the dielectric layer is 4 to 10; (b4) the dielectric layer contains a sintering aid in a mass percentage of z, 40%<z≤80%; the sintering aid is a compound of at least one element selected from K, Na, Ca, Mg, B, Al, Fe, and Zr; or, The medium layer without bubbles has at least one of the following characteristics: (c1) the dielectric layer contains 60-95% by mass of SiO2; (c2) the dielectric layer contains SiO2 with a particle size of 0.1 to 2 μm; (c3) the dielectric constant of the dielectric layer is 4 to 10; (c4) The dielectric layer contains a sintering aid in an amount of 5 to 40% by mass; the sintering aid is a compound of at least one element selected from K, Na, Ca, Mg, B, Al, Fe, and Zr.

9. The method for preparing the multilayer chip inductor according to any one of claims 1 to 8, characterized in that: The following steps are involved: S1: grinding the raw materials for preparing the dielectric layer containing bubbles and the raw materials for preparing the dielectric layer without bubbles separately to form films, thereby obtaining a membrane sheet; S2: preparing a coil conductor on a membrane used in a coil conductor area; S3: stacking and sintering to obtain the stacked body; S4: forming external electrodes at both ends of the stacked body to obtain the stacked chip inductor.

10. An electronic product, characterized in that: A multilayer chip inductor comprising the multilayer chip inductor according to any one of claims 1 to 8.

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