Bonding method and wafer structure

Abstract

The invention provides a bonding method and a wafer structure. The bonding method comprises the following steps: providing a first wafer structure and a second wafer structure; and when at least one of the first wafer structure and the second wafer structure forms a bonding structure, a connection structure in the bonding structure of at least one of the first wafer structure and the second wafer structure is adjusted relative to a preset position based on the expansion state of the first wafer structure and the second wafer structure. According to the method, the preset position of the connection structure in the bonding structure is adjusted before wafer bonding, that is, expansion or contraction caused when the connection structure is formed before wafer bonding is compensated in advance, and therefore the problem that the connection structure position of the bonding structure is not matched before wafer bonding is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a bonding method and a wafer structure. Background Art

[0002] With the continuous development of semiconductor technology, 3D-IC (three-dimensional integrated circuit) technology has been widely used. The multi-layer stacking structure reduces the volume while achieving further extension of functions and signals.

[0003] During the semiconductor manufacturing process, wafers undergo processes such as photolithography, etching, and thin film deposition. Different processes will cause the wafers to expand or contract to varying degrees. When the expansion difference before wafer bonding is small, the expansion of the wafer can be changed by adjusting the chuck of the bonding machine for bonding. However, sometimes the expansion difference of the wafers to be bonded is large, and at this time the adjustment capability of the bonding machine cannot meet the requirements for precise bonding of the expanded or contracted wafers. Summary of the invention

[0004] The present application provides a bonding method and a wafer structure to alleviate the problem of bonding mismatch caused by expansion of the wafer after a manufacturing process.

[0005] In order to solve the above technical problems, the present application provides a bonding method on the one hand, including: providing a first wafer structure and a second wafer structure; when at least one of the first wafer structure and the second wafer structure forms a bonding structure, based on the expansion state of the first wafer structure and the second wafer structure, the connecting structure in the bonding structure of at least one of the first wafer structure or the second wafer structure is adjusted relative to a preset position.

[0006] In some embodiments, a first bonding structure is formed on the first wafer structure.

[0007] Based on the expansion state of the first wafer structure and the second wafer structure, the connecting structure in the bonding structure of at least one of the first wafer structure or the second wafer structure is adjusted relative to a preset position, including: when forming a second bonding structure on the second wafer structure, based on the expansion change of the first wafer structure and the expansion parameters of the second wafer structure, the connecting structure in the second bonding structure in the second wafer structure is adjusted relative to the preset position.

[0008] In some embodiments, the expansion parameters of the second wafer structure include the expansion change of the second wafer structure before forming the second bonding structure, the expected expansion change of the second wafer structure when forming the second bonding structure, and the adjustment capability of the bonding machine.

[0009] In some embodiments, the first wafer structure and the second wafer structure are respectively a multi-wafer structure and / or a single wafer structure.

[0010] In some embodiments, the second bonding structure includes a through silicon via structure, a back metal pattern, a dielectric layer and a bonding metal pattern; wherein the through silicon via structure passes through a wafer in the first wafer structure or the second wafer structure to realize the connection between the back metal pattern arranged on the back side of the wafer and the front metal pattern arranged on the front side of the wafer; the dielectric layer covers the back metal pattern, and the bonding metal pattern is embedded in the dielectric layer and connected to the corresponding back metal pattern; the through silicon via structure, the back metal pattern and the bonding metal pattern are the connection structure in the bonding structure.

[0011] In some embodiments, when the second bonding structure is formed on the second wafer structure, the connection structure in the second bonding structure in the second wafer structure is adjusted relative to the preset position based on the expansion change of the first wafer structure and the expansion parameter of the second wafer structure, including: a first adjustment of the through silicon via in the second wafer structure relative to the first preset position; a second adjustment of the back metal pattern in the second wafer structure relative to the second preset position; and a third adjustment of the bonding metal pattern in the second wafer structure relative to the third preset position.

[0012] In some embodiments, the adjustment amount of the connection structure gradually increases along the direction from the center to the edge of the first wafer structure or the second wafer structure.

[0013] To solve the above problems, the present application provides a wafer structure on the other hand, including: multiple wafers and corresponding bonding structures, each of the wafers is bonded to another adjacent wafer through the corresponding bonding structure; wherein the position of the connecting structure in the bonding structure corresponding to at least one of the wafers has an offset adjustment amount relative to a preset position.

[0014] In some embodiments, the bonding structure includes a through silicon via structure, a back metal pattern, a dielectric layer and a bonding metal pattern; wherein the through silicon via structure passes through a wafer in the wafer structure to realize the connection between the back metal pattern arranged on the back side of the wafer and the front metal pattern arranged on the front side of the wafer; the dielectric layer covers the back metal pattern, and the bonding metal pattern is embedded in the dielectric layer and connected to the corresponding back metal pattern; the through silicon via structure, the back metal pattern and the bonding metal pattern are the connection structure in the bonding structure.

[0015] In some embodiments, the center of the through silicon via structure does not coincide with the center of the corresponding front metal pattern; or the center of the back metal pattern does not coincide with the center of the corresponding through silicon via structure; or the center of the bonding metal pattern does not coincide with the center of the corresponding back metal pattern.

[0016] In some embodiments, the offset adjustment amount of the connection structure gradually increases along the direction from the center to the edge of the wafer structure.

[0017] The bonding method provided in some embodiments of the present application includes: providing a first wafer structure and a second wafer structure; when at least one of the first wafer structure and the second wafer structure forms a bonding structure, based on the expansion state of the first wafer structure and the second wafer structure, the connection structure in the bonding structure of at least one of the first wafer structure or the second wafer structure is adjusted relative to a preset position. When the connection structure in the bonding structure is formed before the first wafer structure and the second wafer structure are bonded, the preset position of the connection structure is adjusted, wherein the connection structure of at least one of the first wafer structure or the second wafer structure includes: a through silicon via structure, a back metal layer pattern, and a bonding metal pattern. Thereby, the problem of mismatch in the position of the connection structure of the bonding structure before wafer bonding is alleviated, the restrictions on the wafers to be bonded are reduced, and the possibility of bonding between wafers and the application scope of the wafer stacking process are increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0019] Figure 1 It is a schematic diagram of the structure of the wafer shrinking after the process;

[0020] Figure 2 This is a schematic diagram of the structure of the wafer expanding after undergoing the manufacturing process;

[0021] Figure 3 A schematic diagram of the structure of two wafers that have expanded or shrunk after bonding;

[0022] Figure 4 It is a schematic structural diagram of a longitudinal cross section of one of the wafers before the two wafers are bonded and the bonding structure is not yet formed;

[0023] Figure 5 A schematic diagram of the structure of a longitudinal cross section of two wafers bonded together, wherein one of the wafers forms a bonding structure before bonding, and the wafer shrinks;

[0024] Figure 6 A flow chart of a bonding method provided for some embodiments of the present application;

[0025] Figure 7 is a structural schematic diagram of a longitudinal cross section of a second bonding structure formed when the second wafer structure has not been subjected to adjustment of the bonding structure setting position;

[0026] Figure 8 A schematic structural diagram of a longitudinal cross section of a second wafer structure in some embodiments of the present application forming a second bonding structure through step S12;

[0027] Fig. 9 A schematic structural diagram of a longitudinal cross section of a first wafer structure 100 and a second wafer structure 200 bonded together provided in some embodiments of the present application;

[0028] Fig.10 A schematic structural diagram of a longitudinal cross-section of a wafer structure provided for some embodiments of the present application. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0030] The terms "first" and "second" in this application are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0031] All directional indications in the embodiments of the present application (such as up, down, left, right, front, back, top, bottom...) are only used to explain the relative position relationship, movement status, etc. between the components in a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0032] In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products or devices.

[0033] Unless otherwise defined, the term “substantially” mentioned in this application, with respect to numerical quantities or quantitative relationships, can be understood as a range of approximately ±15% of a certain numerical value.

[0034] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0035] The "expanded state" mentioned in this article refers to the state of expansion or contraction of a single wafer or multi-wafer structure after undergoing processes such as lithography, etching, and deposition; the "preset position", "first preset position", "second preset position", and "third preset position" mentioned in this article refer to the preset positions before lithography is performed before forming a connecting structure in a bonding structure; the "adjustment relative to the preset position" mentioned in this article refers to adjusting the position of the connecting structure in the bonding structure along the horizontal direction; the "front side" of the wafer mentioned in this article is the side on which electronic components are provided, and the "back side" is the side relative to the "front side". The wafer bonding mentioned in this article is not limited to the bonding of the front side to the back side of the wafer, but can also be the bonding of the front side to the back side or the back side to the back side of the wafer.

[0036] See also Figure 1-5 , Figure 1 It is a schematic diagram of the structure of the wafer shrinking after the process; Figure 2 This is a schematic diagram of the structure of the wafer expanding after undergoing the manufacturing process; Figure 3 The schematic diagram of the structure of two wafers 10 after expansion or contraction. Before the two wafers 10 are bonded, one of the wafers 10 needs to undergo processes such as photolithography, etching, and deposition to form a bonding structure 11. These processes will cause the wafer 10 to expand or contract, and the bonding structure 11 will shift to varying degrees. The closer the bonding structure 11 is to the edge of the wafer 10, the greater the degree of its shift.

[0037] See also Figure 4 , Figure 4It is a schematic diagram of the structure of the longitudinal cross section of one of the wafers before the two wafers are bonded, and the bonding structure is not formed in the second wafer 102 before the first wafer 101 and the second wafer 102 are bonded, and the second wafer 102 shrinks after the bonding structure 11 is formed as an example for explanation. The first dielectric layer 1011 of the first wafer 101 close to the bonded second wafer 102 is provided with a first metal pattern 1012 and a first bonding metal pattern 1013, and the first metal pattern 1012 is connected to the first bonding metal pattern 1013. The second wafer 102 is bonded to a carrier wafer 20 on the side away from the bonding to the first wafer 101, and the second dielectric layer 1021 close to the carrier wafer 20 is provided with a second metal pattern 1022.

[0038] The method for forming a bonding structure in the second wafer 102 includes: first thinning the substrate of the second wafer 102 away from the carrier wafer 20, then depositing a dielectric layer on the side of the second wafer 102 away from the carrier wafer 20, and then etching and metal filling to form a through silicon via structure 1023; depositing a dielectric layer again to form a third metal pattern 1025; further depositing a dielectric layer, and forming a third bonding metal pattern 1026 in the dielectric layer. The through silicon via structure 1023 is filled with a conductive material, such as copper, tungsten, or other metal materials, and the through silicon via structure 1023 connects the second metal pattern 1022 and the third metal pattern 1025, and the third metal pattern 1025 is connected to the third bonding metal pattern 1026. The formed through silicon via structure 1023, the third dielectric layer 1024, the third metal pattern 1025 and the third bonding metal pattern 1026 form a bonding structure. See Figure 5 , Figure 5A schematic diagram of the structure of the longitudinal cross section of two wafers bonded, one of which forms a bonding structure before bonding, and the wafer shrinks. The x side is the center of the first wafer 101 and the second wafer 102, the y side is the edge of the first wafer 101 and the second wafer 102, and the z direction is the direction from the x side to the y side, that is, the direction from the center of the first wafer 101 and the second wafer 102 to the edge of the first wafer 101 and the second wafer 102. Since the second wafer 102 shrinks and becomes smaller after the bonding structure is formed, the position of the bonding structure is offset close to the x side, and the offset gradually increases along the z direction. If the second wafer 102 expands and becomes larger after the bonding structure is formed, it will cause the bonding structure to be offset close to the y side, and similarly, the offset gradually increases along the z direction. As a result, it is difficult for the through silicon via structure 1023, the third metal pattern 1025 and the third bonding metal pattern 1026 of the second wafer 102 to be aligned and connected with the first metal pattern 1012 and the first bonding metal pattern 1013 of the first wafer 101, and it may even cause the third bonding metal pattern 1026 and the first bonding metal pattern 1013 near the edge of the wafer to be completely misaligned.

[0039] When the expansion or contraction of the wafer 10 is small, the bonding machine can be controlled to adjust the deformation of the chuck to change the expansion of the wafer 10 for bonding. Usually, the adjustment capability of the bonding machine is 8-12ppm. However, when the expansion of the wafer 10 varies greatly, the adjustment capability of the bonding machine cannot meet the requirements for accurate bonding of the wafer 10. Figure 3 and Figure 5 As shown, after two wafers 10 with a large degree of expansion or contraction are bonded, only the bonding structures 11 located in the center of the two wafers 10 can be aligned. The closer the bonding structure 11 is to the edge of the wafer 10, the greater the position deviation of the bonding structures 11 of the two wafers 10, and even a phenomenon of complete inability to overlap may occur, resulting in the two wafers 10 being unable to be electrically connected after bonding, and thus unable to achieve the corresponding electrical function.

[0040] In order to solve the above problems, the present application provides a bonding method. Figure 6 , Figure 6 A flow chart of a bonding method provided in some embodiments of the present application. The method specifically comprises:

[0041] Step S11: providing a first wafer structure and a second wafer structure.

[0042] Step S12: When at least one of the first wafer structure and the second wafer structure forms a bonding structure, based on the expansion state of the first wafer structure and the second wafer structure, the connecting structure in the bonding structure of at least one of the first wafer structure or the second wafer structure is adjusted relative to a preset position.

[0043] In some embodiments, the first wafer structure 100 may be a single wafer structure, or a stacked multi-wafer structure; the second wafer structure 200 may also be a single wafer structure, or a stacked multi-wafer structure. In some embodiments, the first wafer structure 100 or the second wafer structure 200 is formed with a bonding structure, and the bonding structure has more than one connection structure from the center of the wafer to the edge of the wafer. The following is a description of the phenomenon that the first wafer structure 100 and the second wafer structure 200 are both single wafer structures, a second bonding structure 210 is formed in the second wafer structure 200 before bonding, and the second wafer structure 200 shrinks after the second bonding structure 210 is formed as an example.

[0044] Before bonding, the first wafer structure 100 and the second wafer structure 200 have undergone different degrees of expansion or contraction due to the processes such as photolithography, etching, and deposition, and after the bonding structure is formed in the first wafer structure 100 or the second wafer structure 200, the first wafer structure 100 or the second wafer structure 200 will experience new expansion or contraction. In some embodiments, in order to alleviate the problem of inaccurate bonding due to the expansion or contraction of the first wafer structure 100 and the second wafer structure 200, it is necessary to adjust the preset position of the connection structure 211 in the second bonding structure 210 when forming the second wafer structure 200.

[0045] See also Figure 7 , Figure 7It is a schematic diagram of the structure of the longitudinal section of the second bonding structure formed when the second wafer structure has not been adjusted to the setting position of the bonding structure, and a schematic diagram of the structure of the longitudinal section of the first wafer structure to be bonded. The second wafer structure 200 includes a front side 200a and a relatively arranged back side 200b. In the present embodiment, the front side 200a of the second wafer structure 200 is bonded to the carrier wafer 300, and the back side 200b is set as the bonding surface bonded to the first wafer structure 100. In other embodiments, the front side of the second wafer structure 200 can also be set as the bonding surface bonded to the first wafer structure 100. In the present embodiment, a front dielectric layer 220 and a front metal pattern 230 are provided on the side of the second wafer structure 200 close to the front side 200a, wherein the front metal pattern 230 is provided in the front dielectric layer 220. The second bonding structure 210 formed before the second wafer structure 200 is bonded includes a connecting structure 211 and a dielectric layer 212 arranged on the side of the back side 200b of the second wafer structure 200. The connection structure 211 includes a through silicon via structure 2111, a back metal pattern 2112 and a bonding metal pattern 2113. The through silicon via structure 2111 runs through the substrate of the second wafer structure 200, and connects the front metal pattern 230 on the front side 200a of the second wafer structure 200 and the back metal pattern 2112 on the back side 200b. At the same time, the through silicon via structure 2111 is filled with a conductive material, wherein the conductive material is copper, tungsten, or other metal materials. The back metal pattern 2112 and the bonding metal pattern 2113 are arranged in the dielectric layer 212, and the back metal pattern 2112 is connected to the bonding metal pattern 2113.

[0046] See also Figure 7-8 , Figure 8 The schematic diagram of the longitudinal cross section of the second wafer structure forming the second bonding structure through step S12 in some embodiments of the present application. In the present embodiment, the x side is the center of the second wafer structure 200, the y side is the edge of the second wafer structure 200, and the z direction is the direction extending from the x side to the y side, that is, the z direction is the direction from the center to the edge of the second wafer structure 200. In some embodiments, the formation process of the second bonding structure 210 is: first, the back side of the substrate of the second wafer structure 200 is thinned, and then a silicon through hole structure 2111 that penetrates the substrate is formed, and then a back metal pattern 2112 and a bonding metal pattern 2113 are formed, and the dielectric layer 212 covers the back metal pattern 2112, and the bonding metal pattern 2113 is embedded in the dielectric layer 212. In other embodiments, when the second wafer structure 200 is a stacked multi-wafer structure, the second bonding structure 210 is formed in the wafer closest to the side bonded to the first wafer structure 100.

[0047] The through silicon via structure 2111, the back metal pattern 2112 and the bonding metal pattern 2113 of the second bonding structure 210 are formed according to the first preset position, the second preset position and the third preset position respectively. When forming the through silicon via structure 2111, the first preset position is set with reference to the front metal pattern 230. When forming the back metal pattern 2112, the second preset position is set with reference to the formed through silicon via structure 2111. When forming the bonding metal pattern 2113, the third preset position is set with reference to the formed back metal pattern 2112. Figure 7 When the second bonding structure 210 is not formed through step S12, the first preset position, the second preset position, and the third preset position of the through silicon via structure 2111, the back metal pattern 2112, and the bonding metal pattern 2113 all coincide with the preset position p0 with reference to the center of the front metal pattern 230. However, since the second wafer structure shrinks during the process of forming the connection structure 211, the front metal pattern 230 is offset to the x side, and the offset gradually increases along the z direction. The connection structure 211 of the second bonding structure 210 formed with reference to the preset position p0 may have a problem of not being able to be aligned with the first bonding metal pattern 110 of the bonding structure of the first wafer structure 100. Therefore, it is necessary to adjust the preset positions of the through silicon via structure 2111, the back metal pattern 2112 and the bonding metal pattern 2113 during the process of forming the connection structure 211, that is, to make a first adjustment to the through silicon via structure 2111 relative to the first preset position; to make a second adjustment to the back metal pattern 2112 relative to the second preset position; and to make a third adjustment to the bonding metal pattern 2113 relative to the third preset position, so as to compensate for the deviation of the connection structure 211 close to the x side caused by the shrinkage of the second wafer structure 200. Figure 8As shown, after the first adjustment, the preset position of the through silicon via structure 2111 is the first adjustment position p1, and the through silicon via structure 2111 is formed with reference to the first adjustment position p1; after the second adjustment, the preset position of the back metal pattern 2112 is the second adjustment position p2, and the back metal pattern 2112 is formed with reference to the second adjustment position p2; after the third adjustment, the preset position of the bonding metal pattern 2113 is the third adjustment position p3, and the bonding metal pattern 2113 is formed with reference to the third adjustment position p3. The first adjustment amount A of the first adjustment is the adjustment amount of the first adjustment position p1 relative to the preset position p0; the second adjustment amount B of the second adjustment is the adjustment amount of the second adjustment position p2 relative to the first adjustment position p1; the third adjustment amount C of the third adjustment is the adjustment amount of the third adjustment position p3 relative to the second adjustment position p2. In some embodiments, the preset position p0 is the position of the center of the front metal pattern 230, the first adjustment position p1 is the position of the center of the through silicon via structure 2111, the second adjustment position p2 is the position of the center of the back metal pattern 2112, and the third adjustment position p3 is the position of the center of the bonding metal pattern 2113. The center refers to when the front metal pattern 230, the through silicon via structure 2111, the back metal pattern 2112 and the bonding metal pattern 2113 are symmetrical regular shapes, the adjustment position is the geometric center of the symmetrical regular shape; when the front metal pattern 230, the through silicon via structure 2111, the back metal pattern 2112 and the bonding metal pattern 2113 are irregular shapes, the adjustment position is some other position in the irregular shape, as long as the electrical connection between the front metal pattern 230, the through silicon via structure 2111, the back metal pattern 2112 and the bonding metal pattern 2113 can be achieved. Since the offset of the connection structure 211 gradually increases along the z direction, the adjustment amounts of the through silicon via structure 2111, the back metal pattern 2112 and the bonding metal pattern 2113, namely the first adjustment amount A, the second adjustment amount B and the third adjustment amount C, also gradually increase along the z direction. In some embodiments, one or two of the first adjustment amount A, the second adjustment amount B and the third adjustment amount C may be zero, that is, only the preset position of one or two of the through silicon via structure 2111, the back metal pattern 2112 and the bonding metal pattern 2113 may be adjusted, as long as the first wafer structure 100 and the second wafer structure 200 can be precisely bonded.

[0048] In some embodiments, the adjustment amount of the preset position of the connection structure 211, i.e., the first adjustment amount A, the second adjustment amount B, and the third adjustment amount C, are determined based on the expansion change amount D of the first wafer structure 100 and the expansion parameter E of the second wafer structure 200. The expansion parameter E of the second wafer structure 200 includes the expansion change amount a of the second wafer structure 200 before forming the second bonding structure 210, the expected expansion change amount b of the second wafer structure 200 when forming the second bonding structure 210, and the adjustment capacity c of the bonding machine. The expansion change amount D of the first wafer structure 100, the expansion change amount a of the second wafer structure 200 before forming the second bonding structure 210, and the expected expansion change amount b of the second wafer structure 200 when forming the second bonding structure 210 represent the change amount of expansion or contraction that occurs after the first wafer structure 100 or the second wafer structure 200 undergoes photolithography, etching, or other processes. In this embodiment, the expected expansion variation b of the second wafer structure 200 when the second bonding structure 210 is formed is the contraction variation of the second wafer structure 200 after the second bonding structure 210 is formed.

[0049] After the second wafer structure 200 forms the second bonding structure 210 and before bonding with the first wafer structure 100, the above parameters should satisfy the following approximate equation:

[0050] E+A+B+C≈D

[0051] Among them, E=a+b+c.

[0052] See also Fig. 9 , Fig. 9 A schematic structural diagram of a longitudinal cross section of a first wafer structure 100 and a second wafer structure 200 bonded together in some embodiments of the present application. In some embodiments, the expansion change D of the first wafer structure 100, the expansion change a of the second wafer structure 200 before forming the second bonding structure 210, and the adjustment capability c of the bonding machine are known parameters before the second wafer structure 200 forms the second bonding structure 210; the expected expansion change b of the second wafer structure 200 when forming the second bonding structure 210 is a predictable parameter. Through the above parameters and approximate equations, the adjustment amount of the preset position of the connection structure 211 that needs to be adjusted, that is, the total adjustment amount of the first adjustment amount A, the second adjustment amount B and the third adjustment amount C, can be calculated. Then, according to different needs, the preset positions of the through silicon via structure 2111, the back metal pattern 2112 and the bonding metal pattern 2113 can be flexibly adjusted to achieve precise bonding with the first wafer structure 100, that is, to achieve connection between the front metal pattern 230, the through silicon via structure 2111, the back metal pattern 2112, the bonding metal pattern 2113 and the first bonding metal pattern 110 of the first wafer structure 100.

[0053] In some embodiments, when forming the through silicon via structure 2111, the back metal pattern 2112 and the bonding metal pattern 2113, if the adjustment is made to the right relative to the preset position, the adjustment value is positive; if the adjustment is made to the left relative to the preset position, the adjustment value is negative. In the actual adjustment process, there are process fluctuations, such as errors in critical dimensions, and OVL fluctuations (overlay, overlay errors) related to the machine, which will affect the actual adjustment range of the through silicon via structure 2111, the back metal pattern 2112 and the bonding metal pattern 2113. Therefore, the upper and lower limit formulas of the first adjustment amount A, the second adjustment amount B and the third adjustment amount C are (taking a wafer with a radius of 150 mm as an example):

[0054] A / B / C≈±[(Δx-β-ε) / 0.15um / ppm]

[0055] Among them, Δx is the ideal adjustable space for adjacent structures to achieve electrical connection, β is the process fluctuation, ε is the OVL fluctuation, and 0.15um is one millionth of the wafer radius. The adjustable space Δx for adjacent structures to achieve electrical connection is generally set in the range of 0.2 to 1.8um.

[0056] For example, in some embodiments, when a regular-patterned through silicon via structure 2111 is formed, an ideal adjustable space Δx for electrical connection between the through silicon via structure 2111 and the front metal pattern 230 is 1.3um, that is, a difference between a preset width of the through silicon via structure 2111 on one side based on its center and a preset width of the front metal pattern 230 on one side based on its center is 1.3um, which is within the preset ideal adjustable space range of 0.2 to 1.8um; an error β of a critical dimension (CD) of the through silicon via structure 2111 is 5um*5%=0.25um, and an OVL fluctuation ε of the machine is 0.15um. According to the above formula, the upper and lower limits of the actual adjustable range of the first adjustment amount A can be calculated as ±[(1.3um-0.25um-0.15um) / 0.15um / ppm]=±6ppm, that is, the actual adjustable range of the first adjustment amount A is between -6 and +6ppm.

[0057] Similarly, when forming a regular pattern of back metal pattern 2112, based on the ideal adjustable space Δx for achieving electrical connection between the back metal pattern 2112 and the through silicon via structure 2111 (i.e., the difference between the preset width of the back metal pattern 2112 on one side based on its center and the preset width of the through silicon via structure 2111 on one side based on its center), the error β of the critical dimension (CD) of the back metal pattern 2112 (e.g., 0.6um*5%=0.03um), and the OVL fluctuation ε of the machine (e.g., 0.15um), the upper and lower limits of the actual adjustable range of the second adjustment amount B corresponding to the back metal pattern 2112 can be calculated according to the above formula.

[0058] When forming a regular pattern of a bonding metal pattern 2113, based on the ideal adjustable space Δx for realizing electrical connection between the bonding metal pattern 2113 and the back metal pattern 2112 (i.e., the difference between the preset width of the bonding metal pattern 2113 on one side based on its center and the preset width of the back metal pattern 2112 on one side based on its center), the error β of the critical dimension (CD) of the bonding metal pattern 2113 (for example, 2um*5%=0.1um), and the OVL fluctuation ε of the machine (for example, 0.15um), the upper and lower limits of the actual adjustable range of the third adjustment amount C corresponding to the bonding metal pattern 2113 can be calculated according to the above formula.

[0059] Therefore, as described above, based on the upper and lower limits of the actual adjustable ranges of the first adjustment amount A, the second adjustment amount B and the third adjustment amount C, and the above equation E+A+B+C≈D, appropriate first adjustment amount A, second adjustment amount B and third adjustment amount C can be selected so that they are within the range specified by the corresponding upper and lower limits of the actual adjustable ranges and satisfy the equation E+A+B+C≈D.

[0060] To solve the above problems, the present application provides a wafer structure 900. Fig.10 , Fig.10 A schematic diagram of the structure of a longitudinal cross section of a wafer structure provided for some embodiments of the present application. The wafer structure 900 includes a plurality of wafers 910 and corresponding bonding structures 210. Each wafer 910 is bonded to an adjacent wafer 910 through a corresponding bonding structure 210. In some embodiments, the bonding structure 210 includes a through silicon via structure 2111, a back metal pattern 2112, a dielectric layer 212, and a bonding metal pattern 2113. The through silicon via structure 2111 penetrates the corresponding substrate of a wafer 910 in the wafer structure 900 to realize the connection between the back metal pattern 2112 disposed on the back of the wafer 910 and the front metal pattern 230 disposed on the front of the wafer 910; the dielectric layer 212 covers the back metal pattern 2112, and the bonding metal pattern 2113 is embedded in the dielectric layer 212 and connected to the corresponding back metal pattern 2112. The TSV structure 2111, the back metal pattern 2112 and the bonding metal pattern 2113 are the connection structure 211 of the bonding structure 210. The position of the connection structure 211 in the bonding structure 210 corresponding to at least one wafer 910 in the wafer structure 900 has an offset adjustment relative to the preset position p0.

[0061] In some embodiments, when the position of the connection structure 211 in the wafer structure 900 is adjusted relative to the preset position p0, the position where the center of the through silicon via structure 2111 is located, that is, the first adjusted position obtained after the first preset position is adjusted, does not coincide with the center of the front metal pattern 230; or, the position where the center of the back metal pattern 2112 is located, that is, the second adjusted position obtained after the second preset position is adjusted, does not coincide with the center of the through silicon via structure 2111; or, the position where the center of the bonding metal pattern 2113 is located, that is, the third adjusted position obtained after the third preset position is adjusted, does not coincide with the center of the back metal pattern 2112. Finally, the center of the bonding metal pattern 2113 after adjustment does not coincide with the center of the back metal pattern 2112. And since the offset of the connection structure 211 gradually increases along the direction from the center to the edge of the wafer structure 900, that is, the z direction, the offset adjustment amount of the connection structure 211, that is, the through silicon via structure 2111, the back metal pattern 2112 and the bonding metal pattern 2113, that is, the first adjustment amount A, the second adjustment amount B and the third adjustment amount C also gradually increase along the z direction.

[0062] The above are only implementation methods of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A bonding method, characterized in that: include: providing a first wafer structure and a second wafer structure; When at least one of the first wafer structure and the second wafer structure forms a bonding structure, based on the expansion state of the first wafer structure and the second wafer structure, the connection structure in the bonding structure of at least one of the first wafer structure and the second wafer structure is adjusted relative to a preset position.

2. The method according to claim 1, characterized in that A first bonding structure is formed on the first wafer structure. Based on the expansion states of the first wafer structure and the second wafer structure, the connection structure in the bonding structure of at least one of the first wafer structure and the second wafer structure is adjusted relative to a preset position, including: When forming the second bonding structure on the second wafer structure, based on the expansion change of the first wafer structure and the expansion parameter of the second wafer structure, the connection structure in the second bonding structure in the second wafer structure is adjusted relative to the preset position.

3. The method according to claim 2, characterized in that The expansion parameters of the second wafer structure include the expansion change amount of the second wafer structure before forming the second bonding structure, the expected expansion change amount of the second wafer structure when forming the second bonding structure, and the adjustment capability of the bonding machine.

4. The method according to claim 2, characterized in that: The first wafer structure and the second wafer structure are respectively a multi-wafer structure and / or a single wafer structure.

5. The method according to claim 2, characterized in that: The second bonding structure includes a through silicon via structure, a back metal pattern, a dielectric layer and a bonding metal pattern; wherein the through silicon via structure penetrates a wafer in the first wafer structure or the second wafer structure to achieve connection between the back metal pattern arranged on the back of the wafer and the front metal pattern arranged on the front of the wafer; the dielectric layer covers the back metal pattern, and the bonding metal pattern is embedded in the dielectric layer and connected to the corresponding back metal pattern; The through silicon via structure, the back metal pattern and the bonding metal pattern are the connection structure in the bonding structure.

6. The method according to claim 5, characterized in that When forming the second bonding structure on the second wafer structure, adjusting the connection structure in the second bonding structure in the second wafer structure relative to the preset position based on the expansion change of the first wafer structure and the expansion parameter of the second wafer structure, including: Performing a first adjustment on the through silicon via structure in the second wafer structure relative to a first preset position; Performing a second adjustment on the back metal pattern in the second wafer structure relative to a second preset position; The bonding metal pattern in the second wafer structure is third adjusted relative to a third preset position.

7. The method according to claim 1, characterized in that Along the direction from the center to the edge of the first wafer structure or the second wafer structure, the adjustment amount of the connection structure gradually increases.

8. A wafer structure, characterized in that: include: A plurality of wafers and corresponding bonding structures, each of the wafers being bonded to another adjacent wafer through the corresponding bonding structure; Wherein, the position of the connection structure in the bonding structure corresponding to at least one of the wafers has an offset adjustment amount relative to a preset position.

9. The wafer structure according to claim 8, characterized in that: The bonding structure includes a through silicon via structure, a back metal pattern, a dielectric layer and a bonding metal pattern; wherein the through silicon via structure penetrates a wafer in the wafer structure to achieve connection between the back metal pattern arranged on the back of the wafer and the front metal pattern arranged on the front of the wafer; the dielectric layer covers the back metal pattern, and the bonding metal pattern is embedded in the dielectric layer and connected to the corresponding back metal pattern; The through silicon via structure, the back metal pattern and the bonding metal pattern are the connection structure in the bonding structure.

10. The wafer structure according to claim 9, characterized in that: The center of the through silicon via structure does not coincide with the center of the corresponding front metal pattern; or The center of the back metal pattern does not coincide with the center of the corresponding through silicon via structure; or The center of the bonding metal pattern does not overlap with the center of the corresponding back metal pattern.

11. The wafer structure according to claim 8, characterized in that: Along the direction from the center to the edge of the wafer structure, the offset adjustment amount of the connection structure gradually increases.

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