Semiconductor device

Abstract

The invention provides a semiconductor device suitable for high heat dissipation, high output, and high integration, and a method for manufacturing the same. A semiconductor device (110) is provided with: a substrate (1) having, on the upper surface thereof, a circuit element and an electrode connected to the circuit element; and a conductive pillar bump (PB) for external connection, which is provided on the substrate (1) and is in contact with and electrically connected to the electrode or the circuit element (21). The substrate (1) includes a first base material (10) and a second base material (20) disposed on the first base material (10), the circuit element (21) and the electrode are formed on the second base material (20), and the thermal resistance of the first base material (10) is lower than the thermal resistance of the second base material (20).

Description

[0001] This application is a divisional application of the invention patent application with application number 202010564522.X, application date June 19, 2020, and invention name “Semiconductor device and manufacturing method thereof”. Technical Field

[0002] The present invention relates to a semiconductor device, and more particularly to a semiconductor device used in a high-frequency circuit and having a heat generating portion, and a method for manufacturing the same. Background Art

[0003] Conventionally, there is known a semiconductor device in which a semiconductor device is mounted on a mounting substrate via a bump and the bump is used as a heat dissipation path.

[0004] For example, Patent Document 1 shows a compound semiconductor device having a heterojunction bipolar transistor (HBT) formed by connecting a plurality of unit transistors in parallel on a compound semiconductor substrate. The plurality of unit transistors are arranged on the compound semiconductor substrate, and the bumps are electrically connected to the emitters of the plurality of unit transistors.

[0005] Patent Document 1: Japanese Patent Application Publication No. 2016-103540

[0006] In MMIC (Monolithic Microwave Integrated Circuit) that forms a high-frequency amplifier circuit used in mobile communications, satellite communications, etc., with the further high speed and high functionality in recent years, the increase in RFFE (RF Front-End) losses and the characteristic limits caused by the self-heating of power amplifier equipment have become issues. For example, in a bipolar transistor, heat is generated due to its collector loss, and the base-emitter voltage Vbe decreases due to the temperature rise of the bipolar transistor itself. Therefore, if positive feedback such as the collector current increases and Vbe further decreases is applied, thermal runaway will occur. If the heat dissipation of the MMIC is not high, the power that can be used within the range where thermal runaway does not occur is limited, so as a result, the power that can be used is in a trade-off relationship with the size of the MMIC.

[0007] In addition, since the RFFE module mixes devices made of different substrate materials, such as power amplifiers using GaAs substrates and SAW devices using LiTaO3 substrates and LiNbO3 substrates, the integration of different types of equipment is required as performance, miniaturization and cost reduction are further improved. Summary of the invention

[0008] Therefore, an object of the present invention is to provide a semiconductor device suitable for high heat dissipation, high output, and high integration, and a method for manufacturing the same.

[0009] A semiconductor device as one embodiment of the present invention comprises: a substrate having a circuit element and an electrode connected to the circuit element on its surface; and a conductor protrusion for external connection, which is arranged on the above-mentioned substrate and connected to the above-mentioned circuit element or the above-mentioned electrode, and the above-mentioned substrate includes: a first base material and a second base material arranged on the first base material and made of a material different from that of the above-mentioned first base material, the above-mentioned circuit element and the above-mentioned electrode are formed on the above-mentioned second base material, and the thermal conductivity of the above-mentioned first base material is higher than that of the above-mentioned second base material.

[0010] A method for manufacturing a semiconductor device as one embodiment of the present disclosure includes: a substrate having a circuit element and an electrode connected to the circuit element on a surface thereof; and a conductor protrusion for external connection, which is provided on the substrate and contacts and is electrically connected to the circuit element or the electrode. The substrate includes: a first substrate and a second substrate arranged on the first substrate, the circuit element and the electrode being formed on the second substrate.

[0011] The method for manufacturing the semiconductor device comprises:

[0012] A step of forming a semiconductor thin film having the circuit element and the electrode on the surface thereof on a compound semiconductor substrate via a release layer;

[0013] A step of removing the release layer by etching to release the semiconductor thin film from the compound semiconductor substrate;

[0014] The step of bonding the semiconductor thin film constituting the second substrate to a predetermined position on the element semiconductor substrate constituting the first substrate; and

[0015] A step of forming a conductor protrusion for external connection, wherein the conductor protrusion for external connection is provided on the second substrate and connected to the circuit element or the electrode.

[0016] According to the present invention, heat dissipation is high, thereby achieving a compact and high-output semiconductor device or a high-output and small-sized semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a cross-sectional view of the semiconductor device 110 according to the first embodiment.

[0018] Figure 2 (A) Figure 2 (B) is a cross-sectional view showing a mounting structure of the semiconductor device 110 on a mounting substrate.

[0019] Figure 3 (A) is a cross-sectional view showing a heat dissipation path of the semiconductor device 110. Figure 3(B) is a cross-sectional view showing a heat dissipation path of a semiconductor device according to a comparative example.

[0020] Figure 4 It is a diagram showing a method for manufacturing the semiconductor device 110 .

[0021] Figure 5 It is a cross-sectional view of a semiconductor device 111 which is a modification of the first embodiment.

[0022] Figure 6 It is a cross-sectional view of a semiconductor device 120 according to the second embodiment.

[0023] Figure 7 It is a cross-sectional view after the semiconductor device 120 is mounted on the mounting substrate 90 .

[0024] Figure 8 (A) Figure 8 (B) is a cross-sectional view of the semiconductor device according to the third embodiment.

[0025] Fig. 9 It is a cross-sectional view of another semiconductor device according to the third embodiment.

[0026] Fig.10 It is a top view of a semiconductor device 140 according to the fourth embodiment.

[0027] Fig.11 (A) is Fig.10 The cross-sectional view of the A-A part in FIG. Fig.11 (B) is Fig.10 Cross-sectional view of the B-B portion.

[0028] Fig.12 The diagram is a perspective view of each step of the method for manufacturing a semiconductor device according to the fifth embodiment.

[0029] Fig.13 It is a partial cross-sectional view of a semiconductor device formed by processing the first substrate 10 after the semiconductor thin film is transferred.

[0030] Fig.14 It is a cross-sectional view of a semiconductor device 160 according to the sixth embodiment.

[0031] Fig.15 (A) Fig.15 (B) is a cross-sectional view showing the mounting structure of the semiconductor device 160 .

[0032] Fig.16 It is a cross-sectional view of a semiconductor device 170 according to the seventh embodiment.

[0033] Fig.17 It is a cross-sectional view of a semiconductor device mounted on a mounting substrate as a comparative example.

[0034] Explanation of reference numerals: PB…conductor post bump; 1…substrate; 10…first substrate; 11…bonding layer; 12…first substrate side electrode; 15…planarization resin layer; 16…insulator layer; 20…second substrate; 20D…epitaxial layer; 20N…semiconductor substrate; 21…circuit element; 22…second substrate side electrode; 13, 23…conductor post; 14, 24…solder layer; 29…peeling layer; 30…GaAs substrate ; 32, 42…electrodes; 33, 43…conductor posts; 34, 44…solder layers; 51A, 51B…heterojunction bipolar transistors; 52…spiral inductors; 53…MIMC; 85…resist film; 90…mounting substrate; 91, 92…mounting substrate-side electrodes; 110, 111, 120, 130A, 130B, 131, 140, 160, 170…semiconductor devices; 200…mother substrate. DETAILED DESCRIPTION

[0035] Hereinafter, some specific examples are given with reference to the accompanying drawings to illustrate a plurality of ways for implementing the present invention. The same reference numerals are marked at the same positions in the respective figures. In consideration of the ease of explanation or understanding of the key points, in order to facilitate the explanation of the embodiments, the embodiments are divided into a plurality of embodiments for representation, but partial replacement or combination of the structures shown in different embodiments is possible. After the second embodiment, the description of matters common to the first embodiment is omitted, and only the differences are described. In particular, the same effects exerted by the same structure are not mentioned sequentially in each embodiment.

[0036] 《First Implementation Mode》

[0037] Figure 1 1 is a cross-sectional view of a semiconductor device 110 according to the first embodiment. The semiconductor device 110 includes a substrate 1, a conductor post 23 in contact with and electrically connected to a second substrate-side electrode 22 provided on the substrate 1, and a solder layer 24 formed on the conductor post 23. The conductor post 23 and the solder layer 24 constitute a conductor post bump PB.

[0038] The substrate 1 includes a first substrate 10 and a second substrate 20 disposed on the first substrate 10. A plurality of circuit elements 21 and electrodes for applying an operating voltage or passing an operating current to the plurality of circuit elements 21 are formed on the second substrate 20. The second substrate 20 is formed by other processes as shown below, and the circuit elements are formed on its epitaxial layer. The epitaxial layer is, for example, about 3 μm, and the electrode (wiring layer) is about 10 μm. Figure 1 In the figure, the protrusion shown in the circuit element 21 is an electrode that is electrically connected to the circuit element.

[0039] In addition, in the present embodiment, the semiconductor device 110 has a first substrate-side electrode 12 formed on the surface of the first substrate 10 at a position that does not overlap with the second substrate 20. Furthermore, the semiconductor device 110 includes a conductor post 13 connected to the first substrate-side electrode 12, and a solder layer 14 formed on the conductor post 13. The conductor post 13 and the solder layer 14 constitute a conductor post bump PB.

[0040] The above-mentioned conductor post bump PB corresponds to the "conductor protrusion" for external connection in the present invention.

[0041] In this example, the first substrate 10 is a material containing any one of GaAs, AlAs, InAs, InP, GaP, InSb, GaN, InN, AlN, Si, Ge, SiC, Ga2O3, DLC (Diamond-Like Carbon), Graphite, Diamond, Glass, Sapphire, Al2O3, or a multi-component mixed crystal material consisting of multiple materials among these materials. In addition, the second substrate 20 is a material containing any one of GaAs, AlAs, InAs, InP, GaP, InSb, GaN, InN, AlN, SiGe, SiC, Ga2O3, and GaBi, or a multi-component mixed crystal material consisting of multiple materials among these materials. However, the material selected for the first substrate 10 and the material selected for the second substrate 20 are different, and the manufacturing process of the first substrate 10 and the second substrate 20 is different. Basically, the second substrate 20 is a material that can obtain predetermined electrical characteristics such as amplification factor and cutoff frequency, and the first substrate 10 is selected so that the thermal conductivity is higher than that of the second substrate 20. The same applies to other embodiments described below.

[0042] In this embodiment, the first substrate 10 is a Si substrate, and the second substrate 20 is a GaAs substrate. The thermal conductivity of the Si substrate is 156, and the thermal conductivity of the GaAs substrate is 46. The circuit element 21 is, for example, a heterojunction bipolar transistor (HBT) formed by connecting a plurality of unit transistors in parallel, and is formed by a process for the second substrate 20, i.e., the GaAs substrate. The conductor column bump PB is electrically connected to the emitters of the plurality of unit transistors. The plurality of unit transistors are arranged in a first direction ( Figure 1 The conductor column bumps PB are arranged in the left-right direction (in the left-right direction), and the conductor column bumps PB are arranged to extend along the first direction.

[0043] The second base material 20 is bonded to the first base material 10 via the bonding layer 11. The bonding layer 11 is, for example, an Au film.

[0044] The conductor posts 13 and 23 are Cu plated films, and the solder layers 14 and 24 are SnAg alloy films.

[0045] Figure 2 (A) Figure 2 (B) is a cross-sectional view showing a mounting structure of the semiconductor device 110 on a mounting substrate. Figure 2 (A) is a cross-sectional view of a stage before the semiconductor device 110 is mounted on the mounting substrate 90. Figure 2 (B) is a cross-sectional view after the semiconductor device 110 is mounted on the mounting substrate 90 .

[0046] The mounting substrate 90 is provided with mounting substrate side electrodes 91 and 92. The semiconductor device 110 is formed by aligning its solder layers 14 and 24 with the mounting substrate side electrodes 91 and 92 and applying heat and pressure. Figure 2 As shown in FIG. 2 (B), the solder layers 14 and 24 of the semiconductor device 110 are connected to the mounting substrate side electrodes 91 and 92 .

[0047] Here, the structure of a semiconductor device is shown as a comparative example. Fig.17 1 is a cross-sectional view of a semiconductor device as a comparative example mounted on a mounting substrate. The semiconductor device of the comparative example has a circuit element formed on a GaAs substrate 30. Electrodes 32 and 42 are formed on the surface of the GaAs substrate 30, and a conductor post 43 and a solder layer 44 are formed on the electrode 42, and a conductor post 33 and a solder layer 34 are formed on the electrode 32. Moreover, the solder layers 34 and 44 of the semiconductor device are connected to the mounting substrate side electrodes 91 and 92, respectively.

[0048] In addition, if Figure 1 As shown, the height of the solder layer 24 and the solder layer 14 differ by the thickness of the second substrate 20 , and this height difference is absorbed by the solder layers 14 , 24 .

[0049] Reference Figure 3 (A) Figure 3 (B) describes the heat dissipation properties of the semiconductor device of the comparative example and the semiconductor device 110 of the first embodiment.

[0050] In a semiconductor device as a comparative example, Figure 3 As shown in FIG. 2(B) , as indicated by the dotted arrows, the heat generated in the circuit element is dissipated (dissipated) to the mounting substrate side electrode 92 and the mounting substrate 90 via the electrode 42 , the conductor post 43 , and the solder layer 44 .

[0051] On the other hand, in the semiconductor device 110 of the present embodiment, as Figure 3As shown in (A), as indicated by the dotted arrows, heat is dissipated through three heat conduction paths. The first heat conduction path is a path for dissipating (discharging) the heat generated by the circuit element to the mounting substrate side electrode 92 and the mounting substrate 90 via the second substrate side electrode 22, the conductor post 23, and the solder layer 24. The second heat conduction path is a path for dissipating (discharging) the heat generated by the circuit element to the first substrate 10. The first substrate 10 is a Si substrate, and its thermal conductivity is 156 [W / cm K]. The thermal conductivity of the GaAs substrate 30 is 46 [W / cm K]. The thermal conductivity of the first substrate 10 is higher than that of the second substrate 20. Therefore, the first substrate 10 acts as a highly efficient heat radiator. The third heat conduction path is a path for dissipating (discharging) the heat generated in the circuit element to the mounting substrate side electrode 91 and the mounting substrate 90 via the first substrate 10, the first substrate side electrode 12, the conductor post 13, and the solder layer 14. Since the first base material 10 functions as a heat conduction path in this manner, the conductor post 13 , the solder layer 14 , and the mounting substrate-side electrode 91 also function as a heat conduction path.

[0052] The semiconductor device 110 of the present embodiment configured as above has the following effects.

[0053] First, by forming three heat dissipation paths, higher heat dissipation is achieved. In this way, the RF characteristics (output power Pout, power added efficiency PAE) that are limited by the self-heating of the HBT are improved. In other words, a small and high-output semiconductor device is obtained. Alternatively, a high-output and small-sized semiconductor device is obtained.

[0054] In addition, since the second substrate is a substrate of a compound semiconductor, its electrical insulation is improved, and a circuit having excellent high-frequency characteristics can be provided.

[0055] In addition, since the second base material 20 is thinner than the first base material 10 , a higher heat dissipation effect of the first base material 10 can be obtained.

[0056] In addition, since the circuit element 21 formed on the second substrate 20 is a heating element that generates heat when in operation, the conductor column bump PB is arranged near the circuit element 21 which is a heating element. The conductor column bump forms a shorter heat conduction path, and the heat generated by the circuit element 21 is efficiently dissipated through the conductor column bump PB.

[0057] In addition, since the second substrate 20 does not protrude from the outer edge of the first substrate 10 (has a smaller area than the first substrate 10 ), the overall thermal resistance of the substrate 1 including the first substrate 10 and the second substrate 20 is low, and a higher heat dissipation effect is obtained from the first substrate 10 .

[0058] In addition, since the first substrate side electrode 12 is formed on the surface of the first substrate 10 at a position not overlapping with the second substrate 20, and the conductor post bump PB is connected to the first substrate side electrode 12, a heat dissipation effect is obtained from the conductor post bump PB connected to the first substrate side electrode 12. In addition, the heat conduction efficiency toward the circuit substrate as the mounting destination is improved through the conductor post bump PB, and the heat dissipation on the circuit substrate is also improved.

[0059] Next, a method for manufacturing the semiconductor device 110 is exemplified. Figure 4 It is a diagram showing a method for manufacturing the semiconductor device 110 . Figure 4 Figures (1) to (7) are cross-sectional views of the semiconductor device 110 in the middle of manufacturing, and (8) is a cross-sectional view of the completed semiconductor device 110. The actual manufacturing is carried out on a wafer basis, but Figure 4 , a single semiconductor device is shown.

[0060] First, if Figure 4 As shown in (1), an Au film as a bonding layer 11 is formed on the surface of a first substrate 10 composed of a Si substrate using a common semiconductor process.

[0061] Next, as shown in (2), the second base material 20 is bonded to the bonding layer 11. Circuit elements and electrodes have already been formed on the second base material 20 by other processes.

[0062] Next, as shown in (3), the second substrate-side electrode 22 is formed on the second substrate 20 by a common semiconductor process, and the first substrate-side electrode 12 is formed on the bonding layer 11 .

[0063] Next, as shown in (4), the conductor post 13 and the solder layer 14 ( Figure 1 , Figure 2 A resist film 85 having an opening is formed in the region of (A)). The electrodes 12 and 22 are exposed in the opening of the resist film 85.

[0064] Then, as shown in (5) and (6), the conductor posts 13 and 23 and the solder layers 14 and 24 are deposited by electroplating on the electrodes 12 and 22 exposed from the opening of the resist film 85. The conductor posts 13 and 23 are formed of Cu, and their thickness is, for example, 40 μm. In this way, a CPB (Copper Pillar Bump) is formed. The solder layers 14 and 24 are formed of SnAg alloy, and their thickness is, for example, 30 μm.

[0065] Thereafter, as shown in (7), the resist film 85 is removed, and finally, the solder layers 14 and 24 are melted by performing a reflow process and then solidified, thereby obtaining the semiconductor device 110 shown in (8).

[0066] According to the above-described manufacturing method, since the second substrate 20 is a semiconductor thin film, a semiconductor device having a low profile and high heat dissipation properties (high thermal conductivity) can be obtained.

[0067] In addition, Figure 1 to Figure 4 In the example shown, an Au film is formed as the bonding layer 11, but other metal films such as a Pt film or a Pd film may also be used. The thermal conductivity of the bonding layer 11 is preferably higher than the thermal conductivity of the second substrate 20. Thus, the heat of the second substrate 20 is efficiently discharged to the first substrate 10 via the bonding layer 11. For example, the thermal conductivity of the GaAs substrate as the second substrate 20 is 46 [W / m K], while the thermal conductivity of the Au film is 319 [W / m K], the thermal conductivity of the Pt film is 70 [W / m K], and the thermal conductivity of the Pd film is 70 [W / m K], all of which are higher than the thermal conductivity of the second substrate 20.

[0068] In addition, it is more preferred that the elastic modulus of the bonding layer 11 is lower than the elastic modulus of the second substrate 20. There is a difference in the linear expansion coefficient between the first substrate 10 and the second substrate 20, and thermal stress caused by the difference in linear expansion coefficient is generated according to temperature changes. However, the above-mentioned thermal stress is reduced by making the elastic modulus of the bonding layer 11 lower than the elastic modulus of the second substrate 20. Thus, the actual bonding strength between the first substrate 10 and the second substrate 20 via the bonding layer 11 can be ensured. For example, the elastic modulus of the GaAs substrate is 85.5 [GPa]. In contrast, the elastic modulus of the Au film is 78 [GPa], the elastic modulus of the Al film is 68.3 [GPa], and the elastic modulus of the In film is 10.8 [GPa], all of which are lower than the elastic modulus of the second substrate 20.

[0069] When the bonding layer 11 is made of metal, it is preferable to form an alloy layer of the bonding layer 11 and the second base material 20 between the bonding layer 11 and the second base material 20. This can provide higher adhesion and higher heat conduction.

[0070] The above-mentioned bonding layer 11 can be, for example, a dielectric composed of an organic material such as a polyimide (PI) film, polybenzoxazole (PBO), or benzocyclobutene (BCB). Preferably, the dielectric constant of the bonding layer 11 is lower than the dielectric constant of the second substrate 20. As a high-frequency characteristic of the circuit element formed on the second substrate 20, it has a transmission loss characteristic of a high-frequency signal. If the dielectric constant of the bonding layer 11 is higher than the dielectric constant of the second substrate 20, the transmission loss characteristic of the high-frequency signal of the circuit element is reduced according to the proximity of the bonding layer 11. If the dielectric constant of the bonding layer 11 is lower than the dielectric constant of the second substrate 20, the reduction of the transmission loss characteristic is avoided. For example, the relative dielectric constant of the GaAs substrate serving as the second substrate 20 is 12.9. In comparison, the dielectric constants of polyimide (PI) are 3.3, polybenzoxazole (PBO) and benzocyclobutene (BCB) are 2.7, all of which are lower than the dielectric constant of the second substrate 20 .

[0071] In addition, it is preferred that the dielectric loss tangent of the bonding layer 11 is smaller than the dielectric loss tangent of the second substrate 20. If the dielectric loss tangent of the bonding layer 11 is large, the high-frequency loss of the bonding layer 11 increases. If the dielectric loss tangent of the bonding layer 11 is smaller than the dielectric loss tangent of the second substrate 20, the increase in the high-frequency loss is avoided. For example, the dielectric loss tangent of the GaAs substrate as the second substrate 20 is 0.3, in contrast, the dielectric loss tangent of polyimide (PI) is 0.0020, the dielectric loss tangent of polybenzoxazole (PBO) is 0.0100, and the dielectric loss tangent of benzocyclobutene (BCB) is 0.0008, which are all smaller than the dielectric loss tangent of the second substrate 20.

[0072] In addition, when the bonding layer 11 is an organic material, it is also preferred that the elastic modulus of the bonding layer 11 is lower than the elastic modulus of the second substrate 20. In this way, the actual bonding strength between the first substrate 10 and the second substrate 20 via the bonding layer 11 can be ensured. For example, the elastic modulus of the GaAs substrate is 85.5 [GPa], while the elastic modulus of polyimide (PI) is 2.5, the elastic modulus of polybenzoxazole (PBO) is 2.8, and the elastic modulus of benzocyclobutene (BCB) is 2.1, all of which are lower than the elastic modulus of the second substrate 20.

[0073] Furthermore, the bonding layer 11 may be an insulator such as AlN, SiC, diamond, etc. Preferably, the resistivity of the bonding layer 11 is higher than that of the first substrate 10. If the resistivity of the bonding layer 11 is higher than that of the first substrate 10, the induced current and eddy current flowing in the bonding layer 11 and the first substrate 10 can be suppressed, so that the good high-frequency characteristics of the circuit element formed on the second substrate 20 can be maintained.

[0074] In addition, when the bonding layer 11 is an insulator, it is also preferred that the thermal conductivity of the bonding layer 11 is higher than the thermal conductivity of the first substrate 10. Thus, the heat of the second substrate 20 is efficiently discharged to the first substrate 10 via the bonding layer 11. For example, the thermal conductivity of the Si substrate as the first substrate 10 is 156 [W / cm K], while the thermal conductivity of the AlN film is 170 [W / cm K], the thermal conductivity of the SiC film is 270 [W / cm K], and the thermal conductivity of the diamond film is 2000 [W / cm K], all of which are higher than the thermal conductivity of the first substrate 10.

[0075] Next, a modification of the first embodiment will be described. Figure 5 is a cross-sectional view of a semiconductor device 111 as a modification example. The semiconductor device 111 does not have Figure 1 The bonding layer 11 is shown. The second substrate 20 is directly bonded to the first substrate 10. The bonding is based on van der Waals bonds or hydrogen bonds. In addition, bonding can also be performed by electrostatic forces, covalent bonds, eutectic alloy bonds, etc.

[0076] The first substrate-side electrode 12 is directly formed on the upper surface of the first substrate 10 , and a conductor post bump PB composed of a conductor post 13 and a solder layer 14 is formed on the first substrate-side electrode 12 .

[0077] As described above, the second base material 20 may be bonded to the first base material 10 without the intermediary of the bonding layer.

[0078] Second Implementation Method

[0079] In the second embodiment, a semiconductor device having a different structure of a conductive protrusion from that in the first embodiment is described.

[0080] Figure 6 is a cross-sectional view of a semiconductor device 120 according to the second embodiment. Figure 1 The example shown is different from that shown in that the first base material side electrode 12 and the conductor protrusion for external connection (conductor post 13 and solder layer 14 ) connected to the first base material side electrode 12 are not provided.

[0081] Figure 7 1 is a cross-sectional view after the semiconductor device 120 is mounted on the mounting substrate 90. The mounting substrate side electrode 92 is formed on the mounting substrate 90. The semiconductor device 120 aligns its conductor post bump PB with the mounting substrate side electrode 92 and heats and presses it so that the solder layer 24 is connected to the mounting substrate side electrode 92.

[0082] Even with such a structure, as indicated by the broken arrows in the figure, heat is dissipated (exhausted) from the heat generating portion in two directions.

[0083] 《Third Implementation Mode》

[0084] In the third embodiment, several semiconductor devices including a planarizing resin layer are exemplified.

[0085] Figure 8 (A) Figure 8 (B) is a cross-sectional view of semiconductor devices 130A and 130B according to the third embodiment. These semiconductor devices 130A and 130B include a first substrate 10 and a second substrate 20 disposed on the first substrate 10. The second substrate 20 includes a semiconductor substrate 20N of a compound semiconductor and an epitaxial layer 20D formed on the surface thereof. A plurality of circuit elements 21 are formed on the epitaxial layer 20D.

[0086] On the upper surface of the epitaxial layer 20D, a second substrate-side electrode 22 is formed to be conductive with the circuit element 21. A planarization resin layer 15 is formed on the surface of the first substrate 10 and the second substrate 20. On the upper portion of the second substrate-side electrode 22, a conductor post bump PB based on a conductor post 23 and a solder layer 24 is formed.

[0087] exist Figure 8 In the example shown in (B), a bonding layer 11 is formed on the upper surface of the first base material 10 , and the second base material 20 is bonded to the first base material 10 via the bonding layer 11 .

[0088] Fig. 9 1 is a cross-sectional view of another semiconductor device 131 of the third embodiment. The semiconductor device 131 includes a first substrate 10 and a second substrate 20 disposed on the first substrate 10. A plurality of circuit elements are formed on the second substrate 20. A bonding layer 11 is formed on the upper surface of the first substrate 10. A planarization resin layer 15 is formed on the surfaces of the bonding layer 11 and the second substrate 20. A conductor post bump PB composed of a conductor post 13 and a solder layer 14 is formed on the upper portion of the first substrate side electrode 12.

[0089] The planarization resin is, for example, a polyimide (PI) film, polybenzoxazole (PBO), benzocyclobutene (BCB), etc. In this way, by forming the planarization resin layer 15 on the surface of the first substrate 10 and the second substrate 20, it is easy to form a relatively thick conductor post 23 and a solder layer 24. In addition, the surfaces of the first substrate 10 and the second substrate 20 are repassivated.

[0090] 《Fourth Implementation Mode》

[0091] In the fourth embodiment, a semiconductor device including conductive bumps for external connection at a plurality of locations is exemplified.

[0092] Fig.10 is a top view of a semiconductor device 140 according to the fourth embodiment. Fig.11 (A) is Fig.10 The cross-sectional view of the A-A part in FIG. Fig.11 (B) is Fig.10 Cross-sectional view of the B-B portion.

[0093] The semiconductor device 140 of this embodiment has solder layers 14 and 24 formed on a plurality of conductive posts. Fig.10 , Fig.11 As shown in (A), at a predetermined position of the semiconductor device 140, a plurality of unit transistors are arranged in Fig.10 Heterojunction bipolar transistors (HBT) 51A and 51B are connected in parallel in the left-right direction. Conductor post bumps PB based on conductor posts 23 and solder layers 24 are formed on the upper parts of the HBTs 51A and 51B. The structures of the HBTs 51A and 51B, the conductor posts 23 and the solder layers 24 are as shown in the first embodiment.

[0094] Conductive post bumps PB formed by the conductive post 13 and the solder layer 14 are formed on both sides of the two HBTs 51A and 51B.

[0095] like Fig.10 As shown in FIG. 1 , the conductor post bumps PB are also formed in the portion other than the AA cross section. The conductor post bumps PB are arranged near the HBTs 51A and 51B. With this structure, the heat generated by the HBTs 51A and 51B is efficiently dissipated.

[0096] In the semiconductor device 140 , in addition to the HBTs 51A and 51B, an LCR circuit is formed by an inductor formed by a spiral conductor pattern, a capacitor formed by electrodes facing each other with a dielectric layer interposed therebetween, and a resistor element formed by a resistor film pattern.

[0097] like Fig.10 as well as Fig.11 As shown in (B), a bonding layer 11 is formed on the surface of the first substrate 10, and an insulating layer 16 is formed at a predetermined position on the surface of the bonding layer 11. A spiral inductor 52 is formed on the surface of the insulating layer 16. A conductor post bump PB composed of a conductor post 13 and a solder layer 14 is formed at an adjacent position of the spiral inductor 52. Fig.10 , Fig.11 A MIMC (Metal-Insulator-Metal-Capacitor) 53 is formed at a predetermined position of the semiconductor device 140 shown in (B). Furthermore, a conductor post bump PB based on the conductor post 13 and the solder layer 14 is formed at a position adjacent to the MIMC 53 .

[0098] 《Fifth Implementation Mode》

[0099] In the fifth embodiment, a method for manufacturing a second base material and a method for joining the second base material to the first base material are described.

[0100] Fig.12 1 is a perspective view of each process of the fifth embodiment. The actual manufacturing is carried out in units of wafers, but Fig.12 , a single semiconductor device is shown.

[0101] like Fig.12 As shown in (1), first, a peeling layer 29 is formed on a mother substrate 200 as a compound semiconductor substrate, and a semiconductor thin film is formed on the upper part of the peeling layer 29 by epitaxial growth method, and a plurality of circuit elements and electrodes connected to the circuit elements are formed on the semiconductor thin film. This part is the second substrate 20 later.

[0102] Next, as shown in (2), the second base material 20 (semiconductor thin film sheet) is peeled off from the mother substrate 200 by performing a process of selectively etching only the peeling layer 29 .

[0103] As shown in (3), the bonding layer 11 is formed on the first substrate 10 through a separate process, and as shown in (4), the second substrate 20 is bonded (joined) to the first substrate 10 by pressing the second substrate 20 and making it close to the surface of the bonding layer 11. In other words, the semiconductor thin film is transferred from the mother substrate 200 to the first substrate 10. For example, Au of the bonding layer 11 is diffused into GaAs of the second substrate and eutecticized to achieve bonding.

[0104] The formation of circuit elements and electrodes on the second substrate 20 is not limited to the stage shown in (1) but can also be performed by a process (photolithography / etching process) on the second substrate 20 after the second substrate 20 is bonded to the first substrate 10 as shown in (4).

[0105] The method for peeling and transferring the semiconductor thin film can be applied to the method disclosed in Patent No. 5132725. In other words, Fig.12 As shown in (2), when the second substrate 20 (semiconductor thin film sheet) is peeled off from the mother substrate 200, the second substrate 20 is peeled off from the mother substrate 200 while being supported by the support. Fig.12 As shown in (3), when the second substrate 20 is bonded to the first substrate 10, it is performed while being supported by the above-mentioned support body. Fig.12 In (2) and (3), the support body is omitted in order to clearly show the second substrate 20.

[0106] Fig.13This is a partial cross-sectional view of a semiconductor device formed by processing the first substrate 10 after transferring the semiconductor thin film sheet. The second substrate 20 includes a semiconductor substrate 20N and a circuit element 21 as a bipolar transistor formed on the surface thereof. A second substrate-side electrode 22 is formed on the upper portion of the second substrate 20. In this example, the second substrate-side electrode 22 is an emitter wiring. A planarization resin layer 15 is formed on the surface of the bonding layer 11 of the first substrate and the second substrate 20.

[0107] A conductor post bump PB including a conductor post 23 and a solder layer 24 is formed on the second substrate-side electrode 22 as the emitter wiring.

[0108] The thickness of the semiconductor substrate 20N and the epitaxial layer 20D are both several μm. For example, the semiconductor substrate 20N is 1 μm, and the epitaxial layer 20D is 3 μm. In the past, when wire bonding to a compound semiconductor element, the total thickness of the semiconductor substrate 20N and the epitaxial layer 20D needed to be 75 μm or more, but in this embodiment, since the thickness of the second substrate 20 attached to the upper part of the first substrate 10 is only several μm, it is possible to form a very thin (low-profile) semiconductor device as a whole.

[0109] 《Sixth Implementation Method》

[0110] In the sixth embodiment, a semiconductor device having a characteristic structure of a bonding layer bonding the first base material 10 and the second base material 20 is described.

[0111] Fig.14 1 is a cross-sectional view of a semiconductor device 160 according to the sixth embodiment. The semiconductor device 160 includes a first substrate 10 and a second substrate 20 disposed on the first substrate 10. The second substrate 20 includes a semiconductor substrate of a compound semiconductor and an epitaxial layer formed on the surface thereof, and a plurality of circuit elements 21 are formed on the epitaxial layer. In this example, the first substrate 10 is a Si substrate, and the second substrate 20 is a GaAs substrate.

[0112] A bonding layer 19 is provided between the first substrate 10 and the second substrate 20. In other words, the first substrate 10 and the second substrate 20 are bonded via the bonding layer 19. A first substrate-side electrode 12 is formed on the surface of the bonding layer 19. A second substrate-side electrode 22 is formed on the surface of the second substrate 20. A planarizing resin layer 15 is formed on the surfaces of the first substrate 10 and the second substrate 20. A conductor post bump PB composed of a conductor post 13 and a solder layer 14 is formed on the upper portion of the first substrate-side electrode 12. A conductor post bump PB composed of a conductor post 23 and a solder layer 24 is formed on the upper portion of the second substrate-side electrode 22.

[0113] The bonding layer 19 is a composite material layer including an insulator layer 17 and a metal layer 18. The insulator layer 17 is, for example, a Si compound layer such as a SiO2 film or a SiN film, or a resin layer such as a polyimide (PI) film. The metal layer 18 is, for example, a Cu film or an Al film. The bonding layer 19 has a three-layer structure.

[0114] The bonding layer 19 is formed with an insulating layer 17 as a first layer on the surface of the first substrate 10, a metal layer 18 as a second layer on the surface of the insulating layer 17, and an insulating layer 17 as a third layer on the surface of the metal layer 18. The metal layer 18 is patterned, and patterns of the metal layer 18 are formed near the second substrate 20 and near the first substrate-side electrode 12, respectively.

[0115] As described above, since the bonding layer 19 is a composite material layer including the insulator layer 17 and the metal layer 18, the bonding layer 19 relieves stress generated by the difference in linear expansion coefficients between the first substrate 10 and the second substrate 20. The linear expansion coefficients of the first substrate 10, the second substrate 20, and the bonding layer 19 are as follows. For example, the linear expansion coefficient of the Si substrate as the first substrate 10 is 2.60 [ppm / °C], and the linear expansion coefficient of the GaAs substrate as the second substrate 20 is 5.73 [ppm / °C]. In contrast, the linear expansion coefficient of the SiO2 film based on the silicon oxynitride film (TEOS) is 0.57 [ppm / °C], and the linear expansion coefficient of the SiN film is 2.30 [ppm / °C], which are lower than the first substrate 10 and the second substrate 20. In addition, the linear expansion coefficient of the Cu film as the metal layer 18 is 17.0 [ppm / °C], which is higher than the first substrate 10 and the second substrate 20. Therefore, the linear expansion coefficient of the bonding layer 19 is an intermediate value between the linear expansion coefficient of the first base material 10 and the linear expansion coefficient of the second base material 20 , and stress at the interface between the second base material 20 and the first base material 10 is relaxed.

[0116] If the insulator layer 17 is a Si compound layer such as a SiO 2 film or a SiN film, it is easy to form the insulator layer 17 on the first base material 10 , and the bonding strength between the first base material 10 and the insulator layer 17 can be improved.

[0117] Only the uppermost layer of the insulating layer 17 may be a resin layer. In this way, when at least a portion of the insulating layer 17 is a layer based on a resin film, the stress is absorbed by the flexibility of the insulating layer 17 regardless of the magnitude relationship of the linear expansion coefficient. In addition, the stress generated between the metal layer 18 and the insulating layer 17 in the bonding layer 19 can also be alleviated by the insulating layer 17.

[0118] In addition, the second substrate 20 expands and contracts due to the heating and stopping of the circuit element 21 formed on the second substrate 20, but the expansion and contraction are stricter than the expansion and contraction of the first substrate 10 separated from the circuit element 21. Even if the linear expansion coefficients of the first substrate 10, the second substrate 20 and the bonding layer 19 are not in the above relationship, the trend is the same. According to this embodiment, due to the presence of the bonding layer 19, the stress at the interface between the second substrate 20 and the first substrate 10 is relieved.

[0119] Fig.15 (A) Fig.15 (B) is a cross-sectional view showing a mounting structure of the semiconductor device 160 . Fig.15 (A) is a cross-sectional view of a stage before the semiconductor device 160 is mounted on the mounting substrate 90. Fig.15 (B) is a cross-sectional view after the semiconductor device 160 is mounted on the mounting substrate 90 .

[0120] The mounting substrate 90 is provided with mounting substrate side electrodes 91, 92. The semiconductor device 160 is formed by aligning its solder layers 14, 24 with the mounting substrate side electrodes 91, 92 and applying heat and pressure. Fig.15 As shown in FIG. 2(B) , the solder layers 14 and 24 of the semiconductor device 160 are connected to the mounting substrate side electrodes 91 and 92 .

[0121] In this way, the conductor post bump PB formed on the second substrate side electrode 22 functions as a terminal for connecting the circuit element 21 formed on the second substrate 20 to the circuit of the mounting substrate. In addition, the conductor post bump PB formed on the second substrate side electrode 22 also functions as a heat dissipation bump for dissipating heat generated by the circuit element 21 formed on the second substrate 20 to the mounting substrate.

[0122] The metal layer 18 in the bonding layer 19 improves the thermal conductivity of the bonding layer 19. Therefore, the heat generated by the circuit element 21 formed on the second substrate 20 is also dissipated to the first substrate 10 via the bonding layer 19. In addition, since the metal layer 18 in the bonding layer 19 improves the thermal conductivity in the surface direction (lateral direction) of the bonding layer 19, the heat generated by the circuit element 21 is also dissipated to the mounting substrate 90 via the metal layer 18 near the first substrate-side electrode 12 and the conductor column bump PB formed on the first substrate-side electrode 12. In addition, the heat generated by the circuit element 21 is also dissipated to the first substrate 10 via the metal layer 18 near the first substrate-side electrode 12.

[0123] In addition, Fig.14 In the cross section shown, the metal layer 18 exists independently, but can be connected to the first substrate-side electrode 12. In addition, it can be connected to the circuit formed on the first substrate 10.

[0124] Seventh Implementation Method

[0125] In the seventh embodiment, a semiconductor device having a characteristic structure of a bonding layer bonding the first base material 10 and the second base material 20 is described.

[0126] Fig.16 1 is a cross-sectional view of a semiconductor device 170 according to a seventh embodiment. The semiconductor device 170 includes a first substrate 10 and a second substrate 20 disposed on the first substrate 10. The structure of the bonding layer 19 is similar to that of the bonding layer 19 in the sixth embodiment. Fig.14 The example shown is different. The other structures are the same as those shown in the sixth embodiment.

[0127] The bonding layer 19 is a composite material layer including an insulator layer 17 and a metal layer 18. The insulator layer 17 is, for example, a Si compound layer such as a SiO2 film or a SiN film, or a resin layer such as a polyimide (PI) film. The metal layer 18 is, for example, a Cu film or an Al film. The bonding layer 19 has a five-layer structure. Fig.14 As in the example shown, the patterns of the metal layer 18 are formed in the vicinity of the second substrate 20 and in the vicinity of the first substrate-side electrode 12 .

[0128] The bonding layer 19 is formed through the following steps.

[0129] (1) On the surface of the first base material 10, the insulating layer 17 is formed as the first layer.

[0130] (2) The metal layer 18A is formed as the second layer on the surface of the insulating layer 17 .

[0131] (3) The insulating layer 17 is formed as the third layer on the surface of the metal layer 18 .

[0132] (4) An opening is formed at a predetermined position of the insulating layer 17 (a position where the lower metal layer 18A is to be formed).

[0133] (5) The metal layer 18C is formed on the insulating layer 17 , and the metal layer 18B is formed in the above-mentioned opening.

[0134] (6) The insulating layer 17 as the uppermost layer is formed.

[0135] According to the present embodiment, since the metal layer 18 has a multilayer structure, the thermal resistance of the bonding layer 19 is kept low even if the thickness of the bonding layer 19 is increased. Therefore, the heat dissipation of the circuit element 21 is high. In addition, since the heat capacity of the bonding layer 19 is increased, even if there is a sudden heat generation of the circuit element 21, the temperature rise suppression effect is also high.

[0136] In addition, similarly to the sixth embodiment, the metal layer 18 may be connected to the first substrate-side electrode 12. In addition, the metal layer 18 may be connected to the circuit formed on the first substrate 10.

[0137] The structure and effect of each embodiment are as shown above. If the methods disclosed in the embodiments are listed, they are as follows:

[0138] A semiconductor device as one embodiment of the present invention comprises: a substrate 1 having a circuit element 21 and an electrode connected to the circuit element on its surface; and a conductor column bump PB for external connection, which is arranged on the substrate 1 and connected to the electrode or the circuit element 21. The substrate 1 includes a first substrate 10 and a second substrate 20 arranged on the first substrate 10 and made of a material different from that of the first substrate 10. The circuit element 21 and the electrode are formed on the second substrate 20, and the thermal conductivity of the first substrate 10 is higher than that of the second substrate 20.

[0139] With the above structure, heat is dissipated through the conductor pillar bump PB and the first substrate 10. In other words, by forming a heat dissipation path from two surfaces, a higher heat dissipation performance can be obtained. In addition, since the circuit element is provided in the semiconductor region formed on the second substrate 20 which is not restricted by the high or low thermal conductivity, a circuit is formed that effectively utilizes the physical properties of the second substrate 20, and the high heat dissipation performance of the first substrate 10 can be maintained.

[0140] As a semiconductor device of one embodiment of the present disclosure, the first substrate 10 is a substrate of an elemental semiconductor, and the second substrate 20 is a substrate of a compound semiconductor. As such, since the first substrate 10 is a substrate of an elemental semiconductor, high heat dissipation is achieved overall by heat dissipation through the first substrate 10. In addition, since the second substrate 20 is a substrate of a compound semiconductor, its electrical insulation can be improved, and a circuit with excellent high-frequency characteristics can be provided.

[0141] The second base material 20 of the semiconductor device as one embodiment of the present disclosure is thinner than the first base material 10. Thus, a high heat dissipation effect of the first base material 10 is obtained.

[0142] The circuit element 21 of the semiconductor device as one embodiment of the present disclosure is a heating element that generates heat during operation, and the conductor post bump PB is provided near the circuit element 21 that is the heating element. With this structure, a shorter heat conduction path is formed through the conductor post bump PB, and the heat generated in the circuit element 21 is efficiently dissipated through the conductor post bump PB.

[0143] The second substrate 20 of the semiconductor device as one embodiment of the present disclosure does not protrude from the outer edge of the first substrate 10. With this structure, the thermal resistance of the substrate including the first substrate 10 and the second substrate 20 becomes lower, and a higher heat dissipation effect is obtained from the first substrate 10.

[0144] The semiconductor device as one embodiment of the present disclosure includes a bonding layer 11 between the first substrate 10 and the second substrate 20, which bonds the first substrate 10 and the second substrate 20. The bonding layer 11 is a metal having a higher thermal conductivity than the second substrate 20. With this structure, the thermal conductivity from the second substrate 20 to the first substrate 10 is ensured, and the heat dissipation (heat removal) of the first substrate 10 is maintained. In addition, the heat dissipation from the first substrate 10 through the bonding layer 11 is ensured. In other words, the heat dissipation from the first substrate 10 is not hindered by the bonding layer 11.

[0145] The bonding layer 11 of the semiconductor device as one embodiment of the present disclosure is made of metal and has a lower elastic modulus than the second base material 20. With this structure, thermal stress generated by the difference in linear expansion coefficient between the first base material 10 and the second base material 20 can be alleviated.

[0146] The bonding layer 11 of the semiconductor device as one embodiment of the present disclosure is metal, and an alloy layer of the bonding layer 11 and the first substrate 10 is formed between the bonding layer 11 and the first substrate 10. With this structure, high adhesion and high thermal conductivity are obtained between the first substrate 10 and the second substrate 20.

[0147] The semiconductor device as one embodiment of the present disclosure includes a bonding layer 11 between a first substrate 10 and a second substrate 20, the bonding layer 11 being a dielectric having a lower dielectric constant than the second substrate 20. With this structure, high-frequency loss of the first substrate 10 can be suppressed, and a circuit having excellent high-frequency characteristics can be provided.

[0148] The bonding layer 11 of the semiconductor device as one embodiment of the present disclosure is a dielectric and has a lower elastic modulus than the second base material 20. With this structure, thermal stress generated by the difference in linear expansion coefficient between the first base material 10 and the second base material 20 is alleviated.

[0149] The semiconductor device as one embodiment of the present disclosure includes a bonding layer 11 between a first substrate 10 and a second substrate 20, and the bonding layer 11 is an insulator having a higher resistivity than the first substrate 10. Thus, the electrical insulation between the first substrate 10 and the second substrate 20 is improved, and high-frequency loss due to the first substrate 10 is suppressed, so that a circuit with excellent high-frequency characteristics can be provided.

[0150] The bonding layer 11 of the semiconductor device as one embodiment of the present disclosure has a higher thermal conductivity than the first base material 10. Thus, the effective thermal resistance of the portion formed by the bonding layer 11 and the first base material 10 is reduced, and high heat dissipation is obtained.

[0151] The semiconductor device as one embodiment of the present disclosure includes a bonding layer 19 between the first substrate 10 and the second substrate 20, and the bonding layer 19 is a composite material layer including an insulator layer 17 and a metal layer 18. Thus, the stress between the first substrate 10 and the second substrate 20 generated due to the difference in linear expansion coefficient between the first substrate 10 and the second substrate 20 can be alleviated. In addition, due to the heat generation and stoppage of the circuit element 21 formed on the second substrate 20, the expansion and contraction of the second substrate 20 are more serious than the first substrate 10, but the stress at the interface between the second substrate 20 and the first substrate 10 generated thereby is alleviated.

[0152] The first substrate 10 of the semiconductor device as one embodiment of the present disclosure is a Si substrate, and the insulator layer 17 in the bonding layer 19 is a Si compound layer. This makes it easy to form the insulator layer 17 on the first substrate 10 and improves the bonding strength between the first substrate 10 and the insulator layer 17.

[0153] At least a portion of the insulator layer 17 of the semiconductor device as one embodiment of the present disclosure is made of resin. Thus, the insulator layer 17 can relieve stress generated between the metal layer 18 in the bonding layer 19 and the insulator layer 17 .

[0154] The semiconductor device as one embodiment of the present disclosure forms a first substrate-side electrode 12 on the surface of the first substrate 10 at a position not overlapping with the second substrate 20, and the conductor post bump PB is connected to the first substrate-side electrode 12. With this structure, a heat dissipation effect is obtained from the conductor post bump PB connected to the first substrate-side electrode 12. In addition, the heat conduction efficiency to the circuit substrate as the mounting destination is improved through the conductor post bump PB, and the heat dissipation on the circuit substrate is also improved.

[0155] As a method for manufacturing a semiconductor device in one embodiment of the present invention, the semiconductor device comprises: a substrate 1 having a circuit element 21 and an electrode connected to the circuit element 21 on its surface; and a conductor column bump PB for external connection, which is arranged on the substrate 1 and contacts and is electrically connected to the electrode or the circuit element 21, the substrate 1 includes a first substrate 10 and a second substrate 20 arranged on the first substrate 10, the circuit element 21 and the electrode are formed on the second substrate 20, and the method for manufacturing the semiconductor device comprises: a step of forming a semiconductor thin film having a circuit element 21 and an electrode on its surface on a mother substrate 200 of a compound semiconductor via a peeling layer 29; a step of peeling the semiconductor thin film from the mother substrate 200 of the compound semiconductor substrate by etching away the peeling layer 29; a step of joining the semiconductor thin film constituting the second substrate 20 to a predetermined position on the elemental semiconductor substrate constituting the first substrate 10, that is, the first substrate 10; and a step of forming a conductor column bump PB for external connection, which is arranged on the second substrate 20 and is connected to the electrode or the circuit element 21.

[0156] According to the above-mentioned manufacturing method, a compact and high-output semiconductor device or a high-output and small-sized semiconductor device can be obtained.

[0157] Finally, the description of the above-mentioned embodiments is illustrative at all points and is not restrictive. It is possible for those skilled in the art to appropriately modify and change. The scope of the present invention is not represented by the above-mentioned embodiments, but by the claims. Further, within the scope of the present invention, changes from the embodiments within the scope equivalent to the claims are included.

Claims

1. A semiconductor device comprising: A substrate having a circuit element and a second substrate-side electrode on a surface thereof; and The conductor protrusion for external connection is provided on the substrate and is in contact with and electrically connected to the second substrate-side electrode. The substrate includes: a first substrate, and a second substrate disposed on the first substrate and made of a material different from that of the first substrate. The circuit element is formed on the second substrate, and the second substrate-side electrode is formed on the circuit element. The thermal conductivity of the first substrate is higher than the thermal conductivity of the second substrate. The first substrate is an elemental semiconductor substrate. The second substrate is a compound semiconductor substrate. The second substrate does not protrude from an outer edge of the first substrate.

2. The semiconductor device according to claim 1, wherein A bonding layer for bonding the first substrate and the second substrate is provided between the first substrate and the second substrate. The bonding layer is a dielectric having a lower dielectric constant than that of the second base material.

3. The semiconductor device according to claim 1, wherein A bonding layer for bonding the first substrate and the second substrate is provided between the first substrate and the second substrate. The bonding layer is an insulator having a higher resistivity than the first base material.

4. The semiconductor device according to claim 1, wherein A bonding layer for bonding the first substrate and the second substrate is provided between the first substrate and the second substrate. The bonding layer is a composite material layer including an insulating layer and a metal layer.

5. The semiconductor device according to any one of claims 1 to 4, wherein: The second substrate includes a semiconductor substrate directly disposed on the first substrate, and an epitaxial layer formed on a surface of the semiconductor substrate.

6. The semiconductor device according to any one of claims 1 to 4, wherein: The circuit element is disposed on the second substrate.

7. The semiconductor device according to any one of claims 1 to 4, wherein: The circuit element is embedded in the second base material.

8. The semiconductor device according to any one of claims 1 to 4, wherein: The conductor protrusion is arranged to cover the plurality of circuit elements in a plan view.

9. The semiconductor device according to any one of claims 1 to 4, wherein: There are multiple heat dissipation paths for dissipating the heat generated by the above circuit elements.

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