Semiconductor device and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a three-dimensional integrated chip and a packaging substrate, the three-dimensional integrated chip comprises a system-on-chip and at least one storage chip; the three-dimensional integrated chip is connected to the packaging substrate through the salient point, and the three-dimensional integrated chip is connected to the salient point through the first silicon through hole; the three-dimensional integrated chip also includes a first heat dissipation channel surrounding the first through-silicon via, the first heat dissipation channel exposing the first sidewall layer surrounding the first through-silicon via.

Description

Technical Field

[0001] The present disclosure relates to the technical field of microchannel liquid cooling and heat dissipation, and in particular, to a semiconductor device and a method for manufacturing the same. Background Art

[0002] As the integration of electronic devices continues to increase, the computing speed gradually increases, and the size continues to shrink, the number of electronic components integrated per unit area continues to increase, and the heat generated also increases, resulting in an increase in the heat flux density of electronic devices. In addition, the performance and life of electronic devices are closely related to their temperature. Therefore, the temperature control of electronic devices is very prominent, and the heat dissipation capacity of electronic devices is particularly important.

[0003] In practical applications, with the development of microfluidic technology, coolant can be directly delivered to the inside of electrical devices, thereby achieving more efficient cooling to solve the heat dissipation problem of electrical devices. However, in the application of microfluidic technology, there are still many problems that need to be solved. Summary of the invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same.

[0005] To achieve the above purpose, the technical solution of the present disclosure is implemented as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a semiconductor device, comprising: a three-dimensional integrated chip and a packaging substrate; the three-dimensional integrated chip comprises a system-level chip and at least one memory chip; the three-dimensional integrated chip is connected to the packaging substrate via a bump, and the three-dimensional integrated chip is connected to the bump via a first through-silicon via; the three-dimensional integrated chip also comprises a first heat dissipation channel surrounding the first through-silicon via, and the first heat dissipation channel exposes a first sidewall layer surrounding the first through-silicon via.

[0007] In some embodiments, it also includes: a silicon adapter board; the three-dimensional integrated chip is connected to the packaging substrate through the silicon adapter board; wherein the three-dimensional integrated chip is connected to the silicon adapter board through a first bump, and the silicon adapter board is connected to the packaging substrate through a second bump; the silicon adapter board also includes a second through silicon via and a second heat dissipation channel surrounding the second through silicon via, and the second heat dissipation channel exposes a second sidewall layer surrounding the second through silicon via.

[0008] In some embodiments, the first heat dissipation channel surrounding the first through silicon via is a connected integral structure, and a liquid inlet and a liquid outlet are respectively provided at two ends of the integral structure along a first direction; the first direction is perpendicular to the stacking direction.

[0009] In some embodiments, the second heat dissipation channel surrounding the second through silicon via is a connected integral structure, and a liquid inlet and a liquid outlet are respectively provided at two ends of the integral structure along a first direction; the first direction is perpendicular to the stacking direction.

[0010] In some embodiments, a size of the first heat dissipation channel along the stacking direction is smaller than a size of the first through silicon via along the stacking direction; a size of the second heat dissipation channel along the stacking direction is smaller than a size of the second through silicon via along the stacking direction.

[0011] In some embodiments, the system-level chip and at least one memory chip are connected by hybrid bonding; a third silicon via extending along the stacking direction is formed in the system-level chip and the at least one memory chip, and the third silicon via is used to achieve chip interconnection.

[0012] In a second aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising: bonding a system-level chip and a substrate; the substrate comprising a first substrate and a second substrate bonded together; wherein the first substrate is located between the system-level chip and the second substrate; removing the second substrate to form a first silicon via that penetrates the first substrate and is connected to the system-level chip; removing the first substrate to form a first heat dissipation channel surrounding the first silicon via, the first heat dissipation channel exposing a first sidewall layer surrounding the first silicon via.

[0013] In some embodiments, before removing the second substrate, the method further includes: bonding the three-dimensional stacked chip to the system-level chip; the three-dimensional stacked chip includes a plurality of memory chips.

[0014] In some embodiments, a first through silicon via is formed that penetrates a first substrate and is connected to a system-level chip, including: forming a first through hole that penetrates the first substrate, the first through hole exposing an interconnection layer in the system-level chip; forming a first sidewall layer on an inner wall of the first through hole, and filling the first through hole to form a first through silicon via, the first through silicon via being connected to the interconnection layer in the system-level chip.

[0015] In some embodiments, a first through silicon via (TSV) is formed that penetrates a first substrate and is connected to a system-level chip, including: forming a first through hole that penetrates the first substrate, the first through hole exposing an interconnection layer in the system-level chip; filling the first through hole to form an initial sidewall layer; forming a second through hole in the initial sidewall layer, the second through hole exposing the interconnection layer in the system-level chip; filling the second through hole to form a first through silicon via, the first through silicon via being connected to the interconnection layer in the system-level chip.

[0016] In some embodiments, the substrate also includes a dielectric layer located between the first substrate and the second substrate; removing the second substrate to expose the dielectric layer; removing the first substrate to form a first heat dissipation channel surrounding the first silicon via, including: forming a third through hole penetrating the dielectric layer, the third through hole exposing the first substrate; removing the first substrate through the third through hole to form a first heat dissipation channel surrounding the first silicon via.

[0017] In some embodiments, the method further includes: depositing a dielectric material to close a third through hole penetrating the dielectric layer.

[0018] In some embodiments, the method further includes: forming a conductive layer in the dielectric layer, the conductive layer being connected to the first through silicon via; and forming a bump on the conductive layer.

[0019] In some embodiments, the ratio of the thickness of the second substrate to the thickness of the first substrate is in the range of 5-7.

[0020] In some embodiments, the first substrate has a thickness in the range of 50 μm-200 μm.

[0021] The disclosed embodiment provides a semiconductor device and a method for manufacturing the same, the semiconductor device comprising: a three-dimensional integrated chip and a packaging substrate; the three-dimensional integrated chip comprises a system-level chip and at least one memory chip; the three-dimensional integrated chip is connected to the packaging substrate via a bump, and the three-dimensional integrated chip is connected to the bump via a first through silicon via; the three-dimensional integrated chip also comprises a first heat dissipation channel surrounding the first through silicon via, the first heat dissipation channel exposing a first sidewall layer surrounding the first through silicon via. The disclosed embodiment provides a three-dimensional integrated chip having a first heat dissipation channel, the heat dissipation channel is integrated into the chip, has high heat dissipation efficiency, and the first heat dissipation channel exposes the sidewall of the first through silicon via, so that the coolant can dissipate heat from the first through silicon via through the first heat dissipation channel, thereby improving the heat dissipation performance and extending the service life of the device to be cooled. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1A A cross-sectional view of a semiconductor device provided in an embodiment of the present disclosure;

[0023] Figure 1B A top perspective view of a semiconductor device provided in accordance with an embodiment of the present disclosure;

[0024] Figure 2 A schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0025] Figures 3 to 16 A schematic diagram of a manufacturing process of a semiconductor device provided in an embodiment of the present disclosure.

[0026] In the above drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation. DETAILED DESCRIPTION

[0027] The following will be combined with the embodiments of the present disclosure and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0028] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0029] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0030] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0031] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0032] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0033] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0034] As the integration of electronic devices (such as chips) becomes higher and higher, the heat generated also increases. It is difficult to meet the demand for efficient heat dissipation through air cooling. Therefore, microchannel liquid cooling technology came into being. Microfluidic heat dissipation technology is a new type of heat dissipation solution. It introduces tiny channels and fine structures in the area around the chip, which can guide the coolant into the area around the chip to achieve rapid transfer and dissipation of the heat energy generated by the chip. In other words, heat dissipation technology can be used to allow liquid (usually water or special coolant) to flow through the tiny channels around the chip to take away the heat, thereby achieving heat dissipation on the chip surface. However, this heat dissipation method is usually for two-dimensional chips, and is not suitable for three-dimensional integrated chips.

[0035] Based on one or more of the above problems, the present disclosure provides a semiconductor device, referring to Figure 1A and Figure 1B , Figure 1AA cross-sectional view of a semiconductor device provided in an embodiment of the present disclosure, Figure 1B A top perspective view of a semiconductor device provided in an embodiment of the present disclosure, referring to Figure 1A The semiconductor device includes: a three-dimensional integrated chip 100 and a packaging substrate (not shown in the figure); the three-dimensional integrated chip 100 includes a system-level chip 10 and at least one memory chip 20; the system-level chip 10 is connected to the packaging substrate through a bump 11, and the three-dimensional integrated chip 100 is connected to the bump 11 through a first silicon via 12; the three-dimensional integrated chip 100 also includes a first heat dissipation channel 13 surrounding the first silicon via 12, and the first heat dissipation channel 13 exposes a first sidewall layer 121 surrounding the first silicon via 12.

[0036] Before describing the semiconductor device in detail, various directions that may be used in the following description are defined. In the present disclosure, the stacking direction of the three-dimensional integrated chip is defined as the Z direction (i.e., the vertical direction). In a plane perpendicular to the Z direction, a first direction (i.e., the X direction) and a second direction (i.e., the Y-axis direction) that intersect are defined. In some embodiments, the X direction, the Y direction, and the Z direction may be perpendicular to each other.

[0037] In the embodiment of the present disclosure, since the first TSV 12 has a relatively large thermal conductivity and the first heat dissipation channel 13 exposes the first TSV 12 , the heat dissipation efficiency of the semiconductor device can be greatly improved.

[0038] In some embodiments, the first heat dissipation channel 13 is located between the system-on-chip 10 and the packaging substrate.

[0039] In some embodiments, the memory chip 20 is configured to store data, and the system-level chip 10 (also called SOC Die) is configured to calculate the data. In the disclosed embodiment, the types of the system-level chip 10 include but are not limited to a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, an image processor (ISP) chip, an application processor (AP) chip, an embedded neural network processing unit (NPU) chip, and a video processing unit (VPU) chip. The types of memory chips 20 include, but are not limited to, dynamic random access memory (DRAM) chips, static random access memory (SRAM) chips, phase change random access memory (PRAM) chips, magnetoresistive random access memory (MRAM) chips, ferroelectric random access memory (FeRAM) chips, resistive random access memory (RRAM) chips, and flash memory (FlashMemory) chips. It should be noted that the three-dimensional integrated chip can improve performance, reduce the size, and improve energy efficiency by stacking multiple chips in the vertical direction, and the three-dimensional integrated chip can be applied to multiple fields, such as high-performance computing, artificial intelligence, the Internet of Things, cloud computing, and other fields. In this way, multiple chips can be stacked vertically to provide higher computing density and lower latency to meet the needs of these fields for high-performance computing and high storage density.

[0040] In the embodiment of the present disclosure, the system-level chip 10 is configured to calculate data. It can be understood that compared with the memory chip 20, the system-level chip 10 consumes more power and has a higher demand for heat dissipation. In the implementation of the present disclosure, the first heat dissipation channel 13 is arranged between the system-level chip 10 and the packaging substrate. In the three-dimensional integrated chip, the first heat dissipation channel 13 is closest to the system-level chip 10, thereby maximizing the heat dissipation efficiency of the system-level chip 10.

[0041] In some embodiments, the stacked system-on-chip 10 and the at least one memory chip 20 are connected by hybrid bonding.

[0042] In some embodiments, a third through silicon via (TSV) extending along the stacking direction (i.e., Z direction) is formed in the system-on-chip 10 and at least one memory chip 20. The third through silicon via is filled with conductive materials such as copper, tungsten, or polysilicon, thereby realizing vertical interconnection between different chips.

[0043] It is understandable that due to the high thermal conductivity of hybrid bonding and through silicon vias, the overall thermal conductivity of the semiconductor device is improved, the heat dissipation efficiency of each chip is enhanced, and the stability of the semiconductor device is improved.

[0044] refer to Figure 1A and Figure 1B The first heat dissipation channel 13 surrounding the first silicon through via 12 is a connected integral structure, and the two ends of the integral structure along the X direction are respectively provided with a liquid inlet 131 and a liquid outlet 132; the X direction is perpendicular to the stacking direction. The first heat dissipation channel in the embodiment of the present disclosure is a connected integral structure. Compared with the solution of combining the horizontal and vertical heat dissipation channels for heat dissipation, the embodiment of the present disclosure increases the heat dissipation area of ​​the first heat dissipation channel to the greatest extent. The integral structure is formed in the first substrate 14.

[0045] It can be understood that the first heat dissipation channel 13 surrounding the first through silicon via 12 is a connected integrated structure, which can increase the inner surface area of ​​the first heat dissipation channel 13 to the greatest extent, thereby improving the heat dissipation efficiency.

[0046] It should be noted that the first substrate 14 is not a substrate for forming the system-on-chip 10 .

[0047] In some embodiments, the liquid inlet 131 is used to introduce cooling liquid, and the liquid outlet 132 is used to discharge cooling liquid. In this way, the first heat dissipation channel 13 can introduce cooling liquid through the liquid inlet 131, and then discharge the cooling liquid through the liquid outlet 132, so that the cooling liquid takes away the heat of the three-dimensional integrated chip, thereby achieving heat dissipation of the three-dimensional integrated chip.

[0048] In some embodiments, the coolant may include water, a solution containing a magnetic fluid, an organic acid, or any other liquid suitable for cooling. In other embodiments, a gas for cooling may be introduced into the first heat dissipation channel through the liquid inlet; this is not limited in the present disclosure. In order to facilitate a clear understanding of the present disclosure, the coolant is used as an example of the gas or liquid for cooling in the following description.

[0049] It should be noted that Figure 1Aand Figure 1B The liquid inlet 131 and the liquid outlet 132 of the first heat dissipation channel 13 are for illustration only. The first heat dissipation channel 13 circulates the coolant through the liquid inlet 131 and the liquid outlet 132. The present disclosure does not limit the specific location of the liquid inlet 131 and the liquid outlet 132. In the embodiment of the present disclosure, the specific shape and size of the first heat dissipation channel 13, and the specific location of the liquid inlet 131 and the liquid outlet 132 can be adaptively adjusted according to the actual structure of the semiconductor device.

[0050] In some embodiments, the size of the first heat dissipation channel 13 along the stacking direction is smaller than the size of the first silicon via 12 along the stacking direction. Therefore, even if the first heat dissipation channel 13 is a connected integrated structure, the first silicon via 12 can support the device as a supporting structure to prevent collapse.

[0051] In some embodiments, the first heat dissipation channel 13 exposes a partial side surface of the first through silicon via 12 in the Z direction. The first through silicon via 12 may include an end surface and a side surface, wherein one of the two end surfaces of the first through silicon via 12 in the Z direction is connected to the interconnect layer in the system-level chip 10, and the other is connected to the bump. The side surface of the first through silicon via 12 is surrounded by the first sidewall layer 121.

[0052] In the disclosed embodiment, the first heat dissipation channel 13 is a three-dimensional channel extending in the three-dimensional integrated chip 100, so that the first silicon through-via 12 can be cooled in multiple directions (360° around), so that the heat dissipation efficiency of the three-dimensional integrated chip is further improved.

[0053] In some embodiments, the semiconductor device also includes: a silicon adapter board (not shown in the figure); the three-dimensional integrated chip is connected to the packaging substrate through the silicon adapter board; wherein the three-dimensional integrated chip is connected to the silicon adapter board through a first bump, and the silicon adapter board is connected to the packaging substrate through a second bump; the silicon adapter board also includes a second through silicon via and a second heat dissipation channel surrounding the second through silicon via, and the second heat dissipation channel exposes a second sidewall layer surrounding the second through silicon via.

[0054] In some embodiments, the silicon transfer board is located between the system-level chip 10 and the packaging substrate. The second heat dissipation channel is located between the first heat dissipation channel 13 and the packaging substrate. The first heat dissipation channel 13 and the second heat dissipation channel are both located between the system-level chip 10 and the packaging substrate.

[0055] In some embodiments, the second heat dissipation channel surrounding the second through silicon via is a connected integral structure, and the two ends of the integral structure along the first direction are respectively provided with a liquid inlet and a liquid outlet; the first direction is perpendicular to the stacking direction. It can be understood that the second heat dissipation channel surrounding the second through silicon via is a connected integral structure, which can maximize the inner surface area of ​​the second heat dissipation channel, thereby improving the heat dissipation efficiency.

[0056] In the disclosed embodiment, the second heat dissipation channel is a three-dimensional channel extending in the silicon adapter plate, so that the second silicon through-hole can be cooled in all directions (360° around), so that the heat dissipation efficiency of the three-dimensional integrated chip is further improved.

[0057] The liquid inlet of the second heat dissipation channel is used to introduce the coolant, and the liquid outlet of the second heat dissipation channel is used to discharge the coolant. In this way, the second heat dissipation channel can introduce the coolant through the liquid inlet and then discharge the coolant through the liquid outlet, so that the coolant takes away the heat of the three-dimensional integrated chip, thereby achieving heat dissipation of the three-dimensional integrated chip.

[0058] In some embodiments, the size of the second heat dissipation channel along the stacking direction is smaller than the size of the second silicon through via along the stacking direction. In other words, the second heat dissipation channel exposes a partial side surface of the second silicon through via in the Z direction. The second silicon through via may include an end surface and a side surface, wherein one of the two end surfaces of the second silicon through via along the Z direction is connected to the first bump and the other is connected to the second bump. The side surface of the second silicon through via is surrounded by the second sidewall layer.

[0059] It should be noted that the second heat dissipation channel has the same structure as the first heat dissipation channel, and the structure of the second heat dissipation channel can be understood with reference to the first heat dissipation channel.

[0060] In an embodiment of the present disclosure, a three-dimensional integrated chip with a first heat dissipation channel is provided. The heat dissipation channel is integrated in the chip and has high heat dissipation efficiency. The first heat dissipation channel exposes the side wall of the first through silicon via, so that the coolant can dissipate heat to the first through silicon via through the first heat dissipation channel, thereby improving the heat dissipation performance and extending the service life of the device to be cooled. Furthermore, in an embodiment of the present disclosure, a second heat dissipation channel can also be set in the silicon adapter board, and the second heat dissipation channel exposes the side wall of the second through silicon via, so that the coolant can dissipate heat to the second through silicon via through the second heat dissipation channel, thereby further improving the heat dissipation performance. Furthermore, the semiconductor device provided by the present disclosure has a simple structure, is easy to operate, and is suitable for large-scale mass production.

[0061] Based on the above semiconductor device, the present disclosure also provides a method for manufacturing a semiconductor device, referring to Figure 2 , Figure 2 The present invention is a schematic flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present invention; the manufacturing method comprises the following steps:

[0062] Step S201: bonding the system-level chip to a substrate; the substrate comprises a first substrate and a second substrate that are bonded to each other; wherein the first substrate is located between the system-level chip and the second substrate.

[0063] Step S202: removing the second substrate, and forming a first through silicon via penetrating the first substrate and connected to the system-on-chip.

[0064] Step S203: removing the first substrate to form a first heat dissipation channel surrounding the first through silicon via, wherein the first heat dissipation channel exposes a first sidewall layer surrounding the first through silicon via.

[0065] It should be understood that Figure 2 The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; Figure 2 The steps shown in the figure can be adjusted in sequence according to actual needs. Figures 3 to 16 The schematic diagram of the formation process of the three-dimensional integrated chip provided in the embodiment of the present disclosure is as follows: Figures 3 to 16 This is a complete schematic diagram of the implementation process of the manufacturing method of the semiconductor device. The unmarked parts in some drawings can be shared with each other. Figures 3 to 16 The manufacturing method of the semiconductor device provided by the embodiment of the present disclosure is introduced in detail.

[0066] refer to Figure 3 , providing a substrate 300; the substrate 300 includes a first substrate 301 and a second substrate 302 bonded together. The thickness of the second substrate 302 is greater than the thickness of the first substrate 301. It should be noted that, Figure 3 The dashed lines in the figure are used to illustrate the bonding interface.

[0067] The substrate 300 is formed by bonding a first substrate 301 and a second substrate 302, and the bonding connection includes direct bonding or fusion bonding. Before bonding the first substrate 301 and the second substrate 302, a dielectric layer is formed on two surfaces of the first substrate 301 along the Z direction, and a dielectric layer is formed on one of the two surfaces of the second substrate 302 along the Z direction by a thermal oxidation process or a CVD process. When bonding the first substrate 301 and the second substrate 302, the surface of the second substrate 302 formed with the dielectric layer is used as a bonding surface to bond with the first substrate 301.

[0068] In some embodiments, the first substrate 301 is a first wafer, and the second substrate 302 is a second wafer.

[0069] In some embodiments, the substrate 300 further includes a dielectric layer 303 located between the first substrate 301 and the second substrate 302. The material of the dielectric layer 303 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide, and the deposition process of the dielectric layer 303 can be thermal oxidation, chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.

[0070] In some embodiments, the ratio of the thickness of the second substrate 302 to the thickness of the first substrate 301 is in the range of 5-7.

[0071] In some embodiments, the thickness of the first substrate 301 is in the range of 50 μm-200 μm.

[0072] In a specific example, the thickness of the first substrate 301 is 100 μm, and the thickness of the second substrate 302 is 775 μm.

[0073] refer to Figure 4 , the system-level chip 400 and the substrate 300 are bonded and connected, and the bonding connection includes direct bonding connection or fusion bonding connection. Among them, the two surfaces of the system-level chip 400 along the Z direction are the first surface and the second surface, and the first surface of the system-level chip 400 is bonded and connected to the substrate 300. It should be noted that, Figure 4 The dashed lines in the figure are used to illustrate the bonding interface.

[0074] In some embodiments, the system-level chip 400 is formed on a third wafer, and a plurality of system-level chips 400 are formed on the third wafer. The bonding of the system-level chip 400 and the substrate 300 is the bonding between the third wafer and the first wafer and the second wafer bonded together.

[0075] refer to Figure 5 , a thinning process is performed on the second surface of the system-on-chip 400 to thin the substrate 401 of the system-on-chip 400 to 3 μm-10 μm. The thinning process includes a chemical mechanical planarization (CMP) process.

[0076] refer to Figure 6 , forming a third through silicon via 403 penetrating through the substrate 401 and connected to the interconnection layer 402 in the system-on-chip 400. The material of the third through silicon via 403 may be at least one of aluminum, copper, gold and tungsten.

[0077] The system-on-chip 400 includes an interconnection layer 402, which is used to realize electrical connection between the system-on-chip 400 and external circuits. The interconnection layer 402 is formed by a back end of line (BEOL) process.

[0078] refer to Figure 7 , the three-dimensional stacked chip 500 is bonded to the system-level chip 400; the three-dimensional stacked chip 500 includes a plurality of memory chips 501. The bonding connection includes a hybrid bonding connection (also known as a "metal / dielectric hybrid bonding connection"), which is a direct bonding technology, for example, forming a bond between surfaces without using an intermediate layer such as solder or adhesive, and can simultaneously obtain metal-metal bonding and dielectric-dielectric bonding. The third silicon through-hole via 402 in the system-level chip 400 is used for vertical interconnection with the three-dimensional stacked chip 500.

[0079] In some embodiments, the three-dimensional stacked chip 500 is bonded to the supporting wafer 502 , and the bonding of the three-dimensional stacked chip 500 to the system-level chip 400 is the bonding between the supporting wafer 502 and the bonded first wafer, second wafer and third wafer.

[0080] In some embodiments, third through silicon vias (not shown in the figure) are formed in the plurality of memory chips 501 , and the third through silicon vias are used to realize vertical interconnection between different chips.

[0081] refer to Figure 8 ,Will Figure 7 The structure shown is turned over to perform a backside thinning process to remove the second substrate 302. The backside thinning process includes a CMP process. After removing the second substrate 302, the oxide layer 303 is exposed.

[0082] refer to Fig. 9 , forming a first through hole penetrating the first substrate 301, the first through hole exposing the interconnection layer 402 in the system-level chip 400; filling the first through hole to form an initial sidewall layer 601'. The method of forming the first through hole includes but is not limited to etching, and the etching includes dry etching, wet etching, and laser etching.

[0083] refer to Fig.10 , a second through hole is etched in the initial sidewall layer 601', the second through hole exposes the interconnection layer 402 in the system-level chip 400, and the remaining initial sidewall layer 601' serves as the first sidewall layer 601; a first through silicon via 602 is filled in the second through hole, and the first through silicon via 602 is connected to the interconnection layer in the system-level chip 400. The material of the first sidewall layer 601 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The material of the first through silicon via 602 may be at least one of aluminum, copper, gold, and tungsten.

[0084] refer to Fig.11 , forming a third through hole 603 penetrating the dielectric layer 203 , wherein the third through hole 603 exposes the first substrate 201 .

[0085] Fig.12 for Fig.11 The top perspective view of the structure shown in FIG. 1 shows the first substrate 301 under the dielectric layer 303. The arrangement of the third through hole 603 and the first silicon through hole 602 can refer to FIG. Fig.12 .like Fig.12 As shown, the third through holes 603 are distributed around the first through silicon via 602, and specifically include a plurality of third through holes 603 arranged along the second direction (X direction) and a plurality of third through holes 603 arranged along the third direction (Y direction). It should be noted that, Fig.12 The number of the third through holes 603 shown in the figure is only an example. The number of the third through holes 603 in the present disclosure is not limited to Fig.12 Quantity shown.

[0086] refer to Fig.13 , the first substrate 301 is removed through the third through hole 603 to form a first heat dissipation channel 700 surrounding the first through silicon via 602 .

[0087] Fig.14 for Fig.13 A top perspective view of the structure shown, such as Fig.14 As shown, the first heat dissipation channel 700 surrounding the first TSV is a connected integrated structure, and the integrated structure exposes all of the first TSV 602 .

[0088] refer to Fig.15 , a dielectric material is deposited to close the third through hole 603 penetrating the dielectric layer 303. The dielectric material is the same as the material of the dielectric layer 303. The process of depositing the dielectric material includes but is not limited to physical vapor deposition (PVD, Physical Vapor Deposition), CVD, ALD and other processes.

[0089] It should be noted that after the dielectric material is deposited to seal the three through holes 603 , the dielectric layer 303 will be thickened to a certain extent.

[0090] refer to Fig.16 , a conductive layer 801 is formed in the dielectric layer 303, and the conductive layer 801 is connected to the first through silicon via 604; a bump 802 is formed on the conductive layer 801. Here, the conductive layer 801 serves as a bump bottom metal layer (UBM), and the bump 802 is connected to the first through silicon via 602 through the bump bottom metal layer (UBM). The bump 802 is used to electrically connect to the packaging substrate, or to electrically connect to the silicon interposer.

[0091] In some embodiments, the conductive layer 801 may be made of any suitable conductive material, including Cu, Ni, Pt, Al or any combination thereof, and may be formed by any suitable technique, such as PVD, CVD, electrochemical deposition (ECD), molecular beam epitaxy (MBE), ALD, electroplating, etc. In the disclosed embodiment, the conductive layer 801 and the first through silicon via 604 are made of the same material, both made of copper (Cu).

[0092] In some embodiments, the material of the bump 802 may include at least one or more of the following metals: copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), zinc (Zn), and tungsten (W).

[0093] exist Fig.16 After the multi-layer stacked bonded wafer is formed, the multi-layer stacked bonded wafer is cut into a plurality of three-dimensional integrated chips by a wafer cutting process. Then, the three-dimensional integrated chip is electrically connected to the packaging substrate through the bumps, or the three-dimensional integrated chip is electrically connected to the packaging substrate through the bumps and the silicon adapter plate to form a semiconductor device. Here, the semiconductor device can also be a packaging device.

[0094] In an embodiment of the present disclosure, a three-dimensional integrated chip with a first heat dissipation channel is provided. The heat dissipation channel is integrated in the chip and has high heat dissipation efficiency. The first heat dissipation channel exposes the side wall of the first through silicon via, so that the coolant can dissipate heat to the first through silicon via through the first heat dissipation channel, thereby improving the heat dissipation performance and extending the service life of the device to be cooled. Furthermore, in an embodiment of the present disclosure, a second heat dissipation channel can also be set in the silicon adapter board, and the second heat dissipation channel exposes the side wall of the second through silicon via, so that the coolant can dissipate heat to the second through silicon via through the second heat dissipation channel, thereby further improving the heat dissipation performance. Furthermore, the semiconductor device provided by the present disclosure has a simple structure, is easy to operate, and is suitable for large-scale mass production.

[0095] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0096] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: A three-dimensional integrated chip and a packaging substrate; the three-dimensional integrated chip includes a system-level chip and at least one memory chip; The three-dimensional integrated chip is connected to the packaging substrate through a bump, and the three-dimensional integrated chip is connected to the bump through a first through silicon via; The three-dimensional integrated chip further includes a first heat dissipation channel surrounding the first through silicon via, wherein the first heat dissipation channel exposes a first sidewall layer surrounding the first through silicon via.

2. The semiconductor device according to claim 1, wherein: Also includes: Silicon adapter board; The three-dimensional integrated chip is connected to the packaging substrate through the silicon adapter plate; wherein the three-dimensional integrated chip is connected to the silicon adapter plate through the first bump, and the silicon adapter plate is connected to the packaging substrate through the second bump; The silicon interposer further includes a second through silicon via and a second heat dissipation channel surrounding the second through silicon via, wherein the second heat dissipation channel exposes a second sidewall layer surrounding the second through silicon via.

3. The semiconductor device according to claim 1, wherein: The first heat dissipation channel surrounding the first through silicon via is a connected integral structure, and a liquid inlet and a liquid outlet are respectively provided at two ends of the integral structure along a first direction; the first direction is perpendicular to the stacking direction.

4. The semiconductor device according to claim 2, characterized in that The second heat dissipation channel surrounding the second through silicon via is a connected integral structure, and a liquid inlet and a liquid outlet are respectively provided at two ends of the integral structure along a first direction; the first direction is perpendicular to the stacking direction.

5. The semiconductor device according to claim 2, wherein: The size of the first heat dissipation channel along the stacking direction is smaller than the size of the first through silicon via along the stacking direction; the size of the second heat dissipation channel along the stacking direction is smaller than the size of the second through silicon via along the stacking direction.

6. The semiconductor device according to claim 1, wherein: The system-level chip and at least one of the memory chips are connected via hybrid bonding; A third through silicon via extending along the stacking direction is formed in the system-level chip and at least one of the memory chips, and the third through silicon via is used to realize chip interconnection.

7. A method for manufacturing a semiconductor device, characterized in that: The method comprises: Bonding the system-level chip to a substrate; the substrate comprises a first substrate and a second substrate bonded to each other; wherein the first substrate is located between the system-level chip and the second substrate; removing the second substrate, and forming a first through silicon via penetrating the first substrate and connected to the system-level chip; The first substrate is removed to form a first heat dissipation channel surrounding the first through silicon via, wherein the first heat dissipation channel exposes a first sidewall layer surrounding the first through silicon via.

8. The manufacturing method according to claim 7, characterized in that: Before removing the second substrate, the method further includes: The three-dimensional stacked chip is bonded to the system-level chip; the three-dimensional stacked chip includes a plurality of memory chips.

9. The manufacturing method according to claim 7, characterized in that: Forming a first through silicon via penetrating the first substrate and connected to the system-level chip, comprising: forming a first through hole penetrating the first substrate, wherein the first through hole exposes an interconnection layer in the system-on-chip; A first sidewall layer is formed on the inner wall of the first through hole, and a first through silicon via is filled in the first through hole, wherein the first through silicon via is connected to an interconnection layer in the system-on-chip.

10. The manufacturing method according to claim 7, characterized in that: Forming a first through silicon via penetrating the first substrate and connected to the system-level chip, comprising: forming a first through hole penetrating the first substrate, wherein the first through hole exposes an interconnection layer in the system-on-chip; Filling the first through hole to form an initial sidewall layer; forming a second through hole in the initial sidewall layer, the second through hole exposing an interconnect layer in the system-on-chip; A first through silicon via is formed by filling the second through hole, wherein the first through silicon via is connected to an interconnection layer in the system-on-chip.

11. The manufacturing method according to claim 9 or 10, characterized in that: The substrate further includes a dielectric layer located between the first substrate and the second substrate; removing the second substrate to expose the dielectric layer; Removing the first substrate to form a first heat dissipation channel surrounding the first through silicon via comprises: forming a third through hole penetrating the dielectric layer, wherein the third through hole exposes the first substrate; The first substrate is removed through the third through hole to form a first heat dissipation channel surrounding the first through silicon via.

12. The manufacturing method according to claim 11, characterized in that: The method further comprises: A dielectric material is deposited to close the third through hole penetrating the dielectric layer.

13. The manufacturing method according to claim 12, characterized in that: The method further comprises: forming a conductive layer in the dielectric layer, wherein the conductive layer is connected to the first through silicon via; Bumps are formed on the conductive layer.

14. The manufacturing method according to claim 7, characterized in that: The ratio of the thickness of the second substrate to the thickness of the first substrate is in the range of 5-7.

15. The manufacturing method according to claim 7, characterized in that: The thickness of the first substrate is in the range of 50 μm to 200 μm.

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