Packaging structure and packaging method

Abstract

The embodiment of the invention discloses a packaging structure and a packaging method. The packaging structure comprises a stacking structure and a bonding substrate, the stacking structure comprises a plurality of chips which are stacked in sequence; the bonding substrate is located between the packaging substrate and the stacking structure and comprises a first substrate, a second substrate and a passivation layer, the first substrate and the second substrate are connected in a bonding mode, at least one of the first substrate and the second substrate is provided with a heat dissipation channel for heat dissipation media to circulate, and the passivation layer covers the surface, making contact with the heat dissipation media, of the heat dissipation channel.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor packaging technology, and are related to but not limited to a packaging structure and a packaging method. Background Art

[0002] Three Dimensions (3D) stacking packaging technology, also known as stacked chip packaging technology, is a packaging technology that stacks two or more chips vertically in the same packaging structure without changing the planar dimensions of the packaging structure. By stacking multiple chips in three dimensions, larger storage capacity, higher bandwidth, and greater computing power can be achieved, significantly improving the performance of the packaged device.

[0003] However, since multiple chips are stacked closely in the vertical direction, it becomes more difficult to dissipate the heat of the chip. If the heat generated by the chip during operation is difficult to dissipate quickly, the temperature of the chip will be too high, affecting the performance and reliability of the chip, and in severe cases, the chip may be damaged. Therefore, how to improve the heat dissipation performance of the packaging structure has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] According to a first aspect of an embodiment of the present disclosure, a packaging structure is provided, comprising: a stacking structure, a bonding substrate and a packaging substrate, wherein the bonding substrate is located between the stacking structure and the packaging substrate; the stacking structure comprises a plurality of chips stacked in sequence; the bonding substrate comprises a first substrate, a second substrate and a passivation layer, wherein the first substrate is located between the packaging substrate and the second substrate and is bonded to the second substrate, wherein the first substrate has a first heat dissipation channel for circulating a heat dissipation medium, and the passivation layer covers the surface where the first heat dissipation channel contacts the heat dissipation medium.

[0005] In some embodiments, the packaging substrate has a second heat dissipation channel for the heat dissipation medium to flow through, wherein the second heat dissipation channel is connected to the first heat dissipation channel.

[0006] In some embodiments, the first heat dissipation channel includes a first input channel and a first output channel; the second heat dissipation channel includes a second input channel and a second output channel, wherein the second input channel is connected to the first input channel, and the second output channel is connected to the first output channel.

[0007] In some embodiments, the packaging structure further includes an input pipeline and an output pipeline, wherein the input pipeline, the output pipeline and the bonding substrate are located on the same side of the packaging substrate, wherein the input pipeline is connected to the second input channel, and the output pipeline is connected to the second output channel.

[0008] In some embodiments, the first substrate includes a first carrier and a first dielectric layer, the first dielectric layer is located between the first carrier and the second substrate, wherein the first heat dissipation channel extends into the first carrier along a surface of the first dielectric layer relatively away from the first carrier, and the passivation layer covers a surface of the first dielectric layer relatively away from the first carrier;

[0009] The second substrate includes a second dielectric layer and a bonding layer, wherein the bonding layer is located between the second dielectric layer and the first substrate, wherein the second dielectric layer is bonded to the stacked structure, and the bonding layer is bonded to the passivation layer.

[0010] In some embodiments, the material of the bonding layer is the same as the material of the passivation layer.

[0011] In some embodiments, the material of the passivation layer includes silicon nitride.

[0012] In some embodiments, the bonding substrate also includes a connecting structure and a first bonding contact, the connecting structure extending through the second substrate and the first substrate, the first bonding contact being located on a side of the connecting structure relatively away from the packaging substrate and connected to the connecting structure, wherein the connecting structure and the first heat dissipation channel are spaced apart from each other, and the first bonding contact is engaged with a second bonding contact of the stacking structure.

[0013] In some embodiments, a cross-sectional dimension of the connection structure relatively close to the packaging substrate is smaller than or equal to a cross-sectional dimension of the connection structure relatively far from the packaging substrate.

[0014] In some embodiments, the bonding substrate also includes a connecting structure and a bump, the connecting structure extending through the second substrate and the first substrate, the bump being located on a side of the connecting structure relatively close to the packaging substrate and connected to the connecting structure, wherein the connecting structure and the first heat dissipation channel are spaced apart from each other, and the connecting structure is connected to the chip.

[0015] In some embodiments, a cross-sectional dimension of the connection structure relatively close to the packaging substrate is greater than or equal to a cross-sectional dimension of the connection structure relatively far from the packaging substrate.

[0016] According to a second aspect of an embodiment of the present disclosure, a packaging method is provided, comprising: forming a stacking structure, the stacking structure comprising a plurality of chips stacked in sequence; forming a bonding substrate, the bonding substrate comprising a first substrate, a second substrate and a passivation layer, the first substrate and the second substrate being bonded together, wherein the first substrate has a first heat dissipation channel for a heat dissipation medium to flow through, and the passivation layer covers a surface where the first heat dissipation channel and the heat dissipation medium are in contact; packaging the bonding substrate and the stacking structure to one side of a packaging substrate, such that the bonding substrate is located between the packaging substrate and the stacking structure, wherein the first substrate is located between the packaging substrate and the second substrate.

[0017] In some embodiments, the forming of the bonding substrate includes: forming a first dielectric layer on one side of a first carrier; etching the first dielectric layer to form the first heat dissipation channel extending into the first carrier; forming the passivation layer covering the surface of the first dielectric layer and the surface of the first heat dissipation channel; sequentially forming a second dielectric layer and a bonding layer on one side of a second carrier; bonding the first carrier having the passivation layer formed thereon and the second carrier having the bonding layer formed thereon so that the bonding layer and the passivation layer are bonded; and removing the second carrier to form the bonding substrate.

[0018] In some embodiments, the forming of the bonding substrate further includes: etching the second dielectric layer to form a connecting hole extending into the first carrier, wherein the connecting hole and the first heat dissipation channel are spaced apart from each other, and the cross-sectional size of the bottom of the connecting hole is less than or equal to the cross-sectional size of the top of the connecting hole; filling the connecting hole with a conductive material to form a connecting structure; forming a first bonding contact on the exposed surface of the connecting structure, the first bonding contact connecting the connecting structure; the packaging method further includes: bonding the bonding substrate and the stacking structure so that the first bonding contact and the second bonding contact of the stacking structure are joined; thinning the first carrier until the connecting structure is exposed.

[0019] In some embodiments, the packaging method also includes: bonding the bonding substrate and the stacking structure so that the second dielectric layer and the stacking structure are joined; thinning the first carrier to a preset thickness, wherein the preset thickness is greater than the height of the first heat dissipation channel located in the first carrier; forming the bonding substrate also includes: etching the thinned first carrier to form a connecting hole extending into the stacking structure, wherein the connecting hole and the first heat dissipation channel are spaced apart from each other, and the cross-sectional size of the bottom of the connecting hole is less than or equal to the cross-sectional size of the top of the connecting hole; filling the connecting hole with a conductive material to form a connecting structure; and forming a bump on the exposed surface of the connecting structure, wherein the bump connects the connecting structure.

[0020] In some embodiments, the packaging method also includes: after forming the bump, etching the thinned first carrier to form a first input channel and a first output channel of the first heat dissipation channel; packaging the bonding substrate and the stacking structure to one side of the packaging substrate includes: packaging the bonded bonding substrate and the stacking structure to one side of the packaging substrate so that the bump is connected to the circuit on the packaging substrate, wherein the first input channel is connected to the second input channel on the packaging substrate, and the first output channel is connected to the second output channel on the packaging substrate.

[0021] In some embodiments, the packaging method further includes: installing an input pipeline and an output pipeline on one side of the packaging substrate, wherein the input pipeline is communicated with the second input channel, and the output pipeline is communicated with the second output channel.

[0022] In the disclosed embodiment, the packaging structure includes a stacking structure, a bonding substrate and a packaging substrate, the bonding substrate is located between the stacking structure and the packaging substrate, the stacking structure includes a plurality of chips stacked in sequence, the bonding substrate includes a first substrate, a second substrate and a passivation layer, the first substrate is located between the packaging substrate and the second substrate and is bonded to the second substrate, the first substrate has a first heat dissipation channel for the circulation of a heat dissipation medium, and the passivation layer covers the surface where the first heat dissipation channel and the heat dissipation medium contact. In this way, on the first hand, since the bonding substrate with the first heat dissipation channel is located between the packaging substrate and the stacking structure, the first heat dissipation channel is closer to the bottom chip in the stacking structure, by adding a circulated heat dissipation medium to the first heat dissipation channel, the heat dissipation medium can take away the heat generated by the bottom chip in time, achieve a better heat dissipation effect, and help improve the heat dissipation performance of the packaging structure; on the second hand, since the surface where the first heat dissipation channel and the heat dissipation medium contact is covered with a passivation layer, the passivation layer can prevent the heat dissipation medium from causing leakage between devices, corroding the heat dissipation channel and causing the heat dissipation channel to be blocked. On the third hand, the packaging structure is simple in structure and easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application.

[0024] Figure 1 It is a schematic diagram of a packaging structure provided by an exemplary embodiment.

[0025] Figure 2 It is a schematic diagram of a packaging structure provided by an embodiment of the present disclosure.

[0026] Figure 3 It is a schematic diagram of a packaging structure provided by an embodiment of the present disclosure, which is equipped with an input pipeline and an output pipeline.

[0027] Figure 4 It is a flow chart of a packaging method provided by an embodiment of the present disclosure.

[0028] Figure 5A and Figure 5B It is a schematic diagram of forming a stacking structure provided by an embodiment of the present disclosure.

[0029] Figures 6 to 18 It is a schematic diagram of forming a bonding substrate provided by an embodiment of the present disclosure.

[0030] Figures 19 to 21 It is a schematic diagram of forming a packaging structure provided by an embodiment of the present disclosure.

[0031] Figure 22 to Figure 25 It is a schematic diagram of another packaging structure provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] In order to facilitate the understanding of the present disclosure, the exemplary embodiments of the present disclosure will be described in more detail below with reference to the relevant drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0033] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In some embodiments, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of the actual embodiment may not be described here, and well-known functions and structures may not be described in detail.

[0034] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or characteristics in a plural sense. Similarly, terms such as "one" or "the" can also be understood to convey singular usage or to convey plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.

[0035] Unless otherwise defined, the purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0036] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0037] Before introducing the embodiments of the present disclosure, various directions that may be involved in the following description are defined. In a plane parallel to the semiconductor layer, the intersecting x-direction and y-direction are defined, and the direction perpendicular to the plane of the semiconductor layer is defined as the z-direction. The x-direction and the y-direction intersect, and the angle between the x-direction and the y-direction includes an acute angle, a right angle, or an obtuse angle. For ease of understanding, the angle between the x-direction and the y-direction will be taken as a right angle below, that is, the x-direction, the y-direction, and the z-direction are perpendicular to each other.

[0038] In today's three-dimensional stacking process, memory chips and logic chips can be stacked up and down to effectively improve computing performance. However, during the operation of high-performance chips, a large amount of heat energy is easily generated on the memory chips and logic chips. Due to the three-dimensional integrated packaging structure, the geothermal energy is concentrated, resulting in poor heat dissipation performance of the packaged devices, leading to energy efficiency and performance degradation of three-dimensional integrated devices. Therefore, how to solve the heat dissipation problem of three-dimensional integrated devices has become the key to industry development research. The following will combine Figure 1 An exemplary description is given.

[0039] Figure 1 1 is a schematic diagram of a three-dimensional integrated device provided by an exemplary embodiment, wherein the three-dimensional integrated device includes but is not limited to a high-performance storage and computing integrated chip, for example, a high bandwidth memory (HBM). Figure 1 As shown, the three-dimensional integrated device 10 includes a first chip 11, a second chip 12 and a plurality of third chips 13 stacked in sequence. The first chip 11 includes but is not limited to a system-on-chip (SoC), on which at least one of a central processing unit (CPU), a graphics processing unit (GPU), a neural network processor (NPU), a video processor (VPU), and a digital signal processor (DSP) is integrated. The second chip 12 includes but is not limited to a logic chip, which includes various control circuits for controlling the memory chip to perform logic operations. The third chip 13 includes but is not limited to a memory chip, which includes but is not limited to a dynamic random access memory (DRAM). By stacking and packaging the first chip 11, the second chip 12 and a plurality of third chips 13 in sequence, a large-capacity, high-bandwidth memory array can be realized.

[0040] However, Figure 1 In the three-dimensional integrated device shown, the heat dissipation performance of the lower half area where the first chip 11 and the second chip 12 are located is poor. The heat generated by the first chip 11 and the second chip 12 is difficult to dissipate through an external heat sink or fan, thereby limiting the improvement of the heat dissipation performance of the three-dimensional integrated device.

[0041] Based on one or more of the above technical problems, the embodiment of the present disclosure provides a packaging structure. The packaging structure includes: a stacking structure, a bonding substrate and a packaging substrate, the bonding substrate is located between the stacking structure and the packaging substrate; the stacking structure includes a plurality of chips stacked in sequence; the bonding substrate includes a first substrate, a second substrate and a passivation layer, the first substrate is located between the packaging substrate and the second substrate and is bonded to the second substrate, wherein the first substrate has a first heat dissipation channel for the circulation of the heat dissipation medium, and the passivation layer covers the surface where the first heat dissipation channel and the heat dissipation medium contact. In this way, on the first aspect, since the bonding substrate with the first heat dissipation channel is located between the packaging substrate and the stacking structure, the first heat dissipation channel is closer to the bottom chip in the stacking structure, by adding a circulated heat dissipation medium to the first heat dissipation channel, the heat dissipation medium can take away the heat generated by the bottom chip in time, achieve a better heat dissipation effect, and help improve the heat dissipation performance of the packaging structure; on the second aspect, since the surface where the first heat dissipation channel and the heat dissipation medium contact is covered with a passivation layer, the passivation layer can prevent the heat dissipation medium from causing damage to the surface of the heat dissipation channel (for example, corrosion, etc.), thereby playing a role in protecting the heat dissipation channel. On the third aspect, the packaging structure is simple in structure and easy to implement.

[0042] Figure 2 is a schematic diagram of a packaging structure provided by an embodiment of the present disclosure, Figure 3 is a schematic diagram of a packaging structure provided by an embodiment of the present disclosure, which is equipped with an input pipeline and an output pipeline. The packaging structure includes but is not limited to a high-performance storage and computing integrated chip, such as HBM, etc. Figure 2 and Figure 3 The packaging structure provided by the embodiment of the present disclosure is exemplarily described. Figure 2 As shown, the packaging structure includes a stacking structure 100, a bonding substrate 200 and a packaging substrate 300, wherein the bonding substrate 200 is located between the packaging substrate 300 and the stacking structure 100, and the bonding substrate 200 can have both connection and heat dissipation functions.

[0043] The stacking structure 100 includes a plurality of chips stacked in sequence, and the plurality of chips may include a first chip 110, a second chip 120, and a plurality of third chips 130 stacked in sequence. The first chip 110 includes but is not limited to SoC, and at least one of the processors such as CPU, GPU, NPU, VPU, DSP, etc. is integrated on the SoC. The second chip 120 includes but is not limited to a logic chip, and the logic chip includes various control circuits for controlling the memory chip to complete the logic operation. The third chip 130 includes but is not limited to a memory chip, and the memory chip includes but is not limited to DRAM. By stacking and packaging the first chip 110, the second chip 120, and the plurality of third chips 130 in sequence, a large-capacity, high-bandwidth storage array can be realized. Multiple chips can be vertically connected to each other through advanced packaging technologies such as through-silicon vias (TSV), micro bumps, and stack bonding. Exemplarily, TSV technology can be used to form a through-silicon connection structure 140 in each chip, and micro bump technology can be used to form micro bumps 150 on the surface of each chip.

[0044] The bottommost chip (i.e., the first chip 110) among the multiple chips can be bonded to the bonding substrate 200, and the topmost chip (i.e., the topmost third chip 130) among the multiple chips can be in contact with the substrate 101, and the substrate 101 can serve as a supporting substrate for supporting the multiple chips. The material of the substrate 101 includes a single semiconductor material (e.g., silicon (Si) or germanium (Ge), etc.), a III-V compound semiconductor material (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc.), a II-VI compound semiconductor material (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc.), an organic semiconductor material, or other semiconductor materials known in the art. In this embodiment, the substrate 101 is a silicon substrate as an example for description.

[0045] The bonding substrate 200 includes a first substrate 210, a second substrate 220 and a passivation layer 212. The first substrate 210 is located between the packaging substrate 300 and the second substrate 220. The first substrate 210 and the second substrate 220 are bonded and connected, wherein the first substrate 210 has a first heat dissipation channel s1 for the heat dissipation medium to flow through, and the passivation layer 212 covers the surface where the first heat dissipation channel s1 and the heat dissipation medium contact. In the embodiment of the present disclosure, the first substrate 210 has the first heat dissipation channel s1. The setting of the first heat dissipation channel s1 can effectively take away the heat generated by the stacked structure 100 through the heat dissipation medium, thereby improving the heat dissipation performance.

[0046] The heat dissipation medium may include at least one of a gas and a liquid. For example, a heat dissipation liquid, such as water or other liquids, may be added to the first heat dissipation channel s1. For another example, a heat dissipation gas, such as an inert gas that has been cooled, may be added to the first heat dissipation channel s1. It is understood that the flow of the heat dissipation medium can promptly take away the heat generated by the chip operation, especially the heat generated by the bottom chip, thereby avoiding the heat concentration of the bottom chip. For ease of understanding, the following description will be made using the heat dissipation medium as a liquid as an example.

[0047] The surface where the first heat dissipation channel s1 contacts the heat dissipation medium is covered with a passivation layer 212. The passivation layer 212 can isolate the heat dissipation liquid from the first heat dissipation channel s1, and can prevent the corrosion of the bonding substrate during the long-term passage of the heat dissipation liquid, thereby preventing the heat dissipation liquid from leaking, thereby protecting the first heat dissipation channel s1. The material of the passivation layer 212 includes but is not limited to at least one of silicon nitride and bonding glue. In the embodiment of the present disclosure, a first groove is formed on the surface of the first substrate 210, and the bottom of the first groove is located in the first substrate 210. After the surface of the first substrate 210 formed with the first groove is bonded to the second substrate 220, the first groove can form a sealed first heat dissipation channel s1, that is, the first substrate 210 has the first heat dissipation channel s1, and the surface of the second substrate 220 can be a flat surface. Here, the passivation layer 212 can be formed on the surface of the first groove before the two substrates are bonded.

[0048] It should be noted that the two substrates may be bonded together using a bonding process, for example, a bond is formed between the surfaces of the two substrates without using an intermediate layer such as solder or adhesive. The "bonding" referred to in the present disclosure may be any appropriate bonding technology, for example, hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, and eutectic bonding.

[0049] In the packaging structure provided by the embodiment of the present disclosure, on the one hand, since the bonding substrate with the first heat dissipation channel is located between the packaging substrate and the stacking structure, the first heat dissipation channel is close to the bottom chip in the stacking structure. By adding a circulated heat dissipation medium into the first heat dissipation channel, the heat dissipation medium can promptly take away the heat generated by the bottom chip at work, thereby achieving a better heat dissipation effect, which is beneficial to improving the heat dissipation performance of the packaging structure; on the other hand, since the surface where the first heat dissipation channel and the heat dissipation medium contact is covered with a passivation layer, the passivation layer can prevent the heat dissipation medium from causing leakage between devices, corroding the heat dissipation channel, and causing the heat dissipation channel to be blocked. On the third hand, the packaging structure is simple in structure and easy to implement.

[0050] In some embodiments, reference Figure 2As shown, the package substrate 300 has a second heat dissipation channel s2 for the heat dissipation medium to flow, wherein the second heat dissipation channel s2 is connected to the first heat dissipation channel s1. The package substrate 300 includes but is not limited to a printed circuit board (PCB). It should be noted that Figure 2 The second heat dissipation channel s2 and the first heat dissipation channel s1 connected in the figure are only examples, which do not constitute a limitation on the protection scope of the present disclosure. Any connection method that can achieve the second heat dissipation channel s2 and the first heat dissipation channel s1 should be included in the protection scope of the present disclosure.

[0051] In the embodiment of the present disclosure, the connected second heat dissipation channel s2 and the first heat dissipation channel s1 can constitute a heat dissipation channel of the packaging structure. By adding a circulated heat dissipation medium into the heat dissipation channel, the heat dissipation medium can promptly take away the heat generated by the bottom chip at work, preventing the chip from degrading or even failing due to overheating. For example, the heat dissipation medium can be transmitted to the entrance of the first heat dissipation channel s1 through the entrance of the second heat dissipation channel s2, and then transmitted to the outlet of the first heat dissipation channel s1 through the entrance of the first heat dissipation channel s1, and finally transmitted to the outlet of the second heat dissipation channel s2 through the outlet of the first heat dissipation channel s1, so that the circulation of the heat dissipation medium can be achieved.

[0052] In some embodiments, reference Figure 2 As shown, the first heat dissipation channel s1 includes a first input channel s 11 and the first output channel s 12 ; The second heat dissipation channel s2 includes a second input channel s 21 and the second output channel s 22 , where the second input channel s 21 and the first input channel s 11 Connected, second output channel s 22 and the first output channel s 12 Connected. The first input channel s 11 and the first output channel s 12 The second input channel s may be located at the edge of the bonding substrate 200. 21 and the second output channel s 22 It may be located at an edge of the packaging substrate 300 .

[0053] In the embodiment of the present disclosure, the first input channel s 11 It can be the entrance of the first heat dissipation channel s1, used to pass the heat dissipation medium into the first heat dissipation channel s1; the first output channel s 12 It can be the outlet of the first heat dissipation channel s1, used to output the heat dissipation medium flowing through the first heat dissipation channel s1. 21It can be the entrance of the second heat dissipation channel s2, used to pass the heat dissipation medium into the second heat dissipation channel s2; the second output channel s 22 It can be the outlet of the second heat dissipation channel s2, used to output the heat dissipation medium flowing through the second heat dissipation channel s2. Therefore, the flow path of the heat dissipation medium can be: the second input channel s 21 →First input channel s 11 →First output channel s 12 → Second output channel s 22 .

[0054] In some embodiments, the first heat dissipation channel s1 may include a plurality of connected first sub-heat dissipation channels, and the surface of each first sub-heat dissipation channel is covered with a passivation layer 212, thereby protecting the surface of each first sub-heat dissipation channel in contact with the heat dissipation medium. In the embodiment of the present disclosure, the plurality of first sub-heat dissipation channels may be evenly distributed in the bonding substrate 200, thereby improving the uniformity of heat dissipation and avoiding heat concentration in some areas.

[0055] In some embodiments, reference Figure 2 As shown, the first substrate 210 includes a first carrier 201 and a first dielectric layer 211, wherein the first dielectric layer 211 is located between the first carrier 201 and the second substrate 220, wherein the first heat dissipation channel s1 extends into the first carrier 201 along a surface of the first dielectric layer 211 relatively away from the first carrier 201, and the passivation layer 212 covers the surface of the first dielectric layer 211 relatively away from the first carrier 201. Here, the first substrate 210 may also include Figure 2 Other film layers not shown.

[0056] Exemplarily, the first dielectric layer 211 has a first surface and a second surface relative to each other, the first surface may be a surface of the first dielectric layer 211 relatively far from the first carrier 201, and the second surface may be a surface of the first dielectric layer 211 relatively close to the first carrier 201. Multiple first sub-heat dissipation channels may extend along the first surface into the first carrier 201, that is, the bottom of the first sub-heat dissipation channel is located in the first carrier 201, therefore, the height of the first sub-heat dissipation channel is less than the height of the first substrate 210, thereby ensuring the sealing of the first sub-heat dissipation channel, and the passivation layer 212 covers each first sub-heat dissipation channel and the first surface. The material of the first dielectric layer 211 includes a dielectric material, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0057] In some embodiments, the second substrate 220 includes a second dielectric layer 221 and a bonding layer 222, wherein the bonding layer 222 is located between the second dielectric layer 221 and the first substrate 210, wherein the second dielectric layer 221 is bonded to the stacked structure 100, and the bonding layer 222 is bonded to the passivation layer 212. Here, the second substrate 220 may also include Figure 2 Other film layers not shown.

[0058] Exemplarily, the second dielectric layer 221 has a third surface and a fourth surface relative to each other, the third surface may be a surface of the second dielectric layer 221 relatively close to the first substrate 210, and the fourth surface may be a surface of the second dielectric layer 221 relatively far from the first substrate 210. In the case where the second dielectric layer 221 and the stacked structure 100 are bonded, the fourth surface constitutes the contact interface between the second dielectric layer 221 and the stacked structure 100, and the third surface may be the contact interface between the second dielectric layer 221 and the bonding layer 222. In the case where the bonding layer 222 and the passivation layer 212 are bonded, the contact interface between the bonding layer 222 and the passivation layer 212 is the bonding interface between the first substrate 210 and the second substrate 220. The material of the second dielectric layer 221 includes a dielectric material, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. The material of the bonding layer 222 includes but is not limited to at least one of silicon nitride and bonding glue.

[0059] In some embodiments, the material of the bonding layer 222 is the same as that of the passivation layer 212. For example, the materials of the bonding layer 222 and the passivation layer 212 are both silicon nitride, that is, the bonding interface between the first substrate 210 and the second substrate 220 is silicon nitride-silicon nitride bonding. Using the same material for bonding can improve the bonding strength between the first substrate 210 and the second substrate 220.

[0060] In some embodiments, the bonding substrate 200 also includes a connecting structure 230 and a first bonding contact 240, the connecting structure 230 extends through the second substrate 220 and the first substrate 210, the first bonding contact 240 is located on a side of the connecting structure 230 relatively away from the packaging substrate 300 and is connected to the connecting structure 230, wherein the connecting structure 230 and the first heat dissipation channel s1 are spaced apart from each other, and the first bonding contact 240 is joined to the second bonding contact of the stacking structure 100.

[0061] The connection structure 230 may extend along the fourth surface through the second dielectric layer 221, the bonding layer 222, the passivation layer 212 covering the first surface, the first dielectric layer 211 and the first carrier 201, that is, the connection structure 230 extends through the second substrate 220 and the first substrate 210, and the connection structure 230 and the first heat dissipation channel s1 may be spaced apart from each other by the first dielectric layer 211 and the first carrier 201, so as to avoid mutual interference. The connection structure 230 is used to realize the interconnection between the chip in the stacked structure 100 and the circuit in the package substrate 300, and the material of the connection structure 230 includes a conductive material, for example, at least one of polysilicon, doped polysilicon, metal (for example, tungsten, titanium, tantalum, etc.), metal silicide (for example, tungsten silicide, titanium silicide, etc.), and metal nitride (for example, tungsten nitride, tantalum nitride, etc.).

[0062] The first bonding contact 240 may be located on the exposed surface of the connection structure 230, and the bonding substrate 200 and the stacking structure 100 may be vertically connected by bonding the first bonding contact 240 and the second bonding contact, and the materials of the first bonding contact 240 and the second bonding contact include but are not limited to copper. The bonding connection includes a hybrid bonding connection (also known as a "metal / dielectric hybrid bonding connection"), which is a direct bonding technology, for example, forming a bond between surfaces without using an intermediate layer such as solder or adhesive, and metal-metal bonding and dielectric-dielectric bonding can be obtained at the same time. The first bonding contact 240 is connected to the connection structure 230, and the second bonding contact is connected to the chip in the stacking structure 100, so that the connection between the stacking structure 100 and the packaging substrate 300 can be achieved. Here, the second bonding contact can be formed on the surface of the first chip 110 relatively away from the second chip 120.

[0063] It should be noted that, in the present embodiment, the connection structure 230 (also known as the TSV first process) can be formed before the bonding substrate 200 and the stacking structure 100 are bonded. Therefore, it is necessary to start etching the bonding substrate 200 from the fourth surface. Considering the process limitations of TSV hole etching, the cross-sectional dimension of the connection structure 230 relatively close to the fourth surface formed in the end is greater than or equal to the cross-sectional dimension of the connection structure 230 relatively far from the fourth surface, that is, the cross-sectional dimension of the connection structure 230 relatively close to the packaging substrate 300 is less than or equal to the cross-sectional dimension of the connection structure 230 relatively far from the packaging substrate 300. Of course, in other embodiments, the connection structure 230 (also known as the TSV last process) can also be formed after the bonding substrate 200 and the stacking structure 100 are bonded. The TSV last process will be described in detail below and will not be repeated here.

[0064] In some embodiments, reference Figure 2 As shown, the bonding substrate 200 also includes a bump 250, which is located on a side of the connection structure 230 relatively close to the packaging substrate 300 and connected to the connection structure 230. Here, after the bonding substrate 200 and the stacking structure 100 are bonded, the bump 250 can be formed on a side of the first carrier 201 relatively far away from the stacking structure 100 using a micro-bump technology, and the bump 250 of the bonding substrate 200 is packaged on one side of the packaging substrate 300, so that the bump 250 is embedded in the packaging substrate 300 and connected to the circuit in the packaging substrate 300. The material of the bump 250 includes a conductive material, for example, at least one of copper, gold, silver, and platinum. It can be understood that, Figure 2 The first chip 110 in the package substrate 300 can be connected to the circuit in the package substrate 300 through the second bonding contacts, the first bonding contacts 240 , the connection structures 230 , and the bumps 250 .

[0065] In other embodiments, the bonding substrate 200 further includes a connection structure 230 and a bump 250, wherein the connection structure 230 extends through the second substrate 220 and the first substrate 210, and the bump 250 is located on a side of the connection structure 230 relatively close to the packaging substrate 300 and connected to the connection structure 230, wherein the connection structure 230 and the first heat dissipation channel s1 are spaced apart from each other, and the connection structure 230 connects the chip. In this embodiment, the connection structure 230 can be formed by a TSV last process, so the first chip 110 can be connected to the circuit in the packaging substrate 300 through the connection structure 230 and the bump 250, that is, the bonding contact can be omitted. The TSV last process will be described in detail below and will not be repeated here.

[0066] It should be noted that in the TSV last process, the bonding substrate 200 needs to be etched starting from the thinned first carrier. Considering the process limitations of TSV hole etching, the cross-sectional size of the finally formed connection structure 230 relatively close to the packaging substrate 300 is greater than or equal to the cross-sectional size of the connection structure 230 relatively far away from the packaging substrate 300.

[0067] In some embodiments, reference Figure 3 As shown, the packaging structure further includes an input pipeline 410 and an output pipeline 420. The input pipeline 410, the output pipeline 420 and the bonding substrate 200 are located on the same side of the packaging substrate 300. The input pipeline 410 and the second input channel s 21 The output pipeline 420 and the second output channel s are connected. 22 The heat dissipation medium can be passed into the heat dissipation channel through the input pipeline 410 , and the heat dissipation medium flowing through the heat dissipation channel can be output through the output pipeline 420 .

[0068] It should be noted that solder balls need to be formed on the side of the packaging substrate that is relatively far away from the bonding substrate (for example, the back side of the packaging substrate) and soldered to other circuit boards through the solder balls. If the input pipeline 410 and the output pipeline 420 are installed on the back side of the packaging substrate, the liquid discharge from the back side will affect the welding, and the space on the back side of the packaging substrate is small, which is not conducive to the installation of an external liquid cooling circulation system. In the embodiment of the present disclosure, by arranging the input pipeline 410, the output pipeline 420 and the bonding substrate 200 to be located on the same side of the packaging substrate 300 (for example, the front side of the packaging substrate), the liquid discharge from the front side will not affect the welding of the solder balls on the back side, and the inlet and outlet liquid pipelines of the external liquid cooling circulation system are also simpler.

[0069] In some embodiments, reference Figure 3As shown, the packaging structure further includes a plastic sealing layer 430, and the plastic sealing layer 430 covers the bonding substrate 200 and the stacking structure 100. In order to prevent the plastic sealing glue from flowing into the input pipeline 410 and the output pipeline 420 during plastic sealing and causing the input pipeline 410 and the output pipeline 420 to be blocked, the distance between the plastic sealing layer 430 and the input pipeline 410 and the distance between the plastic sealing layer 430 and the output pipeline 420 can be controlled to be above 200 microns.

[0070] Based on the above packaging structure, an embodiment of the present disclosure provides a packaging method, which is used to form the packaging structure in any of the above embodiments.

[0071] Figure 4 is a flow chart of a packaging method provided by an embodiment of the present disclosure. It should be noted that: Figure 4 The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; Figure 4 The steps shown in the figure can be adjusted in order according to actual needs. Figure 4 As shown, the packaging method includes the following steps:

[0072] S510: forming a stack structure, the stack structure comprising a plurality of chips stacked in sequence;

[0073] S520: forming a bonding substrate, the bonding substrate comprising a first substrate, a second substrate and a passivation layer, the first substrate and the second substrate being bonded to each other, wherein the first substrate has a first heat dissipation channel for heat dissipation medium to flow through, and the passivation layer covers a surface of the first heat dissipation channel in contact with the heat dissipation medium;

[0074] S530: packaging the bonding substrate and the stacking structure to one side of the packaging substrate, so that the bonding substrate is located between the packaging substrate and the stacking structure, wherein the first substrate is located between the packaging substrate and the second substrate.

[0075] Figure 5A and Figure 5B This is a schematic diagram of a stacking structure provided by an embodiment of the present disclosure. Figure 4 , Figure 5A and Figure 5B The formation process of the stacking structure is exemplarily described.

[0076] Reference Figure 4 and Figure 5A As shown, the above step S510 includes: providing a substrate 101, and forming a plurality of third chips 130, a second chip 120 and a first chip 110 stacked in sequence on one side of the substrate 101. For the substrate, the first chip 110, the second chip 120 and the plurality of third chips 130, refer to Figure 2 The relevant description will not be repeated here.

[0077] The substrate 101 and the third chip 130, the plurality of third chips 130, and the third chip 130 and the second chip 120 can be vertically connected to each other through advanced packaging technologies such as TSV, Micro bump, and stack bonding. For example, TSV technology can be used to form a through-silicon connection structure 140 in the chip, and Micro bump technology can be used to form a micro bump 150 on the surface of each chip, and then each chip is stacked and bonded in sequence.

[0078] It should be noted that the first chip 110 may include a first conductive layer 111 and a second conductive layer 112. The first conductive layer 111 is formed on the front side of the first chip 110, so the first conductive layer 111 is also called a top metal layer (Top Metal, TM); the second conductive layer 112 is formed on the back side of the first chip 110, so the second conductive layer 112 is also called a bottom metal layer. Here, after completing the front side process of the first chip 110, a through-silicon connection structure 140 extending through the first chip 110 can be formed from the back side of the first chip 110 using TSV technology, and then the second conductive layer 112 is formed. The second conductive layer 112 is connected to the micro bumps 150 on the surface of the second chip 120.

[0079] In some embodiments, reference Figure 4 , Figure 5A and Figure 5B As shown, the above step S510 further includes: forming a second bonding contact 113 on a surface of the first chip 110 relatively far from the second chip 120, and the second bonding contact 113 is connected to the first conductive layer 111. For example, a third dielectric layer covering the first chip 110 may be formed; the third dielectric layer may be etched until the first conductive layer 111 is exposed to form a bonding through hole; and a conductive material may be filled into the bonding through hole to form the second bonding contact 113. For ease of understanding, Figure 5B The third dielectric layer is omitted.

[0080] Figures 6 to 18 This is a schematic diagram of forming a bonding substrate provided by an embodiment of the present disclosure. Figure 4 , Figures 6 to 18 The formation process of the bonding substrate is exemplarily described.

[0081] Reference Figure 4 , reference Figures 6 to 12As shown, the above step S520 includes: forming a first dielectric layer 211 on one side of the first carrier 201; etching the first dielectric layer 211 to form a first heat dissipation channel s1 extending into the first carrier 201; forming a passivation layer 212 covering the surface of the first dielectric layer 211 and the surface of the first heat dissipation channel s1; forming a second dielectric layer 221 and a bonding layer 222 in sequence on one side of the second carrier 202; bonding the first carrier 201 formed with the passivation layer 212 and the second carrier 202 formed with the bonding layer 222 so that the bonding layer 222 and the passivation layer 212 are bonded; and removing the second carrier 202 to form a bonded substrate 200.

[0082] Reference Figure 6 As shown, a first carrier 201 is provided, and a first dielectric layer 211 is deposited on one side of the first carrier 201. The material of the first carrier 201 includes but is not limited to silicon, and the material of the first dielectric layer 211 can refer to the relevant description of the above embodiment, and the formation process of the first dielectric layer 211 includes a thin film deposition process, for example, at least one of chemical vapor deposition, physical vapor deposition and other thin film deposition processes.

[0083] Reference Figure 6 As shown, the first dielectric layer 211 is etched from the surface of the first dielectric layer 211 to form a Figure 7 The first heat dissipation channel s1 shown in FIG. 1 extends into the first carrier 201, that is, the height of the first heat dissipation channel s1 is greater than the height of the first dielectric layer 211, and the height of the first heat dissipation channel s1 is less than the sum of the heights of the first dielectric layer 211 and the first carrier 201. The top view of the first heat dissipation channel s1 is shown in FIG. Figure 8 As shown, the first heat dissipation channel s1 may include a plurality of interconnected first sub-heat dissipation channels, and the plurality of first sub-heat dissipation channels may be cross-arranged along the x direction and the y direction, respectively. The etching includes at least one of dry etching and wet etching.

[0084] Reference Figure 7 As shown, a passivation material is deposited on the exposed surface of the first dielectric layer 211 and the exposed surface of the first heat dissipation channel s1 to form a Fig. 9 The passivation layer 212 shown covers the surface of the first dielectric layer 211 and the surface of the first heat dissipation channel s1. The material of the passivation layer 212 can refer to the relevant description of the above embodiment. The formation process of the passivation layer 212 includes but is not limited to the atomic layer deposition process.

[0085] Reference Fig.10As shown, a second carrier 202 is provided, and a second dielectric layer 221 and a bonding layer 222 are sequentially deposited on one side of the second carrier 202. The material of the second carrier 202 includes but is not limited to silicon, and the materials of the second dielectric layer 221 and the bonding layer 222 can refer to the relevant description of the above embodiment, and the formation process of the second dielectric layer 221 and the bonding layer 222 includes a thin film deposition process.

[0086] Will Fig. 9 The structure shown and Fig.10 The structure shown is bonded face to face so that the bonding layer 222 and the passivation layer 212 are bonded, as shown in FIG. Fig.11 Of course, in order to reduce the height of the entire packaging structure, the second carrier 202 can also be removed to expose the second dielectric layer 221, as shown in FIG. Fig.12 As shown, the remaining second dielectric layer 221 and bonding layer 222 constitute the second substrate 220. Here, the bonding layer 222 and the passivation layer 212 are bonded to form a silicon nitride-silicon nitride bonding interface.

[0087] In some embodiments, reference Figure 4 , reference Figure 12 to Figure 14 As shown, the above step S520 also includes: etching the second dielectric layer 221 to form a connection hole extending into the first carrier 201, wherein the connection hole and the first heat dissipation channel s1 are spaced apart from each other, and the cross-sectional size of the bottom of the connection hole is less than or equal to the cross-sectional size of the top of the connection hole; filling the connection hole with a conductive material to form a connection structure 230; forming a first bonding contact 240 on the exposed surface of the connection structure 230, and the first bonding contact 240 is connected to the connection structure 230.

[0088] Reference Fig.12 As shown, etching is started from the exposed surface of the second dielectric layer 221 to form a connection hole extending into the first carrier 201, and a conductive material is filled into the connection hole to form a Fig.13 The connection structure 230 shown in the figure has its bottom located in the first carrier 201. The material of the connection structure 230 can refer to the relevant description of the above embodiment. Here, the connection structure 230 is formed by the TSV first process. Considering the process limitation of TSV hole etching, the cross-sectional size of the bottom of the connection hole actually formed may be smaller than or equal to the cross-sectional size of the top of the connection hole. After the bonded bonding substrate 200 and the stacking structure 100 are packaged to one side of the packaging substrate 300, the cross-sectional size of the connection structure 230 relatively close to the packaging substrate 300 is smaller than or equal to the cross-sectional size of the connection structure 230 relatively far from the packaging substrate 300, as shown in FIG. Fig.19 shown.

[0089] It should be noted that the cross-sectional shape of the connection hole includes a circle, an ellipse or other geometric shapes, and therefore, the cross-sectional size of the connection hole includes at least one of the size of the connection hole in the x direction and the size in the y direction. For example, when the cross-sectional shape of the connection hole is a circle, the cross-sectional size of the connection hole may be the radius or diameter of the circle.

[0090] Reference Fig.13 As shown, the exposed surface of the connection structure 230 is formed as shown in FIG. Fig.14 The number of the first bonding contacts 240 is not limited to Fig.14 The material of the first bonding contact 240 can refer to the relevant description of the above embodiment, and the formation process of the first bonding contact 240 includes but is not limited to the electroplating process. For example, copper can be electroplated on the exposed surface of the connection structure 230 to form the first bonding contact 240.

[0091] In some embodiments, reference Fig.15 and Fig.16 As shown, the packaging method further includes: bonding the bonding substrate 200 and the stacking structure 100 so that the first bonding contact 240 and the second bonding contact 113 of the stacking structure 100 are bonded; and thinning the first carrier 201 until the connection structure 230 is exposed.

[0092] Will Fig.14 The structure shown and Figure 5B The structure shown is bonded face to face so that the first bonding contact 240 and the second bonding contact 113 are bonded, as shown in FIG. Fig.15 As shown, then, the first carrier 201 is thinned from the side of the first carrier 201 relatively far from the first dielectric layer 211 until the connection structure 230 is exposed, as shown in FIG. Fig.16 As shown, the retained first carrier 201 and the first dielectric layer 211 constitute as follows Figure 2 The first substrate 210 shown has a first heat dissipation channel s1. The thinning process of the first carrier 201 includes but is not limited to a chemical mechanical polishing process.

[0093] It should be noted that in order to avoid exposing the first heat dissipation channel s1 during the process of thinning the first carrier board 201 , the sealing performance of the first heat dissipation channel s1 is affected. Fig.13 The height of the connection structure 230 located in the first carrier 201 may be greater than the height of the first heat dissipation channel s1 located in the first carrier 201. Fig.15 During the thinning process of the first carrier 201 shown, the connection structure 230 may be exposed first.

[0094] In some embodiments, the packaging method further includes: performing a planarization process on the exposed connection structure 230 so that the exposed surface of the connection structure 230 is flush. It should be understood that in the process of etching to form the connection holes, due to etching deviation, the bottoms of different connection holes may not be flush, so that Fig.13 After exposing the plurality of connection structures 230, the exposed plurality of connection structures 230 may be planarized so that the exposed surfaces of the plurality of connection structures 230 are level, thereby ensuring the uniformity of subsequent connection of the bumps 250.

[0095] In some embodiments, reference Fig.17 As shown, the above step S520 further includes: forming a bump 250 on the exposed surface of the connection structure 230. For example, using the Micro bump technology to form Fig.17 There are multiple bumps 250 shown, each of which is connected to a connection structure 230 . The material of the bumps 250 can refer to the relevant description of the above embodiments.

[0096] In some embodiments, reference Fig.18 As shown, the packaging method further includes: after forming the bump 250, etching the thinned first carrier 201 to form a first input channel s1 of the first heat dissipation channel s1. 11 and the first output channel s 12 For example, holes may be punched at the edge of the thinned first carrier plate 201 to form Fig.18 The first input channel s shown 11 and the first output channel s 12 , the first input channel s 11 It can be used as the entrance of the first heat dissipation channel s1 and the first output channel s 12 Serves as the outlet of the first heat dissipation channel s1.

[0097] Figures 19 to 21 This is a schematic diagram of a packaging structure provided by an embodiment of the present disclosure. Figure 4 , Figures 19 to 21 The formation process of the packaging structure is exemplarily described.

[0098] Reference Figure 4 and Fig.19 As shown, the above step S530 includes: packaging the bonded bonding substrate 200 and the stacked structure 100 to one side of the packaging substrate 300, so that the bump 250 is connected to the circuit on the packaging substrate 300, wherein the first input channel s 11 The second input channel s on the package substrate 300 is connected 21 , the first output channel s 12 The second output channel s on the package substrate 300 is connected22 .

[0099] Can Fig.18 The structure shown is flip-chip mounted on the package substrate 300, so that the bump 250 is embedded in the package substrate 300 and connected to the circuit in the package substrate 300, the first input channel s 11 and the second input channel s 21 Connect and first output channel s 12 and the second output channel s 22 connected, thus forming Fig.19 As shown in the structure. In this way, the first heat dissipation channel s1 and the second heat dissipation channel s2 are connected to form a heat dissipation channel of the packaging structure. It can be understood that the bonding substrate 200 and the packaging substrate 300 are connected through the bump 250. Specifically, the bump 250 is respectively connected to the circuit in the connection structure 230 and the packaging substrate 300.

[0100] In some embodiments, reference Fig. 20 As shown, the packaging method further includes: forming a plastic packaging layer 430 covering the stacking structure 100 and the bonding substrate 200 on one side of the packaging substrate 300 .

[0101] In some embodiments, reference Fig.21 As shown, the packaging method further includes: installing an input pipeline 410 and an output pipeline 420 on one side of the packaging substrate 300, wherein the input pipeline 410 and the second input channel s 21 The output pipeline 420 and the second output channel s are connected. 22 Here, the input pipeline 410 can be installed in the second input channel s 21 Above, the input line 410 is connected to the infusion device and the second input channel s 21 The heat dissipation liquid provided by the infusion device can be transmitted to the heat dissipation channel via the input pipeline 410. The output pipeline 420 can be installed in the second output channel s 22 Above, the output pipeline 420 is connected to the discharge device and the second output channel s 22 The heat dissipation liquid discharged from the heat dissipation channel can be transmitted to the liquid discharge device via the output pipeline 420, thereby realizing the heat dissipation of the packaging structure.

[0102] Figure 22 to Figure 25 This is another schematic diagram of forming a packaging structure provided by an embodiment of the present disclosure. Figure 4 , Figure 22 to Figure 25 The formation process of the packaging structure is exemplarily described.

[0103] Reference Fig. 22 and Fig.23As shown, the above packaging method also includes: bonding the bonding substrate 200 and the stacking structure 100 so that the second dielectric layer 221 and the stacking structure 100 are bonded; thinning the first carrier 201 to a preset thickness, wherein the preset thickness is greater than the height of the first heat dissipation channel s1 located in the first carrier 201.

[0104] Will Fig.12 The structure shown and Figure 5A The structure shown is bonded face to face, so that the second dielectric layer 221 and the stacked structure 100 are bonded, as shown in FIG. Fig. 22 As shown, the first carrier 201 is then thinned from a side of the first carrier 201 relatively far from the first dielectric layer 211, for example, the first carrier 201 is thinned from an initial thickness H1 to a preset thickness H2, as shown in FIG. Fig.23 Here, with Fig.15 The first bonding contact 240 and the second bonding contact 113 are bonded differently, Fig. 22 The second dielectric layer 221 and the stacked structure 100 are bonded to form a silicon oxide-silicon oxide bonding interface. The preset thickness H2 is greater than the height of the first heat dissipation channel s1 located in the first carrier 201, thereby avoiding exposure of the first heat dissipation channel s1 and ensuring the sealing of the first heat dissipation channel s1. In practical applications, the preset thickness H2 can be reasonably set according to the height of the first heat dissipation channel s1 located in the first carrier 201, and the present disclosure has no special restrictions on this.

[0105] In some embodiments, the above step S520 also includes: etching the thinned first carrier 201 to form a connecting hole extending into the stacking structure 100, wherein the connecting hole and the first heat dissipation channel s1 are spaced apart from each other, and the cross-sectional size of the bottom of the connecting hole is less than or equal to the cross-sectional size of the top of the connecting hole; filling the connecting hole with a conductive material to form a connecting structure 230.

[0106] Reference Fig.23 As shown, etching is started from the thinned surface of the first carrier 201 until the first conductive layer 111 is exposed to form a connection hole extending into the stacked structure 100, and a conductive material is filled into the connection hole to form a Fig.24 The connection structure 230 shown. Here, the connection structure 230 is formed by the TSV last process. Considering the process limitation of TSV hole etching, the cross-sectional size of the bottom of the connection hole actually formed may be smaller than or equal to the cross-sectional size of the top of the connection hole. After the bonded bonding substrate 200 and the stacking structure 100 are packaged to one side of the packaging substrate 300, the cross-sectional size of the connection structure 230 relatively close to the packaging substrate 300 is greater than or equal to the cross-sectional size of the connection structure 230 relatively far from the packaging substrate 300. For the cross-sectional shape and cross-sectional size of the connection hole, reference may be made to the relevant description of the above embodiment.

[0107] It should be noted that Figures 13 to 15 The TSV first process is used in the present invention, that is, a plurality of connection structures 230 are first formed and then the first carrier 201 is thinned. The bottoms of the plurality of connection structures 230 may not be flush. In the subsequent thinning process of the first carrier 201, it is necessary to thin the first carrier 201 until each connection structure 230 is exposed. Therefore, the TSV first process has a higher requirement for thinning. After the plurality of connection structures 230 are exposed, the exposed plurality of connection structures 230 need to be planarized so that the exposed surfaces of the plurality of connection structures 230 are flush (refer to Fig.16 ), which adds an extra process. Fig.24 The TSV last process is used, that is, the first carrier 201 is thinned first and then a plurality of connection structures 230 are formed. There is no need to consider whether the bottoms of the plurality of connection structures 230 are flush. Therefore, the TSV last process has lower requirements for thinning, fewer steps, and a simpler process.

[0108] In some embodiments, the step S520 further includes: forming a bump 250 on the exposed surface of the connection structure 230 , wherein the bump 250 is connected to the connection structure 230 .

[0109] Reference Fig.25 As shown, a fourth dielectric layer 251 is formed to cover the thinned first carrier 201 and the connection structure 230, the fourth dielectric layer 251 is etched to form an opening, the bottom of the opening exposes the connection structure 230, a conductive layer 252 is formed in the opening, and the conductive layer 252 is electroplated to form a bump. Here, after the bump is formed, a similar process may be performed. Figures 18 to 21 The step of encapsulating the bonded bonding substrate 200 and the stacked structure 100 to one side of the encapsulation substrate 300 is performed.

[0110] The features disclosed in several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0111] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0112] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0113] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0114] The above description is only an implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A packaging structure, characterized in that: include: A stacking structure, a bonding substrate and a packaging substrate, wherein the bonding substrate is located between the stacking structure and the packaging substrate; The stacking structure includes a plurality of chips stacked in sequence; The bonding substrate includes a first substrate, a second substrate and a passivation layer, wherein the first substrate is located between the packaging substrate and the second substrate and is bonded to the second substrate, wherein the first substrate has a first heat dissipation channel for heat dissipation medium to flow through, and the passivation layer covers the surface where the first heat dissipation channel contacts the heat dissipation medium.

2. The packaging structure according to claim 1, characterized in that: The packaging substrate has a second heat dissipation channel for the heat dissipation medium to flow through, wherein the second heat dissipation channel is connected to the first heat dissipation channel.

3. The packaging structure according to claim 2, characterized in that: The first heat dissipation channel includes a first input channel and a first output channel; the second heat dissipation channel includes a second input channel and a second output channel, wherein the second input channel is connected to the first input channel, and the second output channel is connected to the first output channel.

4. The packaging structure according to claim 3, characterized in that: The packaging structure further includes an input pipeline and an output pipeline, wherein the input pipeline, the output pipeline and the bonding substrate are located on the same side of the packaging substrate, wherein the input pipeline is communicated with the second input channel, and the output pipeline is communicated with the second output channel.

5. The packaging structure according to claim 1, characterized in that: The first substrate comprises a first carrier and a first dielectric layer, wherein the first dielectric layer is located between the first carrier and the second substrate, wherein the first heat dissipation channel extends into the first carrier along a surface of the first dielectric layer relatively far from the first carrier, and the passivation layer covers a surface of the first dielectric layer relatively far from the first carrier; The second substrate includes a second dielectric layer and a bonding layer, wherein the bonding layer is located between the second dielectric layer and the first substrate, wherein the second dielectric layer is bonded to the stacked structure, and the bonding layer is bonded to the passivation layer.

6. The packaging structure according to claim 5, characterized in that: The material of the bonding layer is the same as that of the passivation layer.

7. The packaging structure according to claim 1 or 6, characterized in that: The material of the passivation layer includes silicon nitride.

8. The packaging structure according to claim 1, characterized in that: The bonding substrate also includes a connecting structure and a first bonding contact, wherein the connecting structure extends through the second substrate and the first substrate, and the first bonding contact is located on a side of the connecting structure relatively away from the packaging substrate and is connected to the connecting structure, wherein the connecting structure and the first heat dissipation channel are spaced apart from each other, and the first bonding contact is engaged with a second bonding contact of the stacking structure.

9. The packaging structure according to claim 8, characterized in that: A cross-sectional dimension of the connection structure relatively close to the packaging substrate is smaller than or equal to a cross-sectional dimension of the connection structure relatively far from the packaging substrate.

10. The packaging structure according to claim 1, characterized in that: The bonding substrate also includes a connection structure and a bump, wherein the connection structure extends through the second substrate and the first substrate, and the bump is located on a side of the connection structure relatively close to the packaging substrate and connected to the connection structure, wherein the connection structure and the first heat dissipation channel are spaced apart from each other, and the connection structure connects the chip.

11. The packaging structure according to claim 10, characterized in that: A cross-sectional dimension of the connection structure relatively close to the packaging substrate is greater than or equal to a cross-sectional dimension of the connection structure relatively far from the packaging substrate.

12. A packaging method, characterized in that: include: forming a stacking structure, the stacking structure comprising a plurality of chips stacked in sequence; Forming a bonding substrate, the bonding substrate comprising a first substrate, a second substrate and a passivation layer, the first substrate and the second substrate being bonded to each other, wherein the first substrate has a first heat dissipation channel for heat dissipation medium to flow through, and the passivation layer covers a surface where the first heat dissipation channel contacts the heat dissipation medium; The bonding substrate and the stacking structure are packaged to one side of a packaging substrate, so that the bonding substrate is located between the packaging substrate and the stacking structure, wherein the first substrate is located between the packaging substrate and the second substrate.

13. The packaging method according to claim 12, characterized in that: The forming of the bonding substrate comprises: forming a first dielectric layer on one side of the first carrier; Etching the first dielectric layer to form the first heat dissipation channel extending into the first carrier board; forming the passivation layer covering a surface of the first dielectric layer and a surface of the first heat dissipation channel; forming a second dielectric layer and a bonding layer in sequence on one side of the second carrier; Bonding the first carrier having the passivation layer formed thereon and the second carrier having the bonding layer formed thereon, so that the bonding layer and the passivation layer are bonded; The second carrier is removed to form the bonding substrate.

14. The packaging method according to claim 13, characterized in that: The forming of the bonding substrate further comprises: Etching the second dielectric layer to form a connection hole extending into the first carrier board, wherein the connection hole and the first heat dissipation channel are spaced apart from each other, and a cross-sectional dimension of a bottom of the connection hole is smaller than or equal to a cross-sectional dimension of a top of the connection hole; Filling the connection hole with a conductive material to form a connection structure; forming a first bonding contact on an exposed surface of the connection structure, the first bonding contact connecting the connection structure; The packaging method further comprises: Bonding the bonding substrate and the stacked structure so that the first bonding contact and the second bonding contact of the stacked structure are engaged; The first carrier board is thinned until the connection structure is exposed.

15. The packaging method according to claim 13, characterized in that: The packaging method further comprises: Bonding the bonding substrate and the stacked structure so that the second dielectric layer and the stacked structure are bonded; Thinning the first carrier plate to a preset thickness, wherein the preset thickness is greater than a height of the first heat dissipation channel in the first carrier plate; The forming of the bonding substrate further comprises: Etching the thinned first carrier to form a connection hole extending into the stacked structure, wherein the connection hole and the first heat dissipation channel are spaced apart from each other, and a cross-sectional dimension of a bottom of the connection hole is smaller than or equal to a cross-sectional dimension of a top of the connection hole; Filling the connection hole with a conductive material to form a connection structure; Bumps are formed on the exposed surfaces of the connection structures, and the bumps are connected to the connection structures.

16. The packaging method according to claim 15, characterized in that: The packaging method further comprises: After forming the bumps, etching the thinned first carrier board to form a first input channel and a first output channel of the first heat dissipation channel; The step of packaging the bonding substrate and the stacking structure to one side of a packaging substrate comprises: The bonded bonding substrate and the stacking structure are packaged to one side of the packaging substrate so that the bump is connected to the circuit on the packaging substrate, wherein the first input channel is connected to the second input channel on the packaging substrate, and the first output channel is connected to the second output channel on the packaging substrate.

17. The packaging method according to claim 16, characterized in that: The packaging method further comprises: An input pipeline and an output pipeline are installed on one side of the packaging substrate, wherein the input pipeline is communicated with the second input channel, and the output pipeline is communicated with the second output channel.

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