Power semiconductor device including solder bleeding prevention layer and method of manufacturing same

Abstract

A power semiconductor device includes: a die carrier; a power semiconductor die disposed on the die carrier, the power semiconductor die comprising a first side and an opposite second side, where the first side faces away from the die carrier and comprises a first power terminal having a Cu layer, and where the second side comprises a second power terminal electrically coupled to the die carrier; a contact clip electrically coupled to the Cu layer of the first power terminal through a solder joint; and a patterned capping layer disposed on a first side of the power semiconductor die, the capping layer surrounding the first power terminal on at least one lateral side, the capping layer being arranged over the Cu layer, and the capping layer consisting of Al2O3 or SiO2.

Description

Technical Field

[0001] The present disclosure generally relates to a power semiconductor device including a cover layer configured to prevent solder from seeping from a power terminal, and to a method for manufacturing such a power semiconductor device. Background Art

[0002] A power semiconductor device (e.g., a power semiconductor package) may, for example, include a power semiconductor die attached to a die carrier such that a first side of the power semiconductor die faces away from the die carrier and a second side faces the die carrier. In addition, a contact clip may be coupled to a power terminal on the first side of the power semiconductor die. The contact clip may, for example, electrically connect the power terminal to an external contact of the power semiconductor device or to another die carrier. However, there may be a risk that solder seepage may occur during the manufacture of the power semiconductor device when the contact clip is coupled to the power terminal. Such solder seepage may, for example, result in pad contamination and / or electrical shorts, and may therefore reduce the yield of a batch of usable devices. Improved power semiconductor devices and improved methods for manufacturing power semiconductor devices may help address these and other problems. Summary of the invention

[0003] Various aspects relate to a power semiconductor device comprising: a die carrier; a power semiconductor die arranged on the die carrier, the power semiconductor die comprising a first side and an opposite second side, wherein the first side faces away from the die carrier and comprises a first power terminal having a Cu layer, and wherein the second side comprises a second power terminal electrically coupled to the die carrier; a contact clip electrically coupled to the Cu layer of the first power terminal via a solder joint; and a patterned cover layer arranged on the first side of the power semiconductor die, the cover layer surrounding the first power terminal on at least one lateral side, the cover layer arranged on top of the Cu layer, and the cover layer consisting of Al2O3 or SiO2.

[0004] Various aspects relate to a method for manufacturing a power semiconductor device, the method comprising: providing a die carrier; arranging a power semiconductor die on the die carrier, the power semiconductor die comprising a first side and an opposite second side, wherein the first side faces away from the die carrier and comprises a first power terminal having a Cu layer, and wherein the second side comprises a second power terminal; depositing a capping layer composed of Al2O3 or SiO2 on the first side of the power semiconductor die and above the Cu layer; patterning the capping layer so that the capping layer surrounds the first power terminal on at least one lateral side; electrically coupling the second power terminal to the die carrier; and soldering a contact clip to the Cu layer of the first power terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The accompanying drawings illustrate examples and are used together with the description to explain the principles of the present disclosure. In view of the following detailed description, other examples and many expected advantages of the present disclosure will be easily understood. The elements of the accompanying drawings are not necessarily drawn to scale relative to each other. The same or similar reference numerals represent the same or similar parts.

[0006] Figure 1A and Figure 1B A top view of a power semiconductor device including a patterned capping layer is shown ( Figure 1A ) and Section View ( Figure 1B ).

[0007] Figure 2 A cross-sectional view of another power semiconductor component is shown, in which a cover layer is arranged only above the Cu layer of the first power terminal.

[0008] Figure 3 A cross-sectional view of another power semiconductor device is shown, the power semiconductor device including a cover layer and further including a polymer ring arranged around a first power terminal.

[0009] Figure 4 A top view of another power semiconductor device is shown, the power semiconductor device comprising a metal finger structure arranged below a cover layer.

[0010] FIG. 5A to FIG. 5D A power semiconductor device is shown at various stages of fabrication according to an exemplary method for fabricating a power semiconductor device.

[0011] Figure 6 is a flow chart of an exemplary method for manufacturing a power semiconductor device. DETAILED DESCRIPTION

[0012] In the following detailed description, known structures and elements are shown in schematic form to facilitate description of one or more aspects of the present disclosure. In this regard, directional terms such as "top", "bottom", "left", "right", "upper", "lower", etc. are used with reference to the orientation of the drawings being described. Because the components of the present disclosure can be positioned in many different orientations, the directional terms are used for illustrative purposes only. It should be understood that other examples can be utilized and that structural or logical changes can be made.

[0013] In addition, although the specific features or aspects of the examples may be disclosed only about one of several embodiments, such features or aspects may be combined with one or more other features or aspects of other embodiments, as long as it may be desirable and advantageous for any given or specific application, unless otherwise specifically noted or unless technically limited. In addition, with respect to the terms "including", "having", "with" or other variations thereof used in the specific embodiments or claims, these terms are intended to represent inclusion in a manner similar to the term "including". The terms "coupled" and "connected" and their derivatives may be used. It should be understood that these terms may be used to indicate that two elements cooperate or interact with each other, whether they are in direct physical or electrical contact, or they are not in direct contact with each other; an intermediate element or layer may be provided between the elements of "engagement", "attachment" or "connection". However, the elements of "engagement", "attachment" or "connection" may also be in direct contact with each other. In addition, the term "exemplary" is meant only as an example, not the best or optimal.

[0014] The examples of power semiconductor devices described below may use various types of semiconductor dies or circuits incorporated into semiconductor dies, including: AC / DC or DC / DC converter circuits, inverter circuits, power MOS transistors, power Schottky diodes, JFETs (junction gate field effect transistors), power bipolar transistors, power integrated circuits, etc.

[0015] The semiconductor die may have terminals (or electrodes) that allow electrical contact to be made with an integrated circuit included in the semiconductor die. The terminals may include one or more electrode metal layers applied to the semiconductor material of the semiconductor die. The electrode metal layers may be manufactured to have any desired geometry and any desired material composition. For example, the electrode metal layers may include or be made of a material selected from the group consisting of Cu, Ni, NiSn, Au, Ag, Pt, and Pd.

[0016] Efficient power semiconductor devices and efficient methods for manufacturing power semiconductor devices can, for example, reduce material consumption, ohmic losses, chemical waste, etc., and thus can achieve energy and / or resource savings. Therefore, as specified in the present specification, improved power semiconductor devices and improved methods for manufacturing power semiconductor devices can at least indirectly contribute to green technology solutions, i.e. provide climate-friendly solutions that reduce energy and / or resource usage.

[0017] Figure 1A and Figure 1B A power semiconductor device 100 is shown, comprising a die carrier 110 , a power semiconductor die 120 , a contact clip 130 and a patterned cover layer 140 . Figure 1A 1 shows a top view of a power semiconductor device 100 , Figure 1B Shown along Figure 1A Cross-sectional view along line BB'.

[0018] The power semiconductor device 100 may be, for example, a power semiconductor package or a part of a power semiconductor package. The power semiconductor package may, for example, include a power semiconductor die arranged on a die carrier, an encapsulation encapsulating the power semiconductor die, and external contacts electrically coupled to the power semiconductor die.

[0019] The power semiconductor device 100 may be configured to operate at high voltage and / or high current. The power semiconductor device 100 may provide any suitable circuit, or the power semiconductor device 100 may be part of any suitable circuit. Examples of such circuits are converter circuits, inverter circuits, half-bridge circuits, full-bridge circuits, etc.

[0020] The die carrier 110 may include or consist of a suitable metal or metal alloy. The die carrier 110 may, for example, include Cu or consist of Cu. According to one example, the die carrier 110 is a lead frame part. In this case, the power semiconductor device 100 may, for example, include additional components that are parts of the same lead frame as the die carrier 110, such as external contacts.

[0021] The power semiconductor die 120 is arranged on the die carrier 110. The power semiconductor die 120 may in particular be arranged over an upper side of the die carrier 110. A lower side of the die carrier 110 opposite to the upper side may, for example, be exposed from an encapsulation (not shown) of the power semiconductor device 100. The lower side of the die carrier 110 may, for example, be configured to be coupled to a heat sink and / or to an application board.

[0022] The power semiconductor die 120 includes a first side 121 and an opposite second side 122. The first side 121 faces away from the die carrier 110, and the first side 121 includes a first power terminal 123 having a Cu layer 150. According to an example, the first power terminal 123 may include one or more additional metal layers ( Figure 1B One or more additional metal layers may be arranged between the Cu layer 150 and the semiconductor material of the power semiconductor die 120 .

[0023] The first power terminal 123 may be, for example, a source terminal, a drain terminal, an emitter terminal, or a collector terminal. The second side 122 of the power semiconductor die 120 includes a second power terminal 124 electrically coupled to the die carrier 110. The second power terminal 124 may be coupled to the die carrier 110, for example, via a second solder joint. The second power terminal 124 may be, for example, a source terminal, a drain terminal, an emitter terminal, or a collector terminal. According to one example, the first power terminal 123 is a source terminal and the second power terminal 124 is a drain terminal, while according to another example, the opposite is true.

[0024] The contact clip 130 is electrically coupled to the Cu layer 150 of the first power terminal 123 through the solder joint 160 (note that the solder joint 160 is not shown in FIG. 1 in order to illustrate the Cu layer 150). Figure 1A 1 ). The contact clip 130 may be arranged above the power semiconductor die 120 and above the die carrier 110. The contact clip 130 may include or consist of any suitable metal or metal alloy, such as copper. According to an example, the contact clip 130 is a lead frame part, in particular a part of the lead frame different from the die carrier 110.

[0025] The contact clip 130 may, for example, be configured to provide an electrical connection between the first power terminal 123 of the power semiconductor die 120 and an external contact of the power semiconductor device 100. To this end, a distal end of the contact clip 130 may be coupled to the external contact via, for example, another solder joint (wherein the distal end of the contact clip 130 extends beyond the periphery of the die carrier 110).

[0026] The cover layer 140 is arranged on the first side 121 of the power semiconductor die 120. According to an example, the cover layer 140 is arranged only on the first side 121 of the power semiconductor die 120 and not on the second side 122 of the power semiconductor die 120. The cover layer 140 is a patterned layer, which means that the cover layer 140 has a predefined shape, wherein only a portion of the first side 121 is covered by the cover layer 140. The cover layer 140 may, for example, cover about 5% to about 95% of the first side 121. The lower limit of the range may also be about 10%, about 20%, about 30%, or about 40%, and the upper limit may also be about 90%, about 80%, about 70%, about 60%, or about 50%.

[0027] The cover layer 140 surrounds the first power terminal 123 on at least one lateral side. This may mean that the cover layer 140 is arranged along a portion or all of at least one of the lateral sides of the first power terminal 123. For example, the cover layer 140 may be arranged along the first lateral side 123_1 of the first power terminal 123, but not along one or more of the second lateral side 123_2, the third lateral side 123_3, and the fourth lateral side 123_4. According to another example, the cover layer 140 may be arranged along two of the lateral sides 123_1 to 123_4, along three of the lateral sides 123_1 to 123_4, or along all four of the lateral sides 123_1 to 123_4. In particular, the cover layer 140 may completely surround the first power terminal 123 on all lateral sides 123_1 to 123_4. The periphery of the first power terminal 123 may be defined by the cover layer 140 , ie, the first power terminal 123 is exposed from the cover layer 140 only within the periphery.

[0028] The cover layer 140 is arranged on the Cu layer 150 of the first power terminal 123. In other words, the cover layer 140 may be arranged (directly) on the Cu layer 150 and may cover a portion of the Cu layer 150, for example, an outer portion. Figure 1B In the example shown, the capping layer 140 is also arranged directly on the semiconductor material of the power semiconductor die 120. However, the capping layer 140 may also be arranged only on the Cu layer 150, or the capping layer 140 may be arranged on one or more additional layers (e.g., a hard passivation layer) on the semiconductor material and on the Cu layer 150.

[0029] The cover layer 140 is composed of Al2O3 and / or SiO2. For example, the cover layer 140 may be composed of only Al2O3 except for unavoidable contaminants, or the cover layer 140 may be composed of only SiO2 except for unavoidable contaminants. According to another example, the cover layer 140 may include an Al2O3 layer and a SiO2 layer. The cover layer 140 may be manufactured, for example, using a suitable atomic layer deposition (ALD) process or a suitable chemical vapor deposition (CVD) process.

[0030] The cover layer 140 is configured to prevent the liquid solder material from seeping out from the periphery of the first power terminal 123. In other words, during the manufacture of the power semiconductor device 100, in particular during the manufacture of the solder joint 160, the cover layer 140 can act as a barrier to the liquid solder material and can ensure that no liquid solder material comes into contact with other parts of the first side 121 other than the first power terminal 123. The material of the cover layer 140 can be particularly configured to be non-wettable by the liquid solder material.

[0031] In addition, the capping layer 140 may also prevent oxidation of the Cu layer 150 to prevent delamination of the encapsulation material from the power semiconductor die 120 .

[0032] According to one example, the solder joint 160 includes a Pb-free solder material. According to another example, the solder joint 160 includes a solder material containing Pb. The solder material of the solder joint 160 may, for example, include Sn or consist of Sn.

[0033] According to an example, the power semiconductor device 100 includes one or more further terminals 170 arranged laterally close to the first power terminal 123 on the first side 121 of the power semiconductor die 120. The one or more further terminals 170 may, for example, include a control terminal (e.g. a gate terminal) and / or a sensing terminal (e.g. a source sensing terminal or a temperature sensing terminal).

[0034] According to an example, one or more further terminals 170 are not surrounded by the cover layer 140. It may not be necessary to surround the further terminals 170 with the cover layer 140, since connection wires rather than contact clips are coupled to the further terminals 170, so there is no risk of solder seepage.

[0035] According to an example, the power semiconductor device 100 further comprises a polymer layer 180. The polymer layer 180 may, for example, comprise or consist of an imide. The polymer layer 180 may substantially surround the first power terminal 123. The Cu layer 150 may, for example, be at least partially arranged over the polymer layer 180. The cover layer 140 may, for example, be at least partially arranged over the polymer layer 180. The polymer layer 180 may, for example, cover those portions of the first side 121 of the power semiconductor die 120 that are not part of the first power terminal 123 or the further terminal 170.

[0036] Figure 2 A cross-sectional view of a power semiconductor device 200 is shown, which may be similar or identical to the power semiconductor device 100 except for the differences described below.

[0037] In the power semiconductor device 200 , the cover layer 140 is arranged only (directly) on the Cu layer 150 . In particular, the cover layer 140 is not in contact with the polymer layer 180 . Furthermore, the Cu layer 150 , in particular the outer portion of the Cu layer 150 , is arranged on the polymer layer 180 .

[0038] like Figure 2As shown, only the inner portion of the Cu layer 150 is exposed from the capping layer 140 and can be wetted by the liquid solder material to form the solder joint 160. Note that in both the power semiconductor device 100 and the power semiconductor device 200, the capping layer 140 is configured to act as a solder barrier layer, rather than configuring the polymer layer 180 to act as a solder barrier layer.

[0039] Figure 3 A cross-sectional view of another power semiconductor device 300 is shown, which may be similar or identical to the power semiconductor device 100 or 200 except for the differences described below.

[0040] In the power semiconductor device 300, the polymer layer 180 is patterned so that the polymer ring 180' surrounds the first power terminal 123. The polymer ring 180' can be arranged, for example, along the periphery of the first power terminal 123. Due to the presence of the polymer ring 180', the first power terminal 123 has a topological structure including a raised ring structure. The raised ring structure can, for example, help to properly align the contact clip 130 on top of a drop of liquid solder material during the manufacture of the power semiconductor device 300.

[0041] Figure 4 A top view of another power semiconductor device 400 is shown, which may be similar or identical to any of the power semiconductor devices 100 to 300 , except for the differences described below.

[0042] The power semiconductor device 400 comprises at least one metal finger structure 410 extending from a point outside the periphery of the first power terminal 123 to a point inside the periphery. For example, one or more metal finger structures 410 may extend from one or more of the further terminals 170 to a point inside the periphery of the first power terminal 123. Furthermore, the metal finger structures 410 are arranged on the first side 121 of the power semiconductor die 120, below the Cu layer 150. The one or more metal finger structures 410 may, for example, be configured for voltage sensing and / or for temperature sensing and / or may be configured as an electrical contact between a gate terminal and the first power terminal 123.

[0043] According to an example, the power semiconductor device 400 includes a polymer ring 180 ′. In this case, the polymer ring 180 ′ may have an opening at the metal finger structure 180 ′.

[0044] The metal finger structure may include or consist of any suitable metal. According to one example, the metal finger structure includes or consists of Al, Cu, Ti or W.

[0045] FIG. 5A to FIG. 5DA power semiconductor device 100 is shown at various stages of fabrication according to an exemplary method for fabricating a power semiconductor device.

[0046] like Figure 5A As shown, a power semiconductor die 120 is provided. A Cu layer is deposited on a first side 121 of the power semiconductor die 120. According to an example, manufacturing the Cu layer 150 of the first power terminal 123 further includes patterning the deposited Cu layer. According to an example, the deposited Cu layer may also be patterned to provide an additional terminal 170.

[0047] like Figure 5B As shown, the capping layer is deposited on the first side 121 of the power semiconductor die 120, in particular on the Cu layer 150. In addition, a patterning process is performed on the deposited capping layer to produce a patterned capping layer 140. The capping layer 140 may, for example, be composed of Al2O3 and / or SiO2, and depositing the capping layer may, for example, include using a suitable conformal coating process, such as ALD or CVD. Patterning the deposited capping layer may, for example, include suitable photolithography and etching processes, followed by resist stripping and cleaning processes. The etching process may, for example, be performed using hydrofluoric acid.

[0048] According to one example, the capping layer is deposited such that the patterned capping layer 140 has a thickness in the range of about 4 nm to about 50 nm, wherein the thickness is measured perpendicular to the first side 121 of the power semiconductor die 120. The lower limit of the range may also be about 5 nm, about 6 nm, about 7 nm, about 8 nm, or about 10 nm, and the upper limit may also be about 40 nm, about 30 nm, about 20 nm, or about 15 nm. According to one example, the patterned capping layer 140 has a minimum width w or a maximum width w in the range of about 200 μm to about 500 μm around the periphery of the first power terminal 123, wherein the width w is measured parallel to the first side 121 of the power semiconductor die 120. The lower limit of the range may also be about 250 μm, about 300 μm, or about 350 μm, and the upper limit may also be about 450 μm or about 400 μm.

[0049] like Figure 5C As shown in , a die carrier 110 is provided and a power semiconductor die 120 is coupled to the die carrier 110. This may, for example, include soldering the second side 122 of the power semiconductor die 120 to the die carrier 110. Instead of soldering, for example also a sintering process or a gluing process using a conductive glue may be used.

[0050] like Figure 5D As shown, a contact clip 130 is provided and the contact clip 130 is welded to the Cu layer 150 of the first power terminal 123 via a welding joint 160 (compare Figure 1B). During soldering, the cover layer 140 prevents solder from seeping out of the first power terminal 123. The cover layer 140 can also prevent the covered portion of the Cu layer 150 from being oxidized. This can, for example, prevent or at least mitigate delamination issues between the Cu layer 150 and the molding compound encapsulating the power semiconductor die 120.

[0051] According to an example, manufacturing the power semiconductor device 100 may include a further process of encapsulating the power semiconductor die 120 with an encapsulation. This may, for example, include molding over the power semiconductor die 120. The cover layer 140 may be completely encapsulated by the encapsulation. The contact clip 130 may be partially or completely encapsulated by the encapsulation.

[0052] Figure 6 is a flow chart of an exemplary method 600 for manufacturing a power semiconductor device. The method 600 may be used, for example, to manufacture any of the power semiconductor devices 100-400.

[0053] Method 600 includes: a process of providing a die carrier at 601; a process of arranging a power semiconductor die on the die carrier at 602, the power semiconductor die including a first side and an opposite second side, wherein the first side faces away from the die carrier and includes a first power terminal having a Cu layer, and wherein the second side includes a second power terminal; a process of depositing a covering layer composed of Al2O3 or SiO2 on the first side of the power semiconductor die and above the Cu layer at 603; a process of patterning the covering layer so that the covering layer surrounds the first power terminal on at least one lateral side at 604; a process of electrically coupling the second power terminal to the die carrier at 605; and a process of soldering a contact clip to the Cu layer of the first power terminal at 606, wherein the covering layer is configured to prevent liquid solder material from seeping out from the periphery of the first power terminal.

[0054] Example

[0055] Hereinafter, a power semiconductor device and a method for manufacturing the power semiconductor device are further explained using specific examples.

[0056] Example 1 is a power semiconductor device comprising: a die carrier; a power semiconductor die arranged on the die carrier, the power semiconductor die comprising a first side and an opposite second side, wherein the first side faces away from the die carrier and comprises a first power terminal having a Cu layer, and wherein the second side comprises a second power terminal electrically coupled to the die carrier; a contact clip electrically coupled to the Cu layer of the first power terminal via a solder joint; and a patterned covering layer arranged on the first side of the power semiconductor die, the covering layer surrounding the first power terminal on at least one lateral side, the covering layer arranged on top of the Cu layer, and the covering layer consisting of Al2O3 or SiO2.

[0057] Example 2 is the power semiconductor device of Example 1, wherein the cover layer (140) includes an opening larger than the contact clip, and wherein the solder joint is arranged within the opening.

[0058] Example 3 is the power semiconductor device of Example 1, wherein the cover layer is configured to prevent liquid solder material from seeping out from a periphery of the first power terminal.

[0059] Example 4 is the power semiconductor device of Examples 1-3, further comprising: an imide ring disposed on the first side of the power semiconductor die, below the Cu layer, and along a periphery of the first power terminal.

[0060] Example 5 is the power semiconductor device of Examples 1-4, wherein the opening is located within the imide ring (180').

[0061] Example 6 is a power semiconductor device of Example 4, which further includes: one or more metal finger structures extending from a point outside the periphery of the first power terminal to a point inside the periphery, the metal finger structures being arranged on the first side of the power semiconductor die and below the Cu layer, wherein the imide ring has an opening at the metal finger structures.

[0062] Example 7 is a power semiconductor device of any one of the preceding examples, the power semiconductor device further comprising: at least one control or sensing terminal arranged on a first side of the power semiconductor die and laterally adjacent to the first power terminal, wherein the covering layer separates the first power terminal from the control or sensing terminal.

[0063] Example 8 is the power semiconductor device of any of the preceding examples, wherein the cover layer has a width of at least 200 μm around a perimeter of the first power terminal, the width being measured parallel to the first side of the power semiconductor die.

[0064] Example 9 is the power semiconductor device of any of the preceding examples, wherein the capping layer has a thickness in a range of 4 nm to 50 nm, the thickness being measured perpendicular to the first side of the power semiconductor die.

[0065] Example 10 is the power semiconductor device of any of the preceding examples, wherein the solder joint comprises a Pb-free solder material.

[0066] Example 11 is the power semiconductor device of any of the preceding examples, wherein the first power terminal is a source terminal, the second power terminal is a drain terminal, and the contact clip electrically connects the first power terminal to an external contact of the power semiconductor device.

[0067] Example 12 is the power semiconductor device of any of the preceding examples, wherein the cover layer surrounds the first power terminal on all lateral sides such that the cover layer defines a perimeter of the first power terminal.

[0068] Example 13 is a method for manufacturing a power semiconductor device, the method comprising: providing a die carrier; arranging a power semiconductor die on the die carrier, the power semiconductor die comprising a first side and an opposite second side, wherein the first side faces away from the die carrier and comprises a first power terminal having a Cu layer, and wherein the second side comprises a second power terminal; depositing a covering layer composed of Al2O3 or SiO2 on the first side of the power semiconductor die and above the Cu layer; patterning the covering layer so that the covering layer surrounds the first power terminal on at least one lateral side; electrically coupling the second power terminal to the die carrier; and soldering a contact clip to the Cu layer of the first power terminal.

[0069] Example 14 is the method of Example 13, wherein the cover layer is configured to prevent liquid solder material from seeping from a periphery of the first power terminal.

[0070] Example 15 is the method of Example 13 or 14, wherein depositing the capping layer comprises depositing the capping layer using an atomic layer deposition process or a chemical vapor deposition process.

[0071] Example 16 is the method of Examples 13-15, wherein patterning the capping layer includes depositing the capping layer over the first power terminal and subsequently at least partially removing the capping layer over the first power terminal.

[0072] Example 17 is the method of any of Examples 13-16, wherein patterning the capping layer includes removing the capping layer over a specific portion of the first side of the power semiconductor die using a photolithography process.

[0073] Example 18 is the method of Example 15 or 16, wherein the covering layer is removed using hydrofluoric acid.

[0074] Example 19 is the method of any of Examples 13-18, further comprising disposing an imide ring on the first side of the power semiconductor die, below the Cu layer, and along a perimeter of the first power terminal.

[0075] Example 20 is a method of any of Examples 13-19, wherein the first side of the power semiconductor die also includes at least one control or sense terminal arranged laterally proximate to the first power terminal, and wherein the covering layer is deposited over the control or sense terminal and the covering layer is subsequently removed over the control or sense terminal.

[0076] Example 21 is the method of any of Examples 13-20, wherein the capping layer is deposited to have a thickness in a range of 4 nm to 50 nm.

[0077] Example 22 is the method of any of Examples 13-21, wherein the cover layer is patterned such that the cover layer surrounds the first power terminal on all lateral sides and such that the cover layer defines a perimeter of the first power terminal.

[0078] Example 23 is an apparatus comprising means for performing the method according to any one of Examples 13-22.

[0079] Although the present disclosure has been shown and described with respect to one or more embodiments, changes and / or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular, with respect to the various functions performed by the above-described components or structures (assemblies, devices, circuits, systems, etc.), unless otherwise indicated, the terms used to describe these components (including references to "means") are intended to correspond to any component or structure (e.g., functionally equivalent) that performs the specific functions of the components, even if not structurally equivalent to the disclosed structures that perform the functions of the exemplary embodiments shown herein of the present disclosure.

Claims

1. A power semiconductor device (100), comprising: a bare die carrier (110), A power semiconductor die (120) is arranged on the die carrier (110), the power semiconductor die (120) comprising a first side (121) and an opposite second side (122), wherein the first side (121) faces away from the die carrier (110) and comprises a first power terminal (123) having a Cu layer (150), and the second side (122) comprises a second power terminal (124) electrically coupled to the die carrier (110), a contact clip (130) electrically coupled to the Cu layer (150) of the first power terminal (123) via a solder joint (160), and A patterned cover layer (140) is arranged on the first side (121) of the power semiconductor die (120), the cover layer (140) surrounds the first power terminal (123) on at least one lateral side, the cover layer (140) is arranged on the Cu layer (150), and the cover layer (140) is composed of Al2O3 or SiO2.

2. The power semiconductor device (100) according to claim 1, wherein: The cover layer (140) includes an opening larger than the contact clip, and the weld joint is arranged in the opening.

3. The power semiconductor device (100) according to claim 1 or 2, wherein: The power semiconductor device (100) further comprises: An imide ring (180') is arranged on the first side (121) of the power semiconductor die (120), below the Cu layer (150), and along the periphery of the first power terminal (123).

4. The power semiconductor device (100) according to claim 3, wherein: The opening is located within the imide ring (180').

5. The power semiconductor device (100) according to claim 3 or 4, further comprising: one or more metal finger structures (410) extending from a point outside the periphery of the first power terminal (123) to a point inside the periphery, the metal finger structures (410) being arranged on the first side (121) of the power semiconductor die (120) and below the Cu layer (150), The imide ring (180') has an opening at the metal finger structure (410).

6. The power semiconductor device (100) according to any one of the preceding claims, further comprising: at least one control or sensing terminal (170) arranged on a first side (121) of the power semiconductor die (120) laterally adjacent to the first power terminal (123), The cover layer (140) separates the first power terminal (123) from the control or sensing terminal (170).

7. The power semiconductor device (100) according to any one of the preceding claims, wherein: The cover layer (140) has a width of at least 200 μm around the periphery of the first power terminal (123), the width being measured parallel to the first side (121) of the power semiconductor die (120).

8. The power semiconductor device (100) according to any one of the preceding claims, wherein: The capping layer (140) has a thickness in the range of 4 nm to 50 nm, the thickness being measured perpendicularly to the first side (121) of the power semiconductor die (120).

9. The power semiconductor device (100) according to any one of the preceding claims, wherein: The solder joint (160) comprises a Pb-free solder material.

10. The power semiconductor device (100) according to any one of the preceding claims, wherein: The first power terminal (123) is a source terminal, the second power terminal (124) is a drain terminal, and the contact clip (130) electrically connects the first power terminal (123) to an external contact of the power semiconductor device (100).

11. The power semiconductor device (100) according to any one of the preceding claims, wherein: The cover layer (140) surrounds the first power terminal (123) on all lateral sides such that the cover layer (140) defines a periphery of the first power terminal (123).

12. A method (600) for manufacturing a power semiconductor device, the method (600) comprising: providing (601) a die carrier, A power semiconductor die is arranged (602) on the die carrier, the power semiconductor die comprising a first side and an opposite second side, wherein the first side faces away from the die carrier and comprises a first power terminal having a Cu layer, and the second side comprises a second power terminal, depositing (603) a capping layer consisting of Al2O3 or SiO2 on the first side of the power semiconductor die, over the Cu layer, patterning (604) the cover layer so that the cover layer surrounds the first power terminal on at least one lateral side, electrically coupling (605) the second power terminal to the die carrier, and A contact clip is soldered (606) to the Cu layer of the first power terminal.

13. The method (600) of claim 12, wherein: Depositing (603) the capping layer includes depositing the capping layer using an atomic layer deposition process or a chemical vapor deposition process.

14. The method (600) according to claim 12 or 13, wherein: Patterning (604) the capping layer includes depositing the capping layer over the first power terminal and subsequently at least partially removing the capping layer over the first power terminal.

15. The method (600) according to any one of claims 12-14, wherein: Patterning (604) the capping layer includes removing the capping layer over certain portions of the first side of the power semiconductor die using a photolithography process.

16. The method (600) according to claim 14 or 15, wherein: The cover layer was removed using hydrofluoric acid.

17. The method (600) according to any one of claims 12-16, further comprising: An imide ring is arranged on a first side of the power semiconductor die, beneath the Cu layer and along a perimeter of the first power terminal.

18. The method (600) according to any one of claims 12 to 17, wherein: The first side of the power semiconductor die also includes at least one control or sense terminal arranged laterally adjacent to the first power terminal, and The cover layer is deposited over the control or sense terminals and the cover layer is subsequently removed over the control or sense terminals.

19. The method (600) according to any one of claims 12 to 18, wherein: The capping layer is deposited (603) to have a thickness in the range of 4 nm to 50 nm.

20. The method (600) according to any one of claims 12-19, wherein: The cover layer is patterned (604) such that the cover layer surrounds the first power terminal on all lateral sides and such that the cover layer defines a perimeter of the first power terminal.

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