Electronic chip with connecting columns

Abstract

The invention relates to an electronic chip with connecting columns. The present description relates to an electronic circuit comprising a semiconductor substrate having opposite first and second faces, and an electrically conductive post intended to be connected to an element external to the electronic circuit, extending through the semiconductor substrate from the second face to the first face and protruding from the first face.

Description

Technical Field

[0001] The present description relates to the field of electrical connection between an electronic chip and a housing or between two electronic chips, and more particularly to connection pillars of an electronic chip. Background Art

[0002] In order to connect the electronic chip to an external element, a connection post or pad can be provided on one side of the electronic chip, and the connection post or pad is connected to a conductive track on the electronic chip. In this way, the connection post can be made to contact a conductive area or track located on an external element (such as a housing or another electronic chip).

[0003] There are some disadvantages to using connecting posts, specifically, the fragility of the connecting posts when they are small or when they have a high aspect ratio, the aspect ratio being the ratio between the height and the diameter of the connecting pad, the high duration and cost of the method for manufacturing the connecting pad when the aspect ratio is high, and the risk of tearing the connecting post off the face of the electronic chip on which it is formed. Summary of the invention

[0004] One embodiment addresses all or some of the disadvantages of known electronic chips including connection pillars.

[0005] One embodiment provides an electronic circuit comprising a semiconductor substrate (12) having opposing first and second faces and a conductive post intended to be connected to an element external to the electronic circuit, extending from the second face through the semiconductor substrate to the first face and protruding from the first face.

[0006] According to an embodiment, the electronic circuit includes, for each electrically conductive pillar, an electrically insulating layer located in the semiconductor substrate and completely surrounding the electrically conductive pillar in the semiconductor substrate.

[0007] According to an embodiment, the electronic circuit comprises an active area extending from the second face into the semiconductor substrate and comprising at least one electronic component, each conductive pillar further comprising a connecting track extending over the second face and electrically connected to the active area.

[0008] According to an embodiment, the electronic circuit further comprises at least one electrically insulating wall extending from the second side through the semiconductor substrate to the first side and delimiting a semiconductor portion of the semiconductor substrate including the active area.

[0009] According to an embodiment, the electrically insulating wall is separated from the electrically insulating layer surrounding the electrically conductive pillar by material of the semiconductor substrate.

[0010] According to an embodiment, the electrically insulating layer surrounding the electrically conductive pillar is part of the electrically insulating wall.

[0011] According to an embodiment, each conductive pillar protrudes from the first face to a height greater than 25 μm.

[0012] One embodiment also provides a method of manufacturing an electronic circuit as defined above, comprising: for each conductive pillar, forming a first opening in the semiconductor substrate, the first opening extending from the second face into the semiconductor substrate over a portion of the thickness of the semiconductor substrate, and filling the first opening with a conductive material.

[0013] According to an embodiment, the method comprises the step of thinning the semiconductor substrate on the side of the first face such that each conductive pillar protrudes from the first face.

[0014] According to an embodiment, the method comprises the step of forming an electrically insulating layer on the walls of each first opening before filling the first openings with the electrically conductive material.

[0015] According to an embodiment, the method includes forming at least one second opening extending from the second face into the semiconductor substrate over a portion of the thickness of the semiconductor substrate, the second opening being shallower than the first opening, and completely filling the second opening with an electrically insulating material. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The foregoing features and advantages, as well as other features and advantages, will be described in detail in the following description of specific embodiments given by way of illustration and not limitation, with reference to the accompanying drawings, in which:

[0017] Figure 1 is a schematic partial cross-sectional view of an example electronic chip;

[0018] Figure 2 is a schematic partial cross-sectional view of an electronic chip;

[0019] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 and Fig.13 Each is Figure 2 A schematic partial cross-sectional view of a structure obtained at one step of an embodiment of a method for manufacturing an electronic chip shown in ;

[0020] Fig.14 It is a graphic Figure 1 Schematic partial cross-sectional view of the deposition of conductive material on the connection pillars of the electronic chip shown in ;

[0021] Fig.15 It is a graphic Figure 2Schematic partial cross-sectional view of the deposition of conductive material on the connection pillars of the electronic chip shown in ;

[0022] Fig.16 , Fig.17 , Fig.18 and Fig.19 yes Figure 2 A schematic partial top cross-sectional view of an embodiment of an electronic chip at a step in a manufacturing method; and

[0023] Fig. 20 is a schematic partial cross-sectional view of an embodiment of an electronic circuit. DETAILED DESCRIPTION

[0024] Similar features in the various figures are denoted by similar reference numerals. In particular, common structural and / or functional features among the various embodiments may have the same reference numerals and may have exactly the same structure, dimensions, and material properties.

[0025] For clarity, only operations and elements that are useful for understanding the embodiments described herein are illustrated and described in detail.

[0026] Unless otherwise indicated, when referring to two elements being connected together, this means a direct connection without any intermediate elements except conductors, and when referring to two elements being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0027] In the following disclosure, unless otherwise indicated, when referring to absolute position qualifiers (such as terms "front", "back", "top", "bottom", "left", "right", etc.) or relative position qualifiers (such as terms "above", "below", "higher", "lower", etc.) or referring to orientation qualifiers (such as "horizontal", "vertical", etc.), they all refer to the orientation shown in the figure.

[0028] Unless otherwise specified, the expressions "about", "approximately", "substantially" and "around" mean within 10%, and preferably within 5%. In addition, the terms "insulator" and "conductor" herein mean "electrically insulating" and "conductive", respectively.

[0029] Figure 1 is a schematic partial cross-sectional view of an example electronic chip 10 .

[0030] The electronic chip 10 comprises:

[0031] A semiconductor substrate 12 including a bottom surface 14 and a top surface 16;

[0032] an insulating layer 18 covering the bottom surface 14;

[0033] an active region 20 in the substrate 12 flush with the top surface 16 , and one or more electronic components (not shown) formed in and / or on the active region 20 ;

[0034] an interconnect structure 22 covering the top surface 16 , comprising a stack of insulating layers 24 and conductive tracks 26 in and / or between the insulating layers 24 , some of the conductive tracks 26 being in contact with the active area 20 ;

[0035] openings 28 in the stack of insulating layers 24 , each opening 28 exposing a portion of one of the conductive tracks 26 ; and

[0036] Connecting studs or pads 30, Figure 1 Two connecting posts are shown by way of example in FIG. 2 , each post being connected to one of the conductive tracks 26 .

[0037] Each connecting column 30 includes a trunk 32 extending along an axis A substantially orthogonal to the top surface 16. The trunk 32 includes a base 34 on a side closest to the substrate 12, an end surface 36 opposite the base 34 on a side farthest from the substrate 12, and a sidewall 38 coupling the base 34 with the end surface 36. The connecting column 30 also includes an interface layer 40 between the base 34 and the interconnect structure 22. The column 30 also includes a finishing layer 42 covering the end surface 36 and a block 44 of bonding material covering the finishing layer 42.

[0038] Use as Figure 1 The connecting posts 30 shown in the drawings may have some disadvantages. When the connecting posts 30 are small in size or when they have a high aspect ratio (also known as form factor), the connecting posts 30 may be fragile. In addition, each connecting post 30 is mechanically connected to the interconnect structure 22 only by the interface layer 34. The method for manufacturing the connecting posts 30 may include an etching step, which may cause the interface layer 34 to be partially etched from its periphery. This weakens the bond between the trunk 32 and the interconnect structure 22. Therefore, the risk of tearing the connecting post 30 off from the connecting structure 22 increases. In addition, when the trunk 32 of the connecting post 30 is made of copper, the trunk 32 is generally manufactured by electroplating of copper deposited from the interface layer 34. The disadvantage of this method is that when the aspect ratio of the connecting pad 30 is high, the method for manufacturing the connecting pad 30 has a high duration and cost.

[0039] Figure 2 is a schematic partial cross-sectional view of an exemplary electronic chip 50. The electronic chip 50 includes, except that the connecting studs 30 are replaced by connecting studs or pads 60. Figure 1 All components of the electronic chip 10 shown in FIG.

[0040] According to one embodiment, each connecting column 60 comprises:

[0041] A trunk 62 extending along an axis Δ substantially orthogonal to the top surface 16 and extending from the top surface 16 through the substrate 12 to the bottom surface 14 and protruding from the bottom surface 14 to the outside of the substrate 12, the trunk 62 having a base 64 on a side closest to the top surface 16 of the substrate 12, an end surface 66 opposite to the base 64 on a side closest to the bottom surface 14 of the substrate 12, and a side wall 68 coupling the base 64 with the end surface 66;

[0042] An interface layer 70 covering the sidewall 68 of the backbone 62 and in direct physical contact with the sidewall 68;

[0043] A surface layer 72 covering the end surface 66 and in direct physical contact with the end surface 66;

[0044] a block 74 of bonding material, covering the facing 72;

[0045] a connecting track 76 located on the interconnect structure 22 and connecting the base 64 of the stem 62 to one of the conductive tracks 26 in one of the openings 28, with the interface layer 70 also being present between the connecting track 76 and the interconnect structure 22; and

[0046] An insulating layer 77 covers each connecting track 76 .

[0047] For each pillar 60, the electronic chip 50 also includes an insulating layer 78 located in the substrate 12, which surrounds the stem 62 over the entire portion of the stem 62 that extends into the substrate 12 and is interposed between the stem 62 and the substrate 12. The insulating layer 78 extends into the substrate 12 over the entire thickness of the substrate 12, from the bottom surface 14 to the top surface 16. The insulating layer 78 is in direct physical contact with the interface layer 70.

[0048] According to one embodiment, electronic chip 50 further comprises a lateral electrically isolating wall 80 extending into substrate 12 over the entire thickness of substrate 12, from bottom surface 14 to top surface 16. Wall 80 electrically isolates the portion of substrate 12 containing active area 20 from the rest of substrate 12.

[0049] Each post 60 is anchored in the substrate 12 over the entire thickness 12 of the substrate 12. Thus, the mechanical strength of the connecting posts 60 is advantageously improved compared to the posts 30. In addition, the risk of the connecting posts 60 being torn off is also reduced.

[0050] According to one embodiment, the substrate 12 is made of silicon (Si), silicon carbide (SiC), III-V compounds (particularly gallium nitride (GaN)) or II-VI compounds. The substrate 12 may have a single-layer or multi-layer structure, for example, a structure of the silicon-on-insulator (SOI) type. As an example, the substrate 12 may include a GaN layer covering a silicon support. According to one embodiment, the thickness of the substrate 12 ranges from 50 μm to 300 μm.

[0051] The trunk 62 may have a substantially cylindrical shape with a Δ axis, with a circular, square or rectangular base, etc. The average dimension D (in this embodiment, the diameter) of the trunk 62 ranges from 10 μm to 150 μm, and the average diameter D corresponds to the diameter of a trunk with a circular base whose surface is the same as the surface of the trunk 62. Figure 2 In this embodiment shown in , the average diameter D remains the same from the first end (i.e., base 64) of the trunk 62 protruding, extending or extending outward from the first face 14 of the semiconductor substrate 12 to the second end (i.e., end face 66) protruding, extending or extending outward from the second face 16 of the semiconductor substrate 12 opposite to the first end. In other words, the average diameter D remains the same along the length L of the trunk 62, which extends from the first end (i.e., base 64) of the trunk 62 to the second end (i.e., end face 66). According to one embodiment, the end face 66 is substantially perpendicular to the axis Δ. The trunk 62 and the connecting track 76 are made of metal (e.g., copper, nickel, silver, gold) or alloys of these metals. The total height H of the trunk 62 from the end face 66 to the top surface of the connecting track 76 ranges from 75μm to 400μm. The height of the trunk 62 protruding from the insulating layer 18 ranges from 25μm to 100μm. The aspect ratio of the trunk 62 , corresponding to the ratio between the overall height H of the trunk 62 and the average diameter D of the trunk 62 , ranges from 0.5 to 40.

[0052] The metal tracks 26 are made of, for example, a material selected from copper, copper alloys, titanium, titanium alloys, titanium nitride, platinum, and platinum alloys. According to one embodiment, the thickness of each metal track 26 ranges from 0.5 μm to 1.5 μm.

[0053] Each insulating layer 18, 24, 77 and 78 and each insulating wall 80 can be made of a dielectric material, for example, silicon oxide (SiO2), silicon nitride (e.g., Si3N4), silicon oxynitride (e.g., Si2ON2), or hafnium oxide (HfO2). According to one embodiment, the thickness of the insulating layer 18 ranges from 0.1 μm to 0.5 μm. According to one embodiment, the thickness of each insulating layer 24 ranges from 0.5 μm to 1.5 μm. According to one embodiment, the thickness of the insulating layer 77 ranges from 0.5 μm to 1.5 μm. According to one embodiment, the thickness of the insulating layer 78 ranges from 0.2 μm to 1 μm. According to one embodiment, the thickness of the wall 80 ranges from 1 μm to 3 μm.

[0054] The thickness of the interface layer 70 ranges from 10 nm to 1 μm. The interface layer 70 serves as a primer for forming the backbone 62 and the connection track 76 of the connection pillar 60. The interface layer 70 may include a titanium or chromium layer serving as an adhesion layer, and a copper layer serving as a base layer for subsequently forming the backbone 62 and the connection track 76.

[0055] The thickness of the surface layer 72 ranges from 10 nm to 5 μm, for example 3 μm. The surface layer 72 is made of a conductive material, which improves the adhesion of the block 74. The surface layer 72 is made of, for example, a metal, in particular gold or silver, and optionally includes one or more bonding layers and / or one or more barrier layers between the trunk material 62 and the block material 74 deposited on the trunk 62, including, for example, platinum (Pt), palladium (Pd), nickel (Ni), titanium (Ti), chromium (Cr) and / or tantalum (Ta). The surface layer 72 also allows to prevent oxidation of the end face 66 of the trunk 62 when the assembly method is not performed in a neutral or reducing atmosphere.

[0056] The material forming the block 74 depends in particular on the assembly method implemented to attach the electronic chip 50 to another component. In particular, the assembly method may include a welding step or a sintering step. The material forming the block 74 may include an active filler comprising particles of a metallic material, such as silver, copper, tin or an alloy of these metals. The active filler may also include gold and other additives, such as polymers and / or ceramics, which do not participate in the attachment of the connecting column, but facilitate the method for implementing the block 74. The height of the block 74 measured from the top layer 72 may be approximately 25 μm.

[0057] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 and Fig.13 Each is used to manufacture Figure 2 Schematic partial cross-sectional view of the structure obtained at one step of an embodiment of the method of an electronic chip 50 shown in FIG.

[0058] Figure 3 The structure obtained after forming an active area 20 and forming an interconnect structure 22 on the top surface 16 of the substrate 12 is illustrated. One or more electronic components (not shown) are formed in and / or on the active area 20. According to one embodiment, at this stage of the process, the substrate 12 corresponds to a board and the active areas 20 of several electronic chips are formed in and / or on the substrate 12, the active areas 20 being able to be identical or different. Figure 3, a single active area 20 is illustrated and the interconnect structure 22 includes two conductive tracks 26 connected to the active area 20, and one insulating layer 24 covering the conductive tracks 26 and the top surface 16 of the substrate 12 around the conductive tracks 26. At this stage of the method, the thickness of the substrate 12 is greater than the desired final thickness of the substrate 12. At this stage of the method, the thickness of the substrate 12 may range from 500 μm to 1.3 mm.

[0059] Figure 4 The structure obtained after forming an opening 82 at a desired location of each connecting column 60 and forming an opening 84 at a desired location of each wall 80 is illustrated. The openings 82 and 84 completely pass through the interconnect structure 22 and extend from the top surface 16 over a portion of the thickness of the substrate 12. The openings 82 have the same depth, and the openings 84 have the same depth. The depth of the opening 82 is greater than the depth of the opening 84. According to one embodiment, the depth of the opening 84 is substantially equal to the desired final thickness of the substrate 12. The depth of the opening 84 can range from 50 μm to 300 μm. According to one embodiment, the openings 82 and 84 are performed by deep reactive ion etching (DRIE). Depending on the method used to form the openings 82 and 84, the openings 82 and 84 can be performed simultaneously or in separate steps. In particular, for deep reactive ion etching, the etching rate depends on the opening diameter, so that the opening 84 having a width less than the average diameter of the opening 82 can be performed simultaneously with the opening 82.

[0060] Figure 5 The structure obtained after forming an insulating layer 78 in each opening 82 and forming an insulating wall 80 in each opening 84 is illustrated. At this stage of the method, the insulating layer 78 covers the sidewalls and bottom of the opening 82. This step may include depositing an insulating layer on the walls of the opening 84 and the walls of the opening 82 at the same time, the insulating layer having a thickness such that it completely fills the opening 84 but does not completely fill each opening 82, so that a cavity 86 is present in each opening 82 after forming the insulating layer.

[0061] Figure 6 The structure obtained after forming, for each connection stud to be made, an opening 28 in the insulating layer 24 for exposing one of the conductive tracks 26, depositing on the insulating layer 24 a mask 88 including, for each connection stud to be made, an opening 90, and forming an interface layer 70 in each opening 90, wherein the opening 90 exposes the cavity 86, the opening 28 and the portion of the insulating layer 24 coupling the cavity 86 with the opening 28. At this stage of the method, the interface layer 70 covers all the walls of the cavity 86, in particular the side walls and the bottom of the cavity 86, the walls of the opening 28 and the exposed portion of the insulating layer 24 coupling the cavity 86 with the corresponding opening 28. The mask 88 may correspond to a film applied on the insulating layer 24.

[0062] Figure 7 The structure obtained after completely filling each cavity 86 with a conductive material for each connection column to be formed, thereby forming the stem 62 of the connection column and forming the connection portion 76 of each connection column is illustrated. The conductive material constituting the stem 62 can be deposited by electroplating on the interface layer 70. In this case, the deposition of the conductive material is performed starting from the interface layer 70 in a direction substantially perpendicular to the interface layer 70. This advantageously enables the filling of the cavity 86 even if the form factor of the cavity 86 (i.e., the ratio between the height of the cavity and the diameter of the cavity) is high, because the conductive material is deposited in particular from the side walls of the cavity 86.

[0063] Figure 8 The structure obtained after removing the film 88 and forming an insulating layer 77 covering the connection track 76 for each connection stud is illustrated.

[0064] Fig. 9 The structure obtained after etching the substrate 12 from the bottom surface 14 of the substrate 12 is illustrated. At the end of the etching step, for each connection column, a portion of the trunk 62 surrounded by the interface layer 70 and the insulating layer 78 protrudes from the bottom surface 14 to the outside of the substrate 12, and the protrusion height H'. The etching step may include selective chemical etching with respect to the material forming the insulating layer 78. According to one embodiment, the etching of the substrate 12 is stopped when one end of the wall 80 is flush with the bottom surface 14. The height H' is set by the etching step.

[0065] Fig.10 The structure obtained after forming an insulating layer 18 on the bottom surface 14 of the substrate 12 is illustrated. According to one embodiment, the insulating layer 18 is made of the same material as the insulating layer 78, and the thickness of the insulating layer 18 at this stage of the method is substantially equal to the sum of the thickness of the insulating layer 78 and the desired final thickness of the insulating layer 18, for example, equal to twice the thickness of the insulating layer 78.

[0066] Fig.11 The structure obtained after completely etching away the portion of the insulating layer 78 exposed on the side of the bottom surface 14 of the substrate 12 is illustrated. This step may further allow the insulating layer 18 to be etched through the thickness of the insulating layer 78. An insulating layer 18 having a desired final thickness is then obtained.

[0067] Fig.12 The structure obtained after etching the interface layer 70 covering the end surface 66 , forming the top layer 72 , and forming a mass 74 of bonding material for each connection stud 60 is illustrated.

[0068] Fig.13 The structure obtained after a dicing step for separating the electronic chips 50 is illustrated. According to one embodiment, the dicing lines 91 are located between the walls 80 of adjacent electronic chips 50.

[0069] Each electronic chip 50 thus individualized can then be attached to an external element, such as a housing or another electronic chip. The wall 80 protects the active area 20 of the electronic chip 50, in particular from electrostatic discharges at the side walls of the electronic chip 50 during handling and attachment of the electronic chip 50 to external elements.

[0070] Fig.14 It is a graphic Figure 1 Schematic partial cross-sectional view of the formation of the connection column 30 of the electronic chip. Fig.14 The structure obtained after depositing a mask 92 on the interconnect structure 22, forming an interface layer 40 on the portion of the interconnect structure 22 exposed in the opening 94, and depositing a conductive material to form the backbone 32 of the connecting column is shown, wherein the mask 92 includes an opening 94 exposing the opening 28 for each connecting column to be performed. The conductive material forming the backbone 32 can be deposited by electroplating on the interface layer 70. In this case, the deposition of the conductive material is performed starting from the interface layer 70 in a direction substantially perpendicular to the interface layer 70, as shown by the arrow F1 parallel to the axis A of the backbone 32. In order to form the backbone 32, the conductive material should be deposited substantially at a height H" measured along the axis A. The accuracy of the height H" of the backbone 62 that can be achieved fundamentally depends on the accuracy that can be achieved by the electroplating method.

[0071] Fig.15 It is a graphic Figure 2 The schematic partial cross-sectional view of the formation of the connecting column 60 of the electronic chip is similar to the above description of Figure 7 The conductive material constituting the backbone 62 may be deposited by electroplating on the interface layer 70. In this case, the deposition of the conductive material is performed starting from the interface layer 70 in a direction substantially perpendicular to the interface layer 70, as indicated by the arrow F2. In order to form the backbone 62, the conductive material should therefore be deposited substantially to a thickness equal to half the average diameter D of the backbone 62. Therefore, the duration of the backbone formation step 62 is substantially independent of the total height of the backbone 62 and of the height at which the backbone 62 protrudes from the bottom surface 14 of the substrate 12 on the finished electronic chip. In fact, this height is determined by the above description of Fig. 9 The step of thinning the substrate 12 is defined as follows. Since half of the average diameter D of the trunk 62 is less than Fig.14 The height H″ shown in FIG. 1 , therefore, the duration of the step of forming the stem 62 by electroplating can be advantageously reduced compared to the duration of forming the stem 32 .

[0072] The achievable accuracy of the height H of the trunk 62 depends primarily on the achievable accuracy of the etching method implemented for forming the opening 82. Advantageously, the achievable accuracy of the height H of the trunk 62 is greater than the achievable accuracy of the height H" of the trunk 32. In addition, the achievable accuracy of the height of the portion of the trunk 62 protruding from the bottom surface 16 depends primarily on the achievable accuracy of the etching method implemented for forming the opening 82 and the achievable accuracy of the method implemented for thinning the substrate 12. Advantageously, the achievable accuracy of the height of the portion of the trunk 62 protruding from the bottom surface 16 is greater than the achievable accuracy of the height H" of the trunk 32. The uniformity of the height of the protruding portion of the connecting column 60 is improved.

[0073] Fig.16 , Fig.17 , Fig.18 and Fig.19 Each is for Figure 2 Different embodiments of the electronic chip described above Figure 5 Schematic partial top cross-sectional view of the structure obtained in the steps described. Figures 16 to 19 In FIG. 1 , the cross-sectional plane is located between the bottom surface 14 and the top surface 16 of the substrate 12 and is parallel to the top surface 16 .

[0074] exist Fig.16 and Fig.17 In the embodiment, the opening 82 has a circular straight cross section. Fig.18 and Fig.19 , the opening 82 has a rectangular cross-section with rounded corners.

[0075] exist Fig.16 and Fig.18 In FIG. 8 , a wall 80 is separated from each insulating layer 78 by a portion of the substrate 12 and surrounds two openings 82. Fig.17 and Fig.19 In the embodiment, the wall 80 includes two sub-walls 80A and 80B, each of which is joined at its end to the insulating layer 78 intended to surround the connection column. The insulating layer 78 intended to surround the connection column is then a part of the wall 80.

[0076] Advantageously, according to the previous Figures 3 to 13 In the depicted embodiment, the wall 80 is formed simultaneously with the opening 82 and the insulating layer 78. Therefore, no additional steps are required to form the wall 80.

[0077] Fig. 20 is a schematic partial cross-sectional view of an embodiment of an electronic circuit 100 .

[0078] The electronic circuit 100 comprises a stack of two electronic chips 50A and 50B, each having Figure 2The structure shown in FIG. The active areas 20 of the electronic chips 50A and 50B may contain different electronic components and / or be arranged in different ways. The connection pads 60 on the electronic chip 50A are attached to the electronic chip 50B on one side of the top surface 16 of the electronic chip 50B. Fig. 20 In FIG. 5 , the connection pads 60 of the electronic chip 50A are attached to the connection tracks 76 of the electronic chip 50B through openings 102 provided in the insulating layer 77 covering the connection tracks 76 of the electronic chip 50B.

[0079] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these embodiments may be combined, and those skilled in the art will readily conceive of other variations.

[0080] Finally, actual implementation of the embodiments and variations described herein is well within the capabilities of those skilled in the art, based on the functional description provided above.

[0081] The electronic circuit (50) of the present disclosure comprises a semiconductor substrate (12) having first and second opposite faces (14, 16) and a conductive post (60) intended to be connected to an element external to the electronic circuit, extending from the second face (16) through the semiconductor substrate (12) to the first face (14) and protruding from the first face (14).

[0082] For each conductive pillar (60), the electronic circuit includes an electrically insulating layer (78) located in the semiconductor substrate (12) and completely surrounding the conductive pillar in the semiconductor substrate (12).

[0083] The electronic circuit includes an active area (20) extending from the second face (16) into the semiconductor substrate (12) and including at least one electronic component, and each conductive pillar (60) also includes a connecting track (76) extending over the second face (16) and electrically connected to the active area (20).

[0084] The electronic circuit also includes at least one electrically insulating wall (80) extending through the semiconductor substrate (12) from the second face (16) to the first face (14) and delimiting a semiconductor portion of the semiconductor substrate (12) containing the active area (20).

[0085] An electrically insulating wall (80) is separated from the electrically insulating layer (78) surrounding the conductive pillar (60) by material of the semiconductor substrate (12).

[0086] The electrically insulating layer (78) surrounding the conductive pillar (60) is part of the electrically insulating wall (80).

[0087] Each conductive pillar (60) protrudes from the first face (14) to a height greater than 25 μm.

[0088] The disclosed method of manufacturing an electronic circuit (60) includes: for each conductive pillar (60), forming a first opening (82) in a semiconductor substrate (12), the first opening (82) extending from a second face (16) into the semiconductor substrate (12) over a portion of the thickness of the semiconductor substrate (12), and filling the first opening (82) with a conductive material.

[0089] The method comprises the step of thinning a semiconductor substrate (12) on one side of a first surface (14) so ​​that each conductive column (60) protrudes from the first surface (14).

[0090] The method includes the step of forming an electrically insulating layer (78) on the walls of each first opening (82) before filling the first opening (82) with a conductive material.

[0091] The method includes forming at least one second opening (84) extending from the second face (16) into the semiconductor substrate (12) over a portion of the thickness of the semiconductor substrate (12), the second opening (84) being shallower than the first opening (82), and completely filling the second opening (84) with an electrically insulating material.

[0092] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary, to employ concepts of the various patents, applications, and publications to provide further embodiments.

[0093] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be interpreted to limit the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents to which these claims are entitled. Therefore, the claims are not limited by the present disclosure.

Claims

1. A device comprising: A semiconductor substrate having a first surface and a second surface opposite to each other; as well as A plurality of conductive pillars configured to be connected to an element external to the semiconductor substrate, the plurality of conductive pillars extending from the second side through the semiconductor substrate to the first side, and each respective conductive pillar of the plurality of conductive pillars comprising: A trunk portion extends completely through the semiconductor substrate from the first side and the second side, the trunk portion comprising: a first end protruding from the first side; a second end opposite to the first end and protruding from the second surface; and A dimension in a direction transverse to the first face and the second face, the dimension remaining the same from the first end to the second end. 2 . The electronic circuit of claim 1 , comprising, for each conductive pillar, an electrically insulating layer located in the semiconductor substrate and completely surrounding the conductive pillar in the semiconductor substrate.

3. The electronic circuit of claim 1 , comprising an active area extending from the second face into the semiconductor substrate and comprising at least one electronic component, each conductive pillar further comprising a connection track extending over the second face and electrically connected to the active area. 4 . The electronic circuit of claim 1 , further comprising at least one electrically insulating wall extending through the semiconductor substrate from the second side to the first side and delimiting a semiconductor portion of the semiconductor substrate containing the active area.

5. The electronic circuit of claim 2, wherein the electrically insulating wall is separated from the electrically insulating layer surrounding the conductive pillar by material of the semiconductor substrate. The electronic circuit of claim 2 , wherein the electrically insulating layer surrounding the conductive pillar is a portion of the electrically insulating wall.

7. The electronic circuit of claim 1, wherein each conductive pillar protrudes from the first face to a height greater than 25 μm.

8. A method comprising: forming a first opening extending from the second face into the semiconductor substrate over a first portion of the thickness of the semiconductor substrate; forming a second opening extending from the second face into the semiconductor substrate over a second portion of the thickness of the semiconductor substrate, the second portion being shallower than the first portion; as well as partially filling the first opening with an insulating material; filling the second opening with an insulating material; as well as The remaining portion of the first opening is filled with one or more conductive materials to form a conductive pillar. 9 . The method of claim 8 , further comprising thinning the semiconductor substrate at the first side so that the conductive pillars protrude from the first side of the semiconductor substrate. 10 . The method of claim 8 , partially filling the first opening with an insulating material further comprising forming the insulating material on one or more walls of the semiconductor substrate defining the first opening.

11. The method of claim 8, further comprising forming a mask layer on the insulating material, the mask layer comprising an opening exposing a region of the insulating material within the first opening, and Filling the remaining portion of the first opening with one or more conductive materials to form a conductive pillar comprises: forming a conductive interface layer on one or more walls of the insulating material partially filling the first opening; as well as A conductive plating material is formed on the conductive interface layer.

12. A device comprising: A semiconductor substrate having a first face, a second face opposite to the first face, and one or more sidewalls, the one or more sidewalls being transverse to the first face and the second face and extending from the first face to the second face; as well as A plurality of conductive pillars configured to be connected to an element external to the semiconductor substrate, the plurality of conductive pillars extending from the second side through the semiconductor substrate to the first side, and each respective conductive pillar of the plurality of conductive pillars comprising: A trunk portion extends completely through the semiconductor substrate from the first side and the second side, the trunk portion comprising: a first end protruding from the first side; a second end opposite to the first end and protruding from the second surface; and The insulating material extends from the first side through the semiconductor substrate to the second side, the insulating material covers the first side and the second side, and the insulating material includes one or more sidewalls coplanar with the one or more sidewalls of the semiconductor substrate.

13. The apparatus of claim 12, wherein the first ends of the plurality of conductive pillars are coupled to a plurality of conductive connection tracks coupled between the first ends of the plurality of conductive connection tracks and a plurality of conductive tracks on the second side of the semiconductor substrate.

14. The apparatus of claim 13, wherein the plurality of conductive tracks overlap an active area of ​​a semiconductor substrate.

15. The apparatus of claim 12, wherein the semiconductor substrate includes an active region spaced inwardly from the plurality of conductive pillars.

16. The apparatus of claim 12, wherein insulating material comprises walls surrounding the plurality of conductive pillars and an active area of ​​the semiconductor substrate.

17. The apparatus of claim 12, wherein the insulating material comprises a plurality of first portions and a wall portion, each respective first portion of the plurality of first portions surrounding a corresponding conductive post of the plurality of posts. 18 . The apparatus of claim 17 , wherein a wall portion surrounds the plurality of first portions, the plurality of conductive pillars, and an active area of ​​the semiconductor substrate.

19. The apparatus of claim 18, wherein the wall portion is separated from the plurality of first portions by a portion of the semiconductor substrate.

20. The apparatus of claim 17, wherein the wall portion is part of the plurality of first portions.

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