Semiconductor device

Abstract

[Problem] To improve the durability of a semiconductor device. [Solution] A semiconductor device (100) is provided with: a semiconductor element (2) which is placed on an insulating substrate (1) and has an electrode (21) on a surface (2a); a bonding wire (3) that is bonded to the electrode (21) and electrically connects the semiconductor element (2); and a first resin material (4) that covers a joint part (31) between the electrode (21) and the bonding wire (3). The bonding portion (31) includes a non-bonding region (32) in which the electrode (21) and the bonding wire (3) are not bonded.

Description

Technical Field

[0001] Embodiments relate to a semiconductor device. Background Art

[0002] A semiconductor device is being developed, comprising: an insulating substrate having a conductor pattern; a semiconductor element having a surface provided with an electrode and a back surface bonded to the conductor pattern; and a bonding wire bonded to the electrode. In such a semiconductor device, if the number of times of use increases, cracks may occur at the bonding portion between the electrode and the bonding wire, and there is room for improvement from the viewpoint of durability.

[0003] Prior art literature:

[0004] Patent Literature:

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 8-115941 Summary of the invention

[0006] Problems to be solved by the invention:

[0007] An object of the embodiment is to improve the durability of a semiconductor device.

[0008] Means used to solve the problem:

[0009] The semiconductor device according to the embodiment includes: a semiconductor element mounted on an insulating substrate and having an electrode on the surface; a bonding wire bonded to the electrode to electrically connect the semiconductor element; and a first resin material covering a bonding portion between the electrode and the bonding wire. The bonding portion includes a non-bonding region where the electrode and the bonding wire are not bonded. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 FIG. 1 is a cross-sectional view of a main part of a semiconductor device 100 according to an embodiment.

[0011] Figure 2 is an enlarged cross-sectional view of the semiconductor device 100 .

[0012] Figure 3 is an enlarged plan view of the semiconductor device 100 .

[0013] Figure 4 It is a diagram showing a method for manufacturing the semiconductor device 100 .

[0014] Figure 5 is equivalent to the semiconductor device R involved in the reference example Figure 2 .

[0015] Figure 6 The semiconductor device 100 according to the first modification is equivalent to Figure 3 .

[0016] Figure 7 The semiconductor device 100 according to the second modification is equivalent to Figure 2 .

[0017] Figure 8 The semiconductor device 100 according to the third modification is equivalent to Figure 2 .

[0018] Fig. 9 It is a diagram showing the analysis results of the creep analysis.

[0019] Fig.10 It is a diagram showing the analysis results of the creep analysis.

[0020] Fig.11 This is a diagram showing an analytical model for estimating the width of the inelastic region.

[0021] Fig.12 This is a diagram showing the analysis results for estimating the width of the inelastic region.

[0022] Fig.13 This is a diagram showing the analysis results for estimating the width of the inelastic region.

[0023] Fig.14 This is a diagram showing the analysis results for estimating the width of the inelastic region.

[0024] Description of reference numerals:

[0025] 1: insulating substrate, 2: semiconductor element, 3: bonding wire, 4: first resin material, 6: second resin material, 11: lead frame, 12: conductor pattern, 21: electrode, 22: surface electrode, 24: laser irradiation source, 31: bonding portion, 32: non-bonding region, 33: recessed portion, 34: opening, 35: shielding layer, 100: semiconductor device. DETAILED DESCRIPTION

[0026] <1. Implementation Method>

[0027] (1.1. Semiconductor Device 100)

[0028] The following describes the implementation method. In the following figures, sometimes Figure 1 and Figure 3 The X-axis, Y-axis, and Z-axis shown in FIG. 1 represent directions. Specifically, the X-axis direction along the X-axis represents Figure 1 The Y-axis direction along the Y-axis indicates the direction perpendicular to the X-axis direction in the horizontal plane. The Z-axis direction along the Z-axis indicates the vertical direction. In addition, the positive direction of the Z-axis is upward, and the negative direction of the Z-axis is downward.

[0029] Figure 1 FIG. 1 is a cross-sectional view of a main part of a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, the semiconductor device 100 mainly includes an insulating substrate 1, a semiconductor element 2, and bonding wires 3. The semiconductor device 100 may also include: a base plate for mounting the insulating substrate 1, a housing for storing the insulating substrate 1, the semiconductor element 2, and the bonding wires 3, and a heat sink for dissipating heat from the semiconductor element 2.

[0030] The insulating substrate 1 has a front surface 1a and a back surface 1b. The back surface 1b is a surface on the opposite side of the front surface 1a. The insulating substrate 1 is made of, for example, aluminum oxide (Al2O3) or aluminum nitride (AlN).

[0031] A conductor pattern 12 is provided on the insulating substrate 1. The conductor pattern 12 is made of, for example, copper (Cu).

[0032] The semiconductor element 2 has a surface 2a and a back surface 2b. The back surface 2b is the surface on the opposite side of the surface 2a. As an example, the semiconductor element 2 may also be a power semiconductor element having a vertical structure in which current flows from the surface 2a side to the back surface 2b side. The semiconductor element 2 may also be a switching element such as an IGBT (Insulated Gate Bipolar Transistor), a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or a rectifying element such as a Schottky barrier diode.

[0033] As an example, the semiconductor element 2 is formed using a single crystal of silicon (Si). However, the semiconductor material constituting the semiconductor element 2 is not limited thereto. As another example, the semiconductor element 2 may also be formed using a semiconductor material having a wide bandgap such as silicon carbide (SiC) or silicon nitride (GaN).

[0034] An electrode 21 is provided on the surface 2a of the semiconductor element 2. As an example, an Al alloy containing Al and Si is used for the electrode 21. The electrode 21 may further include a covering layer. As the covering layer, for example, Ni, Au, or a structure in which these are laminated may be used.

[0035] The bonding wire 3 is a metal wire that electrically connects the semiconductor element 2 to the lead frame 11. For example, Au, Al, Cu, etc. are used for the bonding wire 3. The electrode 21 has a bonding portion 31 bonded to the bonding wire 3. As an example, the bonding portion 31 is formed by ultrasonic bonding to be rectangular in a plan view.

[0036] In the bonding portion 31, the bonding wire 3 and the electrode 21 are bonded along the extending direction of the bonding wire 3 (hereinafter also referred to as the extending direction). The bonding portion 31 includes a non-bonding region 32 where the electrode 21 and the bonding wire 3 are not bonded. Figure 2 and Figure 3 In the illustrated example, the non-bonding region 32 is formed by providing a recess 33 on the upper surface 21 a of the electrode 21 .

[0037] Specifically, if Figure 2 As shown, the recess 33 is formed in a groove shape with a rectangular cross section and extending in the Y-axis direction, and is provided in the central part of the extending direction of the joint 31. Figure 3 As shown in FIG. 2 , the recess 33 is formed in a rectangular shape in a plan view. In this way, the non-joining region 32 is formed in the joining portion 31 by the opening 34 of the recess 33 in the upper surface 21 a.

[0038] In addition, the ratio of the length W2 of the recessed portion 33 in the X-axis direction (i.e., the extending direction of the bonding wire 3) to the length W1 of the bonding portion 31 is preferably 6% or more, and more preferably 10% or more. In addition, the length D2 of the recessed portion 33 is preferably longer than the length D1 of the bonding portion 31 in the Y-axis direction. In this way, it is easy to generate an area not covered by the bonding wire 3 in the opening 34, and the first resin material 4 is filled into the recessed portion 33.

[0039] The joint portion 31 is covered with the first resin material 4. Figure 1 to Figure 3 In the example shown, the bonding wires 3 around the bonding portion 31 are covered by the first resin material 4. However, the first resin material 4 does not need to cover the entire bonding wires 3 around the bonding portion 31. As an example, the first resin material 4 may not cover the bonding wires 3 above the bonding portion 31, but may cover the gaps between the bonding wires 3 and the electrodes 21 at both ends of the bonding portion 31 in the extending direction.

[0040] The first resin material 4 functions as a reinforcing material for reinforcing the joint at the joint portion 31. The Young's modulus of the first resin material 4 is preferably 1000 MPa or more. As a material used for the first resin material 4, for example, polyimide can be cited.

[0041] like Figure 1As shown, the second resin material 6 is filled inside the housing of the semiconductor device 100. Thus, the second resin material 6 seals the insulating substrate 1, the semiconductor element 2 and the bonding wire 3. The second resin material 6 has insulating properties. The second resin material 6 preferably has a Young's modulus lower than that of the first resin material 4. Thus, it is possible to prevent the second resin material 6 from being peeled off on the surface of the semiconductor element 2 due to the difference in thermal expansion coefficient from the semiconductor element 2. More specifically, the elastic modulus of the second resin material 6 is preferably 0.1 MPa or less. As a material used for the second resin material 6, for example, silicone gel can be cited.

[0042] (1.2. Method for Manufacturing Semiconductor Device 100)

[0043] The following describes the manufacturing process of the semiconductor device 100 according to the embodiment. The manufacturing process of the semiconductor device 100 includes a recess forming process, a bonding process, a covering process, and a sealing process.

[0044] First, the concave portion forming process is performed. Figure 4 As shown in (a), the recess 33 is formed in the recess forming step. For example, the recess 33 is formed by irradiating the electrode 21 with laser light L from a laser irradiation source S. The portion to be bonded with the bonding wire 3 and forming the bonding portion 31 is irradiated with laser light L. The laser irradiation source S is, for example, a carbon dioxide laser processing machine.

[0045] Next, if Figure 4 As shown in (b), in the bonding step, the bonding wire 3 is bonded to the electrode 21 of the semiconductor element 2. For example, the bonding wire 3 made of Al and the electrode 21 made of an Al alloy containing Si are bonded at the bonding portion 31 of the electrode 21 by ultrasonic bonding.

[0046] Next, if Figure 4 As shown in (c) of FIG. 1 , in the covering step, the liquid first resin material 4 is supplied to the joint portion 31. As an example, when the first resin material 4 is a resin, a mixture of a main agent and a curing agent may be dripped near the joint portion 31.

[0047] In the covering process, the supplied liquid first resin material 4 is solidified. As an example, when the first resin material 4 is a resin, the first resin material 4 is solidified by keeping the liquid first resin material 4 at room temperature. As another example, when the first resin material 4 is a solder alloy, the first resin material 4 is solidified by cooling the liquid first resin material 4. Thus, the joint 31 is covered with the first resin material 4.

[0048] Next, in the sealing process, the semiconductor element 2, the bonding wire 3, and the first resin material 4 are stored in the housing of the semiconductor device 100. Then, the liquid second resin material 6 is supplied to the interior of the housing. By curing the liquid second resin material 6, Figure 1 As shown, the insulating substrate 1 , the semiconductor element 2 , and the bonding wires 3 are sealed by the second resin material 6 .

[0049] (1.3. Summary)

[0050] According to the embodiment described above, the semiconductor device 100 includes: a semiconductor element 2 mounted on an insulating substrate 1 and having an electrode 21 on a surface 2a; a bonding wire 3 bonded to the electrode 21 to electrically connect the semiconductor element 2; and a first resin material 4 covering a bonding portion 31 between the electrode 21 and the bonding wire 3. The bonding portion 31 includes a non-bonding region 32 where the electrode 21 and the bonding wire 3 are not bonded. By setting such a configuration, when the bonding wire 3 is repeatedly energized, thermal stress generated due to the difference in thermal expansion coefficient between the bonding wire 3 and the electrode 21 can be suppressed. As a result, it is possible to suppress the occurrence of fracture inside the bonding wire 3 near the bonding portion 31, thereby improving the durability of the semiconductor device 100.

[0051] More specifically, for example, Figure 5 In the semiconductor device R shown as a reference example, thermal stress is generated in the interval T1 between the two ends of the bonding portion 31 in the extending direction. Figure 2 As shown, in the semiconductor device 100 according to the embodiment, a recess 33 is provided at the center of the extending direction of the bonding portion 31, and a non-bonding region 32 is formed accordingly. Therefore, the region where thermal stress may be generated is divided by the non-bonding region 32, and thermal stress is generated in the interval T2 from the end of the bonding portion 31 on both sides of the recess 33 to the end of the non-bonding region 32. The interval T2 is shorter than the interval T1, so the deformation caused by thermal expansion generated in the semiconductor device 100 is smaller than that of the semiconductor device R, and the generated thermal stress is also smaller. As described above, in the semiconductor device 100 according to the present embodiment, since the bonding portion 31 includes the non-bonding region 32, the thermal stress that may be generated inside the bonding wire 3 can be dispersed.

[0052] (1.4. Modification)

[0053] Reference Figure 6 to Figure 8 , a semiconductor device 100 according to a modification of the present embodiment will be described focusing on differences from the above-described embodiment. Figure 6 FIG. 1 is an enlarged plan view of a semiconductor device 100 according to Modification 1. In Modification 1, the semiconductor device 100 is different from the above-described embodiment in that a plurality of recesses 33 are provided on the upper surface 21 a of the electrode 21 . Figure 6 In the example shown, two recesses 33 are arranged side by side along the extension direction on the upper surface 21a of the electrode 21. By setting such a structure, the thermal stress generated by the energization of the bonding wire 3 can be dispersed more finely along the extension direction. Figure 6 The example shown is just an example, and the number of the recessed portions 33 provided on the upper surface 21 a of the electrode 21 may be three or more.

[0054] Figure 7 2 is an enlarged plan view of a semiconductor device 100 according to Modification 2. In Modification 2, the shape of the recess 33 provided on the upper surface 21a of the electrode 21 is different from that in the above-described embodiment. Figure 7 In the example shown, a recessed portion 33 having a bottom surface with a sawtooth-shaped cross section is formed on the upper surface 21a of the electrode 21. With such a configuration, the same effects as those of the above-described embodiment can be achieved.

[0055] Figure 8 2 is an enlarged plan view of a semiconductor device 100 according to Modification 3. Modification 3 is different from the above-described embodiment in that a shielding layer 35 is provided on the upper surface 21a of the electrode 21 instead of forming the recess 33. Figure 8 In the example shown, a shielding layer 35 containing a third resin material is stacked on the upper surface 21a of the electrode 21. As a result, a non-bonding area 32 is formed in a part of the bonding portion 31 where the electrode 21 cannot be ultrasonically bonded to the bonding wire 3. As the third resin material, for example, an insulating material can be used, and specifically, polyimide, or polyimide silicone (polyimide resin), polyamide imide, epoxy resin, phenol resin, or a resin containing a filler as a conductive material can be used. In addition, as a filler, for example, a metal or ceramic can be used. By adding a filler, thermal conductivity or electrical conductivity can be improved. In addition, the shielding layer 35 is not limited to a resin material, as long as it is a material that shields the ultrasonic bonding of the electrode 21 and the bonding wire 3, for example, it can also be an Ag sintered body or solder. Through such a structure, the same effect as the above-mentioned embodiment can be achieved.

[0056] <2. Example>

[0057] Hereinafter, an example of the semiconductor device 100 according to the present embodiment will be described. As an example, creep analysis and estimation of the width of the non-joint region will be described below.

[0058] (2.1. Creep analysis)

[0059] Reference Fig. 9 and Fig.10 , the results of creep analysis as an example are described.

[0060] In the creep analysis, the inelastic deformation energy density range and the life ratio were calculated for the two examples and three comparative examples shown below.

[0061] Semiconductor device 100A according to the embodiment (width of non-joint region 32 is 200 μm)

[0062] Semiconductor device 100B according to the embodiment (width of non-joint region 32 is 100 μm)

[0063] Semiconductor device 200A according to the first comparative example (without the non-joining region 32 and without the first resin material 4)

[0064] Semiconductor device 200B according to the second comparative example (without the non-joining region 32)

[0065] Semiconductor device 200C according to the third comparative example (width of the non-bonding region 32 is 200 μm / no first resin material 4)

[0066] As the thermal condition, it is assumed that the current flowing to the semiconductor element 2 is repeatedly turned on for 2 seconds and off for 8 seconds, and the temperature changes from 40 degrees to 140 degrees. As a result, the heat density given to the semiconductor element 2 and the bonding wire 3 is 6.3 (W / mm 3 ), the heat density of the bonding wire 3 is 0.45 (W / mm 3 ).

[0067] As a mesh model, the mesh elements of 10 μm×10 μm are divided. In addition, it is assumed that the mesh elements of the electrode 21 are not adjacent to the mesh elements of the bonding wire 3 in the non-bonding area 32 of the bonding part 31. In addition, the inelastic deformation energy density range is obtained from both ends of the bonding part 31 in the X-axis direction. In addition, the inelastic deformation energy density range means the inelastic deformation energy generated per unit amount.

[0068] Fig. 9 is a graph showing the calculation results based on creep analysis. Fig. 9 In the semiconductor devices 100A and 100B according to the embodiment, the inelastic deformation energy density range (J / m 3 That is, according to this embodiment, it can be seen that in the semiconductor devices 100A and 100B involved in the embodiment, the energy of thermal deformation generated inside the bonding wire 3 can be suppressed due to the above-mentioned structure.

[0069] In addition, the semiconductor devices 100A and 100B according to the embodiment have a lifespan ratio of approximately 5000 times that of the first comparative example. That is, according to the present embodiment, the semiconductor devices 100A and 100B can have high durability by suppressing the energy of thermal deformation generated inside the bonding wire 3 .

[0070] Fig.10 3 is a diagram showing the distribution of thermal stress generated inside the bonding wire 3 during creep analysis. Fig.10 (a) and Fig.10 In (b), locations where the thermal stress inside the bonding wire 3 is stronger are indicated by darker gray.

[0071] like Fig.10 As shown in (a), in the semiconductor device 200A according to the first comparative example, strong stress is generated at both ends of the joint 31 in the extending direction. Fig.10 As shown in (b), in the semiconductor device 100B according to the embodiment, strong thermal stress is not generated at both ends of the bonding portion 31 in the extension direction. That is, according to this embodiment, it is known that in the semiconductor device 100B, the thermal stress generated due to the difference in thermal expansion coefficients between the bonding wire 3 and the electrode 21 can be suppressed.

[0072] (2.2. Estimation of the width of the non-bonded region 32)

[0073] Reference Figure 11 to Figure 14 , the estimation result of the width of the non-bonding region 32 as an example is described. Fig.11 : represents the model M corresponding to the electrode 21 near the joint 31. The model M includes an end 41, a joint layer 42, a relaxation layer 43, and a lower layer 44. The end 41 corresponds to the end of the joint 31. The joint layer 42 corresponds to the joint 31 of the electrode 21. The relaxation layer 43 corresponds to the recess 33 provided in the electrode 21. The lower layer 44 corresponds to the layer below the recess 33 of the electrode 21.

[0074] First, regarding the semiconductor device 200C according to the third comparative example not including the first resin material 4, a change F1 of the stress σ1 generated inside the model M when the Young's modulus E2 of the relaxation layer 43 is changed is calculated. Here, the pressure on the bonding layer 42 is set to P1, and the pressure on the lower layer 44 is set to P2, and the equation (3) is derived from the following conditional equations (1) and (2).

[0075] [Mathematical formula 1]

[0076] P1+P2=0 Formula (1)

[0077] [Mathematical formula 2]

[0078] 2λ1+12=λ3Formula (2)

[0079] [Mathematical formula 3]

[0080]

[0081] l1: length of the bonding layer 42, l2: length of the relaxation layer 43

[0082] λ1: elongation of the bonding layer 42, λ2: elongation of the relaxation layer 43, λ2: elongation of the lower layer 44

[0083] α1: thermal expansion coefficient of the bonding layer 42, α2: thermal expansion coefficient of the relaxation layer 43, α3: thermal expansion coefficient of the lower layer 44

[0084] E1: Young's modulus of the bonding layer 42, E2: Young's modulus of the relaxation layer 43, E3: Young's modulus of the lower layer 44

[0085] ΔT: Temperature change

[0086] Next, regarding the semiconductor device 100A according to the embodiment including the first resin material 4, a change F2 in stress σ1 generated inside the model M when the Young's modulus E2 of the relaxation layer 43 is changed is calculated. Here, equation (5) is derived from the following conditional equation (4).

[0087] [Formula 4]

[0088] 2λ1+λ2=0 Formula (4)

[0089] [Mathematical formula 5]

[0090]

[0091] According to the above formula (3) and formula (5), if Fig.12 FIG. 1 shows a change F1 of the stress σ1 in the semiconductor device 200C according to the comparative example and a change F2 of the stress σ1 in the semiconductor device 100A according to the embodiment when the Young's modulus E2 of the relaxation layer 43 is changed.

[0092] Next, in the above-described creep analysis, the equivalent stress generated in the joint portion 31 is estimated for the semiconductor device 200C according to the comparative example and the semiconductor device 100A according to the embodiment. Fig.13 (a) is a diagram showing the time change of the equivalent stress generated in the joint 31 of the semiconductor device 200C according to the comparative example in the creep analysis. Fig.13 As can be seen from (a), the equivalent stress of about 60 MPa at the maximum is generated by converging over time.

[0093] Fig.13(b) is a diagram showing the time change of the equivalent stress generated in the joint 31 of the semiconductor device 100A according to the embodiment in the creep analysis. Fig.13 As can be seen from (b), the equivalent stress of about 35 MPa at maximum is generated by converging over time.

[0094] Fig.12 Line L1 (red line) representing the Young's modulus E2 when the stress σ1 is 60 MPa in the semiconductor device 200C involved in the comparative example, and line L2 (blue line) representing the Young's modulus E2 when the stress σ1 is 35 MPa in the semiconductor device 100A involved in the embodiment are shown. Here, in the above-mentioned creep analysis, the joint 31 of the semiconductor device 200C shows elastic plasticity, while the joint 31 of the semiconductor device 100A shows elasticity, so the Young's modulus E2 of the relaxation layer 43 is estimated to be between the line L1 and the line L2. In this analysis, the Young's modulus E2 of the relaxation layer 43 is estimated to be 10000 MPa. At this time, according to Fig.12 The value of F2 at E2=10000 Pa in FIG. 1 indicates that a stress of at least 55 MPa is generated in the joint portion 31 .

[0095] Next, based on the above-mentioned formula (5), the change F3 of the stress σ1 generated inside the model M when the length l2 of the relaxation layer 43 is changed is calculated for the semiconductor device 100A according to the embodiment. F3 is as follows: Fig.14 As shown in the figure. Fig.14 From F3, the width of the relaxation layer 43 corresponding to the above-inferred stress of 55 MPa is calculated to be 0.03 mm (= 30 μm). Therefore, the length of the recess 33 corresponding to the relaxation layer 43 in the extension direction is preferably 30 μm or more. In addition, the length of the joint 31 along the extension direction of the bonding wire 3 in this analysis is 480 μm, so it is inferred that the ratio of the length of the recess 33 along the extension direction to the length of the joint 31 is preferably 6% or more.

[0096] <3. Other embodiments>

[0097] The above describes the embodiments of the present disclosure, but is not limited to the above. For example, in the above embodiment, one recess 33 provided on the upper surface 21a of the electrode 21 is provided at the center of the extension direction in the joint 31, but is not limited to this embodiment, and one recess 33 may be provided at a position other than the center of the extension direction.

[0098] In addition, in the above-mentioned embodiment, the length D2 of the recessed portion 33 is longer than the length D1 of the joint portion 31 in the Y-axis direction, but the present invention is not limited to this mode. For example, the length D2 of the recessed portion 33 in the Y-axis direction may be the same as the length D1 of the joint portion 31, or may be shorter than the length D1 of the joint portion 31.

[0099] In addition, the recess 33 may also be a shape other than the above. Specifically, for example, the recess 33 may be formed by providing a plurality of dimple-shaped projections and depressions on the surface of the joint 31 of the electrode 21. In the above other embodiments, by applying the technical concept of the present disclosure, the same effect as the above embodiment can be achieved.

[0100] Several embodiments of the present invention are described above, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are also included in the invention described in the claims and their equivalents.

[0101] The present invention includes the following aspects.

[0102] (Note 1)

[0103] A semiconductor device comprising:

[0104] A semiconductor element is placed on an insulating substrate and has electrodes on its surface;

[0105] bonding wires bonded to the electrodes to electrically connect the semiconductor element; and

[0106] a first resin material covering a junction between the electrode and the bonding wire;

[0107] The bonding portion includes a non-bonding region where the electrode and the bonding wire are not bonded.

[0108] (Note 2)

[0109] The semiconductor device according to Supplementary Note 1, further comprising:

[0110] a second resin material that seals the semiconductor element, the bonding wire, and the first resin material;

[0111] The Young's modulus of the second resin material is lower than the Young's modulus of the first resin material.

[0112] (Note 3)

[0113] The semiconductor device according to Supplementary Note 1 or 2, wherein the Young's modulus of the first resin material is 1000 MPa or more.

[0114] (Note 4)

[0115] The semiconductor device according to any one of appendices 1 to 3, wherein:

[0116] A recess is provided on the upper surface of the electrode,

[0117] The non-bonding region is formed by the opening of the recess in the upper surface.

[0118] (Note 5)

[0119] The semiconductor device according to Supplementary Note 4, wherein:

[0120] At the bonding portion, the bonding wire and the electrode are bonded along an extending direction of the bonding wire.

[0121] A ratio of a length of the recessed portion along the extending direction to a length of the joining portion is 6% or more.

[0122] (Note 6)

[0123] The semiconductor device according to Supplementary Note 4, wherein:

[0124] At the bonding portion, the bonding wire and the electrode are bonded along an extending direction of the bonding wire.

[0125] The recessed portion is provided at the center of the engaging portion in the extending direction.

[0126] (Note 7)

[0127] In the semiconductor device according to any one of Appendixes 1 to 6, the non-bonding region has a shielding layer that prevents ultrasonic bonding between the electrode and the bonding wire.

Claims

1. A semiconductor device, wherein: have: A semiconductor element is placed on an insulating substrate and has electrodes on its surface; bonding wires bonded to the electrodes to electrically connect the semiconductor element; and a first resin material covering a junction between the electrode and the bonding wire; The bonding portion includes a non-bonding region where the electrode and the bonding wire are not bonded.

2. The semiconductor device according to claim 1, wherein: Also available: a second resin material that seals the semiconductor element, the bonding wire, and the first resin material; The Young's modulus of the second resin material is lower than the Young's modulus of the first resin material.

3. The semiconductor device according to claim 1, wherein: The Young's modulus of the first resin material is 1000 MPa or more.

4. The semiconductor device according to any one of claims 1 to 3, wherein: A recess is provided on the upper surface of the electrode, The non-bonding region is formed by the opening of the recess in the upper surface.

5. The semiconductor device according to claim 4, wherein: At the bonding portion, the bonding wire and the electrode are bonded along an extending direction of the bonding wire. A ratio of a length of the recessed portion along the extending direction to a length of the joining portion is 6% or more.

6. The semiconductor device according to claim 4, wherein: At the bonding portion, the bonding wire and the electrode are bonded along an extending direction of the bonding wire. The recessed portion is provided at the center of the engaging portion in the extending direction.

7. The semiconductor device according to any one of claims 1 to 3, The non-bonding region has a shielding layer between the electrode and the bonding wire that prevents ultrasonic bonding.

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