Packaging structure and packaging method

Abstract

The invention discloses a packaging structure and a packaging method. The packaging structure comprises a substrate; the interconnection structure plate is bonded on the substrate, the interconnection structure plate comprises a first surface and a second surface which are opposite to each other, and the first surface faces the substrate; the device chip is positioned on the first surface of the interconnection structure plate and is electrically connected with the interconnection structure plate; the first chip structure is bonded on the second surface of the interconnection structure plate, and the first chip structure is electrically connected with the device chip through the interconnection structure plate; and the second chip structure is bonded on the second surface of the interconnection structure plate at the side part of the first chip structure, the second chip structure is electrically connected with the device chip through the interconnection structure plate, and the second chip structure is electrically connected with the first chip structure through the device chip. According to the invention, the circuit diversity is increased, and the adaptability and integration of the packaging structure are improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a packaging structure and a packaging method. Background Art

[0002] Conventional chip manufacturing technologies are being pushed to their limits in terms of the size of a single chip. However, applications are eager to use the latest technology to achieve the capabilities of large-scale integrated circuits, and achieving high-speed and small-volume interconnections between chips is a major challenge.

[0003] One current solution is to use a smaller integrated circuit of a silicon bridge (Si Bridge) chip embedded in a silicon substrate to interconnect chips through the silicon bridge chip, thereby providing a heterogeneous chip package.

[0004] However, the current packaging structure is relatively complex. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a packaging structure and a packaging method, which are beneficial to improving the packaging effect of the packaging structure.

[0006] To solve the above problems, the present invention provides a packaging structure, including: a substrate; an interconnection structure board bonded to the substrate, the interconnection structure board including a first surface and a second surface opposite to each other, the first surface facing the substrate; a device chip, located on the first surface of the interconnection structure board and electrically connected to the interconnection structure board; a first chip structure bonded to the second surface of the interconnection structure board, the first chip structure is electrically connected to the device chip through the interconnection structure board; a second chip structure bonded to the second surface of the interconnection structure board at the side of the first chip structure, the second chip structure is electrically connected to the device chip through the interconnection structure board, and the second chip structure is electrically connected to the first chip structure through the device chip.

[0007] Optionally, the device chip includes a device layer and a first interconnection layer located on the device layer, the first interconnection layer is located on a side of the device chip close to an interconnection structure board, the device layer is located on a side of the device chip away from the interconnection structure board, the first interconnection layer is electrically connected to the device of the device layer, and the first interconnection layer is electrically connected to the interconnection structure board; the first chip structure is electrically connected to the first interconnection layer through the interconnection structure board; the second chip structure is electrically connected to the first interconnection layer through the interconnection structure board, and the first chip structure and the second chip structure are electrically connected through the first interconnection layer.

[0008] Optionally, the interconnection structure board includes: a first interconnection structure that passes through the interconnection structure board, the first interconnection structure is located at the position of the device chip, the first interconnection structure electrically connects the device chip with the first chip structure, and the device chip with the second chip structure; a second interconnection structure that passes through the interconnection structure board, the second interconnection structure is located on the side of the device chip, and the second interconnection structure electrically connects the first chip structure with the substrate, and the second chip structure with the substrate.

[0009] Optionally, the packaging structure further includes: a second interconnection layer located on the first surface of the interconnection structure board at the side of the device chip, the second interconnection layer is electrically connected to the interconnection structure board, and the interconnection structure board is bonded to the substrate through the second interconnection layer.

[0010] Optionally, a surface of the second interconnect layer facing away from the interconnect structure board is flush with a surface of the device chip facing away from the interconnect structure board.

[0011] Optionally, the second interconnect layer is electrically isolated from the device chip.

[0012] Optionally, the second interconnection layer includes a third interconnection structure penetrating the second interconnection layer, and the third interconnection structure electrically connects the interconnection structure plate and the substrate.

[0013] Optionally, the packaging structure also includes: a first conductive bump, located between the second interconnect layer and the substrate, and electrically connecting the second interconnect layer and the substrate; a second conductive bump, located between the interconnect structure board and the first chip structure, and between the interconnect structure board and the second chip structure, and electrically connecting the interconnect structure board and the first chip structure, and electrically connecting the interconnect structure board and the second chip structure.

[0014] Optionally, the packaging structure further includes: a first sealing layer located between the second interconnect layer and the substrate and filling the gap between the second interconnect layer and the substrate and the gap between adjacent first conductive bumps; and a second sealing layer filling between adjacent second conductive bumps and covering the second conductive bumps.

[0015] Optionally, the first chip structure includes a logic chip, the second chip structure includes one or a plurality of second chips stacked in a vertical direction, and the second chip includes a memory chip.

[0016] Correspondingly, an embodiment of the present invention also provides a packaging method, including: providing a device chip; forming an interconnection structure board electrically connected to the device chip, the interconnection structure board including a first surface and a second surface opposite to each other, the first surface facing the device chip; providing a first chip structure; providing a second chip structure; bonding the second chip structure and the first chip structure to the second surface of the interconnection structure board, the second chip structure is located on the side of the first chip structure, the first chip structure is electrically connected to the device chip through the interconnection structure board, the second chip structure is electrically connected to the device chip through the interconnection structure board, and the second chip structure is electrically connected to the first chip structure through the device chip; providing a substrate; after bonding the second chip structure and the first chip structure to the second surface of the interconnection structure board, the interconnection structure board is bonded to the substrate, with the first surface facing the substrate.

[0017] Optionally, in the step of providing a device chip, the device chip includes a device layer and a first interconnection layer located on the device layer, and the first interconnection layer is electrically connected to the device of the device layer; in the step of forming an interconnection structure board electrically connected to the device chip, the interconnection structure board is located on the first interconnection layer, and the first interconnection layer is electrically connected to the interconnection structure board; in the step of bonding the second chip structure and the first chip structure to the second surface of the interconnection structure board, the first chip structure is electrically connected to the first interconnection layer through the interconnection structure board, the second chip structure is electrically connected to the first interconnection layer through the interconnection structure board, and the first chip structure is electrically connected to the second chip structure through the first interconnection layer.

[0018] Optionally, the step of forming an interconnection structure board electrically connected to the device chip also includes: forming a first interconnection structure and a second interconnection structure that penetrate the interconnection structure board, the first interconnection structure is located at the position of the device chip, the second interconnection structure is located at the side of the device chip, and the first interconnection structure is electrically connected to the device chip; in the step of bonding the second chip structure and the first chip structure to the second surface of the interconnection structure board, the first interconnection structure electrically connects the device chip to the first chip structure, and the device chip to the second chip structure, and the second interconnection structure electrically connects the first chip structure and the second chip structure; in the step of bonding the interconnection structure board to the substrate, the second interconnection structure electrically connects the first chip structure to the substrate, and the second chip structure to the substrate.

[0019] Optionally, before bonding the second chip structure and the first chip structure to the second surface of the interconnection structure board, the packaging method further includes: forming a second interconnection layer electrically connected to the interconnection structure board, the second interconnection layer being located on the first surface of the interconnection structure board on the side of the device chip; in the step of bonding the interconnection structure board to the substrate, the interconnection structure board is bonded to the substrate through the second interconnection layer.

[0020] Optionally, before forming an interconnection structure board electrically connected to the device chip, the method further includes: providing a substrate; the step of forming a second interconnection layer includes: placing the device chip on the substrate; forming a second interconnection layer on the substrate on both sides of the device chip; in the step of forming an interconnection structure board electrically connected to the device chip, the interconnection structure board covers the device chip and the second interconnection layer.

[0021] Optionally, the step of forming a second interconnection layer on the substrate on both sides of the device chip includes: forming a discrete third interconnection structure on the substrate on both sides of the device chip; forming a packaging layer covering the third interconnection structure and the device chip; removing the packaging layer and the third interconnection structure above the top surface of the device chip, and retaining the remaining third interconnection structure and packaging layer on the substrate on both sides of the device chip as the second interconnection layer.

[0022] Optionally, in the step of forming the second interconnect layer, the second interconnect layer is electrically isolated from the device chip.

[0023] Optionally, after the second chip structure and the first chip structure are bonded to the second surface of the interconnection structure board and before the interconnection structure board is bonded to the substrate, the method further includes: removing the substrate; after removing the substrate, forming a first conductive bump on the surface of the second interconnection layer facing away from the interconnection structure board; in the step of bonding the interconnection structure board to the substrate, electrically connecting the second interconnection layer and the substrate through the first conductive bump.

[0024] Optionally, after bonding the interconnect structure plate to the substrate, the packaging method further includes: forming a first sealing layer between the second interconnect layer and the substrate to fill the gap between the second interconnect layer and the substrate and the gap between adjacent first conductive bumps.

[0025] Optionally, in the step of providing a first chip structure, the first chip structure includes a logic chip; in the step of providing a second chip structure, the second chip structure includes one or a plurality of second chips stacked vertically, and the second chip includes a memory chip.

[0026] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0027] An embodiment of the present invention provides a packaging structure, wherein an interconnection structure board is bonded to a substrate, the interconnection structure board includes a first surface and a second surface opposite to each other, the first surface faces the substrate, the device chip is located on the first surface of the interconnection structure board and is electrically connected to the interconnection structure board, the first chip structure is bonded to the second surface of the interconnection structure board, the first chip structure is electrically connected to the device chip through the interconnection structure board, the second chip structure is bonded to the second surface of the interconnection structure board on the side of the first chip structure, the second chip structure is electrically connected to the device chip through the interconnection structure board, and the second chip structure is electrically connected to the first chip structure through the device chip; in an embodiment of the present invention, the first chip structure is electrically connected to the device chip, the second chip structure is electrically connected to the device chip, and the first chip structure is electrically connected to the second chip structure By electrically connecting the device chip and having the device in the device chip, it is possible to realize the interconnection between the first chip structure and the second chip structure while realizing the electrical connection between the first chip structure and the device of the device chip, and between the second chip structure and the device of the device chip. Compared with the interconnection structure board which only has the interconnection function, this scheme can transfer part of the device circuit structure of the first chip structure and the second chip structure to the device chip, and release part of the space in the first chip structure and the second chip structure, which is beneficial to simplify the circuit structure of the first chip structure and the second chip structure, and is also beneficial to increase the circuit composed of the first chip structure and the second chip structure by adding device chips, which is beneficial to increase the circuit diversity and improve the applicability and integration of the packaging structure.

[0028] An embodiment of the present invention provides a packaging method, forming an interconnection structure board electrically connected to a device chip, the interconnection structure board includes a first surface and a second surface opposite to each other, the first surface faces the device chip, a first chip structure is provided; a second chip structure is provided, the second chip structure and the first chip structure are bonded to the second surface of the interconnection structure board, the second chip structure is located on the side of the first chip structure, the first chip structure is electrically connected to the device chip through the interconnection structure board, the second chip structure is electrically connected to the device chip through the interconnection structure board, the second chip structure and the first chip structure are electrically connected through the device chip, a substrate is provided, after the second chip structure and the first chip structure are bonded to the second surface of the interconnection structure board, the interconnection structure board is bonded to the substrate, the first surface faces the substrate; in the embodiment of the present invention, the first chip structure is electrically connected to the device chip, the second chip structure is bonded to the first chip structure The first chip structure is electrically connected to the device chip, and the first chip structure is electrically connected to the second chip structure through the device chip. The device chip has a device. Then, while realizing the interconnection between the first chip structure and the second chip structure, the electrical connection between the first chip structure and the device of the device chip, and between the second chip structure and the device of the device chip can be realized. Compared with the interconnection structure board which only has the interconnection function, the present solution can transfer part of the device circuit structure of the first chip structure and the second chip structure to the device chip, release part of the space in the first chip structure and the second chip structure, which is beneficial to simplifying the circuit structure of the first chip structure and the second chip structure, and is beneficial to increasing the circuit composed of the first chip structure and the second chip structure by adding device chips, which is beneficial to increasing the circuit diversity and improving the applicability and integration of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic diagram of the structure of a packaging structure;

[0030] Figure 2 It is a structural schematic diagram of an embodiment of a packaging structure of the present invention;

[0031] Figures 3 to 12 It is a schematic structural diagram corresponding to each step in an embodiment of a packaging method of the present invention. DETAILED DESCRIPTION

[0032] As can be seen from the background technology, the applicability and integration of the current packaging structure are relatively poor. Now, the reasons why the applicability and integration of the packaging structure are relatively poor are analyzed in combination with a packaging structure.

[0033] Figure 1 It is a structural diagram of a packaging structure.

[0034] The packaging structure includes: a substrate 10; an interconnection board 11 bonded to the substrate 10; a first chip structure 31 bonded to the interconnection board 11; and a second chip structure 32 bonded to the interconnection board 11 at a side of the first chip structure 31.

[0035] The interconnection board 11 is used to electrically connect the first chip structure 31 and the second chip 32. The first chip structure 31 and the second chip structure 32 are interconnected through the interconnection board 11 to form a circuit structure. The first chip structure 31 is interconnected with the substrate 10 through the interconnection board 11 to form a circuit structure. The second chip structure 32 is interconnected with the substrate 10 through the interconnection board 11 to form a circuit structure. The interconnection board 11 only plays the role of interconnection, so that a more complex circuit structure needs to be formed in the first chip structure 31 and the second chip structure 32, which makes it difficult to simplify the circuit structure of the first chip structure and the second chip structure, and it is difficult to improve the integration and applicability of the packaging structure.

[0036] In order to solve the technical problem, an embodiment of the present invention provides a packaging structure, including: a substrate; an interconnection structure board bonded to the substrate, the interconnection structure board including a first surface and a second surface opposite to each other, the first surface facing the substrate; a device chip located on the first surface of the interconnection structure board and electrically connected to the interconnection structure board; a first chip structure bonded to the second surface of the interconnection structure board, the first chip structure is electrically connected to the device chip through the interconnection structure board; a second chip structure bonded to the second surface of the interconnection structure board on the side of the first chip structure, the second chip structure is electrically connected to the device chip through the interconnection structure board, and the second chip structure is electrically connected to the first chip structure through the device chip.

[0037] In an embodiment of the present invention, the first chip structure is electrically connected to the device chip, the second chip structure is electrically connected to the device chip, and the first chip structure and the second chip structure are electrically connected through the device chip. The device chip has a device, so that while realizing the interconnection between the first chip structure and the second chip structure, the electrical connection between the first chip structure and the device of the device chip, and the electrical connection between the second chip structure and the device of the device chip can be realized. Compared with the use of an interconnection structure board that only has an interconnection function, this solution can transfer part of the device circuit structure of the first chip structure and the second chip structure to the device chip, freeing up part of the space in the first chip structure and the second chip structure, which is beneficial to simplifying the circuit structure of the first chip structure and the second chip structure, and is also beneficial to increasing the circuit composed of the first chip structure and the second chip structure by adding device chips, which is beneficial to increasing circuit diversity and improving the applicability and integration of the packaging structure.

[0038] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] Figure 2 It is a structural schematic diagram of an embodiment of a packaging structure of the present invention.

[0040] The packaging structure includes: a substrate 700; an interconnection structure plate 500, bonded to the substrate 700, the interconnection structure plate 500 includes a first surface 500a and a second surface 500b opposite to each other, and the first surface 500a faces the substrate 700; a device chip 200, located on the first surface 500a of the interconnection structure plate 500, and electrically connected to the interconnection structure plate 500; a first chip structure 610, bonded to the second surface 500b of the interconnection structure plate 500, and the first chip structure 610 is electrically connected to the device chip 200 through the interconnection structure plate 500; a second chip structure 620, bonded to the second surface 500b of the interconnection structure plate 500 at the side of the first chip structure 610, the second chip structure 620 is electrically connected to the device chip 200 through the interconnection structure plate 500, and the second chip structure 620 is electrically connected to the first chip structure 610 through the device chip 200.

[0041] The substrate 700 is used to provide a process operation basis for bonding the second chip structure 620 , the first chip structure 610 and the interconnection structure plate 500 .

[0042] Specifically, in this embodiment, the substrate 700 is a packaging substrate, and the packaging substrate is a printed circuit board (PCB).

[0043] The interconnection structure board 500 is used to provide a process operation basis for bonding the second chip structure 620 to the first chip structure 610, and is also used to provide a process operation basis for bonding the device chip 200, wherein the second surface 500b is used as a process operation platform for bonding the second chip structure 620 to the first chip structure 610, and the first surface 500a is used as a process operation platform for bonding the device chip 200.

[0044] In this embodiment, the interconnection structure board is a redistribution structure (Redistribution Layer). Specifically, the redistribution structure may include one or more layers of redistribution interconnection boards.

[0045] Specifically, in this embodiment, the interconnection structure board is used to electrically connect to the second chip structure 620 and the first chip structure 610, as well as to electrically connect to the device chip 200, to achieve electrical connection between the second chip structure 620 and the substrate 700, between the first chip structure 610 and the substrate 700, and between the second chip structure 620 and the first chip structure 610.

[0046] In this embodiment, the interconnection structure board 500 includes: a first interconnection structure 510 that penetrates the interconnection structure board 500, the first interconnection structure 510 is located at the position of the device chip 200, and the first interconnection structure 510 electrically connects the device chip 200 with the first chip structure 610, and the device chip 200 with the second chip structure 620.

[0047] The first interconnect structure 510 is used to electrically connect the first chip structure 610 and the device chip 200 , and the second chip structure 620 and the device chip 200 .

[0048] In this embodiment, the interconnection structure board 500 further includes: a second interconnection structure 520 penetrating the interconnection structure board 500, the second interconnection structure 520 is located on the side of the device chip 200, and the second interconnection structure 520 electrically connects the first chip structure 610 and the substrate 700, and the second chip structure 620 and the substrate 700.

[0049] The second interconnect structure 520 is used to electrically connect the first chip structure 610 and the substrate 700 , and the second chip structure 620 and the substrate 700 .

[0050] The device chip 200 is used to be electrically connected to the interconnection structure board 500, thereby being electrically connected to the first chip structure 610 through the interconnection structure board 500 and being electrically connected to the second chip structure 620 through the interconnection structure board 500, thereby realizing the electrical connection between the first chip structure 610 and the second chip structure 620, and also making the devices in the device chip 200 electrically connected to the first chip structure 610 to form a circuit structure, and making the devices in the device chip 200 electrically connected to the second chip structure 620 to form a circuit structure.

[0051] In this embodiment, the first chip structure 610 is electrically connected to the device chip 200, the second chip structure 630 is electrically connected to the device chip 200, and the first chip structure 610 is electrically connected to the second chip structure 620 through the device chip 200. The device chip 200 has a device, so that while the first chip structure 610 and the second chip structure 620 are interconnected, the first chip structure 610 and the device of the device chip 200, and the second chip structure 620 and the device of the device chip 200 can also be electrically connected. Compared with the interconnection structure board that only has the interconnection function, this solution can transfer part of the device circuit structure of the first chip structure 610 and the second chip structure 620 to the device chip 200, release part of the space in the first chip structure 610 and the second chip structure 620, which is conducive to simplifying the circuit structure of the first chip structure 610 and the second chip structure 620, and is also conducive to increasing the circuit composed of the first chip structure 610 and the second chip structure 620 by adding the device chip 200, which is conducive to increasing the circuit diversity and improving the applicability and integration of the packaging structure.

[0052] In this embodiment, the device chip 200 includes a device layer 210 and a first interconnection layer 220 located on the device layer 210, the first interconnection layer 220 is located on the side of the device chip 200 close to the interconnection structure board 500, the device layer 210 is located on the side of the device chip 200 away from the interconnection structure board 500, the first interconnection layer 220 is electrically connected to the device of the device layer 210, and the first interconnection layer 220 is electrically connected to the interconnection structure board 500.

[0053] The first interconnection layer 220 is located on the side of the device chip 200 close to the interconnection structure board 500, and the device layer 210 is located on the side of the device chip 200 away from the interconnection structure board 500. The first interconnection layer 220 is electrically connected to the devices of the device layer 210, and the first interconnection layer 220 is electrically connected to the interconnection structure board 500, so that the devices of the device layer 210 are electrically connected to the interconnection structure board 500 through the first interconnection layer 220, so that the devices of the device layer 210 are electrically connected to the first chip structure 610 and the second chip structure 620, forming a corresponding circuit structure.

[0054] In this embodiment, the first chip structure 610 is electrically connected to the first interconnect layer 220 through the interconnect structure plate 500 , so that the first chip structure 610 is electrically connected to the devices of the device layer 210 through the first interconnect layer 220 .

[0055] In this embodiment, the second chip structure 620 is electrically connected to the first interconnect layer 220 through the interconnect structure plate 500, so that the second chip structure 620 is electrically connected to the devices of the device layer 210 through the first interconnect layer 220, and the first chip structure 610 and the second chip structure 620 are electrically connected to each other through the first interconnect layer 220.

[0056] In this embodiment, the packaging structure also includes: a second interconnection layer 300, which is located on the first surface 500a of the interconnection structure plate 500 on the side of the device chip 200, the second interconnection layer 300 is electrically connected to the interconnection structure plate 500, and the interconnection structure plate 500 is bonded to the substrate 700 through the second interconnection layer 300.

[0057] The second interconnection layer 300 is used to realize the electrical connection between the interconnection structure plate 500 and the substrate 700 , and correspondingly realize the electrical connection between the first chip structure 610 and the substrate 700 , and the electrical connection between the second chip structure 620 and the substrate 700 .

[0058] In this embodiment, the second interconnection layer 300 is used to realize the electrical connection between the interconnection structure plate 500 and the substrate 700, which is beneficial to reduce the height difference between the first surface 500a of the interconnection structure plate 500 and the surface of the device chip 200 facing the substrate 700. Compared with directly realizing the electrical connection between the interconnection structure plate and the substrate through the bump, this solution is beneficial to reduce the volume of the first conductive bump located under the interconnection structure plate 500, which is beneficial to make the interconnection structure plate 500 easy to bond to the substrate 700.

[0059] In this embodiment, the surface of the second interconnection layer 300 facing away from the interconnection structure board 500 is flush with the surface of the device chip 200 facing away from the interconnection structure board 500 .

[0060] The surface of the second interconnection layer 300 facing away from the interconnection structure board 500 is flush with the surface of the device chip 200 facing away from the interconnection structure board 500. That is, the device chip 200 is embedded in the electrical connection structure formed by the interconnection structure board 500 and the second interconnection layer 300, and the surface of the second interconnection layer 300 flush with the device chip 200 faces the substrate 700, so that the second interconnection layer 300 is easy to bond to the substrate 700, and when the second interconnection layer 300 is bonded to the substrate 700, an appropriate gap is also provided between the device chip 200 and the substrate 700.

[0061] In this embodiment, the second interconnect layer 300 is electrically isolated from the device chip 200 .

[0062] The second interconnect layer 300 is electrically isolated from the device chip 200 , so that the second interconnect layer 300 and the device chip 200 can respectively realize their own electrical connection functions without interfering with each other.

[0063] In this embodiment, the second interconnect layer 300 includes a third interconnect structure 310 penetrating the second interconnect layer 300 , and the third interconnect structure 310 electrically connects the interconnect structure plate 500 and the substrate 700 .

[0064] The third interconnect structure 310 is used to realize electrical connection between the interconnect structure plate 500 and the substrate 700 .

[0065] In this embodiment, the material of the third interconnect structure 310 includes copper.

[0066] In this embodiment, the second interconnect layer 300 further includes a packaging layer 320 covering the third interconnect structure 310 .

[0067] The encapsulation layer 320 is used to isolate adjacent third interconnect structures 310 , and to isolate the third interconnect structures 310 from the device chip 200 .

[0068] In this embodiment, the material of the encapsulation layer 320 is a molding material, such as epoxy resin. Epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, good insulation and low cost. In other embodiments, the encapsulation layer can also use other suitable encapsulation materials.

[0069] The first chip structure 610 is used to be electrically connected to the interconnection structure board 500 , so as to realize electrical connection between the first chip structure 610 and the second chip structure 620 , and between the first chip structure 610 and the substrate 700 .

[0070] Specifically, in this embodiment, the first chip structure 610 is electrically connected to the interconnection structure plate 500 , and is electrically connected to the substrate 700 through the interconnection structure plate 500 . The first chip structure 610 is electrically connected to each second chip structure 620 through the device chip 200 .

[0071] In this embodiment, the first chip structure 610 is a logic chip, and in this embodiment, as a first logic chip, it is used to control the memory chip of the second chip structure 620. Specifically, the first logic chip can be a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or a system on chip (SoC).

[0072] The second chip structure 620 is used to be electrically connected to the interconnection structure board 500 , so as to realize electrical connection between the second chip structure 620 and the first chip structure 610 , and electrical connection between the second chip structure 620 and the substrate 700 .

[0073] In this embodiment, the second chip structure 620 includes one or a plurality of chips stacked in a longitudinal direction, so as to achieve electrical connection between each chip and the first chip structure 610 , and electrical connection between each chip and the substrate 700 .

[0074] Specifically, in this embodiment, the second chip structure 620 is electrically connected to the interconnection structure plate 500 , and is electrically connected to the substrate 700 through the interconnection structure plate 500 . The second chip structure 620 is electrically connected to the first chip structure 610 through the device chip 200 .

[0075] In this embodiment, in the second chip structure 620, a high bandwidth memory (HBM) structure formed by a plurality of chips stacked in the vertical direction adopts the HBM structure, which is conducive to meeting the requirement for higher information transmission speed.

[0076] The plurality of chips stacked in the longitudinal direction include a bottom chip at the bottom and a top chip stacked on the bottom chip, and the number of the top chips may be one or more. In this embodiment, four top chips are used as an example for illustration. In other embodiments, the number of top chips may also be other numbers.

[0077] Therefore, in this embodiment, the top chip is a memory chip. In a specific implementation, the top chip is a high bandwidth memory chip.

[0078] In this embodiment, the bottom chip is a second logic chip. Specifically, the bottom chip is used as a logic control chip in the second chip structure 620 .

[0079] In this embodiment, the bottom chip and the substrate 700 , as well as the adjacent chips in the vertical direction, are electrically connected, thereby achieving electrical integration between the chips and electrical integration between the chip and the substrate 700 .

[0080] In this embodiment, there are multiple second chip structures 620 , and multiple second chip structures 620 are electrically connected to the first chip structure 610 , which is beneficial to increasing the memory of the package structure, improving the chip speed and reducing the chip power consumption.

[0081] In this embodiment, the packaging structure further includes: a first conductive bump 420 , which is located between the second interconnect layer 300 and the substrate 700 and electrically connects the second interconnect layer 300 and the substrate 700 .

[0082] The first conductive bump 420 is used to realize electrical connection between the second interconnect layer 300 and the substrate 700 .

[0083] In this embodiment, the material of the first conductive bump 420 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the first conductive bump 420 is tin.

[0084] In this embodiment, the first conductive bumps 420 may be micro bumps (uBumps), which have a high density and are beneficial for improving the communication speed between the second interconnect layer 300 and the substrate 700 .

[0085] In other embodiments, the first conductive bump can also be C4 (Controlled Collapse Chip Connection), which has excellent electrical and thermal properties. Moreover, under the condition of the same first conductive bump 420 spacing, the number of I / Os can be very high and is not limited by the size of the rewiring structure. In addition, it is suitable for mass production and greatly reduces size and weight.

[0086] In this embodiment, the packaging structure also includes: a second conductive bump 410, which is located between the interconnection structure board 500 and the first chip structure 610, and between the interconnection structure board 500 and the second chip structure 620, and electrically connects the interconnection structure board 500 and the first chip structure 610, and electrically connects the interconnection structure board 500 and the second chip structure 620.

[0087] The second conductive bumps 410 are used to realize electrical connection between the first chip structure 610 and the interconnection structure board 500 , and between the second chip structure 620 and the interconnection structure board 500 .

[0088] In this embodiment, the material of the second conductive bump 410 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the second conductive bump 410 is tin.

[0089] In this embodiment, the second conductive bump 410 may be a micro bump (uBump), which has a high density and is beneficial for improving the communication speed between the first chip structure 610 and the interconnection structure board 500 and between the second chip structure 620 and the interconnection structure board 500.

[0090] In this embodiment, the packaging structure further includes: a first sealing layer 720 located between the second interconnect layer 300 and the substrate 700 and filling the gap between the second interconnect layer 300 and the substrate 700 and the gap between adjacent first conductive bumps 420 .

[0091] The first sealing layer 720 is used to achieve sealing between the second interconnect layer 300 and the substrate 700 , and to achieve sealing between adjacent first conductive bumps 420 .

[0092] In this embodiment, the packaging structure further includes: a second sealing layer 710 filled between adjacent second conductive bumps 410 and covering the second conductive bumps 410 .

[0093] The second sealing layer 710 implements sealing between the interconnection structure plate 500 and the first chip structure 610 , implements sealing between the interconnection structure plate 500 and the second chip structure 620 , and implements sealing between adjacent second conductive bumps 410 .

[0094] In this embodiment, the packaging structure further includes: a third conductive bump 430 located at the bottom of the substrate 700 .

[0095] The third conductive bump 430 is used to realize electrical connection between the substrate 700 and the outside.

[0096] In this embodiment, the material of the third conductive bump 430 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the third conductive bump 430 is tin.

[0097] In this embodiment, the third conductive bump 430 may be a ball grid array (BGA) structure.

[0098] Figures 3 to 12 It is a schematic structural diagram corresponding to each step in an embodiment of a packaging method of the present invention.

[0099] refer to Figure 3 , providing a device chip 200.

[0100] The device chip 200 is used to subsequently electrically connect with the interconnection structure board, thereby electrically connecting with the first chip structure through the interconnection structure board and electrically connecting with the second chip structure through the interconnection structure board, thereby realizing the electrical connection between the first chip structure and the second chip structure, and also making the devices in the device chip 200 electrically connected to the first chip structure to form a circuit structure, and making the devices in the device chip 200 electrically connected to the second chip structure to form a circuit structure.

[0101] In this embodiment, in the step of providing the device chip 200 , the device chip 200 includes a device layer 210 and a first interconnection layer 220 located on the device layer 210 , and the first interconnection layer 220 is electrically connected to the devices of the device layer 210 .

[0102] The first interconnect layer 220 is electrically connected to the devices of the device layer 210 , so that a subsequent interconnect structure plate can be electrically connected to the devices of the device layer 210 through the first interconnect layer 220 .

[0103] Continue to refer Figure 3 Before subsequently forming an interconnection structure board electrically connected to the device chip 200 , the method further includes: providing a substrate 100 .

[0104] The substrate 100 is used to provide a process platform for subsequently forming a second interconnection layer and an interconnection structure plate electrically connected to the device chip 200, and is also used to provide a supporting platform for subsequently bonding the first chip structure and the second chip structure.

[0105] In this embodiment, the base 100 is a carrier substrate, and the carrier substrate is a wafer. In other embodiments, the carrier substrate may also be a glass substrate.

[0106] Combined with reference Figures 3 to 7 , forming an interconnection structure plate 500 electrically connected to the device chip 200 , the interconnection structure plate 500 includes a first surface 500 a and a second surface 500 b opposite to each other, and the first surface 500 a faces the device chip 200 .

[0107] The interconnect structure board 500 is used to provide a process operation basis for the subsequent bonding of the second chip structure to the first chip structure, and is also used to provide a process operation basis for the bonding of the device chip 200, wherein the second surface 500b is used as a process operation platform for bonding the second chip structure to the first chip structure, and the first surface 500a is used as a process operation platform for bonding the device chip 200.

[0108] In this embodiment, the interconnection structure board 500 is a redistribution structure (Redistribution Layer). Specifically, the redistribution structure may include one or more layers of redistribution interconnection boards.

[0109] Specifically, in this embodiment, the interconnection structure board 500 is used to subsequently electrically connect with the second chip structure and the first chip structure, as well as with the device chip 200, to achieve electrical connection between the second chip structure and the substrate, between the first chip structure and the substrate, and between the second chip structure and the first chip structure.

[0110] In this embodiment, in the step of forming the interconnection structure plate 500 electrically connected to the device chip 200 , the interconnection structure plate 500 is located on the first interconnection layer 220 , and the first interconnection layer 220 is electrically connected to the interconnection structure plate 500 .

[0111] The first interconnection layer 220 is located on the side of the device chip 200 close to the interconnection structure board 500, and the device layer 210 is located on the side of the device chip 200 away from the interconnection structure board 500. The first interconnection layer 220 is electrically connected to the devices of the device layer 210, and the first interconnection layer 220 is electrically connected to the interconnection structure board 500, so that the devices of the device layer 210 are electrically connected to the interconnection structure board 500 through the first interconnection layer 220, so that the devices of the device layer 210 are electrically connected to the first chip structure and the second chip structure, forming a corresponding circuit structure.

[0112] In this embodiment, the step of forming an interconnection structure plate 500 electrically connected to the device chip 200 also includes: forming a first interconnection structure 510 and a second interconnection structure 520 that penetrate the interconnection structure plate 500, the first interconnection structure 510 is located at the position of the device chip 200, the second interconnection structure 520 is located at the side of the device chip 200, and the first interconnection structure 510 is electrically connected to the device chip 200.

[0113] The first interconnect structure 510 is used to subsequently electrically connect the first chip structure and the device chip 200 , and the second chip structure and the device chip 200 .

[0114] The second interconnect structure 520 is used to subsequently electrically connect the first chip structure and the substrate, and the second chip structure and the substrate.

[0115] In this embodiment, before subsequently bonding the second chip structure and the first chip structure to the second surface 500b of the interconnection structure board 500, the packaging method further includes: forming a second interconnection layer 300 electrically connected to the interconnection structure board 500, and the second interconnection layer 300 is located on the first surface 500a of the interconnection structure board 500 on the side of the device chip 200.

[0116] The second interconnection layer 300 is used to subsequently realize the electrical connection between the interconnection structure plate 500 and the substrate, and correspondingly realize the electrical connection between the first chip structure and the substrate, and the electrical connection between the second chip structure and the substrate.

[0117] In this embodiment, the second interconnection layer 300 is used to realize the electrical connection between the interconnection structure plate 500 and the substrate, which is beneficial to reducing the height difference between the first surface 500a of the subsequent interconnection structure plate 500 and the surface of the device chip 200 facing the substrate. Compared with directly realizing the electrical connection between the interconnection structure plate and the substrate through the bump, this solution is beneficial to reducing the volume of the first conductive bump located between the interconnection structure plate 500 and the substrate, which is beneficial to making the interconnection structure plate 500 easy to bond to the substrate.

[0118] In this embodiment, in the step of forming the second interconnect layer 300 electrically connected to the interconnect structure board 500 , the surface of the second interconnect layer 300 facing away from the interconnect structure board 500 is flush with the surface of the device chip 200 facing away from the interconnect structure board 500 .

[0119] The surface of the second interconnection layer 300 facing away from the interconnection structure plate 500 is flush with the surface of the device chip 200 facing away from the interconnection structure plate 500, that is, the device chip 200 is embedded in the electrical connection structure formed by the interconnection structure plate 500 and the second interconnection layer 300, and subsequently the surface of the second interconnection layer 300 flush with the device chip 200 faces the substrate, so that the second interconnection layer 300 is easy to bond to the substrate, and when the second interconnection layer 300 is subsequently bonded to the substrate, an appropriate gap is also provided between the device chip 200 and the substrate.

[0120] In this embodiment, in the step of forming the second interconnection layer 300 , the second interconnection layer 300 is electrically isolated from the device chip 200 .

[0121] The second interconnect layer 300 is electrically isolated from the device chip 200 , so that the second interconnect layer 300 and the device chip 200 can respectively realize their own electrical connection functions without interfering with each other.

[0122] Specifically, refer to Figure 3 The step of forming the second interconnection layer 300 includes: placing the device chip 200 on the substrate 100 .

[0123] The device chip 200 is placed on the substrate 100 , leaving space for forming the second interconnection layer 300 on the substrate 100 at the side of the device chip 200 .

[0124] Combined with reference Figures 4 to 6 , a second interconnection layer 300 is formed on the substrate 100 on both sides of the device chip 200 .

[0125] Specifically, refer to Figure 4 The step of forming the second interconnect layer 300 on the substrate 100 on both sides of the device chip 200 includes: forming a discrete third interconnect structure 310 on the substrate 100 on both sides of the device chip 200 .

[0126] The third interconnect structure 310 is used to subsequently realize electrical connection between the interconnect structure plate 500 and the substrate.

[0127] In this embodiment, the material of the third interconnect structure 310 includes copper.

[0128] refer to Figure 5 , forming a packaging layer 320 covering the third interconnect structure 310 and the device chip 200 .

[0129] The encapsulation layer 320 is used to isolate adjacent third interconnect structures 310 , and to isolate the third interconnect structures 310 from the device chip 200 .

[0130] In this embodiment, the material of the encapsulation layer 320 is a molding material, such as epoxy resin. Epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, good insulation and low cost. In other embodiments, the encapsulation layer can also use other suitable encapsulation materials.

[0131] refer to Figure 6 , remove the packaging layer 320 and the third interconnect structure 310 above the top surface of the device chip 200 , and retain the remaining third interconnect structure 310 and the packaging layer 320 on the substrate 100 on both sides of the device chip 200 as the second interconnect layer 300 .

[0132] The packaging layer 320 and the third interconnection structure 310 that are higher than the top surface of the device chip 200 are removed, so that the top of the device chip 200 and the second interconnection layer 300 have better flatness, thereby obtaining a process platform with better flatness, providing a better process platform for forming an interconnection structure plate 500 electrically connected to the device chip 200.

[0133] Accordingly, with the substrate 100 as a process platform, the surface of the second interconnection layer 300 facing away from the interconnection structure plate 500 can be flush with the surface of the device chip 200 facing away from the interconnection structure plate 500 .

[0134] refer to Figure 7In the step of forming the interconnection structure plate 500 electrically connected to the device chip 200 , the interconnection structure plate 500 covers the device chip 200 and the second interconnection layer 300 .

[0135] The interconnection structure plate 500 covers the device chip 200 and the second interconnection layer 300 , and realizes electrical connection between the interconnection structure plate 500 and the device chip 200 , and electrical connection between the interconnection structure plate 500 and the second interconnection layer 300 .

[0136] refer to Figure 8 Before subsequently bonding the second chip structure and the first chip structure to the second surface 500 b of the interconnection structure board 500 , the method further includes: forming a second conductive bump 410 on the first surface 500 a of the interconnection structure board 500 .

[0137] The second conductive bumps 410 are used to subsequently realize electrical connection between the first chip structure and the interconnection structure board 500 , and electrical connection between the second chip structure and the interconnection structure board 500 .

[0138] In this embodiment, the material of the second conductive bump 410 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the second conductive bump 410 is tin.

[0139] In this embodiment, the second conductive bump 410 may be a micro bump (uBump), which has a high density and is beneficial for improving the communication speed between the first chip structure and the interconnection structure board 500 and between the second chip structure and the interconnection structure board 500.

[0140] refer to Fig. 9 , providing a first chip structure 610; providing a second chip structure 620.

[0141] The first chip structure 610 is used to be electrically connected to the interconnection structure board 500 to achieve electrical connection between the first chip structure 610 and the second chip structure 620 , and between the first chip structure 610 and the substrate.

[0142] In this embodiment, the first chip structure 610 is a logic chip, and in this embodiment, as a first logic chip, it is used to control the memory chip of the second chip structure 620. Specifically, the first logic chip can be a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or a system on chip (SoC).

[0143] The second chip structure 620 is used to be electrically connected to the interconnection structure board 500 to achieve electrical connection between the second chip structure 620 and the first chip structure 610 , and between the second chip structure 620 and the substrate.

[0144] In this embodiment, the second chip structure 620 includes one or a plurality of chips stacked in a longitudinal direction, so as to realize electrical connection between each chip and the first chip structure 610 , and electrical connection between each chip and the substrate.

[0145] In this embodiment, in the second chip structure 620, a high bandwidth memory (HBM) structure formed by a plurality of chips stacked in the vertical direction adopts the HBM structure, which is conducive to meeting the requirement for higher information transmission speed.

[0146] The plurality of chips stacked in the longitudinal direction include a bottom chip at the bottom and a top chip stacked on the bottom chip, and the number of the top chips may be one or more. In this embodiment, four top chips are used as an example for illustration. In other embodiments, the number of top chips may also be other numbers.

[0147] Therefore, in this embodiment, the top chip is a memory chip. In a specific implementation, the top chip is a high bandwidth memory chip.

[0148] In this embodiment, the bottom chip is a second logic chip. Specifically, the bottom chip is used as a logic control chip in the second chip structure 620 .

[0149] In this embodiment, the bottom chip and the substrate, as well as the adjacent chips in the vertical direction, are electrically connected, thereby achieving electrical integration between the chips and electrical integration between the chip and the substrate.

[0150] In this embodiment, there are multiple second chip structures 620 , and multiple second chip structures 620 are electrically connected to the first chip structure 610 , which is beneficial to increasing the memory of the package structure, improving the chip speed and reducing the chip power consumption.

[0151] Continue to refer Fig. 9 The second chip structure 620 and the first chip structure 610 are bonded to the second surface 500b of the interconnection structure plate 500, the second chip structure 620 is located on the side of the first chip structure 610, the first chip structure 610 is electrically connected to the device chip 200 through the interconnection structure plate 500, the second chip structure 620 is electrically connected to the device chip 200 through the interconnection structure plate 500, and the second chip structure 620 is electrically connected to the first chip structure 610 through the device chip 200.

[0152] In this embodiment, the first chip structure 610 is electrically connected to the device chip 200, the second chip structure 630 is electrically connected to the device chip 200, and the first chip structure 610 is electrically connected to the second chip structure 620 through the device chip 200. The device chip 200 has a device, so that while the first chip structure 610 and the second chip structure 620 are interconnected, the first chip structure 610 and the device of the device chip 200, and the second chip structure 620 and the device of the device chip 200 can also be electrically connected. Compared with the interconnection structure board that only has the interconnection function, this solution can transfer part of the device circuit structure of the first chip structure 610 and the second chip structure 620 to the device chip 200, release part of the space in the first chip structure 610 and the second chip structure 620, which is conducive to simplifying the circuit structure of the first chip structure 610 and the second chip structure 620, and is also conducive to increasing the circuit composed of the first chip structure 610 and the second chip structure 620 by adding the device chip 200, which is conducive to increasing the circuit diversity and improving the applicability and integration of the packaging structure.

[0153] In this embodiment, in the step of bonding the second chip structure 620 and the first chip structure 610 to the second surface 500 b of the interconnect structure plate 500, the first chip structure 610 is electrically connected to the first interconnect layer 220 through the interconnect structure plate 500, the second chip structure 620 is electrically connected to the first interconnect layer 220 through the interconnect structure plate 500, and the first chip structure 610 and the second chip structure 620 are electrically connected through the first interconnect layer 220.

[0154] The first chip structure 610 is electrically connected to the first interconnect layer 220 through the interconnect structure plate 500, so that the first chip structure 610 is electrically connected to the devices of the device layer 210 through the first interconnect layer 220. The second chip structure 620 is electrically connected to the first interconnect layer 220 through the interconnect structure plate 500, so that the second chip structure 620 is electrically connected to the devices of the device layer 210 through the first interconnect layer 220, and the first chip structure 610 and the second chip structure 620 are electrically connected to each other through the first interconnect layer 220.

[0155] In this embodiment, in the step of bonding the second chip structure 620 and the first chip structure 610 to the second surface 500 b of the interconnect structure plate 500 , the first interconnect structure 510 electrically connects the device chip 200 with the first chip structure 610 , and the device chip 200 with the second chip structure 620 , and the second interconnect structure 520 electrically connects the first chip structure 610 and the second chip structure 620 .

[0156] In this embodiment, after the second chip structure 620 and the first chip structure 610 are bonded to the second surface of the interconnection structure board 500 , the second sealing layer 710 is further formed to fill between adjacent second conductive bumps 410 and cover the second conductive bumps 410 .

[0157] The second sealing layer 710 implements sealing between the interconnection structure plate 500 and the first chip structure 610 , implements sealing between the interconnection structure plate 500 and the second chip structure 620 , and implements sealing between adjacent second conductive bumps 410 .

[0158] refer to Fig.10 , providing a substrate 700.

[0159] The substrate 700 is used to provide a process operation basis for bonding the second chip structure 620 , the first chip structure 610 and the interconnection structure plate 500 .

[0160] Specifically, in this embodiment, the substrate 700 is a packaging substrate, and the packaging substrate is a printed circuit board (PCB).

[0161] refer to Fig.11 After the second chip structure 620 and the first chip structure 610 are bonded to the second surface 500 b of the interconnection structure plate 500 , before the interconnection structure plate 500 is subsequently bonded to the substrate 700 , the method further includes: removing the base 100 .

[0162] The substrate 100 is removed to expose the surface of the second interconnection layer 300 facing away from the interconnection structure plate 500 , in preparation for the subsequent bonding of the surface of the second interconnection layer 300 facing away from the interconnection structure plate 500 with the substrate 700 .

[0163] In this embodiment, after the substrate 100 is removed, a first conductive bump 420 is formed on the surface of the second interconnection layer 300 facing away from the interconnection structure board 500 .

[0164] The first conductive bump 420 is used to realize electrical connection between the second interconnect layer 300 and the substrate 700 .

[0165] In this embodiment, the material of the first conductive bump 420 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the first conductive bump 420 is tin.

[0166] In this embodiment, the first conductive bumps 420 may be micro bumps (uBumps), which have a high density and are beneficial for improving the communication speed between the second interconnect layer 300 and the substrate 700 .

[0167] In other embodiments, the first conductive bump can also be C4 (Controlled Collapse Chip Connection), which has excellent electrical and thermal properties. Moreover, under the condition of the same first conductive bump 420 spacing, the number of I / Os can be very high and is not limited by the size of the rewiring structure. In addition, it is suitable for mass production and greatly reduces size and weight.

[0168] refer to Fig.12 After the second chip structure 620 and the first chip structure 610 are bonded to the second surface 500 b of the interconnection structure plate 500 , the interconnection structure plate 500 is bonded to the substrate 700 with the first surface 500 a facing the substrate 700 .

[0169] The first chip structure 610 is electrically connected to the interconnection structure plate 500, and is electrically connected to the substrate 700 through the interconnection structure plate 500. The first chip structure 610 is electrically connected to each second chip structure 620 through the device chip 200. The second chip structure 620 is electrically connected to the interconnection structure plate 500, and is electrically connected to the substrate 700 through the interconnection structure plate 500. The second chip structure 620 is electrically connected to the first chip structure 610 through the device chip 200.

[0170] In this embodiment, in the step of bonding the interconnection structure plate 500 to the substrate 700 , the second interconnection structure 520 electrically connects the first chip structure 610 and the substrate 700 , and the second chip structure 620 and the substrate 700 .

[0171] The second interconnect structure 520 electrically connects the first chip structure 610 and the substrate 700 , and the second chip structure 620 and the substrate 700 , thereby achieving electrical connection between the first chip structure 610 and the substrate 700 , and between the second chip structure 520 and the substrate 700 .

[0172] In this embodiment, in the step of bonding the interconnection structure plate 500 to the substrate 700 , the interconnection structure plate 500 is bonded to the substrate 700 through the second interconnection layer 300 .

[0173] In this embodiment, in the step of bonding the interconnection structure plate 500 to the substrate 700 , the second interconnection layer 300 and the substrate 700 are electrically connected through the first conductive bumps 420 .

[0174] In this embodiment, after the interconnect structure plate 500 is bonded to the substrate 700, the packaging method further includes: forming a first sealing layer 720 between the second interconnect layer 300 and the substrate 700 to fill the gap between the second interconnect layer 300 and the substrate 700 and the gap between adjacent first conductive bumps 420.

[0175] The first sealing layer 720 is used to achieve sealing between the second interconnect layer 300 and the substrate 700 , and to achieve sealing between adjacent first conductive bumps 420 .

[0176] In this embodiment, the packaging method further includes: forming a third conductive bump 430 on the bottom of the substrate 700 .

[0177] The third conductive bump 430 is used to realize electrical connection between the substrate 700 and the outside.

[0178] In this embodiment, the material of the third conductive bump 430 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the third conductive bump 430 is tin.

[0179] In this embodiment, the third conductive bump 430 may be a ball grid array (BGA) structure.

[0180] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A packaging structure, characterized in that: include: substrate; An interconnection structure plate, bonded to the substrate, the interconnection structure plate comprising a first surface and a second surface opposite to each other, the first surface facing the substrate; A device chip, located on the first surface of the interconnection structure board and electrically connected to the interconnection structure board; A first chip structure, bonded to the second surface of the interconnection structure board, the first chip structure being electrically connected to the device chip through the interconnection structure board; The second chip structure is bonded to the second surface of the interconnection structure plate on the side of the first chip structure, the second chip structure is electrically connected to the device chip through the interconnection structure plate, and the second chip structure is electrically connected to the first chip structure through the device chip.

2. The packaging structure according to claim 1, characterized in that: The device chip comprises a device layer and a first interconnection layer located on the device layer, the first interconnection layer is located on a side of the device chip close to the interconnection structure board, the device layer is located on a side of the device chip away from the interconnection structure board, the first interconnection layer is electrically connected to the device of the device layer, and the first interconnection layer is electrically connected to the interconnection structure board; The first chip structure is electrically connected to the first interconnect layer through the interconnect structure board; The second chip structure is electrically connected to the first interconnect layer through the interconnect structure board, and the first chip structure is electrically connected to the second chip structure through the first interconnect layer.

3. The packaging structure according to claim 1, characterized in that: The interconnect structure board comprises: a first interconnect structure penetrating the interconnect structure board, the first interconnect structure being located at the position of the device chip, the first interconnect structure electrically connecting the device chip with a first chip structure, and the device chip with a second chip structure; A second interconnect structure runs through the interconnect structure plate, the second interconnect structure is located at a side of the device chip, and the second interconnect structure electrically connects the first chip structure and the substrate, and the second chip structure and the substrate.

4. The packaging structure according to claim 1, characterized in that: The packaging structure further includes: a second interconnect layer located on the first surface of the interconnect structure plate at the side of the device chip, the second interconnect layer is electrically connected to the interconnect structure plate, and the interconnect structure plate is bonded to the substrate through the second interconnect layer.

5. The packaging structure according to claim 4, characterized in that: The surface of the second interconnect layer facing away from the interconnect structure board is flush with the surface of the device chip facing away from the interconnect structure board.

6. The packaging structure according to claim 4, characterized in that: The second interconnect layer is electrically isolated from the device chip.

7. The packaging structure according to claim 4, characterized in that: The second interconnect layer includes a third interconnect structure penetrating the second interconnect layer, and the third interconnect structure electrically connects the interconnect structure plate and the substrate.

8. The packaging structure according to claim 4, characterized in that: The packaging structure further includes: a first conductive bump, located between the second interconnect layer and the substrate, and electrically connecting the second interconnect layer and the substrate; The second conductive bump is located between the interconnection structure board and the first chip structure, and between the interconnection structure board and the second chip structure, and electrically connects the interconnection structure board and the first chip structure, and electrically connects the interconnection structure board and the second chip structure.

9. The packaging structure according to claim 8, characterized in that: The packaging structure further includes: a first sealing layer, located between the second interconnect layer and the substrate, and filling the gap between the second interconnect layer and the substrate, and the gap between adjacent first conductive bumps; The second sealing layer is filled between adjacent second conductive bumps and covers the second conductive bumps.

10. The packaging structure according to claim 1, wherein: The first chip structure includes a logic chip, the second chip structure includes one or a plurality of second chips stacked in a vertical direction, and the second chip includes a memory chip.

11. A packaging method, characterized in that: include: Provide device chips; forming an interconnection structure plate electrically connected to the device chip, the interconnection structure plate comprising a first surface and a second surface opposite to each other, the first surface facing the device chip; Providing a first chip structure; providing a second chip structure; Bonding the second chip structure and the first chip structure to the second surface of the interconnection structure board, wherein the second chip structure is located at the side of the first chip structure, the first chip structure is electrically connected to the device chip through the interconnection structure board, the second chip structure is electrically connected to the device chip through the interconnection structure board, and the second chip structure is electrically connected to the first chip structure through the device chip; providing a substrate; After the second chip structure and the first chip structure are bonded to the second surface of the interconnection structure board, the interconnection structure board is bonded to the substrate, with the first surface facing the substrate.

12. The packaging method according to claim 11, characterized in that: In the step of providing the device chip, the device chip comprises a device layer and a first interconnection layer located on the device layer, wherein the first interconnection layer is electrically connected to the device of the device layer; In the step of forming an interconnection structure plate electrically connected to the device chip, the interconnection structure plate is located on the first interconnection layer, and the first interconnection layer is electrically connected to the interconnection structure plate; In the step of bonding the second chip structure and the first chip structure to the second surface of the interconnect structure board, the first chip structure is electrically connected to the first interconnect layer through the interconnect structure board, the second chip structure is electrically connected to the first interconnect layer through the interconnect structure board, and the first chip structure is electrically connected to the second chip structure through the first interconnect layer.

13. The packaging method according to claim 12, characterized in that: The step of forming an interconnection structure plate electrically connected to the device chip further includes: forming a first interconnection structure and a second interconnection structure penetrating the interconnection structure plate, wherein the first interconnection structure is located at the position of the device chip, the second interconnection structure is located at the side of the device chip, and the first interconnection structure is electrically connected to the device chip; In the step of bonding the second chip structure and the first chip structure to the second surface of the interconnect structure board, the first interconnect structure electrically connects the device chip to the first chip structure and the device chip to the second chip structure, and the second interconnect structure electrically connects the first chip structure and the second chip structure; In the step of bonding the interconnect structure plate to the substrate, the second interconnect structure electrically connects the first chip structure and the substrate, and the second chip structure and the substrate.

14. The packaging method according to claim 11, characterized in that: Before bonding the second chip structure and the first chip structure to the second surface of the interconnection structure board, the packaging method further includes: forming a second interconnection layer electrically connected to the interconnection structure board, the second interconnection layer being located on the first surface of the interconnection structure board at the side of the device chip; In the step of bonding the interconnect structure plate to the substrate, the interconnect structure plate is bonded to the substrate through the second interconnect layer.

15. The packaging method according to claim 14, characterized in that: Before forming an interconnection structure plate electrically connected to the device chip, the method further includes: providing a substrate; The step of forming the second interconnect layer includes: placing the device chip on the substrate; forming the second interconnection layer on the substrate at both sides of the device chip; In the step of forming an interconnection structure plate electrically connected to the device chip, the interconnection structure plate covers the device chip and the second interconnection layer.

16. The packaging method according to claim 15, characterized in that: The step of forming the second interconnect layer on the substrates on both sides of the device chip includes: forming a discrete third interconnect structure on the substrates on both sides of the device chip; forming a packaging layer covering the third interconnect structure and the device chip; The packaging layer and the third interconnection structure that are higher than the top surface of the device chip are removed, and the remaining third interconnection structure and the packaging layer on the substrate at both sides of the device chip are retained as the second interconnection layer.

17. The packaging method according to claim 15, characterized in that: In the step of forming the second interconnect layer, the second interconnect layer is electrically isolated from the device chip.

18. The packaging method according to claim 15, characterized in that: After bonding the second chip structure and the first chip structure to the second surface of the interconnection structure board and before bonding the interconnection structure board to the substrate, the method further includes: removing the substrate; After removing the substrate, forming a first conductive bump on the surface of the second interconnect layer facing away from the interconnect structure board; In the step of bonding the interconnection structure plate to the substrate, the second interconnection layer is electrically connected to the substrate through the first conductive bumps.

19. The packaging method according to claim 18, characterized in that: After bonding the interconnect structure plate to the substrate, the packaging method further includes: forming a first sealing layer between the second interconnect layer and the substrate to fill the gap between the second interconnect layer and the substrate and the gap between adjacent first conductive bumps.

20. The packaging method according to claim 11, characterized in that: In the step of providing the first chip structure, the first chip structure includes a logic chip; in the step of providing the second chip structure, the second chip structure includes one or a plurality of second chips stacked in a longitudinal direction, and the second chip includes a memory chip.

Images