Chip packaging structure, electronic equipment and preparation method of chip packaging structure

Abstract

The invention provides a chip packaging structure, electronic equipment and a preparation method of the chip packaging structure. Relates to the technical field of chip packaging. The chip packaging structure can comprise a carrier plate, a packaging body and at least one bare chip integrated on the carrier plate, the packaging body covers the at least one bare chip, at least one hole is formed in the packaging body, the bottom face and the side face of the hole and at least part of the surface, away from the carrier plate, of the packaging body are covered with shielding layers made of the same material, and the shielding layers are made of the same material. And the shielding layer is connected with the grounding layer in the carrier plate. The shielding layer in the hole, the shielding layer on the wall surface of the packaging body and the grounding layer are utilized to divide the cavity where the bare chip is located into a plurality of areas, so that the resonant frequency of the cavity is improved, the resonant frequency is far away from the working frequency of the chip, and the working frequency band of the chip is protected.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and in particular to a chip packaging structure, an electronic device, and a method for preparing the chip packaging structure. Background Art

[0002] With the improvement of product integration, the integration of multi-channel circuits such as multiple RF signals or multiple microwave signals on PCB boards has increased, resulting in a phenomenon of tight area on PCB boards. As a result, there is a trend of packaging and integrating multiple functional chips.

[0003] For RF or microwave chips, since most of the working scenarios are analog small signal modes, the signals are easily interfered by the outside world, so it is often necessary to add shielding to the chips. Figure 1 , usually a metal shielding layer is formed on the surface of the chip package, and the metal shielding layer is connected with the copper foil on the carrier board to form a cavity, which plays the role of electromagnetic shielding.

[0004] However, the formed cavity is prone to cavity resonance. If the resonance frequency falls within the chip operating frequency band, it will seriously affect the normal operation of the chip, especially for large-size chips, which are more likely to produce cavity resonance. Summary of the invention

[0005] The present application provides a chip packaging structure, an electronic device and a method for preparing the chip packaging structure, with the purpose of suppressing or eliminating cavity resonance and improving the electromagnetic shielding effect on the chip.

[0006] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0007] On the one hand, the present application provides a chip packaging structure, which may be a single-chip package or a multi-chip package.

[0008] The chip packaging structure may include: a carrier, a package body, and at least one bare chip integrated on the carrier, such as one or more bare chips; the at least one bare chip is arranged on one side of the carrier; the package body covers the at least one bare chip; the side surface of the package body and the first surface facing away from the carrier board both have a shielding layer, the carrier board includes a grounding layer, and the shielding layer covering the side surface of the package body is connected to the grounding layer.

[0009] In addition, in the present application, the package has at least one hole, which penetrates from the first surface of the package away from the carrier into the package; and the bottom and side surfaces of the hole and the first surface of the package are at least partially covered by a shielding layer of the same material, such as a metallized shielding layer. By opening a hole in the package and metallizing the inner wall of the hole with the shielding layer, it is equivalent to using the metallized hole to divide the larger shielding cavity surrounded by the shielding layer and the grounding layer on the first surface of the package into multiple smaller shielding cavities. The smaller the size of the shielding cavity, the smaller the resonant wavelength and the higher the resonant frequency, which can keep the resonant frequency away from the operating frequency of the chip, suppress or eliminate the cavity resonance, and protect the chip operating frequency band.

[0010] In one achievable manner, the shielding layer on the bottom surface and the side surface of the hole is connected to the shielding layer on the first surface of the package body to form an integral structure.

[0011] In a feasible process, the shielding layer may be manufactured by a sputtering process, and the first surface of the package body, as well as the bottom and side surfaces of the hole may be covered by the shielding layer at the same time, so as to obtain a continuous and integrated shielding structure.

[0012] The shielding layer with an integrated structure manufactured by the sputtering process can ensure that the bonding force between the shielding layer and the packaging body at different positions is basically consistent, thereby reducing the risk of delamination and falling off of the shielding layer and improving the durability of electromagnetic shielding.

[0013] In one achievable manner, the conductivity of the shielding layer on the bottom surface and the side surface of the hole is equal to the conductivity of the shielding layer on the first surface of the package body.

[0014] The conductivity of the shielding layer in the hole is made equal to the conductivity of the shielding layer on the first surface of the package body, thus improving the shielding effect.

[0015] In one achievable manner, the side surface of the package body is also covered by a shielding layer, and the shielding layer on the side surface of the package body is connected to the shielding layer on the first surface of the package body to form an integral structure.

[0016] For example, a sputtering process may be used to simultaneously form an integrated shielding layer on the bottom and side surfaces of the hole, and the first surface and side surfaces of the package body.

[0017] In addition, in one achievable manner, the material of the shielding layer on the side surface of the package body may be the same as or different from the material of the shielding layer on the first surface of the package body.

[0018] In one achievable manner, the conductivity of the shielding layer on the bottom surface and the side surface of the hole is equal to the conductivity of the shielding layer on the first surface and the side surface of the package body.

[0019] In one achievable manner, the hole passes through the package body to the surface of the carrier board for arranging the package body; or the hole passes through a portion of the package body, and there is a gap between the bottom surface of the hole and the surface of the carrier board.

[0020] That is, in the example of the present application, the hole may or may not penetrate the package body.

[0021] In one achievable manner, a surface of the carrier board for arranging the package body has a ground layer; the hole passes through the package body and is in ohmic contact with the ground layer on the surface of the carrier board.

[0022] When the metallized hole is in direct contact with the ground layer on the surface of the carrier, the upper end of the hole is connected to the ground layer through the shielding layer on the first surface of the package, and the lower end of the hole is also connected to the ground layer, that is, an ohmic contact is formed between the lower end of the hole and the carrier. Compared with a solution without ohmic contact, electromagnetic waves of a specific frequency generated by the chip will be blocked by the ohmic contact structure, especially for electromagnetic interference of bare chips operating at high frequencies, which will suppress the generation of resonant modes.

[0023] In one achievable manner, the hole whose bottom and side surfaces are covered by the shielding layer is also filled with a filling medium; or, the hole whose bottom and side surfaces are covered by the shielding layer is a hollow structure.

[0024] When a filling medium is also filled in the hole whose bottom and side surfaces are covered by the shielding layer, the material of the filling medium can be the same as the material of the shielding layer on the side and bottom surfaces of the hole, or other materials can be selected.

[0025] In one achievable manner, the diameter of the hole gradually decreases from the opening of the hole to the bottom surface of the hole.

[0026] In this way, the hole will not occupy a large area on the carrier, thereby improving the integration of the chip packaging structure.

[0027] In one implementation, the at least one die includes a first die and a second die arranged side by side, and at least one hole is arranged between the first die and the second die.

[0028] The metallized hole is arranged between the first die and the second die. The metallized hole is equivalent to an isolation barrier arranged between the first die and the second die, which can further enhance the electromagnetic shielding effect on the first die and the second die.

[0029] In one achievable manner, the first die and the second die are arranged on the carrier along a first direction; there are a plurality of holes, and the plurality of holes are arranged between the first die and the second die at intervals along a second direction, and the first direction intersects the second direction.

[0030] The first die and the second die are shielded by using a plurality of holes arranged at intervals between the first die and the second die, thereby improving the electromagnetic shielding effect of the first die and the second die.

[0031] In one achievable manner, a hole is provided in a region of the package body located above the first die; and a gap exists between a bottom surface of the hole located above the first die and a top surface of the first die.

[0032] In this implementation structure, a hole is opened above the first bare chip, so that the resonant mode and resonant field of the electromagnetic wave of the first bare chip can be destroyed by the hole, thereby achieving the purpose of suppressing resonance.

[0033] In one implementation, a depth of the hole located above the first die is less than or equal to a depth of the hole located between the first die and the second die.

[0034] In one implementation, the diameter of the hole located above the first die is smaller than or equal to the diameter of the hole located between the first die and the second die.

[0035] In one implementation, a plurality of holes are disposed around the periphery of the first die; and / or a plurality of holes are disposed around the periphery of the second die.

[0036] By utilizing a plurality of shielded holes and arranging the first bare chip and the second bare chip in relatively independent shielding cavities respectively, the electromagnetic shielding effect of the two bare chips can be enhanced.

[0037] In one practicable manner, the shielding layer may be a single-layer structure or a stacked multi-layer structure.

[0038] In one achievable manner, the material of the shielding layer includes at least one of stainless steel, copper, titanium Ti or gold Au. For example, it may be a layer of stainless steel, or a stainless steel layer, a copper layer and a stainless steel layer stacked in sequence, or a Ti layer and an Au layer stacked in sequence.

[0039] On the other hand, the present application also provides a method for preparing a chip packaging structure, the preparation method comprising:

[0040] Disposing at least one bare die on a carrier board;

[0041] Disposing a package body so that the package body covers the at least one bare chip;

[0042] At least one hole is formed on the package body, and the hole penetrates from a first surface of the package body away from the carrier into the package body;

[0043] A shielding layer made of the same material is at least partially formed on the bottom and side surfaces of the hole and the first surface of the package body, and the shielding layer is connected to the grounding layer in the carrier board.

[0044] When the preparation method provided in the present application is adopted, a hole is opened in the package body, and a shielding layer structure is arranged on the bottom and side surfaces of the hole, which is connected to the shielding body on the first surface of the package body. In this way, it is equivalent to using metallized holes to encapsulate the bare chip in multiple small shielding cavities to reduce the resonant wavelength, increase the resonant frequency, suppress or eliminate the cavity resonance, and make the resonant frequency away from the operating frequency of the chip, thereby protecting the chip operating frequency band.

[0045] In one achievable method, when forming a shielding layer, it includes: simultaneously forming a shielding layer on the bottom and side surfaces of the hole and at least partially on the first surface of the package body, so that the shielding layer on the bottom and side surfaces of the hole is connected to the shielding layer on the first surface of the package body to form an integrated structure.

[0046] For example, a sputtering process can be used to produce an integrated shielding layer, which not only simplifies the process but also ensures that the connection strength between the shielding layer and the package body at different positions is basically consistent.

[0047] In one practicable manner, at least one hole is opened on the package body, including:

[0048] At least one hole is formed on the package body, and the hole passes through the package body to the surface of the carrier; or the hole passes through a portion of the package body, and there is a gap between the bottom surface of the hole and the surface of the carrier.

[0049] The large shielding chamber can be divided into a plurality of small shielding chambers by using holes of two different structures.

[0050] In one practicable manner, at least one bare die is arranged on a carrier, including: arranging a first bare die and a second bare die side by side on the carrier;

[0051] At least one hole is formed on the package body, comprising:

[0052] A plurality of holes arranged at intervals are opened between the first die and the second die.

[0053] By opening a hole between two adjacent bare chips, the shielding effect on each of the two bare chips can be further improved.

[0054] In one practicable manner, at least one hole is opened on the package body, including:

[0055] A plurality of holes are opened between the first die and the second die, and an arrangement direction of the plurality of holes intersects with an arrangement direction of the first die and the second die, for example, is perpendicular to the arrangement direction of the first die and the second die.

[0056] On the other hand, the present application also provides an electronic device, which includes a circuit board, and a chip packaging structure of any of the above-mentioned implementation methods, or a chip packaging structure manufactured using the preparation method, and the chip packaging structure is arranged on the circuit board.

[0057] In the electronic device provided in the present application, in the chip packaging structure, the large cavity where the bare chip is located is divided into multiple small cavities by using metallized holes to increase the resonance frequency, thereby suppressing or eliminating the cavity resonance.

[0058] In one practicable manner, the electronic device further includes an electronic device and a shielding cover, the electronic device being arranged on a circuit board, and the electronic device and the chip packaging structure being arranged on the same side of the circuit board; the shielding cover being connected to the circuit board; and the side of the shielding cover facing the circuit board having a first chamber and a second chamber separated from each other, the electronic device being arranged in the first chamber, and the multi-chip packaging structure being arranged in the second chamber.

[0059] By using the cavity isolation method, the electromagnetic shielding effect of the chip can be further improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 It is a structural schematic diagram of a chip packaging structure in the prior art;

[0061] Figure 2 A schematic diagram of a structure including a PCB, a chip packaging structure and a shielding structure in an electronic device provided in an embodiment of the present application;

[0062] Figure 3 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0063] Figure 4 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0064] Figure 5A A schematic structural diagram of a carrier board in a chip packaging structure provided in an embodiment of the present application;

[0065] Figure 5B A schematic diagram of the structure of another carrier board in the chip packaging structure provided in an embodiment of the present application;

[0066] Figure 5C A schematic diagram of the structure of another carrier board in the chip packaging structure provided in an embodiment of the present application;

[0067] Figure 6 A top view of a chip packaging structure provided in an embodiment of the present application;

[0068] Figure 7A top view of a chip packaging structure provided in an embodiment of the present application;

[0069] Figure 8 It is a structural schematic diagram of a chip packaging structure in the prior art;

[0070] Fig. 9 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0071] Fig.10 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0072] Fig.11 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0073] Fig.12 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0074] Fig.13 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0075] Fig.14 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0076] Fig.15 A top view of a chip packaging structure provided in an embodiment of the present application;

[0077] Fig.16 A three-dimensional view of a chip packaging structure provided in an embodiment of the present application;

[0078] Fig.17 A top view of a chip packaging structure provided in an embodiment of the present application;

[0079] Fig.18 A three-dimensional view of a chip packaging structure provided in an embodiment of the present application;

[0080] Fig.19 A top view of a chip packaging structure provided in an embodiment of the present application;

[0081] Fig. 20 A top view of a chip packaging structure provided in an embodiment of the present application;

[0082] Fig.21 A flowchart of a method for preparing a chip packaging structure provided in an embodiment of the present application;

[0083] FIG. 22A to FIG. 22D A schematic diagram of the corresponding structure after each step is completed in the manufacturing process of a multi-chip packaging structure provided in an embodiment of the present application.

[0084] Reference numerals:

[0085] 100-PCB;

[0086] 201-first chamber; 202-second chamber;

[0087] 301-first chip packaging structure; 302-second chip packaging structure;

[0088] 400-shielding cover;

[0089] 500- electrical connection structure;

[0090] 1a-Packaging substrate;

[0091] 1b-Rewiring layer;

[0092] 1c-intermediary layer;

[0093] 111-core material;

[0094] 112-Laminated circuit;

[0095] 113-conductive through hole;

[0096] 114- dielectric layer;

[0097] 1-Carrier board;

[0098] 21-a first bare chip; 22-a second bare chip;

[0099] 3-Package;

[0100] 4-hole; 41-first hole; 42-second hole;

[0101] 5- Shielding layer;

[0102] 61-binding wire; 62-metal bump;

[0103] 7- Conductive silver glue;

[0104] 8-Polymer. DETAILED DESCRIPTION

[0105] The embodiment of the present application provides an electronic device. The electronic device may include a base station, a satellite, a microwave device, an optoelectronic device, a terminal device, a router, a vehicle-mounted device, etc. The embodiment of the present application does not impose any special restrictions on the specific form of the above electronic device.

[0106] In an electronic device such as the above example, Figure 2As shown, a circuit board 100, such as a printed circuit board (PCB), can be included. Electronic devices can be integrated on the circuit board 100. For example, a first chip packaging structure 301 and a second chip packaging structure 302 are integrated on the circuit board 100. The chip packaging structure can be electrically connected to the circuit board 100 through an electrical connection structure 500, so that the chip packaging structure can realize signal interconnection with other chips or other electronic devices on the circuit board 100.

[0107] In an alternative embodiment, the electrical connection structure 500 may include a plurality of solder balls, such as a ball grid array (BGA), or a plurality of metal pillars.

[0108] For example Figure 2 As shown, the electronic device may further include a shielding cover 400, which is disposed on the circuit board 100, and the electronic components on the circuit board 100 are disposed in a receiving cavity formed by the shielding cover 400 and the circuit board 100. The shielding cover 400 here can not only play an electromagnetic shielding role, but also play a heat dissipation and temperature reduction role.

[0109] In order to avoid external interference of the signal, Figure 2 The structure shown is subjected to chamber isolation treatment, for example, an isolation plate can be provided on the side of the shielding cover 400 facing the circuit board 100 to form a first chamber 201 for accommodating the first chip packaging structure 301, and a second chamber 202 for accommodating the second chip packaging structure 302. In this way, electromagnetic interference from the outside to the first chip packaging structure 301 and the second chip packaging structure 302 can be resisted.

[0110] In some other examples, multiple electronic devices may be placed in the same chamber without the need for chamber isolation.

[0111] The chip packaging structure of the example of this application may include a radio frequency chip or a microwave chip, or chips with other functions, such as a digital chip. As the product integration increases further, multi-channel circuits such as multi-radio signals or multi-microwave signals emerge, and these multiple chips can be packaged on the same carrier.

[0112] Then, the mutual interference between these radio frequency or microwave signals becomes more prominent, and it is necessary to set a shielding structure in the chip packaging structure. The examples of this application give some shielding structures, which can increase the isolation between the circuit in the packaging carrier and the outside world, improve the ability to resist electromagnetic wave interference, and suppress cavity resonance. The specific shielding structures that can be implemented are shown below.

[0113] Figure 3 and Figure 4Some chip packaging structures of the present application are exemplified, and the chip packaging structure includes at least one bare chip. Figure 3 In this example, a bare chip 2 is placed on a carrier board 1. Figure 4 In the example, a plurality of bare chips are disposed on the carrier 1 , and the plurality of bare chips are located on the same side of the carrier 1 . Figure 4 By way of example, it is shown that a first die 21 and a second die 22 are integrated on the carrier 1 .

[0114] Figure 3 and Figure 4 This is only an exemplary structure, and more bare chips, such as three or four, may be arranged on the carrier board 1. Such a packaging structure may be referred to as a multi-chip packaging structure.

[0115] The embodiment of the present application relates to a bare chip integrated on a carrier board 1, which may be a single bare chip or a plurality of bare chips stacked in three dimensions. For example, Figure 4 The first die 21 in the figure may refer to one die, and the second die 22 may include a plurality of die stacked in three dimensions. The three-dimensional stacking here refers to stacking in a direction perpendicular to the carrier 1 .

[0116] Figure 3 and Figure 4 An exemplary die may be a chip that is cut from a wafer but not packaged.

[0117] Figure 3 and Figure 4 There are multiple electrical connection modes between the bare chip and the carrier 1, for example, Figure 4 In the embodiment, the first bare chip 21 can be electrically connected to the carrier board 1 through a bonding wire 61. For example, the bonding wire can include but is not limited to gold wire, silver wire, copper wire, aluminum wire, etc.; or, the second bare chip 22 can be electrically connected to the carrier board 1 through a metal bump 62.

[0118] The carrier board 1 involved in the present application has a variety of achievable structures.

[0119] For example, the carrier 1 may be a wafer.

[0120] As another example, the carrier board 1 may be Figure 5A The package substrate 1 a shown includes a core material 111 and a laminated circuit 112 located on the upper surface of the core material 111 .

[0121] As another example, the carrier board 1 may be Figure 5BThe redistribution layer (RDL) 1b made by the redistribution process is shown, and RDL1b includes one or more layers of metal wiring and multiple dielectric layers, and each two adjacent layers of metal wiring are separated by a dielectric layer. In order to electrically connect the metal wirings on different layers, a conductive channel can be made in the dielectric layer so that the metal wirings on different layers are electrically connected through the conductive channel. When RDL1b is used as a carrier, the flexibility can also be improved and the warping degree of the package can be suppressed.

[0122] As another example, the carrier board 1 may be Figure 5C An interposer 1c is shown, and the interposer 1c includes a dielectric layer 114, a redistribution layer 1b integrated on the dielectric layer 114, and a conductive via 113 penetrating the dielectric layer 114, wherein the conductive via 113 is electrically connected to the redistribution layer 1b.

[0123] exist FIG. 5A to FIG. 5C In the example carrier board 1, there may be a ground layer (also called a GND plane). Return to Figure 3 and Figure 4 The ground layer 11 in the carrier board 1 can be one layer, two layers, or more layers stacked in the carrier board 1 .

[0124] See you next time Figure 3 and Figure 4 The chip packaging structure further includes a packaging body 3, which covers the bare chips integrated on the carrier board 1. For example, the first bare chip 21 and the second bare chip 22 are covered by the packaging body 3, thereby protecting the bare chips.

[0125] like Figure 3 When the bare chip 2 of the example is working, it may affect other electronic devices arranged on the carrier board 1, such as inductors, capacitors or resistors, due to electromagnetic interference, and may also affect the Figure 3 In addition to the structure shown, other circuits or chips on the electronic device system, or other circuits or chips on the system may interfere with the bare die 2.

[0126] Figure 4 The RF first die 21 or the microwave second die 22 in the example, since the working scenes are basically analog small signal modes, the signals are easily interfered by the outside world, or the first die 21 and the second die interfere with each other.

[0127] Therefore, in Figure 3 and Figure 4 The example also includes a shielding structure for electromagnetically shielding the bare die. The shielding structure is described in detail below.

[0128] like Figure 3 and Figure 4The package body 3 has at least one hole 4 therein, and the hole 4 penetrates from the first surface of the package body 3 away from the carrier 1 into the package body 3, or, in some examples, it can be understood that: the hole 4 is opened in the package body 3 along the thickness direction of the package body 3.

[0129] The bottom and side surfaces of the hole 4 and at least part and side surfaces of the first surface of the package body 3 are covered by the shielding layer 5, and the shielding layer 5 is connected to the grounding layer 11. For example, the shielding layer 5 may be provided on the entire first surface of the package body 3, or may be provided on part of the first surface.

[0130] When the hole 4 is not provided in the package body 3, the shielding layer 5 located on the first surface and the side surface of the package body 3 can enclose a larger cavity with the grounding layer 11, and the first bare chip 21 and the second bare chip 22 are packaged in the larger cavity, based on the following formula for the resonance wavelength λ of the cavity:

[0131]

[0132] In the above formula: a, b, l represent the length, width and height of the cavity respectively; m, n, p represent the resonant mode respectively, ε r represents the relative dielectric constant of the package 3 material).

[0133] As shown in the above formula, when the dimensions a, b, and l of the cavity are large, the resonant wavelength λ of the cavity is large and the resonant frequency f is low. In this way, the cavity can resonate at low frequencies.

[0134] In this application, if Figure 3 and Figure 4 A hole 4 is formed in the package body 3, and a shielding layer 5 is provided on the bottom and side surfaces of the hole 4, and the shielding layer 5 is connected to the shielding layer 5 on the wall surface of the package body 3. Figure 3 and Figure 4 By using the holes treated with the metal shield, a larger cavity can be divided into at least two smaller cavities.

[0135] According to the above formula, when the size of the cavity decreases, the resonant wavelength λ of the cavity decreases, and the resonant frequency f increases, and resonance will only occur at a relatively high frequency. For example, when the operating frequency of the first die or the second die in the chip packaging structure is around the 4G frequency band, if the cavity is a large cavity, the chip packaging structure may resonate at 2G, then, resonance will occur in the frequency band range above 2G, so that the first die and the second die are subject to electromagnetic interference, which will affect the working performance of the die. However, when the present application divides the large cavity into small cavities through holes, the cavity resonance and self-excitation can be eliminated. For example, the resonant frequency can be increased from the 2G frequency band to the 5G frequency band, and the resonant frequency can be kept away from the 4G operating frequency of the two dies, which is equivalent to eliminating the cavity resonance of the working frequency band and its accessories, thereby playing a role in protecting the working frequency band.

[0136] In addition, when the hole 4 is not provided in the package 3, the electromagnetic waves generated by the first die and the second die oscillate back and forth in the larger cavity, and the electromagnetic waves radiated by the die and the electromagnetic waves reflected by the cavity may be superimposed, and at a certain phase, the peaks are superimposed, and the troughs are superimposed, the oscillation is strengthened, and the anti-interference ability is poor. However, when the hole 4 is provided in the package 3, the shielded hole 4 will destroy the superposition of the electromagnetic waves radiated by the die and the reflected waves, that is, the hole 4 can locally destroy the resonant mode and resonant field of the electromagnetic waves, thereby achieving the purpose of suppressing resonance.

[0137] The small cavity described in the examples of the present application can be understood as: not a completely closed cavity, but rather a larger cavity is divided into multiple areas using these holes to reduce the length, width and height of the larger cavity.

[0138] Figure 6 and Figure 7 , which exemplarily shows the position of hole 4. Figure 6 In the embodiment, the hole 4 is opened between the first die 21 and the second die 22. Figure 7 In the embodiment, the hole 4 may be provided between the first die 21 and the second die 22 , or the hole 4 may be provided at other locations around the first die 21 and the second die 22 .

[0139] For example, in some scenarios, the resonance point of the chip packaging structure is at Figure 6 When the chip package structure is at position A shown in FIG. 1 , a hole 4 may be provided at position A. In other scenarios, the resonance point of the chip package structure is as follows: Figure 7 When the B position is shown, a hole 4 can be set at the B position.

[0140] No matter where the hole 4 is opened in the package body 3, the bare chip can be integrated into a plurality of divided smaller cavities by using the metallized hole, so as to effectively play the role of electromagnetic shielding and suppress or eliminate the self-excitation of the cavity.

[0141] In some examples, such as Figure 3 and Figure 4 The material of the bottom and side surfaces of the hole 4 and the shielding layer 5 on the first surface of the package body 3 is the same, and the material of the shielding layer 5 on the side surfaces of the package body 3 is different from that of the bottom and side surfaces of the hole 4 and the shielding layer 5 on the first surface of the package body 3.

[0142] In some other examples, the material of the bottom surface and the side surface of the hole 4 and the shielding layer 5 on the first surface and the side surface of the package body 3 are the same.

[0143] In a feasible process step, metal can be sputtered on the first surface of the package body 3, the bottom and the side of the hole 4, so that the shielding layer 5 on the first surface of the package body 3, the bottom and the side of the hole 4 are connected to form an integral structure; and another metal is sputtered on the side of the package body 3.

[0144] In another possible process step, sputtering can be used, see Figure 3 and Figure 4 , metal can be sputtered on the first surface and side of the package body 3, and the metal will cover the bottom and side of the hole 4, and connect with the metal on the first surface of the package body 3, and connect with the ground layer of the carrier 1. In this way, the shielding layer 5 located in the hole 4 is connected with the shielding layer 5 located on the first surface and side of the package body 3 to form an integrated structure.

[0145] Alternatively, in some process steps, the shielding layer 5 may be manufactured by electroplating, chemical plating or other process means.

[0146] The shielding layer 5 in the example of the present application can be a single-layer structure or a stacked multi-layer structure, for example, a stainless steel layer, or a stainless steel layer, a copper layer and a stainless steel layer stacked in sequence, or a stacked Ti layer and Au layer.

[0147] When the material of the bottom and side surfaces of the hole 4 and the shielding layer 5 on the first surface of the package body 3 is the same as that of the shielding layer 5 on the side surfaces of the package body 3, the shielding layer 5 on the bottom and side surfaces of the hole 4 and the first surface of the package body 3 can be one layer, and the shielding layer 5 on the side surfaces of the package body 3 can be multiple layers.

[0148] Alternatively, the bottom and side surfaces of the hole 4 and the shielding layer 5 on the first surface of the package body 3 may be multiple layers, and the shielding layer 5 on the side surfaces of the package body 3 may be single layer.

[0149] In some prior arts, such as Figure 8 As shown, a trench can be made in the package body 3 by a laser trenching process, and then a conductive silver paste 7 is applied in the trench, and finally a shielding layer 5 is made.

[0150] exist Figure 8 In the shielding structure shown, the materials of the conductive silver glue 7 and the shielding layer 5 are different, and the adhesion between the conductive silver glue 7 and the package body 3 is different from the adhesion between the shielding layer 5 and the package body 3. Delamination may occur between the conductive silver glue 7 and the package body 3, and the conductive silver glue 7 may also break with the shielding layer 5, which may easily cause the electromagnetic shielding effect to degrade or fail.

[0151] In this application example Figure 3 and Figure 4 The material of the shielding layer 5 filled in the hole 4 is the same as the material of the shielding layer 5 arranged on the first surface of the package body 3, so that at various positions of the package body 3, the bonding strength between the shielding layer 5 and the package body 3 is basically consistent, and there is basically no delamination or breakage, thereby improving the durability of the shielding structure.

[0152] In addition, the shielding layer 5 located in the hole 4 and the shielding layer 5 located on the first surface of the package body 3 are an integrally formed structure, which not only simplifies the preparation process steps but also improves the reliability of the shielding structure.

[0153] Except, in the present application, the conductivity of the shielding layer 5 located in the hole 4 is equal to the conductivity of the shielding layer 5 located on the first surface of the package body 3; Figure 8 In the present invention, the conductivity of the conductive silver paste 7 is low and the shielding effect is poor. Therefore, the present application can further improve the shielding effect.

[0154] See you next time Figure 8 In this technology, since the conductivity of the conductive silver paste 7 is poor, the capacity of the conductive silver paste 7 can be increased by increasing the width of the groove. In this way, a larger groove will occupy a larger area on the carrier board, affecting the integration of multiple chips.

[0155] However, in the example of this application Figure 3 and Figure 4 In the embodiment, since the shielding layer 5 in the hole 4 is made of the same material as the shielding layer 5 on the first surface of the package body 3 and has a higher conductivity, the hole 4 does not need to occupy a large area on the carrier 1. For example, in one example, Figure 3 and Figure 4 , the aperture of hole 4 gradually decreases from the opening to the bottom of hole 4, that is, the closer to carrier 1, the smaller the aperture size of hole 4, and the orthographic projection area on carrier 1 becomes smaller and smaller, which can reduce the area occupied on carrier 1, thereby improving the integration of the chip.

[0156] exist Figure 8 In the structure shown, the preparation process is also relatively complicated. After the groove is opened, the conductive silver glue 7 is first applied, and then the shielding layer 5 is prepared. In the example of the present application, the shielding layer 5 can be prepared in the hole 4 and on the first surface of the package body 3 at the same time. The molding process of the shielding layer 5 is simple and the manufacturing cost is low.

[0157] In some examples that can be implemented, such as Fig. 9 , the bottom and side surfaces of the hole 4 are covered by the shielding layer 5, and the remaining space can be empty and does not need to be filled with other materials. In other examples that can be implemented, such as Fig.10 , the shielding layer 5 can fill the hole 4, or, as Fig.11 , a shielding layer 5 can be used to cover the bottom and side surfaces of the hole 4, and the remaining space can be filled with other filling medium materials, such as a polymer 8.

[0158] The hole 4 provided in the embodiment of the present application has at least two structures. Fig.12 In the figure, the holes include a first hole 41 and a second hole 42 with different structures. The first hole 41 penetrates the package body 3 to the surface of the carrier 1 for carrying the first bare chip 21 and the second bare chip 22, that is, the first hole 41 penetrates to the upper surface of the carrier 1, and such a hole can be called a through hole (Through Molding Via, TMV) on the plastic package; the second hole 42 penetrates a part of the package body 3, that is, there is a gap between the bottom surface of the second hole 42 and the surface of the carrier 1, and such a hole can be called a hole (Molding Via, MV) on the plastic package.

[0159] Whether Fig.12 The exemplary structure is a first hole 41 that is a through hole or a second hole 42 that is a blind hole. The bottom and side surfaces of these holes are covered by the shielding layer 5 and connected to the shielding layer 5 located on the wall surface of the package body 3 .

[0160] Fig.13 is a schematic diagram of another chip packaging structure provided in an embodiment of the present application. Fig.12 In comparison, Fig.12 In the embodiment, a first hole 41 having a through hole structure and a second hole 42 having a blind hole structure are included. Fig.13 In the figure, the holes are all second holes 42 with a blind hole structure.

[0161] like Fig.12 and Fig.13 In some examples, a hole may be opened at a position of the package body 3 above the die, for example, Fig.12 and Fig.13In the embodiment, a second hole 42 may be opened above both the first die 21 and the second die 22 , and a gap exists between the bottom surface of the second hole 42 and the surface of the die.

[0162] In some examples, when there is a hole between the first die 21 and the second die 22 and there is a hole above the first die 21 , the depth of the hole above the first die 21 may be less than or equal to the depth of the hole between the first die 21 and the second die 22 .

[0163] In the example of the present application, the aperture of the hole located above the first die 21 may be smaller than, equal to, or larger than the aperture of the hole between the first die 21 and the second die 22 .

[0164] Fig.14 1 is a schematic diagram of another chip packaging structure provided by an embodiment of the present application. In this example, the surface of the carrier 1 for carrying the first bare chip 21 and the second bare chip 22 has a grounding layer 11, the first hole 41 passes through the package body 3 to the grounding layer 11, and the shielding layer 5 on the bottom surface of the first hole 41 is in ohmic contact with the grounding layer 11.

[0165] Fig.14 In the example, the shielding layer 5 on the side of the first hole 41 is connected to the ground layer 11 through the shielding layer 5 on the wall of the package body 3, and the shielding layer 5 on the bottom of the first hole 41 is also in contact with the ground layer 11. It can be understood that there is no gap between the bottom end of the first hole 41 and the carrier 1 for electromagnetic waves to pass through, which can suppress the generation of resonant modes.

[0166] In some other examples, the ground layer 11 may not be disposed on the surface of the carrier 1 , but may be stacked inside the carrier 1 , and the first hole 41 passes through the package body 3 to the surface of the carrier 1 .

[0167] In some examples, there are multiple holes in the package body 3, and the structures and layouts of the multiple holes are in various forms. Several examples that can be implemented are given below, which are described in detail as follows:

[0168] like Fig.15 and Fig.16 , Fig.15 It shows the top view of the chip packaging structure. Fig.16 In this example, a first die 21, a second die 22, a third die 23 and a fourth die 24 are provided on a carrier 1. A plurality of holes 4 can be provided between each two adjacent die. For example, the first die 21 and the second die 22 are provided along a first direction (such as Fig.15 The third die 23 and the fourth die 24 are arranged along the first direction (eg, Fig.15 The first die 21 and the third die 23 are arranged along the second direction (eg, Fig.15 The second die 22 and the fourth die 24 are arranged along the second direction (such as Fig.15 The plurality of holes arranged between the first die 21 and the second die 22 are arranged at intervals along the Y direction, and the plurality of holes arranged between the first die 21 and the third die 23 are arranged at intervals along the X direction. The plurality of holes arranged in a cross pattern are used to divide the cavity into four cavities, and a die is arranged in each cavity.

[0169] exist Fig.15 and Fig.16 In the example, all of the holes 4 may be through holes; or, some may be through holes and some may be blind holes; or, all may be blind holes.

[0170] like Fig.17 and Fig.18 , Fig.17 It shows the top view of the chip packaging structure. Fig.18 The three-dimensional structure diagram is shown. Fig.15 and Fig.16 Compared with the example, in this embodiment, in addition to opening a plurality of first holes 41 arranged at intervals between each two adjacent dies, blind second holes 42 may also be opened. These second holes 42 may be opened above the die or around the die.

[0171] like Fig.19 , Fig.19 The top view of the chip packaging structure is shown. The holes between two adjacent dies may not be arranged in a straight line. Fig.19 In the scattered and irregular arrangement shown in FIG. 1 , the hole between two adjacent bare chips may be a second hole 42 of a blind hole or a first hole 41 of a through hole structure; in addition, Fig.19 In the embodiment, the second holes 42 of the blind hole structure may also be opened at other positions, and the positions of the second holes 42 are not particularly limited.

[0172] In the above examples, the cross-sectional shape of the hole 4 opened in the package body 3 is circular. In other examples, such as Fig. 20 The cross-sectional shape of the hole 4 may also be a square or a rectangle.

[0173] The present application also provides a method for preparing a chip packaging structure. Fig.21 As shown, Fig.21 A flowchart of a method for preparing a chip packaging structure is exemplarily shown, wherein the preparation method comprises:

[0174] S1: Arrange at least one bare chip on a carrier board.

[0175] In some process steps, more bare dies may be arranged on the carrier, and some bare dies may be stacked on the carrier in a three-dimensional structure.

[0176] S2: Arrange a package body so that the package body covers the at least one bare chip.

[0177] The package body may be a plastic packaging material or other selectable materials.

[0178] S3: opening at least one hole on the package body, the hole penetrating from a first surface of the package body away from the carrier into the package body;

[0179] S4: A shielding layer made of the same material is at least partially formed on the bottom and side surfaces of the hole and the first surface of the package body, and the shielding layer is connected to the ground layer in the carrier board.

[0180] The specific process flow involved in the preparation method of the above chip packaging structure is introduced below in conjunction with the accompanying drawings.

[0181] FIG. 22A to FIG. 22D The process structure after each step of the process of preparing a multi-chip packaging structure according to an embodiment of the present application is given.

[0182] like Fig.22A As shown, the first die 21 and the second die 22 are disposed on the carrier 1 , and the first die 21 and the second die 22 are arranged side by side on the carrier 1 .

[0183] In some examples, there is a gap between the first die 21 and the second die 22 .

[0184] like Fig.22A The carrier board 1 has a grounding layer 11 , and the grounding layer 11 can be formed on the surface of the carrier board 1 , or can be stacked inside the carrier board 1 .

[0185] In this example, there may be many ways to electrically connect the first die 21 and the second die 22 to the carrier 1, which are not particularly limited in this application.

[0186] like Fig. 22B As shown, a package body 3 is manufactured, and the package body 3 may be a molding body, and the first die 21 and the second die 22 are wrapped inside the molding body.

[0187] like Fig. 22C As shown, at least one hole 4 is opened in the packaging body 3 .

[0188] For example, laser vias may be made by laser technology. Some of these laser vias may penetrate the package 3 to the surface of the carrier 1 , and some may penetrate a portion of the package 3 .

[0189] The hole may be opened between the dies, the hole may be opened above the die, or the hole may be opened at other positions around the die.

[0190] like Fig.22D As shown, a layer of metal can be sputtered by magnetron sputtering. This step mainly uses metal to form a continuous shielding layer 5 on the bottom and side of the hole 4 and the surface and side of the package body 3, so that the shielding layer 5 is in contact with the grounding layer 11 in the carrier 1.

[0191] use FIG. 22A to FIG. 22D When a multi-chip package structure is obtained by the example method, the position, depth and aperture of the hole can be determined according to the resonance point position, resonance wavelength, resonance frequency, etc. of the package structure. In this way, by using the metallized holes, a large-sized cavity can also be divided into multiple small cavities to reduce the resonance wavelength and increase the resonance frequency, so that the resonance frequency is far away from the working frequency of the chip to play an electromagnetic shielding role. Especially for large-sized chip package structures, the electromagnetic shielding effect is better.

[0192] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0193] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip packaging structure, characterized in that: include: A carrier board, including a ground plane; at least one bare chip and a package, wherein the at least one bare chip is disposed on one side of the carrier, and the package covers the at least one bare chip; at least one hole, the hole extending from a first surface of the package body away from the carrier into the package body; The bottom surface and the side surface of the hole and the first surface of the package body are at least partially covered by a shielding layer made of the same material, and the shielding layer is connected to the ground layer.

2. The chip packaging structure according to claim 1, characterized in that: The shielding layer on the bottom surface and the side surface of the hole is connected with the shielding layer on the first surface of the package body to form an integrated structure.

3. The chip packaging structure according to claim 1 or 2, characterized in that: The conductivity of the shielding layer on the bottom and side surfaces of the hole is equal to the conductivity of the shielding layer on the first surface of the package body.

4. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The side surface of the package body is also covered by a shielding layer, and the shielding layer on the side surface of the package body is connected with the shielding layer on the first surface of the package body to form an integral structure.

5. The chip packaging structure according to any one of claims 1 to 4, characterized in that: The hole passes through the package body and reaches the surface of the carrier board for arranging the package body; or, The hole passes through a portion of the package body, and a gap exists between a bottom surface of the hole and a surface of the carrier board.

6. The chip packaging structure according to any one of claims 1 to 5, characterized in that: The surface of the carrier board for arranging the package body has the ground layer; The hole passes through the package body and is in ohmic contact with the ground layer on the surface of the carrier.

7. The chip packaging structure according to any one of claims 1 to 6, characterized in that: The hole whose bottom and side surfaces are covered by the shielding layer also has a filling medium; or, The hole, whose bottom and side surfaces are covered by the shielding layer, is in a hollow structure.

8. The chip packaging structure according to any one of claims 1 to 7, characterized in that: The area of ​​the package body located above the die is provided with the hole; A bottom surface of the hole located above the die has a spacing from a top surface of the die.

9. The chip packaging structure according to any one of claims 1 to 8, characterized in that: The at least one die includes a first die and a second die disposed side by side, and at least one hole is disposed between the first die and the second die.

10. The chip packaging structure according to claim 9, characterized in that: The first die and the second die are arranged on the carrier along a first direction; There are a plurality of holes, and the plurality of holes are arranged between the first die and the second die at intervals along a second direction, and the first direction intersects with the second direction.

11. The chip packaging structure according to claim 9 or 10, characterized in that: The area of ​​the package body located above the first die is provided with the hole; A depth of the hole located above the first die is less than or equal to a depth of the hole located between the first die and the second die.

12. The chip packaging structure according to any one of claims 1 to 11, characterized in that: The hole diameter gradually decreases from the opening of the hole to the bottom surface of the hole.

13. The chip packaging structure according to any one of claims 1 to 12, characterized in that: The material of the shielding layer includes at least one of copper, titanium, gold and stainless steel.

14. A method for preparing a chip packaging structure, characterized in that: The preparation method comprises: Disposing at least one bare die on a carrier board; Disposing a package body so that the package body covers the at least one bare chip; At least one hole is formed on the package body, and the hole penetrates from a first surface of the package body away from the carrier into the package body; A shielding layer made of the same material is at least partially formed on the bottom surface and the side surface of the hole and the first surface of the package body, and the shielding layer is connected to the grounding layer in the carrier board.

15. The method for preparing a chip packaging structure according to claim 14, characterized in that: When forming the shielding layer, it includes: The shielding layer is formed at least partially on the bottom and side surfaces of the hole and the first surface of the package body at the same time, so that the shielding layer on the bottom and side surfaces of the hole is connected with the shielding layer on the first surface of the package body to form an integrated structure.

16. The method for preparing a chip packaging structure according to claim 14 or 15, characterized in that: Opening at least one hole on the package body comprises: At least one hole is formed on the package body, and the hole passes through the package body and reaches the surface of the carrier board; or The hole passes through a portion of the package body, and a gap exists between a bottom surface of the hole and a surface of the carrier board.

17. An electronic device, characterized in that: include: Circuit board; The chip packaging structure according to any one of claims 1 to 13, or a chip packaging structure obtained by the method for preparing a chip packaging structure according to any one of claims 14 to 16; Wherein, the chip packaging structure is arranged on the circuit board.

18. The electronic device according to claim 17, characterized in that: The electronic device further comprises: An electronic device, wherein the electronic device is arranged on the circuit board, and the electronic device and the chip packaging structure are arranged on the same side of the circuit board; A shielding cover connected to the circuit board; The shielding cover has a first chamber and a second chamber separated from each other on one side facing the circuit board. The electronic device is arranged in the first chamber, and the chip packaging structure is arranged in the second chamber.

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