Chip carrier, lead frame and packaging device

Abstract

The invention relates to the technical field of chip packaging, and discloses a chip carrier, a lead frame and a packaging device.The chip carrier comprises a base island, a first type of pins and a second type of pins; the first type of pins are positioned on the outer side of the base island and are directly connected with the base island; the second type of pins are located on the outer side of the base island and are spaced from the base island; the back surfaces of the edge areas of the base island, the first type of pins and the second type of pins are all first concave areas, the base island and the first concave areas of the first type of pins form a continuous integral area, and the first concave areas are formed on the back surface of the chip carrier through a local thinning process. For a packaging device using the chip carrier, when an operator contacts the back surface of an exposed base island in the packaging device to introduce static electricity, the static electricity can be transmitted to an electrostatic protection area of a chip through the chip carrier, and the electrostatic protection area can release the static electricity, so that an internal circuit of the chip is effectively protected from being damaged by the static electricity, and the service life of the chip is prolonged. And failure of the packaging device due to static electricity is avoided.

Description

Technical Field

[0001] The present disclosure relates to the technical field of chip packaging, for example, to a chip carrier, a lead frame and a packaging device. Background Art

[0002] In the chip packaging process, the bare die is usually fixed to the base island of the chip carrier, and then the pads on the bare die are connected to the corresponding pins on the chip carrier through bonding wires. Finally, the bare die, chip carrier and leads are wrapped with packaging materials to form the final packaged device.

[0003] In the related art, there is usually no electrical connection between the base island and the pins in the chip carrier. Although this design simplifies the manufacturing process and reduces costs, it brings significant electrostatic protection risks in practical applications. Specifically, during the packaging test process, if the operator accidentally touches the back of the exposed base island in the packaged device, static electricity may be introduced. Static electricity can be directly transmitted to the back of the die through the base island, and eventually break through to the circuit area on the front of the die, causing the packaged device to fail. This situation not only affects the quality of the packaged device, but also increases the scrap rate and subsequent maintenance costs in the production process.

[0004] Therefore, the packaging design of the related art has obvious deficiencies in electrostatic protection. In particular, when operators touch the packaged device, static electricity can easily be transmitted to the internal circuit of the die through the large exposed base island, causing irreversible damage. This not only reduces the reliability of the product, but also increases the cost burden of the manufacturer.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0007] The chip carrier, lead frame and packaging device provided by the present disclosure can significantly improve the electrostatic protection capability of the packaging device and reduce the risk of failure of the packaging device caused by static electricity.

[0008] According to a first aspect of the present disclosure, a chip carrier is provided, the chip carrier comprising a base island, a first type of pins and a second type of pins;

[0009] The first type of pins are located outside the base island and are directly connected to the base island;

[0010] The second type of pins are located outside the base island and spaced apart from the base island;

[0011] The back sides of the edge areas of the base island, the first type of pins and the second type of pins are all first recessed areas, and the first recessed areas of the base island and the first type of pins form a continuous overall area, wherein the first recessed area is formed on the back side of the chip carrier through a local thinning process.

[0012] In some embodiments, the first recessed area corresponding to the first type of pins partially surrounds the first type of pins to form an incompletely closed arc structure.

[0013] In some embodiments, the first recessed area corresponding to the second type of pins partially surrounds the second type of pins to form an incompletely closed arc structure.

[0014] In some embodiments, a second recessed area is disposed on the front side of the first type of pins, the first recessed area does not overlap with the second recessed area, and the second recessed area is formed on the front side of the chip carrier through a local thinning process.

[0015] In some embodiments, a second recessed area is disposed on the front side of the second type of pins, and the first recessed area does not overlap with the second recessed area, wherein the second recessed area is formed on the front side of the chip carrier by a local thinning process.

[0016] In some embodiments, the first recessed area corresponding to the base island completely surrounds the base island to form a complete annular structure.

[0017] In some embodiments, the local thinning process includes any one of the following: half etching, milling, grinding, stamping, and laser processing.

[0018] According to a second disclosed aspect, a lead frame is provided, the lead frame comprising a plurality of chip carriers provided by the first aspect of the present disclosure.

[0019] According to a third aspect disclosed, a packaged device is provided, the packaged device comprising a bare die, a packaging material, and a chip carrier provided by the first aspect of the present disclosure;

[0020] The back side of the bare chip is attached to the front side of the base island in the chip carrier, and the pads of the bare chip are connected to the front sides of the corresponding first type pins and second type pins in the chip carrier through bonding wires;

[0021] The packaging material covers the front sides of the bare die and the chip carrier and fills each first recessed area of ​​the chip carrier. The packaging material on the back side of the chip carrier is flush with the back side of the chip carrier.

[0022] In some embodiments, the packaging material fills each second recessed area of ​​the chip carrier.

[0023] The chip carrier, lead frame and packaging device provided by the embodiments of the present disclosure can achieve the following technical effects:

[0024] For a packaged device using the chip carrier provided by the embodiment of the present disclosure, when an operator touches the back of the exposed base island in the packaged device and introduces static electricity, since the first type of pin is directly connected to the base island, the static electricity can be transmitted to the first type of pin, and then continue to be transmitted to the pad of the bare chip through the welding wire of the first type of pin, and finally the static electricity is transmitted to the electrostatic protection area of ​​the chip through this pad, and the electrostatic protection area can release static electricity, thereby effectively protecting the internal circuit of the chip from static electricity damage and avoiding the failure of the packaged device due to static electricity. The chip carrier provided by the embodiment of the present disclosure significantly improves the electrostatic protection capability of the packaged device through the optimized electrostatic transmission path, reduces the failure risk of the packaged device caused by static electricity, thereby improving the overall quality and market competitiveness of the packaged device. Moreover, by forming the first recessed area of ​​the base island and the first type of pin into a continuous overall area, it can be ensured that the functional test equipment and method for testing the packaged device do not need to be adjusted due to design changes, and the related fixtures required by subsequent customers do not need to be changed to adapt to the new design, maintaining good compatibility and consistency.

[0025] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0027] Figure 1 is a front schematic diagram of a chip carrier provided by an embodiment of the present disclosure;

[0028] Figure 2 is a schematic diagram of the back side of a chip carrier provided by an embodiment of the present disclosure;

[0029] Figure 3 The embodiment of the present disclosure provides Figure 2 The cross-section diagram of the middle A;

[0030] Figure 4 The embodiment of the present disclosure provides Figure 1 The cross-section diagram of the middle B;

[0031] Figure 5 is a front schematic diagram of a lead frame provided by an embodiment of the present disclosure;

[0032] Figure 6is a schematic diagram of a process for preparing a packaged device provided by an embodiment of the present disclosure;

[0033] Figure 7 is a front schematic diagram of a packaging device provided by an embodiment of the present disclosure;

[0034] Figure 8 is a perspective view of the front side of a packaging device provided by an embodiment of the present disclosure;

[0035] Fig. 9 is a schematic diagram of the back side of a packaging device provided by an embodiment of the present disclosure;

[0036] Fig.10 It is a side schematic diagram of a packaging device provided by an embodiment of the present disclosure.

[0037] Reference numerals:

[0038] 100 chip carriers;

[0039] 1 base island, 2 first type pin, 3 second type pin;

[0040] 101 a first recessed area, 102 a second recessed area;

[0041] 200 bare chips, 300 packaging materials, 400 lead frames, 500 bonding wires;

[0042] 1000 packaged devices. DETAILED DESCRIPTION

[0043] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0044] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0045] In the embodiments of the present disclosure, the terms "upper", "lower", "inside", "middle", "outside", "front", "back" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings. These terms are mainly intended to better describe the embodiments of the present disclosure and their embodiments, and are not intended to limit the indicated devices, elements or components to have a specific direction, or to be constructed and operated in a specific direction. Moreover, in addition to being used to indicate directions or positional relationships, some of the above terms may also be used to indicate other meanings. For example, the term "upper" may also be used to indicate a certain dependency or connection relationship in certain circumstances. For those of ordinary skill in the art, the specific meanings of these terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0046] In addition, the terms "set", "connected", and "fixed" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present disclosure can be understood according to specific circumstances. In the embodiments of the present disclosure, the communication connection includes an electrical connection for realizing the transmission of electrical signals, and also includes an optical fiber connection for realizing the transmission of optical signals. Without violating the inventive concept of the embodiments of the present disclosure, the communication connection can be a wired connection or a wireless connection.

[0047] Unless otherwise stated, the term "plurality" means two or more.

[0048] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0049] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0050] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.

[0051] The embodiment of the present disclosure provides a chip carrier 100 , and the material of the chip carrier 100 is a conductive material, such as copper, copper alloy, iron-nickel alloy or aluminum. Figure 1 is a front schematic diagram of the chip carrier 100, Figure 2 is a schematic diagram of the back side of the chip carrier 100, combined with Figure 1 and Figure 2As shown, the chip carrier 100 includes a base island 1, a first type of pin 2 and a second type of pin 3. The number of the first type of pin 2 and the second type of pin 3 can be determined according to actual design requirements. The number of the first type of pin 2 and the second type of pin 3 can be one or more. Figure 1 For example, the chip carrier 100 may include one first-type pin 2 and seven second-type pins 3 , and the first-type pin 2 may be a default ground pin.

[0052] The first type of pins 2 are located outside the base island 1 and are directly connected to the base island 1, and the second type of pins 3 are located outside the base island 1 and are spaced apart from the base island 1. Since the first type of pins 2 are directly connected to the base island 1, an electrostatic transmission path is formed, so that the static electricity in the base island 1 can be quickly transmitted to the first type of pins 2, thereby preventing the static electricity from being directly transmitted to the internal circuit of the bare chip 200.

[0053] In order to improve the connection stability between the packaging material 300 and the chip carrier 100 and optimize the packaging effect, the chip carrier 100 is provided with recessed areas. These recessed areas are formed by a local thinning process, so that the thickness of the corresponding solid part is smaller than that of other areas. For ease of understanding and description, the embodiment of the present disclosure defines the side of the chip carrier 100 used for bonding with the chip as the "front side" and the side away from the chip as the "back side". Figure 2 and Figure 3 As shown, the back sides of the edge areas of the base island 1, the first type of pins 2 and the second type of pins 3 are all first recessed areas 101. The first recessed areas 101 of the base island 1 and the first type of pins 2 form a continuous overall area. It can be understood that these first recessed areas 101 are formed on the back side of the chip carrier 100 through a local thinning process.

[0054] When forming a packaged device 1000 based on the bare die 200, the packaging material 300 and the chip carrier 100 provided in the above embodiment, the packaging material 300 will fill the first recessed area 101, thereby improving the connection stability between the packaging material 300 and the back of the chip carrier 100. Since the first recessed area 101 of the base island 1 and the first type of pin 2 forms a continuous overall area, the connection portion between the base island 1 and the first type of pin 2 will also be covered by the packaging material 300. Although the first type of pin 2 is directly connected to the base island 1, since the connection portion is covered by the packaging material 300, the outer dimensions, pin positions and other properties of the packaged device 1000 specified by the package outline drawing will not change. Therefore, the test equipment and methods do not need to be adjusted due to design changes, and the related fixtures required to be used by subsequent customers do not need to be changed to adapt to the new design, maintaining good compatibility and consistency.

[0055] For the packaged device 1000 using the chip carrier 100 provided by the embodiment of the present disclosure, when the operator touches the back of the exposed base island 1 in the packaged device 1000 and introduces static electricity, since the first type pin 2 is directly connected to the base island 1, the static electricity can be transmitted to the first type pin 2, and then continue to be transmitted to the pad of the bare chip 200 through the bonding wire 500 of the first type pin 2, and finally the static electricity is transmitted to the electrostatic protection area of ​​the chip through this pad, so that the electrostatic protection area can release static electricity, thereby effectively protecting the internal circuit of the chip from electrostatic damage and preventing the packaged device 1000 from failing due to static electricity. The chip carrier 100 provided by the embodiment of the present disclosure significantly improves the electrostatic protection capability of the packaged device 1000 through the optimized electrostatic transmission path, reduces the risk of failure of the packaged device 1000 caused by static electricity, and thus improves the overall quality and market competitiveness of the packaged device 1000. Moreover, by forming the base island 1 and the first recessed area 101 of the first type of pin 2 into a continuous integral area, it can be ensured that the test equipment and methods do not need to be adjusted due to design changes, and the related fixtures required by subsequent customers do not need to be changed to adapt to the new design, maintaining good compatibility and consistency.

[0056] In some embodiments, the first recessed area 101 corresponding to the first type pin 2 partially surrounds the first type pin 2 to form an incompletely closed arc structure. When the packaging material 300 is filled in the first recessed area 101 corresponding to the first type pin 2, since only a portion of the first type pin 2 is partially surrounded by the first recessed area 101 corresponding to the first type pin 2, the back and one side of the first type pin 2 can be exposed outside the packaging material 300, so that the first type pin 2 can be connected to other components.

[0057] In some embodiments, the first recessed area 101 corresponding to the second type pin 3 partially surrounds the second type pin 3, forming an incompletely closed arc structure. When the packaging material 300 is filled in the first recessed area 101 corresponding to the second type pin 3, since only a portion of the second type pin 3 is partially surrounded by the first recessed area 101 corresponding to the second type pin 3, the back and one side of the second type pin 3 can be exposed outside the packaging material 300, so that the second type pin 3 can be connected to other components.

[0058] In some embodiments, in combination Figure 1 and Figure 4 As shown, a second recessed area 102 is provided on the front side of the first type pin 2, and the second recessed area 102 is formed by a local thinning process on the front side of the chip carrier 100. When a packaged device 1000 is formed based on the bare die 200, the packaging material 300, and the chip carrier 100 provided in the above embodiment, the packaging material 300 will be filled into the second recessed area 102, thereby improving the connection stability between the packaging material 300 and the front side of the chip carrier 100.

[0059] In the embodiment of the present disclosure, the first recessed area 101 and the second recessed area 102 corresponding to the first type of pin 2 do not overlap. The non-overlapping design of the first recessed area 101 and the second recessed area 102 ensures that the local thinning process will not be superimposed at the same position, thereby avoiding the risk of excessive thinning or even penetration of the first type of pin 2 at the same position, which helps to maintain the overall structural integrity of the first type of pin 2. By separating the recessed areas, it can ensure that the stress is more evenly distributed on the first type of pin 2, reducing the risk of mechanical failure caused by local stress concentration.

[0060] In some embodiments, a second recessed area 102 is provided on the front side of the second type pin 3, and the second recessed area 102 is formed by a local thinning process on the front side of the chip carrier 100. When a packaged device 1000 is formed based on the bare die 200, the packaging material 300, and the chip carrier 100 provided in the above embodiment, the packaging material 300 will be filled into the second recessed area 102, thereby improving the connection stability between the packaging material 300 and the front side of the chip carrier 100.

[0061] In the embodiment of the present disclosure, the first recessed area 101 and the second recessed area 102 corresponding to the second type pin 3 do not overlap. The non-overlapping design of the first recessed area 101 and the second recessed area 102 ensures that the local thinning process will not be superimposed at the same position, thereby avoiding the risk of excessive thinning or even penetration of the second type pin 3 at the same position, which helps to maintain the overall structural integrity of the second type pin 3. By separating the recessed areas, it can ensure that the stress is more evenly distributed on the second type pin 3, reducing the risk of mechanical failure caused by local stress concentration.

[0062] In some embodiments, the first recessed area 101 corresponding to the base island 1 completely surrounds the base island 1 to form a complete annular structure. The first recessed area 101 of the annular structure significantly increases the contact area between the packaging material 300 and the edge of the base island 1, and improves the adhesion and connection stability of the packaging material 300. This helps to ensure that the packaging material 300 is firmly fixed on the chip carrier 100, reducing the risk of the packaging material 300 falling off or loosening. The first recessed area 101 of the annular structure can more evenly distribute the stress generated during the curing process of the packaging material 300, reduce stress concentration points, and avoid structural failure due to excessive local stress.

[0063] In some embodiments, the local thinning process includes any one of the following: half-etching, milling, grinding, stamping, and laser processing.

[0064] In the disclosed embodiment, half etching refers to selectively removing part of the thickness of a metal layer or a substrate by chemical or electrochemical methods to form a desired recessed area. Specifically, a layer of photosensitive material (such as photoresist) can be coated on the surface of the chip carrier 100, and the area to be retained can be defined by photolithography. The portion not covered by the mask is exposed to an etching solution, and the material of a predetermined depth is etched away to form a recessed area. After etching is completed, the mask is cleaned and peeled off.

[0065] In the disclosed embodiments, milling refers to mechanically cutting metal or a substrate using a rotating tool to remove unwanted material and form a recessed area.

[0066] In the disclosed embodiments, grinding refers to grinding a metal or substrate surface using a grinding wheel or other abrasive tools to remove material to form a recessed area.

[0067] In the disclosed embodiments, stamping refers to using a mold and a press to form a metal or substrate in one step to directly form a recessed area.

[0068] In the disclosed embodiment, laser processing refers to locally heating a metal or substrate using a high energy density laser beam to melt or vaporize the material, thereby forming a recessed area.

[0069] The present disclosure provides a lead frame 400, which is combined with Figure 5 As shown, the lead frame 400 includes a plurality of chip carriers 100 provided in the above embodiments, and these chip carriers 100 are integrally formed on the same metal sheet and connected to adjacent chip carriers 100 by a specific connection method. By using the above-mentioned local thinning process in the lead frame 400, a first recessed area 101 and a second recessed area 102 can be formed in each chip carrier 100.

[0070] Combination Figure 6 As shown, the following are specific steps for preparing a packaged device 1000 based on this lead frame 400: For each chip carrier 100 in the lead frame 400, apply a layer of glue on the base island 1 of each chip carrier 100 to fix the die 200. Use a chip bonding device to accurately place the die 200 on the base island 1, and apply appropriate pressure to evenly distribute the glue to ensure that the die 200 is firmly fixed. Subsequently, the bonded die 200 and lead frame 400 are placed in an oven for curing to ensure that the glue is completely hardened and provides stable mechanical support.

[0071] Next, a wire bonding machine is used to connect the pads on the die 200 to the front of the first type pins 2 and the second type pins 3 of the corresponding chip carrier 100 in the lead frame 400 through wire bonding 500 to form an electrical connection. The connection between each pad and the pin needs to be precisely controlled to ensure the bonding quality. After the wire bonding 500 connection is completed, a corresponding mold is prepared according to the size and shape of the lead frame 400. A release agent is applied inside the mold to prevent the packaging material 300 from sticking.

[0072] Then, the lead frame 400 is placed in the mold, and a liquid packaging material 300 (such as epoxy resin) is injected. It can be understood that the packaging material 300 mutually fills each of the first recessed area 101 and the second recessed area 102. The packaging material 300 is cured under high temperature and high pressure to form a solid packaging body, thereby obtaining a packaged device 1000. Finally, each chip carrier 100 is cut from the lead frame 400 along the cutting line shown in the figure, thereby obtaining an independent packaged device 1000.

[0073] The present disclosure provides a packaging device 1000. Figure 7 is a front schematic diagram of the packaged device 1000, Figure 8 is a perspective view of the front side of the packaged device 1000, Fig. 9 is a schematic diagram of the back side of the packaged device 1000. Fig.10 is a side view of the packaged device 1000. Figure 8 2 is a perspective view, so the chip carrier 100 and the die 200 are both indicated by dashed lines. Figures 7 to 10 As shown, the packaged device 1000 includes a bare chip 200, a packaging material 300, and the chip carrier 100 provided in the above embodiment. The packaging material 300 may be epoxy resin, silicone gel, polyimide or ceramic packaging material 300, etc.

[0074] like Figure 8 As shown, the back side of the die 200 is attached to the front side of the base island 1 in the chip carrier 100, and the pads of the die 200 are connected to the front sides of the corresponding first type pins 2 and second type pins 3 in the chip carrier 100 through the welding wires 500. The first type pin 2 may be a default ground pin, and the ground pads of the die 200 and the first type pins 2 are connected through the welding wires 500. The welding wires 500 may be metal wires, for example, the welding wires 500 may be copper wires, copper alloy wires, iron-nickel alloy wires, or aluminum wires. The packaging material 300 covers the front sides of the die 200 and the chip carrier 100, and fills each first recessed area 101 of the chip carrier 100. As shown in FIG. Fig. 9 As shown, the packaging material 300 located on the back side of the chip carrier 100 is flush with the back side of the chip carrier 100. Further, the packaging material 300 is filled in each second recessed area 102 of the chip carrier 100.

[0075] Combination Fig. 9 and Fig.10 As shown, the first recessed area 101 corresponding to the first type pin 2 partially surrounds the first type pin 2, forming an incompletely closed arc structure. When the packaging material 300 is filled in the first recessed area 101 corresponding to the first type pin 2, since only a portion of the first type pin 2 is partially surrounded by the first recessed area 101 corresponding to it, the back and one side of the first type pin 2 can be exposed outside the packaging material 300, so that the first type pin 2 can be connected to other components. The first recessed area 101 corresponding to the second type pin 3 partially surrounds the second type pin 3, forming an incompletely closed arc structure. When the packaging material 300 is filled in the first recessed area 101 corresponding to the second type pin 3, since only a portion of the second type pin 3 is partially surrounded by the first recessed area 101 corresponding to it, the back and one side of the second type pin 3 can be exposed outside the packaging material 300, so that the second type pin 3 can be connected to other components.

[0076] The above description and the accompanying drawings sufficiently illustrate the embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural and other changes. The embodiments represent only possible variations. Unless explicitly required, individual components and functions are optional, and the order of operations may vary. Portions and features of some embodiments may be included in or replace portions and features of other embodiments. The embodiments of the present disclosure are not limited to the structures described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A chip carrier, characterized in that: Including base island, first type pins and second type pins; The first type of pins are located outside the base island and are directly connected to the base island; The second type of pins are located outside the base island and spaced apart from the base island; The back sides of the edge areas of the base island, the first type of pins and the second type of pins are all first recessed areas, and the first recessed areas of the base island and the first type of pins form a continuous overall area, wherein the first recessed area is formed on the back side of the chip carrier through a local thinning process.

2. The chip carrier according to claim 1, characterized in that: The first recessed area corresponding to the first type of pins partially surrounds the first type of pins to form an incompletely closed arc structure.

3. The chip carrier according to claim 1, characterized in that: The first recessed area corresponding to the second type of pin partially surrounds the second type of pin to form an incompletely closed arc structure.

4. The chip carrier according to claim 1, characterized in that: A second recessed area is arranged on the front side of the first type of pins, the first recessed area does not overlap with the second recessed area, and the second recessed area is formed on the front side of the chip carrier through a local thinning process.

5. The chip carrier according to claim 1, characterized in that: A second recessed area is disposed on the front side of the second type of pins, and the first recessed area does not overlap with the second recessed area, wherein the second recessed area is formed on the front side of the chip carrier through a local thinning process.

6. The chip carrier according to claim 1, characterized in that: The first recessed area corresponding to the base island completely surrounds the base island to form a complete annular structure.

7. The chip carrier according to any one of claims 1 to 6, characterized in that: The local thinning process includes any of the following: half etching, milling, grinding, stamping, and laser processing.

8. A lead frame, characterized in that: The method comprises a plurality of chip carriers according to any one of claims 1 to 7.

9. A packaged device, characterized in that: comprising a bare die, a packaging material and a chip carrier as claimed in any one of claims 1 to 7; The back side of the bare chip is attached to the front side of the base island in the chip carrier, and the pads of the bare chip are connected to the front sides of the corresponding first type pins and second type pins in the chip carrier through bonding wires; The packaging material covers the front sides of the bare die and the chip carrier and fills each first recessed area of ​​the chip carrier. The packaging material on the back side of the chip carrier is flush with the back side of the chip carrier.

10. The packaged device according to claim 9, characterized in that: The packaging material is filled in each second recessed area of ​​the chip carrier.

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