Power management circuit, display device and method for driving display device

Abstract

The embodiment of the invention relates to a power management circuit, a display device and a driving method of the display device. More specifically, the feedback circuit includes a resistance control circuit capable of adjusting a resistance value between the first input terminal and the output node based on a safety mode signal, thereby operating in a safety mode when an overcurrent occurs.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a power management circuit, a display device, and a method for driving the display device. Background Art

[0002] As the information society develops, the demand for display devices for displaying images in various forms is increasing. Therefore, in recent years, various display devices such as liquid crystal displays, organic light emitting display devices, etc. have been used.

[0003] The display device may include power management circuitry to generate and provide power.

[0004] A load connected to the power management circuit may receive the output voltage from the power management circuit and may be driven using the output voltage.

[0005] The description provided in the Background section should not be assumed to be prior art merely because it is mentioned in the Background section or associated with the Related Art section.The Background section may include information that describes one or more aspects of the subject technology. Summary of the invention

[0006] If an overcurrent occurs in the load, the operation of the power management circuit may stop.

[0007] In this case, the display device may be suddenly turned off, and as a result, a normal stop operation may not be performed.

[0008] Embodiments of the present disclosure may provide a power management circuit, a display device, and a method of driving the display device that are capable of operating in a safe mode when an overcurrent occurs.

[0009] Embodiments of the present disclosure may provide a power management circuit capable of stably outputting an output voltage from a DC voltage converter, a display device, and a method of driving the display device.

[0010] Embodiments of the present disclosure may provide a power management circuit, a display device, and a method of driving the display device that are capable of reducing power consumption by operating in a safety mode when an overcurrent occurs.

[0011] Additional features and aspects of the present disclosure are partially set forth in the following description and partially will become apparent from the description or can be learned by practicing the inventive concepts provided herein. Other features and aspects of the inventive concepts can be realized and obtained by structures pointed out or derivable therefrom in the present disclosure as well as the attached claims and drawings.

[0012] An embodiment of the present disclosure may provide a power management circuit, comprising: a DC voltage converter, which is configured to generate an output voltage based on a first input voltage and output the output voltage to an output node; and a feedback circuit, which is configured to generate a feedback signal based on the output voltage output to the output node, wherein the feedback circuit comprises: an amplifier, which is used to compare a voltage provided to a first input terminal and a second input voltage provided to a second input terminal and output a first comparison signal; a feedback signal output circuit, which is configured to output a feedback signal based on the first comparison signal; and a resistance control circuit, which is electrically connected between the first input terminal and the output node, and wherein the resistance control circuit adjusts the resistance value between the first input terminal and the output node based on a safety mode signal.

[0013] An embodiment of the present disclosure may provide a display device, comprising: a display panel, on which a plurality of sub-pixels are arranged; and a power management circuit, which is configured to provide power to the sub-pixels, wherein the power management circuit comprises: a DC voltage converter, which is configured to generate an output voltage based on a first input voltage and output the output voltage to an output node; and a feedback circuit, which is configured to generate a feedback signal based on the output voltage output to the output node, wherein the feedback circuit comprises: an amplifier, which is used to compare a voltage provided to a first input terminal with a second input voltage provided to a second input terminal and output a first comparison signal; a feedback signal output circuit, which is configured to output a feedback signal based on the first comparison signal; and a resistance control circuit, which is electrically connected between the first input terminal and the output node, and wherein the resistance control circuit adjusts the resistance value between the first input terminal and the output node based on a safety mode signal.

[0014] An embodiment of the present disclosure may provide a driving method for a display device, the driving method comprising: a first step in which a safety mode driving circuit outputs a safety mode signal after receiving an overcurrent pulse signal; a second step in which a resistance control circuit that receives the safety mode signal adjusts a resistance value; a third step in which a feedback circuit including a resistance control circuit outputs a feedback signal; and a fourth step in which a DC voltage converter provided with a feedback signal reduces a voltage level of an output voltage.

[0015] According to an embodiment of the present disclosure, a power management circuit, a display device, and a method of driving the display device that are capable of operating in a safe mode when an overcurrent occurs may be provided.

[0016] According to an embodiment of the present disclosure, a power management circuit capable of stably outputting an output voltage from a DC voltage converter, a display device, and a method of driving the display device can be provided.

[0017] According to an embodiment of the present disclosure, a power management circuit, a display device, and a method of driving the display device capable of reducing power consumption by operating in a safety mode when an overcurrent occurs may be provided.

[0018] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the inventive concepts as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings, which may be included to provide a further understanding of the disclosure and may be incorporated in and constitute a part of this disclosure, illustrate embodiments of the disclosure and together with the description serve to explain various principles of the disclosure.

[0020] Figure 1 A schematic configuration of a display device according to an exemplary embodiment of the present disclosure is illustrated.

[0021] Figure 2 is a system diagram of a display device according to an example embodiment of the present disclosure.

[0022] Figure 3 and Figure 4 A direct current voltage converter, a feedback circuit, and a load according to example embodiments of the present disclosure are illustrated.

[0023] Figure 5 A power management circuit operating in a safe mode according to an example embodiment of the present disclosure is illustrated.

[0024] Figure 6 is an example diagram of a power management circuit operating in a safe mode according to an example implementation of the present disclosure.

[0025] Figure 7 is an example diagram of a power management circuit operating in a safe mode according to an example implementation of the present disclosure.

[0026] Figure 8 is an example waveform that occurs when the safety mode driving circuit according to the example embodiment of the present disclosure is driven.

[0027] Fig. 9 A resistance control circuit according to an example embodiment of the present disclosure is illustrated.

[0028] Fig.10 is a flowchart of a driving method of a display device driven in a safety mode according to an exemplary embodiment of the present disclosure.

[0029] Throughout the drawings and detailed description, unless otherwise described, the same drawing reference numerals should be understood to refer to the same elements, features, and structures. The relative sizes and depictions of these elements may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0030] In the following description of examples or embodiments of the present disclosure, reference will be made to the accompanying drawings, in which specific examples or embodiments that can be implemented are shown by way of example, and the same reference numerals and symbols may be used to represent the same or similar components, even if they are shown in different drawings from each other. In addition, in the following description of examples or embodiments of the present disclosure, when it is determined that the detailed description of the well-known functions and components incorporated herein may make the subject matter of some embodiments of the present disclosure unclear, the description will be omitted. Terms such as "including", "having", "comprising", "comprising", "consisting of", and "formed of" used herein are generally intended to allow the addition of other components unless these terms are used with terms such as "only". As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0031] The progression of processing steps and / or operations described is an example; however, the order of steps and / or operations is not limited to the order set forth herein and may be varied as known in the art, except for steps and / or operations that must occur in a particular order. The names of corresponding elements used in the following description may be selected solely for ease of writing the description and therefore may differ from the names used in an actual product.

[0032] By referring to the following example embodiments described in detail with reference to the accompanying drawings, the advantages and features of the present disclosure and methods for implementing the same will become clear. However, the present disclosure can be implemented in different forms and should not be construed as being limited to the example embodiments set forth herein. On the contrary, these example embodiments can be provided so that the present disclosure can be sufficiently thorough and complete to help those skilled in the art fully understand the scope of the present disclosure. In addition, the present disclosure will only be limited by the scope of the appended claims. Any implementation described herein as an "example" is not necessarily to be construed as being preferred or advantageous over other implementations.

[0033] The shapes, sizes, ratios, angles, numbers, etc. illustrated in the drawings for describing various exemplary embodiments of the present disclosure are given only by way of example. Therefore, the present disclosure is not limited to the illustrations in the drawings.

[0034] When explaining an element, the element is interpreted as including an error range or a tolerance range even if there is no explicit description of such an error range or a tolerance range.

[0035] When describing a positional relationship, for example, when using "on", "above", "below", "over", "under", "down", "adjacent", "close to", or "adjacent", "beside", "next to", etc. to describe the positional relationship between two components, one or more other components may be arranged between the two components, unless more restrictive terms such as "immediately", "directly" or "closely" are used. For example, when a structure is described as being located "on", "above", "below", "above", "below", "below", "adjacent to" another structure, "close to" another structure, or "adjacent to" another structure, "beside", "next to" another structure, this description should be interpreted as including the situation where the structures are in contact with each other and the situation where a third structure is arranged or inserted therebetween. In addition, the terms "left", "right", "top", "bottom", "downward", "upward", "up", "down", etc. refer to an arbitrary reference system.

[0036] Terms such as "first", "second", "A", "B", "(A)" or "(B)" may be used herein to describe elements of the present disclosure. Each of these terms is not used to define the nature, sequence, order or quantity of the elements, etc., but is only used to distinguish the corresponding element from other elements.

[0037] When it is mentioned that a first element is "connected or coupled", "contacted or overlapped", etc. with a second element, it should be understood that the first element may not only be "directly connected or coupled" or "directly contacted or overlapped" with the second element, but also a third element may be "interposed" between the first element and the second element, or the first element and the second element may be "connected or coupled", "contacted or overlapped", etc. with each other through a fourth element. Here, the second element may be included in at least one of the two or more elements that are "connected or coupled", "contacted or overlapped", etc. with each other.

[0038] When time relative terms such as “after,” “subsequently,” “next,” “before,” etc. are used to describe a process or operation of an element or configuration, or a flow or step in an operation, process, or method of manufacture, these terms may be used to describe non-sequential or non-sequential processes or operations unless used with the terms “directly” or “immediately.”

[0039] In addition, when referring to any size, relative size, etc., it should be considered that the numerical value or corresponding information (e.g., level, range, etc.) of the element or feature includes a tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is specified. In addition, the term "may" fully encompasses all meanings of the term "can".

[0040] The term "at least one" should be understood to include any and all combinations of one or more associated listed items. For example, the meaning of "at least one of the first element, the second element, and the third element" covers the combination of all three listed elements, the combination of any two of the three elements, and each individual element (the first element, the second element, or the third element).

[0041] The features in the various embodiments of the present disclosure may be partially or entirely connected or combined with each other, and may be technically interoperable and technically driven in various ways as those skilled in the art can fully understand. The embodiments of the present disclosure may be implemented independently of each other, or may be implemented together in a mutually dependent relationship.

[0042] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments belong. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having, for example, a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein. For example, the term "component" or "unit" may apply, for example, to a separate circuit or structure, an integrated circuit, a computing block of a circuit device, or any structure configured to perform the described function, as will be understood by one of ordinary skill in the art.

[0043] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In addition, all components of each power management circuit and each display device according to the present disclosure are operatively connected and configured.

[0044] Figure 1 A schematic configuration of a display device 100 according to an embodiment of the present disclosure is illustrated.

[0045] Reference Figure 1 According to an embodiment of the present disclosure, a display device 100 may include: a display panel 110, in which a plurality of gate lines GL and data lines DL are provided and a plurality of sub-pixels SP are arranged in a matrix form; a gate driving circuit 120 for driving the plurality of gate lines GL; a data driving circuit 130 for providing data voltages through the plurality of data lines DL; a controller 140 for controlling the gate driving circuit 120 and the data driving circuit 130; and a power management circuit 150.

[0046] The display panel 110 may display an image based on a scan signal transmitted from the gate driving circuit 120 through the plurality of gate lines GL and a data voltage transmitted from the data driving circuit 130 through the plurality of data lines DL.

[0047] In the case of an organic light emitting display, the display panel 110 may be implemented as a top emission method, a bottom emission method, or a double-sided emission method.

[0048] The display panel 110 may include a plurality of pixels arranged in a matrix, and each pixel may include sub-pixels SP of different colors, for example, white sub-pixels, red sub-pixels, green sub-pixels, and blue sub-pixels. In addition, each sub-pixel SP may be defined by a plurality of data lines DL and a plurality of gate lines GL.

[0049] One subpixel SP may include a thin film transistor TFT formed in a region where one data line DL intersects one gate line GL, a light emitting device (such as an organic light emitting diode) charged with a data voltage, and a storage capacitor electrically connected to the light emitting device to maintain a certain voltage.

[0050] For example, in the case where the display device 100 having a resolution of 2160×3840 includes four sub-pixels of white (W), red (R), green (G), and blue (B), each of the 3840 data lines DL is connected to four sub-pixels (WRGB), and 2160 gate lines GL and a total of 3840×4=15360 data lines DL may be provided. The sub-pixel SP may be provided at each point where the gate line GL and the data line DL intersect.

[0051] The gate driving circuit 120 may be controlled by the controller 140 , and sequentially output scan signals to a plurality of gate lines GL disposed on the display panel 110 to control driving timing of a plurality of sub-pixels SP.

[0052] In this case, the gate driving circuit 120 may include one or more gate driving integrated circuits GDIC, and depending on a driving method, the gate driving circuit 120 may be located only on one side of the display panel 110, or may be located on both sides of the display panel 110. Alternatively, the gate driving circuit 120 may be embedded in a bezel area of ​​the display panel 110 to be implemented with a gate in panel (GIP) type.

[0053] The data driving circuit 130 may receive the image data DATA from the controller 140 and convert the received image data DATA into an analog data voltage. Then, the data driving circuit 130 may output a data voltage to each data line DL according to the timing of applying a scan signal through the gate line GL, so that each sub-pixel SP connected to the data line DL may display light of brightness corresponding to the data voltage.

[0054] Similarly, the data driving circuit 130 may include one or more source driver integrated circuits SDIC, and the source driver integrated circuits SDIC may be connected to bonding pads of the display panel 110 using a tape automated bonding (TAB) method or a chip on glass (COG) method, or may be directly set on the display panel 110.

[0055] Depending on the situation, each source driver integrated circuit SDIC may be integrated and disposed on the display panel 110. In addition, each source driver integrated circuit SDIC may be implemented using a chip on film (COF) method. In this case, each source driver integrated circuit SDIC may be mounted on a circuit film and may be electrically connected to the data line DL of the display panel 110 through the circuit film.

[0056] The controller 140 may provide various control signals to the gate driving circuit 120 and the data driving circuit 130, and control the operations of the gate driving circuit 120 and the data driving circuit 130. For example, the controller 140 may control the gate driving circuit 120 to output a scan signal according to a timing implemented in each frame, and may transmit image data DATA received from the outside to the data driving circuit 130.

[0057] In this case, the controller 140 may receive the image data DATA and various timing signals including a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable DE signal, and a main clock MCLK from the external host system 200 .

[0058] The host system 200 may be any one of a television system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, and a wearable device.

[0059] Therefore, the controller 140 may generate a control signal using various timing signals received from the host system 200 , and transmit the timing signals to the gate driving circuit 120 and the data driving circuit 130 .

[0060] For example, in order to control the gate drive circuit 120, the controller 140 may output various gate control signals including a gate start pulse signal GSP, a gate clock GCLK, and a gate output enable signal GOE. Here, the gate start pulse signal GSP may control the operation start timing of one or more gate drive integrated circuits GDIC constituting the gate drive circuit 120. Additionally, the gate clock GCLK is a clock signal commonly input to one or more gate drive integrated circuits GDIC, and may control the shift timing of the scan signal. Additionally, the gate output enable signal GOE may specify the timing information of one or more gate drive integrated circuits GDIC.

[0061] In addition, in order to control the data driving circuit 130, the controller 140 may output various data control signals such as a source start pulse SSP, a source sampling clock SCLK, and a source output enable signal SOE. Here, the source start pulse SSP may control the timing at which one or more source driver integrated circuits SDIC constituting the data driving circuit 130 start sampling data. The source sampling clock SCLK is a clock signal that controls the timing of sampling data in the source driver integrated circuit SDIC. The source output enable signal SOE may control the output timing of the data driving circuit 130.

[0062] The display device 100 may include a power management circuit 150 that supplies various voltages or currents to the display panel 110 , the gate driving circuit 120 , and the data driving circuit 130 , or controls the various voltages or currents to be supplied.

[0063] The power management circuit 150 may adjust the DC input voltage Vin provided from the host system 200 to generate power required to drive the display panel 110, the gate driving circuit 120, and the data driving circuit 130. The power management circuit 150 may be referred to as a power management integrated circuit PMIC.

[0064] In addition, the sub-pixel SP may be located at a point where the gate line GL intersects the data line DL, and a light emitting device may be provided in each sub-pixel SP. For example, the organic light emitting display device may include a light emitting device such as an organic light emitting diode in each sub-pixel SP, and may display an image by controlling a current flowing through the light emitting device according to a data voltage.

[0065] The display device 100 may be of various types, such as a liquid crystal display, an organic light emitting display, and a plasma display panel. However, the present disclosure is not limited thereto. For example, the display device 100 may be of various other types, such as a micro LED display device or a QLED display device.

[0066] Figure 2 is a system diagram of a display device 100 according to an embodiment of the present disclosure.

[0067] Figure 2 An example of a display device 100 according to an embodiment of the present disclosure is illustrated, in which a source driver integrated circuit SDIC included in a data driver circuit 130 and a gate driver integrated circuit GDIC included in a gate driver circuit 120 are implemented by a chip on film (COF) method among a variety of methods (TAB, COG, COF, etc.).

[0068] One or more gate driving integrated circuits GDIC included in the gate driving circuit 120 may be mounted on the gate film GF, and one side of the gate film GF may be electrically connected to the display panel 110. In addition, a line for electrically connecting the gate driving integrated circuit GDIC and the display panel 110 may be provided on the gate film GF.

[0069] In this case, the gate driving circuit 120 may be located on only one side or both sides of the display panel 110 depending on the driving method. Alternatively, the gate driving circuit 120 may be embedded in a bezel area of ​​the display panel 110 and implemented in a gate in panel (GIP) form.

[0070] Similarly, one or more source driver integrated circuits SDIC included in the data driver circuit 130 may be each mounted on the source film SF, and one side of the source film SF may be electrically connected to the display panel 110. Additionally, a line for electrically connecting the source driver integrated circuit SDIC and the display panel 110 may be provided on the source film SF.

[0071] The display device 100 may include at least one source printed circuit board SPCB and a control printed circuit board CPCB for mounting various electrical devices and control components for circuit connection between a plurality of source driving integrated circuits SDIC and other devices.

[0072] In this case, the other side of the source film SF on which the source driver integrated circuit SDIC is mounted may be connected to at least one source printed circuit board SPCB. For example, one side of the source film SF on which the source driver integrated circuit SDIC is mounted may be electrically connected to the display panel 110, and the other side may be electrically connected to the source printed circuit board SPCB.

[0073] The controller 140 and the power management circuit (e.g., power management IC) 150 may be mounted on the control printed circuit board CPCB. The controller 140 may control the operations of the data driving circuit 130 and the gate driving circuit 120. The power management circuit 150 may provide a driving voltage or current to the display panel 110, the data driving circuit 130, and the gate driving circuit 120, and may control the provided voltage or current.

[0074] The at least one source printed circuit board SPCB and the control printed circuit board CPCB may be circuit-connected by at least one connection member, and the connection member may be, for example, a flexible printed circuit (FPC), a flexible flat cable (FFC), etc. In this case, the connection member connecting the at least one source printed circuit board SPCB and the control printed circuit board CPCB may be variously modified depending on the size and type of the display device 100. Additionally, the at least one source printed circuit board SPCB and the control printed circuit board CPCB may be integrated and implemented as one printed circuit board.

[0075] In the case of the display device 100 configured as described above, the power management circuit 150 may transmit a driving voltage required for display driving or characteristic value sensing to the source printed circuit board SPCB through a flexible printed circuit (FPC) or a flexible flat cable (FFC). The driving voltage transmitted to the source printed circuit board SPCB may be provided through a source driver integrated circuit SDIC to make a specific sub-pixel SP in the display panel 110 emit light or sense a specific sub-pixel SP in the display panel 110.

[0076] The power management circuit 150 can generate various voltages as the output voltage Vout based on the input voltage Vin. For example, the output voltage Vout can include a driving voltage VDD, a base voltage VSS, a reference voltage Vref, a gate high voltage VGH, a gate low voltage VGL, and the like.

[0077] The voltage generated by the power management circuit 150 may be provided to the display panel 110 , the gate driving circuit 120 , the data driving circuit 130 , and the controller 140 .

[0078] The power management circuit 150 may include a DC-DC converter to generate a voltage. The power management circuit 150 may include a voltage changing circuit such as a buck converter, a boost converter, or a boost-buck converter. A buck converter is a DC-DC converter, and can output by stepping down an input voltage. A boost converter is a DC-DC converter, and a boost converter can output by stepping up an input voltage. A boost-buck converter is a DC-DC converter, and a boost-buck converter can output by stepping down or stepping up an input voltage. The power management circuit 150 can generate a voltage by bypassing an input voltage Vin.

[0079] Figure 3 and Figure 4 A direct current voltage converter 310 , a feedback circuit 320 , and a load according to an embodiment of the present disclosure are illustrated.

[0080] The power management circuit 150 may include a DC voltage converter 310 and a feedback circuit 320 .

[0081] The DC voltage converter 310 may receive an input voltage Vin and then generate an output voltage Vout based on the input voltage Vin. The output voltage Vout may be a boosted voltage or a bucked voltage based on the input voltage Vin.

[0082] The DC voltage converter 310 may be a DC-DC converter, a buck converter, a boost converter, a boost-buck converter, or the like.

[0083] The DC voltage converter 310 may output an output voltage Vout. The output voltage Vout output from the DC voltage converter 310 may be provided to a load 330.

[0084] In addition, the output voltage Vout output from the DC voltage converter 310 may be provided to the feedback circuit 320 .

[0085] The feedback circuit 320 may be a circuit that senses the output voltage Vout and provides a feedback signal FBS to the DC voltage converter 310 .

[0086] The DC voltage converter 310 receiving the feedback signal FBS can control the amplitude of the output voltage Vout. For example, the feedback signal FBS output from the feedback circuit 320 can be a pulse width modulation (PWM) signal. As the duty cycle of the PWM signal is adjusted, the amplitude of the output voltage Vout output from the DC voltage converter 310 can be controlled.

[0087] For ease of explanation, it is assumed hereinafter that the DC voltage converter 310 is a buck converter.

[0088] Reference Figure 4 , illustrates a DC voltage converter that receives an output voltage as feedback.

[0089] The DC voltage converter may output an output voltage. The DC voltage converter may receive a feedback signal for the output voltage from the feedback circuit 320. The DC voltage converter may control the output voltage based on the feedback signal. The DC voltage converter that controls the output voltage according to the feedback signal may be designed in various ways. Figure 4 An example of a DC voltage converter is illustrated.

[0090] Reference Figure 4 , the DC voltage converter may include a first transistor 441, a first diode 451, a first inductor 461, and a first capacitor 471. The DC voltage converter may have a configuration of a general converter circuit.

[0091] The first transistor 441 may be electrically connected between the first node N1 and the second node N2. The input voltage Vin1 may be provided to the first node N1. The gate node of the first transistor 441 may be electrically connected to the third node N3.

[0092] The first diode 451 may be electrically connected between the second node N2 and an eighth node N8. The eighth node N8 may be a node supplied with a ground voltage.

[0093] The first inductor 461 may be electrically connected between the second node N2 and a fifth node N5. The fifth node N5 may be a node at which the output voltage Vout is output.

[0094] The first capacitor 471 may be electrically connected between the fifth node N5 and the tenth node N10. The tenth node N10 may be a node supplied with a ground voltage.

[0095] The feedback circuit 320 may include a first resistor 411, a second resistor 412, an amplifier 421, and a feedback signal output circuit 431. However, the feedback circuit 320 may include only the amplifier 421 and the feedback signal output circuit 431. Hereinafter, for ease of explanation, the feedback circuit 320 will be described under the assumption that it includes the amplifier 421 and the feedback signal output circuit 431.

[0096] The first resistor 411 may be electrically connected between the sixth node N6 and the ninth node N9 .

[0097] The second resistor 412 may be electrically connected between the fifth node N5 and the sixth node N6 .

[0098] The amplifier 421 may include a non-inverting terminal Np, an inverting terminal Nn, and an output terminal No.

[0099] The non-inverting terminal Np of the amplifier 421 may be electrically connected to the sixth node N6 . The non-inverting terminal Np of the amplifier 421 may be electrically connected to the second resistor 412 .

[0100] The inversion terminal Nn of the amplifier 421 may be electrically connected to the seventh node N7. The second input voltage Vin2 may be supplied to the seventh node N7. The inversion terminal Nn of the amplifier 421 may be supplied with the second input voltage Vin2.

[0101] Since the amplifier 421 is electrically connected to the first resistor 411 and the second resistor 412, the amplifier 421 can operate as a comparator circuit, and the output terminal No of the amplifier 421 can output a comparison signal. According to the comparison result between the second input voltage Vin2 and the voltage of the sixth node N6, the comparison signal can be output.

[0102] The feedback signal output circuit 431 may receive the comparison signal. The feedback signal output circuit 431 may output a feedback signal according to the comparison signal. The feedback signal may be a PWM signal. The PWM signal may be a signal with a duty cycle. Depending on the comparison result of the comparator circuit, the feedback signal may have a high duty cycle or a low duty cycle.

[0103] The feedback signal output by the feedback signal output circuit 431 may be provided to the gate node of the first transistor 441. In the case where the feedback signal is a PWM signal, the DC voltage converter 310 may adjust the output voltage Vout based on the PWM signal.

[0104] The regulated output voltage Vout may be provided to the load 330 through the fifth node N5 .

[0105] In addition, the display device 100 may fail due to process errors, external impacts, or long-term use. If a failure occurs, an overcurrent may be generated inside the display device 100. If an overcurrent occurs, the display device 100 may fail. Alternatively, if an overcurrent occurs, a risk such as a fire may occur due to a failure of the display device 100.

[0106] In order to prevent, minimize or reduce the malfunction of the display device 100 due to overcurrent, the display device 100 may include a configuration for blocking overcurrent. For example, an overcurrent may be generated in the load 330 provided with the output voltage Vout. In order to prepare for the occurrence of overcurrent, a fuse or the like may be set on the load 330 side. Alternatively, in order to prepare for the overcurrent generated in the load 330, a fuse or another component may be set on the DC voltage converter 310 side. Components such as fuses can block the flow of current in the event of an overcurrent.

[0107] If the fuse functions in response to the occurrence of the overcurrent, the display device 100 may completely stop. When the fuse functions and the display device 100 stops, a problem may occur in which the display device 100 cannot perform a normal stop operation.

[0108] Specifically, when the display device 100 is an essential component of a vehicle, the complete stop of the display device 100 due to the functioning of the fuse may cause a greater danger to the user. For example, when the vehicle is a vehicle, the necessary driving information of the vehicle may be displayed by the display device 100. In this case, if the display device 100 is completely turned off, the user will not be able to view the necessary driving information of the vehicle. Therefore, the user may be in a dangerous situation.

[0109] Therefore, embodiments of the present disclosure may provide a power management circuit, a display device, and a method of driving a display device, which may operate in a safe mode when an overcurrent occurs.

[0110] Embodiments of the present disclosure may provide a power management circuit that stably outputs an output voltage from a DC voltage converter 310 , a display device, and a method of driving the display device.

[0111] Therefore, embodiments of the present disclosure may provide a power management circuit, a display device, and a method of driving the display device, which achieve low power consumption by operating in a safety mode when an overcurrent occurs.

[0112] Figure 5 A power management circuit operating in a safe mode according to an embodiment of the present disclosure is illustrated.

[0113] exist Figure 5 , a direct current (DC) voltage converter, a feedback circuit 320, a resistance control circuit 580, and a safety mode driving circuit 590 are illustrated.

[0114] Reference Figure 5 , the DC voltage converter may include a first transistor 541 , a first diode 551 , a first inductor 561 , and a first capacitor 571 . Figure 5 The DC voltage converter shown can be used with Figure 4 The DC voltage converters shown are identical.

[0115] Reference Figure 5 , the feedback circuit 320 may include a resistance control circuit 580, a first resistor 511, an amplifier 521, and a feedback signal output circuit 531. However, the feedback circuit 320 may only include the amplifier 521 and the feedback signal output circuit 531. Hereinafter, for ease of explanation, the feedback circuit 320 will be described under the assumption that it includes the amplifier 521 and the feedback signal output circuit 531. Figure 5 The feedback circuit 320 shown can be used with Figure 4 The feedback circuit 320 shown is the same.

[0116] Reference Figure 5 , the resistance control circuit 580 may include a second resistor 512 , a third resistor 513 , and a second transistor 542 .

[0117] The second resistor 512 may be electrically connected between the fifth node N5 and the sixth node N6 .

[0118] The second transistor 542 may be electrically connected between the fifth node N5 and the eleventh node N11.

[0119] The third resistor 513 may be electrically connected between the eleventh node N11 and the sixth node N6 .

[0120] Reference Figure 5 , the safety mode driving circuit 590 can receive the overcurrent pulse signal S1 and then output the safety mode signal S2. Before receiving the overcurrent pulse signal S1, the safety mode signal S2 can be a low level signal. After receiving the overcurrent pulse signal S1, the safety mode signal S2 can become a high level signal.

[0121] The resistance control circuit 580 may receive the safety mode signal S2 as a high level signal. After the resistance control circuit 580 receives the safety mode signal S2 as a high level signal, the resistance control circuit 580 may adjust the resistance value between the fifth node N5 and the sixth node N6. The adjusted resistance value may be less than the resistance value before adjustment.

[0122] Reference Figure 5 , the gate node of the second transistor 542 can receive the safety mode signal S2.

[0123] If the safety mode signal S2 as a low level signal is provided to the gate node of the second transistor 542 , the second transistor 542 may be turned off.

[0124] If the security mode signal S2 as a high level signal is provided to the gate node of the second transistor 542 , the second transistor 542 may be turned on.

[0125] For example, when a safety mode signal S2 for operating a safety mode is provided to the gate node of the second transistor 542 , the second transistor 542 may be switched from a turn-off state to a turn-on state.

[0126] Since the second transistor 542 is switched to the on state, the resistance value between the fifth node N5 and the sixth node N6 can be reduced. Since the resistance value between the fifth node N5 and the sixth node N6 is reduced due to the parallel connection, the voltage across the first resistor 511 can be relatively increased. The relatively large voltage across both ends of the first resistor 511 can be provided to the non-inverting terminal Np of the amplifier 521.

[0127] The comparison signal may be output based on the relatively large voltage across both ends of the first resistor 511. In addition, based on the above-mentioned comparison signal, the feedback signal output circuit 531 may output the control signal as a PWM signal having a relatively low duty ratio.

[0128] Therefore, the DC voltage converter 310 can reduce the output voltage Vout and output a relatively lower voltage. For example, the DC voltage converter 310 can output a voltage that is smaller than the output voltage Vout.

[0129] If the DC voltage converter 310 is Figure 4 If the display device 100 is designed as shown, the display device 100 may suddenly stop due to the fuse blowing in response to the overcurrent. Figure 5 The DC voltage converter 310 shown outputs a relatively small output voltage Vout in a specific period of time based on the safety mode signal S2, so that the display device 100 can operate stably in a certain period of time.

[0130] The safety mode driving circuit 590 may receive the overcurrent pulse signal S1 and then output a safety mode signal S2 to operate the safety mode. The safety mode may be designed using various methods.

[0131] Hereinafter, an implementation of the safety mode driving circuit 590 will be described.

[0132] Figure 6 is an example diagram of a power management circuit operating in a safe mode according to an embodiment of the present disclosure.

[0133] Reference Figure 6 , the DC voltage converter may include a first transistor 641 , a first diode 651 , a first inductor 661 , and a first capacitor 671 . Figure 6 The DC voltage converter shown can be used with Figure 5 The DC voltage converters shown are identical.

[0134] Reference Figure 6 , the feedback circuit 320 may include a resistance control circuit 680, a first resistor 611, an amplifier 621, and a feedback signal output circuit 631. However, the feedback circuit 320 may only include the amplifier 621 and the feedback signal output circuit 631. Hereinafter, for ease of explanation, the feedback circuit 320 will be described under the assumption that it includes the amplifier 621 and the feedback signal output circuit 631. Figure 6 The feedback circuit 320 shown can be used with Figure 5 The feedback circuit 320 shown is the same.

[0135] Reference Figure 6 , the resistance control circuit 680 may include a second resistor 612 , a second transistor 642 , and a third resistor 613 . Figure 6 The resistance control circuit 680 shown can be used with Figure 5 The resistance control circuit shown is the same.

[0136] Reference Figure 6 , the safety mode driving circuit 690 can receive the overcurrent pulse signal S1 and then output the safety mode signal S2 to operate in the safety mode.

[0137] The safety mode driving circuit 690 may include a comparator circuit 691 , a driving time control circuit 692 , and a safety mode starting circuit 693 .

[0138] The safety mode startup circuit 693 may be provided with the overcurrent pulse signal S1. The safety mode startup circuit 693 may be provided with the third input voltage Vin3.

[0139] Overcurrent generated from the load may be sensed by a sensing unit (not shown). If overcurrent is not sensed, the overcurrent pulse signal S1 may be a low level signal, and if overcurrent is sensed, the overcurrent pulse signal S1 may become a high level signal.

[0140] If the safety mode startup circuit 693 receives the overcurrent pulse signal S1 as a high level signal, the safety mode startup circuit 693 may provide the third input voltage Vin3 to the driving time control circuit 692 .

[0141] For example, the safety mode startup circuit 693 may include a switch circuit, and the switch circuit may be switched to an on state by the overcurrent pulse signal S1 being a high level signal. As the switch circuit is turned on, the third input voltage Vin3 may be provided to the driving time control circuit 692 .

[0142] The driving time control circuit 692 may output a driving time control signal after receiving the third input voltage Vin3 .

[0143] The driving time control signal may have a voltage level greater than the safety mode reference voltage level. The safety mode reference voltage level may be a voltage level that causes the comparator circuit 691 to output the safety mode signal S2 as a high level signal.

[0144] The period during which the drive time control signal is outputted may be the same as the period during which the safety mode is operated. Alternatively, the period during which the safety mode is operated may be the same as the period during which the drive time control signal is outputted within a certain range. For example, the period during which the drive time control signal is outputted may overlap with the period during which the safety mode is operated at least partially.

[0145] The comparator circuit 691 may be provided with a driving time control signal and a fourth input voltage Vin4. The comparator circuit 691 may compare the fourth input voltage Vin4 with the driving time control signal. For example, the fourth input voltage Vin4 may have a safety mode reference voltage level. The comparator circuit 691 may output a safety mode signal S2 based on a comparison result between the fourth input voltage Vin4 and the driving time control signal.

[0146] If the driving time control signal has a voltage level greater than the safety mode reference voltage level, the comparator circuit 691 may output the safety mode signal S2 of a high level signal.

[0147] The comparator circuit 691, the driving time control circuit 692, and the safety mode start circuit 693 may be designed in various ways to perform their respective functions. Figure 7 , illustrating an exemplary circuit for each of the comparator circuit 691, the drive time control circuit 692, and the safety mode startup circuit 693.

[0148] Figure 7 is an example diagram of a power management circuit operating in a safe mode according to an embodiment of the present disclosure. Figure 8 is an example waveform that occurs when the safety mode driving circuit according to an embodiment of the present disclosure is driven.

[0149] Reference Figure 7 , the DC voltage converter may include a first transistor 741 , a first diode 751 , a first inductor 761 , and a first capacitor 771 . Figure 7 The DC voltage converter shown can be used with Figure 6 The DC voltage converters 310 shown are identical.

[0150] Reference Figure 7 , the feedback circuit 320 may include a resistance control circuit 780, a first resistor 711, an amplifier 721, and a feedback signal output circuit 731. However, the feedback circuit 320 may only include the amplifier 721 and the feedback signal output circuit 731. Hereinafter, for ease of explanation, the feedback circuit 320 will be described under the assumption that it includes the amplifier 721 and the feedback signal output circuit 731. Figure 7 The feedback circuit 320 shown can be used with Figure 6 The feedback circuit 320 shown is the same.

[0151] Reference Figure 7 , the resistance control circuit 780 may include a second resistor 712 , a second transistor 742 , and a third resistor 713 . Figure 7 The resistance control circuit 780 shown can be used with Figure 6 The resistance control circuit 680 shown is the same.

[0152] Reference Figure 7 The safety mode driving circuit 790 may include a comparator circuit 691 , a driving time control circuit 692 , and a safety mode starting circuit 693 .

[0153] Reference Figure 7 , the safety mode startup circuit 693 may include a ninth resistor 719 and a switch 745 .

[0154] Reference Figure 7 , the ninth resistor 719 may be electrically connected between the fifteenth node N15 and the sixteenth node N16.

[0155] Reference Figure 7 , the switch 745 may be electrically connected between the sixteenth node N16 and the seventeenth node N17.

[0156] Reference Figure 7 , the third input voltage Vin3 may be provided to the seventeenth node N17. The switch 745 may receive the overcurrent pulse signal S1. The switch 745 may be turned on in response to receiving the overcurrent pulse signal S1 as a high level signal.

[0157] Reference Figure 8 , at a first time point t1, the overcurrent pulse signal S1 can be changed from a low level signal to a high level signal Voc. From the first time point t1 to the second time point t2, the overcurrent pulse signal S1 can be in a high level signal Voc state. For example, the switch 745 can be turned on from the first time point t1 to the second time point t2. As the switch 745 is turned on, the third input voltage Vin3 can be provided to the sixteenth node N16. The third input voltage Vin3 can be stepped down or reduced by the ninth resistor 719. In this case, the reduced third input voltage Vin3 can be the first reference voltage Vr1. The first reference voltage Vr1 can be provided to the fifteenth node N15.

[0158] Reference Figure 7 , the driving time control circuit 692 may include an eighth resistor 718 and a second capacitor 722 .

[0159] Reference Figure 7 , the eighth resistor 718 may be electrically connected between the fifteenth node N15 and the ground node.

[0160] Reference Figure 7 , the second capacitor 722 may be electrically connected between the fifteenth node N15 and the ground node.

[0161] Reference Figure 8, before the first time point t1, the voltage VN15 of the fifteenth node may be in a ground voltage state. The voltage VN15 of the fifteenth node from the first time point t1 to the second time point t2 may be the first reference voltage Vr1. After the second time point t2, the voltage level of the first reference voltage Vr1 may decrease. The reduced voltage VN15 of the fifteenth node may become the second reference voltage Vr2 at the third time point t3. The second reference voltage Vr2 may be less than the first reference voltage Vr1. After the third time point t3, the voltage VN15 of the fifteenth node may continue to decrease and become lower than the second reference voltage Vr2. The voltage level of the second reference voltage Vr2 may be the same as the safety mode reference voltage level.

[0162] Since the eighth resistor 718 and the second capacitor 722 form an RC circuit, the voltage VN15 of the fifteenth node can be reduced by drawing an RC delay curve. The time required for the voltage VN15 of the fifteenth node to decrease from the first reference voltage Vr1 to the second reference voltage Vr2 can be as long as the time constant. The time constant can be a value obtained by multiplying the resistance value of the eighth resistor 718 by the capacitance value of the second capacitor 722.

[0163] For example, refer to Figure 8 , from the first time point t1 to the third time point t3, the driving time control circuit 692 can keep the voltage VN15 of the fifteenth node greater than the second reference voltage Vr2.

[0164] Reference Figure 7 , the comparator circuit 691 may include a fourth resistor 714 , a fifth resistor 715 , a sixth resistor 716 , a seventh resistor 717 , and an amplifier 772 .

[0165] Reference Figure 7 , the fourth resistor 714 may be electrically connected between the twelfth node N12 and the fourteenth node N14.

[0166] Reference Figure 7 , the fifth resistor 715 may be electrically connected between the twelfth node N12 and the ground node.

[0167] Reference Figure 7 , the sixth resistor 716 may be electrically connected between the seventeenth node N17 and the thirteenth node N13.

[0168] Reference Figure 7 , the seventh resistor 717 may be electrically connected between the thirteenth node N13 and the ground node.

[0169] Reference Figure 7, the amplifier 772 may include a non-inverting terminal Np2, an inverting terminal Nn2, and an output terminal No2. The non-inverting terminal Np2 of the amplifier 772 may be electrically connected to the thirteenth node N13. The inverting terminal Nn2 of the amplifier 772 may be electrically connected to the fifteenth node N15.

[0170] Reference Figure 7 , the amplifier 772 may operate as the comparator circuit 691. The amplifier 772 may compare the voltage of the thirteenth node N13 with the voltage of the fifteenth node N15. The amplifier 772 may output a comparison signal Vo to the output terminal No2 according to the comparison result.

[0171] Reference Figure 7 , the sixth resistor 716 and the seventh resistor 717 may be connected in series between the seventeenth node N17 and the ground node. Therefore, the voltage corresponding to the voltage difference between the seventeenth node N17 and the ground node may be distributed to each of the sixth resistor 716 and the seventh resistor 717 according to the voltage division principle. When the third input voltage Vin3 is provided to the seventeenth node N17, the voltage of the thirteenth node N13 may be a voltage based on the third input voltage Vin3. The voltage of the thirteenth node N13 may be a fixed voltage. In this case, the voltage of the thirteenth node N13 may be a reference voltage in the comparator circuit 691. The voltage of the thirteenth node N13 may be a fourth input voltage Vin4.

[0172] Reference Figure 8 If the voltage of the fifteenth node N15 is less than the second reference voltage Vr2, the comparator circuit 691 outputs a low-level comparison signal Vo. If the voltage of the fifteenth node N15 is greater than the second reference voltage Vr2, the comparator circuit 691 may output a high-level comparison signal Vo. The comparison signal Vo may be a current or a voltage.

[0173] Reference Figure 7 , the fourth resistor 714 and the fifth resistor 715 may be connected in series between the fourteenth node N14 and the ground node, and therefore, according to the voltage division principle, a voltage corresponding to the voltage difference between the fourteenth node N14 and the ground node may be allocated to each of the fourth resistor 714 and the fifth resistor 715. If the comparison signal Vo is a voltage, the voltage of the thirteenth node N13 may be a voltage based on the comparison signal Vo. The voltage of the thirteenth node N13 (which is a voltage based on the comparison signal Vo) may be a safety mode signal S2. If the comparison signal Vo is a high level signal, the safety mode signal S2 may also be a high level signal.

[0174] Reference Figure 7, as the safety mode signal S2 of the high level signal is provided to the gate node of the second transistor 742, the second transistor 742 may be switched to a conducting state. Therefore, the third resistor 713 may be electrically connected between the fifth node N5 and the sixth node N6. The resistance value between the fifth node N5 and the sixth node N6 may be reduced. Since the resistance value between the fifth node N5 and the sixth node N6 is reduced due to the parallel connection, the voltage across the first resistor 711 may be relatively increased. A relatively large voltage across both ends of the first resistor 711 may be provided to the non-inverting terminal Np1 of the amplifier 721.

[0175] Based on the relatively large voltage across both ends of the first resistor 711 , a comparison signal may be output to the output terminal No1 , and based on the comparison signal, the feedback signal output circuit 731 may output a control signal that is a PWM signal with a relatively low duty cycle.

[0176] Therefore, the DC voltage converter can output a relatively lower output voltage Vout. Figure 8 , the safety mode may be operated from the first time point t1 to the third time point t3, and the voltage output from the DC voltage converter may be the safety mode voltage Vsafe. Figure 8 As shown, the high level period (eg, from time point t1 to time point t3 ) of the safety mode signal S2 , which may be proportional to the comparison signal Vo, may overlap with the active period (eg, from time point t1 to time point t2 ) of the overcurrent pulse signal S1 and be longer.

[0177] Fig. 9 A resistance control circuit 980 according to an embodiment of the present disclosure is illustrated.

[0178] Reference Figure 7 , the resistance control circuit 780 may include a second transistor 742 and a third resistor 713 connected in series. The circuit in which the second transistor 742 and the third resistor 713 are connected in series may be referred to as a "resistance control group".

[0179] Reference Fig. 9 , exemplifies Figure 7 Another example of a resistance control circuit 780 is shown.

[0180] Reference Fig. 9 , the resistance control circuit 980 may include two or more resistance control groups. Since the resistance control circuit 980 includes two or more resistance control groups, the magnitude of the safety mode voltage Vsafe may be adjusted in a variety of ways. The safety mode voltage Vsafe may be a voltage output from the DC voltage converter 310 when operating in the safety mode.

[0181] Reference Fig. 9 , the resistance control circuit 980 may include a second transistor 9421 connected in series with the resistor 9131 and a third transistor 9422 connected in series with the resistor 9132 .

[0182] A gate node of the second transistor 9421 may be electrically connected to the first switch 9423. The first switch 9423 may be controlled by a first switch control signal S3.

[0183] A gate node of the third transistor 9422 may be electrically connected to a second switch 9424. The second switch 9424 may be controlled by a second switch control signal S4.

[0184] The second transistor 9421 and the third transistor 9422 can each be controlled according to the switch control signal, and thus, the resistance value between the fifth node N5 and the sixth node N6 can be adjusted in various ways.

[0185] Fig. 9 Two resistance-controlled groups are shown, but there may be three or more resistance-controlled groups, and in this case, the resistance value may be adjusted in various ways.

[0186] Fig.10 is a flowchart of a driving method of the display device 100 driven in a safety mode according to an embodiment of the present disclosure.

[0187] The driving method of the display device may include a safety mode signal outputting step S1010 , a resistance adjusting step S1020 , a feedback signal outputting step S1030 , and a safety mode voltage setting step S1040 .

[0188] The safety mode signal output step S1010 may be a step in which the safety mode driving circuit outputs a safety mode signal after receiving an overcurrent pulse signal.

[0189] The resistance adjusting step S1020 may be a step of adjusting the resistance value of the resistance control circuit that receives the safety mode signal.

[0190] The feedback signal output step S1030 may be a step in which a feedback circuit including a resistance control circuit outputs a feedback signal.

[0191] The safety mode voltage setting step S1040 may be a step in which the DC voltage converter receiving the feedback signal lowers or steps down the voltage level of the output voltage.

[0192] The above-mentioned embodiments of the present disclosure are briefly described as follows.

[0193] An embodiment of the present disclosure may provide a power management circuit, comprising: a DC voltage converter, which is configured to generate an output voltage based on a first input voltage and output the output voltage to an output node; and a feedback circuit, which is configured to generate a feedback signal based on the output voltage output to the output node, wherein the feedback circuit comprises: an amplifier, which is used to compare a voltage provided to a first input terminal and a second input voltage provided to a second input terminal and output a first comparison signal; a feedback signal output circuit, which is configured to output a feedback signal based on the first comparison signal; and a resistance control circuit, which is electrically connected between the first input terminal and the output node, wherein the resistance control circuit adjusts the resistance value between the first input terminal and the output node based on a safety mode signal.

[0194] The resistance control circuit may include a first resistor electrically connected between a first input terminal and an output node, and a first transistor and a second resistor connected in series between the first input terminal and the output node.

[0195] After the safety mode signal of a high level signal is provided to the gate node of the first transistor, the second resistor may be electrically connected between the first input terminal and the output node.

[0196] When the safety mode signal changes from a low level signal to a high level signal, the resistance control circuit may reduce the resistance value between the first input terminal and the output node.

[0197] The resistance control circuit may further include a second transistor and a third resistor connected in series between the first input terminal and the output node.

[0198] The resistance control circuit may further include a first switch connected between the gate node of the first transistor and the safety mode signal and controlled by a first switch control signal, and a second switch connected between the gate node of the second transistor and the safety mode signal and controlled by a second switch control signal.

[0199] The safety mode driving circuit may output a safety mode signal of a high level signal after receiving the overcurrent pulse signal.

[0200] The high level period of the safety mode signal may be longer than the active period of the overcurrent pulse signal.

[0201] The safety mode driving circuit may include: a safety mode startup circuit, which is used to receive an overcurrent pulse signal; a driving time control circuit, which is used to generate a driving time control signal when the safety mode startup circuit is turned on; and a comparator circuit, which is used to compare the driving time control signal and a reference voltage and output a safety mode signal.

[0202] When the voltage level of the driving time control signal is greater than a predetermined reference value, the comparator circuit may output the safety mode signal of a high level signal.

[0203] The feedback signal output circuit may adjust a duty cycle of the feedback signal based on the first comparison signal.

[0204] The DC voltage converter may reduce the voltage level of the output voltage according to the feedback signal.

[0205] The DC voltage converter may be a buck converter.

[0206] An output voltage from the DC voltage converter may be provided to a load electrically connected to the DC voltage converter.

[0207] The load may be a load in which an overcurrent occurs.

[0208] The feedback circuit may further include a fourth resistor electrically connected between the first input terminal and a node supplied with a ground voltage.

[0209] An embodiment of the present disclosure may provide a display device, comprising: a display panel, on which a plurality of sub-pixels are arranged; and a power management circuit, which is configured to provide power to the sub-pixels. In this case, the power management circuit may include: a DC voltage converter, which is configured to generate an output voltage based on a first input voltage and output the output voltage to an output node; and a feedback circuit, which is configured to generate a feedback signal based on the output voltage output to the output node. The feedback circuit may include: an amplifier, which is used to compare a voltage provided to a first input terminal with a second input voltage provided to a second input terminal and output a first comparison signal; a feedback signal output circuit, which is configured to output a feedback signal based on the first comparison signal; and a resistance control circuit, which is electrically connected between the first input terminal and the output node. The resistance control circuit may adjust the resistance value between the first input terminal and the output node based on the safety mode signal.

[0210] The display panel may be a vehicle display panel.

[0211] The resistance control circuit may include a first resistor electrically connected between a first input terminal and an output node, and a first transistor and a second resistor connected in series between the first input terminal and the output node.

[0212] The safety mode driving circuit may output a safety mode signal of a high level signal after receiving the overcurrent pulse signal.

[0213] The safety mode driving circuit may include: a safety mode startup circuit, which is used to receive an overcurrent pulse signal; a driving time control circuit, which is used to generate a driving time control signal when the safety mode startup circuit is turned on; and a comparator circuit, which is used to compare the driving time control signal and a reference voltage and output a safety mode signal.

[0214] The DC voltage converter may reduce a voltage level of an output voltage based on the feedback signal.

[0215] An embodiment of the present disclosure provides a driving method for a display device, the driving method comprising: a safety mode driving circuit outputting a safety mode signal after receiving an overcurrent pulse signal; a resistance control circuit that receives the safety mode signal adjusting a resistance value; a feedback circuit including the resistance control circuit outputting a feedback signal; and a DC voltage converter provided with the feedback signal reducing a voltage level of an output voltage.

[0216] The above description and accompanying drawings provide examples of the technical ideas of the present disclosure for illustrative purposes only. Various modifications, additions and substitutions to the described embodiments will be apparent to those skilled in the art without departing from the spirit and scope of the present disclosure. In addition, the disclosed embodiments are intended to illustrate the scope of the technical ideas of the present disclosure. Therefore, the scope of the present disclosure is not limited to the embodiments shown.

[0217] CROSS-REFERENCE TO RELATED APPLICATIONS

[0218] This application claims the benefit of and priority to Korean Patent Application No. 10-2023-0127191 filed in Korea on September 22, 2023, the entire contents of which are hereby incorporated by reference for all purposes as if fully set forth herein.

Claims

1. A power management circuit, the power management circuit comprising: a DC voltage converter configured to generate an output voltage based on a first input voltage and output the output voltage to an output node; as well as a feedback circuit configured to generate a feedback signal based on the output voltage output to the output node, Wherein, the feedback circuit comprises: an amplifier configured to compare a second input voltage supplied to the first input terminal and a voltage supplied to the second input terminal and output a first comparison signal; a feedback signal output circuit configured to output a feedback signal based on the first comparison signal; and a resistance control circuit electrically connected between the first input terminal and the output node, and The resistance control circuit is configured to adjust a resistance value between the first input terminal and the output node based on a safety mode signal.

2. The power management circuit according to claim 1, wherein: The resistance control circuit comprises: a first resistor electrically connected between the first input terminal and the output node; and A first transistor and a second resistor are connected in series between the first input terminal and the output node.

3. The power management circuit according to claim 2, wherein: The second resistor is electrically connected between the first input terminal and the output node after the safety mode signal of a high level signal is provided to the gate node of the first transistor.

4. The power management circuit according to claim 3, wherein: When the safety mode signal changes from the low level signal to the high level signal, the resistance control circuit is further configured to reduce a resistance value between the first input terminal and the output node.

5. The power management circuit according to claim 2, wherein: The resistance control circuit also includes a second transistor and a third resistor connected in series between the first input terminal and the output node. 6 . The power management circuit according to claim 1 , further comprising a safety mode driving circuit, wherein the safety mode driving circuit is configured to output the safety mode signal of a high level signal after receiving an overcurrent pulse signal.

7. The power management circuit according to claim 6, wherein: The safety mode driving circuit comprises: a safety mode startup circuit, wherein the safety mode startup circuit is configured to receive the overcurrent pulse signal; a driving time control circuit configured to generate a driving time control signal when the safety mode startup circuit is turned on; and A comparator circuit is configured to compare the driving time control signal with a reference voltage and output the safety mode signal.

8. The power management circuit according to claim 7, wherein: When the voltage level of the driving time control signal is greater than a specific reference value, the comparator circuit is further configured to output the safety mode signal of the high level signal.

9. The power management circuit according to claim 1, wherein: The feedback signal output circuit is further configured to adjust a duty cycle of the feedback signal based on the first comparison signal.

10. The power management circuit according to claim 1, wherein: The DC voltage converter is further configured to reduce a voltage level of the output voltage based on the feedback signal.

11. The power management circuit according to claim 1, wherein: The DC voltage converter is a step-down converter.

12. The power management circuit according to claim 1, wherein: The DC voltage converter is further configured to provide the output voltage to a load electrically connected to the DC voltage converter.

13. The power management circuit according to claim 12, wherein: The load is a load in which an overcurrent occurs.

14. A display device, comprising: A display panel, the display panel comprising a plurality of sub-pixels; as well as a power management circuit configured to provide power to the sub-pixels, Wherein, the power management circuit comprises: a DC voltage converter configured to generate an output voltage based on a first input voltage and output the output voltage to an output node; and a feedback circuit configured to generate a feedback signal based on the output voltage output to the output node, Wherein, the feedback circuit comprises: an amplifier configured to compare a second input voltage supplied to the first input terminal and a voltage supplied to the second input terminal and output a first comparison signal; a feedback signal output circuit configured to output a feedback signal based on the first comparison signal; and a resistance control circuit electrically connected between the first input terminal and the output node, and The resistance control circuit is configured to adjust a resistance value between the first input terminal and the output node based on a safety mode signal.

15. The display device according to claim 14, wherein: The display panel is a vehicle display panel.

16. The display device according to claim 14, wherein: The resistance control circuit comprises: a first resistor electrically connected between the first input terminal and the output node; and A first transistor and a second resistor are connected in series between the first input terminal and the output node.

17. The display device according to claim 14, wherein: The power management circuit further includes a safety mode driving circuit configured to output the safety mode signal of a high level signal after receiving an overcurrent pulse signal.

18. The display device according to claim 17, wherein: The safety mode driving circuit comprises: a safety mode startup circuit, wherein the safety mode startup circuit is configured to receive the overcurrent pulse signal; a driving time control circuit configured to generate a driving time control signal when the safety mode startup circuit is turned on; and A comparator circuit is configured to compare the driving time control signal with a reference voltage and output the safety mode signal.

19. The display device according to claim 14, wherein: The DC voltage converter is further configured to reduce a voltage level of the output voltage based on the feedback signal.

20. A method for driving a display device, the method comprising the following steps: The safety mode driving circuit outputs a safety mode signal after receiving the overcurrent pulse signal; adjusting the resistance value by the resistance control circuit receiving the safety mode signal; Outputting a feedback signal from a feedback circuit including the resistance control circuit; as well as The voltage level of the output voltage is lowered by the DC voltage converter provided with the feedback signal.

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