Totem pole PFC synchronous rectification driving method and driving circuit

Abstract

The invention provides a totem-pole PFC synchronous rectification driving method and a driving circuit, the totem-pole PFC comprises a first switch tube, a second switch tube, a third switch tube and a fourth switch tube, the driving method comprises the following steps: in a positive half cycle, providing a first PWM signal to a control end of the second switch tube, switching on the fourth switch tube, and switching on the third switch tube; the first switch tube and the third switch tube are disconnected, when the sampling voltage on the inductor is larger than the preset first voltage, a second PWM signal is provided for the control end of the first switch tube, and the second PWM signal is opposite to the first PWM signal; in the negative half cycle, a third PWM signal is provided to the control end of the first switching tube, the third switching tube is connected, the second switching tube and the fourth switching tube are disconnected, when the sampling voltage on the inductor is smaller than a preset second voltage, a fourth PWM signal is provided to the control end of the second switching tube, and the fourth PWM signal is opposite to the third PWM signal.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuits, and in particular to a totem pole power factor correction (PFC) synchronous rectification driving method and a driving circuit. Background Art

[0002] The current totem pole PFC does not have a hardware driving solution for synchronous rectification. During freewheeling, the current flows through the body diode in parallel with the switch tube, resulting in high system losses and affecting the overall efficiency of the system. Therefore, a driving method and a driving circuit that can reduce the circuit loss of the totem pole PFC are needed. Summary of the invention

[0003] Based on the above problems in the prior art, the present invention provides a totem pole PFC synchronous rectification driving method, wherein the totem pole PFC comprises a first branch having a first switch tube and a second switch tube connected in series, and a second branch having a third switch tube and a fourth switch tube connected in series, wherein the first branch is connected in parallel with the second branch, wherein the driving method comprises:

[0004] In the positive half cycle, the first PWM signal is first provided to the control end of the second switch tube, the fourth switch tube is turned on, and the first switch tube and the third switch tube are turned off. When the sampled voltage on the inductor is greater than the predetermined first voltage, the second PWM signal is provided to the control end of the first switch tube, wherein the second PWM signal is opposite to the first PWM signal;

[0005] In the negative half cycle, the third PWM signal is first provided to the control end of the first switch tube, the third switch tube is turned on, and the second switch tube and the fourth switch tube are turned off. When the sampled voltage on the inductor is less than the predetermined second voltage, the fourth PWM signal is provided to the control end of the second switch tube, wherein the fourth PWM signal is opposite to the third PWM signal.

[0006] In one embodiment, the first voltage and the second voltage are dynamically adjusted according to the efficiency of the circuit system and the input current harmonics to maximize the efficiency.

[0007] The present invention also provides a totem pole PFC synchronous rectification driving circuit, wherein the totem pole PFC comprises a first branch having a first switch tube and a second switch tube connected in series, and a second branch having a third switch tube and a fourth switch tube connected in series, wherein the first branch is connected in parallel with the second branch, wherein the driving circuit comprises:

[0008] The first switch tube driving circuit includes:

[0009] The first voltage comparison circuit includes a third comparator, which is used to output a first control signal to the control end of the first switch tube when the sampling voltage of the inductor is greater than the first voltage, and pull the control end of the first switch tube down to a low level when the sampling voltage is less than the first voltage;

[0010] A first inverting input terminal control circuit, used for pulling down the inverting input terminal of the third comparator to a low level when the third control signal of the third switch tube is at a high level;

[0011] The second switch tube driving circuit includes:

[0012] The second voltage comparison circuit includes a first comparator, which is used to output a second control signal to the control end of the second switch tube when the sampling voltage is less than the second voltage, and pull the control end of the second switch tube down to a low level when the sampling voltage is greater than the second voltage;

[0013] The second inverting input terminal control circuit is used to pull down the inverting input terminal of the first comparator to a low level when the fourth control signal of the fourth switch tube is at a high level.

[0014] In one embodiment, the non-inverting input terminal of the third comparator is used to receive the sampled voltage, and the inverting input terminal is used to receive the first voltage. The first voltage comparison circuit further includes:

[0015] a tenth resistor connected between the non-inverting input terminal of the third comparator and the sampling voltage;

[0016] A fourteenth diode is connected between the output end of the third comparator and the control end of the first switch tube;

[0017] The sixteenth resistor is connected between the first control signal and the control end of the first switch tube.

[0018] In one embodiment, the first inverting input terminal control circuit further includes:

[0019] A twelfth switch tube is connected between the inverting input terminal of the third comparator and the ground;

[0020] A seventeenth resistor is connected between the control terminal of the twelfth switch tube and the third control signal;

[0021] The eighteenth resistor is connected between the control end of the twelfth switch tube and the ground.

[0022] In one embodiment, the non-inverting input terminal of the first comparator is used to receive the second voltage, and the inverting input terminal is used to receive the sampled voltage, and the second voltage comparison circuit further includes:

[0023] A second resistor is connected between the inverting input terminal of the first comparator and the sampling voltage;

[0024] A twelfth diode is connected between the output end of the first comparator and the control end of the second switch tube;

[0025] The seventh resistor is connected between the second control signal and the control end of the second switch tube.

[0026] In one embodiment, the second inverting input terminal control circuit further includes:

[0027] An eleventh switch tube is connected between the inverting input terminal of the first comparator and the ground;

[0028] an eighth resistor, connected between the control terminal of the eleventh switch tube and the fourth control signal;

[0029] The ninth resistor is connected between the control terminal of the eleventh switch tube and the ground.

[0030] In one embodiment, the first switch tube driving circuit further includes a first ripple control circuit, which is used to clamp the output of the third comparator within a switching cycle of the first control signal.

[0031] In one embodiment, the first ripple control circuit comprises:

[0032] a fourth comparator, whose non-inverting input terminal is used to receive the fourth reference voltage, whose inverting input terminal is used to receive the first control signal, and whose output terminal is connected to the output terminal of the third comparator;

[0033] a fourteenth resistor connected between the non-inverting input terminal of the fourth comparator and the fourth reference voltage;

[0034] a thirteenth resistor connected between the non-inverting input terminal of the fourth comparator and the output terminal of the fourth comparator;

[0035] a fifteenth resistor connected between the inverting input terminal of the fourth comparator and ground;

[0036] Among them, the fourth reference voltage, the fourteenth resistor and the thirteenth resistor are selected so that when the third comparator outputs a low level, the voltage at the non-inverting input terminal of the fourth comparator is less than the voltage at the inverting input terminal, and when the third comparator outputs a high level, the voltage at the non-inverting input terminal of the fourth comparator is greater than the voltage at the inverting input terminal.

[0037] In one embodiment, the second switch tube driving circuit further includes a second ripple control circuit, which is used to clamp the output of the first comparator within a switching cycle of the second control signal.

[0038] In one embodiment, the second ripple control circuit comprises:

[0039] A second comparator, whose non-inverting input terminal is used to receive a second reference voltage, whose inverting input terminal is used to receive a second control signal, and whose output terminal is connected to the output terminal of the first comparator;

[0040] a fifth resistor connected between the non-inverting input terminal of the second comparator and the second reference voltage;

[0041] A fourth resistor is connected between the non-inverting input terminal of the second comparator and the output terminal of the second comparator;

[0042] a sixth resistor connected between the inverting input terminal of the second comparator and ground;

[0043] Among them, the second reference voltage, the fourth resistor and the fifth resistor are selected so that when the first comparator outputs a low level, the voltage at the non-inverting input terminal of the second comparator is less than the voltage at the inverting input terminal, and when the first comparator outputs a high level, the voltage at the non-inverting input terminal of the second comparator is greater than the voltage at the inverting input terminal.

[0044] The totem pole PFC synchronous rectification driving method and driving circuit of the present invention can reduce the loss of the switch tube during the freewheeling period and improve the efficiency of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A schematic diagram of a totem pole power factor correction (PFC) circuit in the prior art is shown.

[0046] Figure 2 The figure shows the current path when the switch tube S2 is turned on in the positive half cycle of the power supply.

[0047] Figure 3 The figure shows the current path when the switch tube S2 is turned off in the positive half cycle of the power supply.

[0048] Figure 4 The figure shows the current path when the switch tube S2 is turned off and the switch tube S1 is turned on in the positive half cycle of the power supply when the inductor current is small and the power supply voltage is low.

[0049] Figure 5 The figure shows the current path when the switch tube S1 is turned on in the negative half cycle of the power supply.

[0050] Figure 6 The figure shows the current path when the switch tube S1 is turned off in the negative half cycle of the power supply.

[0051] Figure 7 The figure shows the current path when the switch tube S1 is turned off and the switch tube S2 is turned on in the negative half cycle of the power supply when the inductor current is small and the power supply voltage is low.

[0052] Figure 8A flow chart of a totem pole PFC synchronous rectification driving method according to an embodiment of the present invention is shown.

[0053] Fig. 9 A schematic diagram showing different signals in the totem pole PFC synchronous rectification driving method of the present invention is shown.

[0054] Fig.10 A totem pole PFC synchronous rectification driving circuit according to an embodiment of the present invention is shown.

[0055] Fig.11 Shows Figure 1 Loss simulation results for the totem-pole PFC circuit shown in .

[0056] Fig.12 The figure shows the loss simulation results of the totem pole PFC synchronous rectification driving method of the present invention. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention will be further described in detail below through specific embodiments in conjunction with the accompanying drawings. It should be noted that the embodiments given in the present invention are only for illustration and do not limit the scope of protection of the present invention.

[0058] Figure 1 FIG. 1 is a schematic diagram of a totem pole power factor correction (PFC) circuit in the prior art. Figure 1 As shown, the totem pole PFC circuit is used to power a load 102, which includes a power supply 101, an inductor L1, switch tubes S1-S4 and a DC bus capacitor C BUS The switches S1 and S2 are connected in series, and the switches S3 and S4 are connected in series. One end of the inductor L1 is connected to the positive electrode of the power supply 101, and the other end is connected to the node between the switches S1 and S2. The negative electrode of the power supply 101 is connected to the node between the switches S3 and S4. The capacitor C BUS The switch tubes S1 and S2 are connected in parallel with the switch tubes S3 and S4. The power supply 101 is an AC power supply, such as a mains supply. The switch tubes S1, S2, S3, and S4 have control terminals for receiving control signals, and each has a body diode D1, D2, D3, and D4 connected in parallel with the corresponding switch tube.

[0059] In one embodiment, the switches S1 and S2 are fast-switching SiC-MOSFET devices (operating at a high carrier frequency), and the switches S3 and S4 are conventional low-speed Si-MOSFET devices (operating at 50 Hz or 60 Hz).

[0060] In the positive half cycle of the power supply, the switch tube S2 is used as the main switch, the switch tube S1 is used as the synchronous rectification switch, and the switch tube S4 is always turned on and acts as a resistor. The control end of the switch tube S2 is used to receive the PWM signal to control the switch tube S2 to be turned on and off periodically. Figure 2 Figure 2 shows the current path when the switch tube S2 is turned on in the positive half cycle of the power supply. Figure 2 As shown, the current path is the positive electrode of the power supply 101 - inductor L1 - switch tube S2 - switch tube S4 - negative electrode of the power supply 101. When the switch tube S2 is turned on, the AC power supply 101 stores energy in the inductor L1, and the output capacitor C BUS Provides load current. Figure 3 Figure 2 shows the current path when the switch tube S2 is turned off in the positive half cycle of the power supply. Figure 3 As shown, the current path is the positive electrode of the power supply 101 - the inductor L1 - the body diode D1 of the switch tube S1 - the capacitor C BUS - Switch tube S4 - Negative pole of power supply 101. When switch tube S2 is turned off, the AC power supply and energy in inductor L1 provide load current and output capacitor C BUS Charge.

[0061] Depend on Figure 3 It can be seen that when the switch tube S2 is turned off, the current path passes through the body diode D1 of the switch tube S1, which increases the circuit loss and reduces the overall efficiency. The purpose of reducing the loss can be achieved by turning on the switch tube S1 so that the current path directly passes through the switch tube S1 instead of the body diode D1 of the switch tube S1. However, the inventors found that when the inductor current is small and the power supply voltage is low, turning on the switch tube S1 when the switch tube S2 is turned off will cause the output capacitor C to be lost. BUS The energy on the circuit leads to reduced circuit efficiency. Figure 4 FIG. 2 shows the current path when the switch tube S2 is turned off and the switch tube S1 is turned on in the positive half cycle of the power supply when the inductor current is small and the power supply voltage is low. Figure 4 As shown, there will be the following current path: negative pole of power supply 101 - switch tube S4 - capacitor C BUS -Switch tube S1-Inductor L1-Positive pole of power supply 101. When the voltage of the power supply is small in the positive half cycle of the power supply, that is, the energy stored on the inductor L1 is insufficient, there will be a voltage from the capacitor C BUS The reverse current of the power supply 101 consumes the capacitor C BUS The energy on the circuit leads to reduced circuit efficiency.

[0062] Similarly, in the negative half cycle, switch S1 is used as the main switch, switch S2 is used as the synchronous rectification switch, and switch S3 is always turned on and acts as a resistor. The control terminal of switch S1 is used to receive a PWM signal to control switch S1 to be periodically turned on and off. Figure 5 Figure 2 shows the current path when the switch S1 is turned on during the negative half cycle of the power supply. Figure 5 As shown, the current path is the negative electrode of the power supply 101 - the switch tube S3 - the switch tube S1 - the inductor L1 - the positive electrode of the power supply 101. When the switch tube S1 is turned on, the AC power supply 101 stores energy in the inductor L1, and the output capacitor C BUS Provides load current. Figure 6 Figure 2 shows the current path when the switch tube S1 is turned off during the negative half cycle of the power supply. Figure 6 As shown, the current path is the negative electrode of the power supply 101 - the switch tube S3 - the capacitor C BUS -Body diode D2 of switch tube S2 -Inductor L1 -Positive terminal of power supply 101. When switch tube S1 is turned off, the AC power supply and energy in inductor L1 provide load current and output capacitor C BUS Charge.

[0063] Depend on Figure 6 It can be seen that when the switch tube S1 is turned off, the current path passes through the body diode D2 of the switch tube S2, which increases the circuit loss and reduces the overall efficiency. The purpose of reducing the loss can be achieved by turning on the switch tube S2 so that the current path directly passes through the switch tube S2 instead of the body diode D2 of the switch tube S2. However, the inventors found that when the inductor current is small and the power supply voltage is low, turning on the switch tube S2 when the switch tube S1 is turned off will cause the output capacitor C to be lost. BUS The energy on the circuit leads to reduced circuit efficiency. Figure 7 FIG. 2 shows the current path when the switch tube S1 is turned off and the switch tube S2 is turned on during the negative half cycle of the power supply when the inductor current is small and the power supply voltage is low. Figure 7 As shown, there will be the following current path: positive pole of power supply 101 - inductor L1 - switch tube S2 - capacitor C BUS - Switch tube S3 - Negative pole of power supply 101. When the voltage of the power supply is small in the negative half cycle of the power supply, that is, when the energy stored on the inductor L1 is insufficient, there will be a BUS The reverse current of the power supply 101 consumes the capacitor C BUS The energy on the circuit leads to reduced circuit efficiency.

[0064] Based on the above content, the present invention provides a totem pole PFC synchronous rectification driving method. Figure 8 A flow chart of a totem pole PFC synchronous rectification driving method according to an embodiment of the present invention is shown, the method comprising:

[0065] In the positive half cycle, the first PWM signal PWM1 is first provided to the control end of the switch tube S2, the switch tube S4 is turned on, and the switch tubes S1 and S3 are turned off. When the sampled voltage on the inductor L1 is greater than the predetermined first voltage V1, the second PWM signal PWM2 is provided to the control end of the switch tube S1, wherein the second PWM signal PWM2 is opposite to the first PWM signal PWM1. In one embodiment, the first PWM signal PWM1 is a BOOST high-frequency switching signal, and the second PWM signal PWM2 is a synchronous rectification high-frequency switching signal.

[0066] In the negative half cycle, the third PWM signal PWM3 is first provided to the control end of the switch tube S1, the switch tube S3 is turned on, and the switch tubes S2 and S4 are turned off. When the sampled voltage on the inductor L1 is less than the predetermined second voltage V2, the fourth PWM signal PWM4 is provided to the control end of the switch tube S2, wherein the fourth PWM signal PWM4 is opposite to the third PWM signal PWM3. In one embodiment, the third PWM signal PWM3 is a BOOST rectifier high-frequency switch signal, and the fourth PWM signal PWM4 is a synchronous rectifier high-frequency switch signal.

[0067] The synchronous rectification interval can be controlled by configuring the amplitude of the first voltage V1 and the second voltage V2. The first voltage V1 and the second voltage V2 are selected to avoid Figure 4 and Figure 7 The current path shown in .

[0068] The sampling voltage Vs on the inductor L1 is obtained by detecting the sampling current on the inductor L1, converting it into a voltage and then superimposing a DC voltage signal, so that the sampling voltage Vs is a positive value. The method for obtaining the sampling voltage Vs is a known technology in the art and will not be described in detail here.

[0069] Fig. 9 The schematic diagram of different signals in the totem pole PFC synchronous rectification driving method of the present invention is shown, wherein the power supply voltage Vin, the sampling voltage Vs, the first voltage V1, the second voltage V2, the superimposed DC voltage signal V0, the control signal Ctr1 of the first switch tube, the control signal Ctr2 of the second switch tube, the control signal Ctr3 of the third switch tube, and the control signal Ctr4 of the fourth switch tube are shown. Fig. 9 As shown, 0-T2 is the positive half cycle, and T2-T5 is the negative half cycle. Fig. 9 The totem pole PFC synchronous rectification driving method of the present invention is further described.

[0070] During the period 0-T0, the switch tube S2 receives the first PWM signal PWM1, the switch tube S4 is turned on, and the switch tube S3 is turned off. At this time, since the sampling voltage Vs is less than the first voltage V1, the switch tube S1 is turned off.

[0071] During T0-T1, switch S2 receives the first PWM signal PWM1, switch S4 is turned on, and switch S3 is turned off. At this time, since the sampling voltage Vs is greater than the first voltage V1, switch S1 is turned on and receives the second PWM signal PWM2.

[0072] During the period T1 - T2 , the switch tube S2 receives the first PWM signal PWM1 , the switch tube S4 is turned on, and the switch tube S3 is turned off. At this time, since the sampling voltage Vs is less than the first voltage V1 , the switch tube S1 is turned off.

[0073] Therefore, in the positive half cycle, the switch tube S1 is turned on only during T0-T1 and is turned off during 0-T0 and T1-T2 when the power supply voltage is small, thus avoiding the situation where the capacitor C is insufficiently charged when the power supply voltage is small, that is, when the energy stored on the inductor L1 is insufficient. BUS The reverse current of the power supply 101 is avoided to consume the capacitor C BUS The energy on the circuit is improved.

[0074] During the period T2-T3, the switch tube S1 receives the third PWM signal PWM3, the switch tube S3 is turned on, and the switch tube S4 is turned off. At this time, since the sampling voltage Vs is greater than the second voltage V2, the switch tube S2 is turned off.

[0075] During T3-T4, the switch tube S1 receives the third PWM signal PWM3, the switch tube S3 is turned on, and the switch tube S4 is turned off. At this time, since the sampling voltage Vs is less than the second voltage V2, the switch tube S2 is turned on and receives the fourth PWM signal PWM4.

[0076] During the period T4-T5, the switch tube S1 receives the third PWM signal PWM3, the switch tube S3 is turned on, and the switch tube S4 is turned off. At this time, since the sampling voltage Vs is greater than the second voltage V2, the switch tube S2 is turned off.

[0077] Therefore, in the negative half cycle, the switch tube S2 is turned on only during T3-T4 and is turned off during T2-T3 and T4-T5 when the power supply voltage amplitude is small, avoiding the presence of capacitor C when the power supply voltage is small, that is, when the energy storage on the inductor L1 is insufficient. BUS The reverse current of the power supply 101 is avoided to consume the capacitor C BUS The energy on the circuit is improved.

[0078] In summary, the driving signal of switch tube S4 is normally high in the positive half cycle and normally low in the negative half cycle. The driving signal of switch tube S3 is opposite to the driving signal of switch tube S4, which is normally low in the positive half cycle and normally high in the negative half cycle. The driving signal of switch tube S2 from 0 to T2 is a BOOST high-frequency switching signal, and the driving signal from T3 to T4 is a synchronous rectification high-frequency switching signal. The driving signal of switch tube S1 from T0 to T1 is a synchronous rectification high-frequency switching signal, and the driving signal from T2 to T5 is a BOOST rectification high-frequency switching signal.

[0079] The selection of the first voltage V1 and the second voltage V2 will affect the efficiency and input current harmonics of the system. The values ​​of the first voltage V1 and the second voltage V2 can be dynamically adjusted to maximize the efficiency of the system. In one embodiment, the first voltage V1 and the second voltage V2 can be initially set to the voltage at the 50% position of the sampled voltage amplitude, and then synchronous rectification is started, and the first voltage V1 and the second voltage V2 are dynamically adjusted according to the efficiency and input current harmonics of the system to maximize the efficiency of the system. In another embodiment, the first voltage V1 and the second voltage V2 are fixed values.

[0080] The totem pole PFC synchronous rectification driving method of the present invention can be implemented by software or hardware. In one embodiment, a PWM signal for driving the switch tubes S1 and S2 can be designed by a digital signal processor (DSP) to implement the method of the present invention. In another embodiment, a corresponding hardware driving circuit can be designed to implement the method of the present invention.

[0081] Fig.10 A totem pole PFC synchronous rectification driving circuit according to an embodiment of the present invention is shown. The driving circuit has two parts, the driving circuit of the upper part is connected to the control end of the switch tube S2, and is used to drive the switch tube S2, and the driving circuit of the lower part is connected to the control end of the switch tube S1, and is used to drive the switch tube S1.

[0082] The driving circuit of the switch tube S2 includes a voltage comparison circuit, which includes a comparator CMP1, which is used to output a control signal Ctr2 to the control end of the switch tube S2 when the sampling voltage Vs is less than the second voltage V2, and pull down the control end of the switch tube S2 to a low level when the sampling voltage Vs is greater than the second voltage V2. In one embodiment, the non-inverting input end of the comparator CMP1 is used to receive the second voltage V2, and the inverting input end of the comparator CMP1 receives the sampling voltage Vs through a resistor R2, the resistor R1 is connected between the first reference voltage Vref1 (for example, 5V) and the second voltage V2, and the resistor R3 is connected between the second voltage V2 and the ground. The cathode of the diode D12 is connected to the output end of the comparator CMP1, and the anode of the diode D12 is connected to the control end of the switch tube S2. The control signal Ctr2 of the switch tube S2 is connected to the control end of the switch tube S2 through a resistor R7. Among them, by configuring the first reference voltage Vref1, the resistor R1 and the resistor R3, the voltage of the non-inverting input end of the comparator CMP1 is the second voltage V2.

[0083] The driving circuit of the switch tube S2 also includes an inverting input terminal control circuit, which is used to pull down the inverting input terminal of the comparator CMP1 to a low level when the control signal Ctr4 of the switch tube S4 is at a high level. In one embodiment, the inverting input terminal control circuit includes a switch tube Q11, the switch tube Q11 is connected between the inverting input terminal of the comparator CMP1 and the ground, and the control terminal of the switch tube Q11 is connected to the control signal Ctr4 of the switch tube S4 via a resistor R8. The resistor R9 is connected between the control terminal of the switch tube Q11 and the ground. When the control signal Ctr4 is at a high level, the switch tube Q11 is turned on, and when the control signal Ctr4 is at a low level, the switch tube Q11 is turned off.

[0084] During the period 0-T2, the control signal Ctr4 is at a high level, the inverting input terminal of the comparator CMP1 is pulled down to a low level, and the voltage at the non-inverting input terminal of the comparator CMP1 is greater than the voltage at the inverting input terminal. Therefore, the comparator CMP1 outputs a high level, and the control signal Ctr2 is output to the switch tube S2, wherein the control signal Ctr2 is the first PWM signal PWM1.

[0085] During T2-T3, the control signal Ctr4 is at a low level, the sampling voltage Vs is greater than the second voltage V2, and the voltage at the non-inverting input terminal of the comparator CMP1 is less than the voltage at the inverting input terminal. Therefore, the comparator CMP1 outputs a low level, so the control terminal of the switch tube S2 is pulled low and the switch tube S2 is disconnected.

[0086] During T3-T4, the control signal Ctr4 is at a low level, the sampling voltage Vs is less than the second voltage V2, and the voltage at the non-inverting input terminal of the comparator CMP1 is greater than the voltage at the inverting input terminal. Therefore, the comparator CMP1 outputs a high level, and the control signal Ctr2 is output to the switch tube S2, wherein the control signal Ctr2 is the fourth PWM signal PWM4 at this time.

[0087] During T4-T5, the control signal Ctr4 is at a low level, the sampling voltage Vs is greater than the second voltage V2, and the voltage at the non-inverting input terminal of the comparator CMP1 is less than the voltage at the inverting input terminal. Therefore, the comparator CMP1 outputs a low level, so the control terminal of the switch tube S2 is pulled low and the switch tube S2 is disconnected.

[0088] However, when the sampling voltage Vs has ripples, the sampling voltage is unstable and has non-periodic changes. Therefore, within a switching cycle of the control signal Ctr2 of the switch tube S2, the switch tube S2 may be controlled to be turned on and off multiple times, affecting the normal operation of the circuit. Therefore, the present invention also provides a ripple control circuit.

[0089] The driving circuit of the switch tube S2 also includes a ripple control circuit, which is used to clamp the output of the comparator CMP1 at a low level or a high level within a switching cycle of the control signal Ctrl2. In one embodiment, the ripple control circuit includes a comparator CMP2, a non-inverting input terminal of the comparator CMP2 receives a second reference voltage Vref2 (for example, 5V) through a resistor R5, an inverting input terminal receives a control signal Ctr2 through a diode D11, and an output terminal is connected to the output terminal of CMP1. In one embodiment, the diode D11 can be omitted. The resistor R4 is connected between the non-inverting input terminal and the output terminal of the comparator CMP2, and the resistor R6 is connected between the inverting input terminal of the comparator CMP2 and the ground.

[0090] Assuming that the resistance values ​​of resistors R4 and R5 are the same, when the comparator CMP1 outputs a low level, the voltage at the non-inverting input terminal of CMP2 is the second reference voltage / 2 (for example, 2.5V), and at this time the control signal Ctr2 is a high level (when Ctr2 is a low level, the switch tube S2 is in a disconnected state, so there is no need to consider this situation), and the voltage at the non-inverting input terminal of the comparator CMP2 is less than the voltage at the inverting input terminal, so the comparator CMP2 outputs a low level, that is, the output of the comparator CMP1 is clamped to a low level, and the output of the comparator CMP1 will not change, even if the sampling voltage Vs fluctuates under the action of the ripple, it will not affect the output of the comparator CMP1.

[0091] When the comparator CMP1 outputs a high level, if the output of the comparator CMP1 jumps to a low level due to the presence of the ripple voltage, the comparator CMP2 will clamp the output of the comparator CMP1 to a low level until the next switching cycle of the control signal Ctr2. The comparator CMP2 ensures that even if the sampling voltage Vs fluctuates near the second voltage V2, a switching cycle will not occur, and the switch tube S2 is controlled to be turned on and off multiple times.

[0092] Among them, the second reference voltage Vref2, the resistor R4 and the resistor R5 are selected so that when the comparator CMP1 outputs a low level, the voltage at the non-inverting input terminal of CMP2 is less than the voltage at the inverting input terminal, and when the comparator CMP1 outputs a high level, the voltage at the non-inverting input terminal of CMP2 is greater than the voltage at the inverting input terminal.

[0093] The driving circuit of the switch tube S1 includes a voltage comparison circuit, including a comparator CMP3, which is used to output a control signal Ctr1 to the control end of the switch tube S1 when the sampling voltage Vs is greater than the first voltage V1, and pull down the control end of the switch tube S1 to a low level when the sampling voltage Vs is less than the first voltage V1. In one embodiment, the non-inverting input end of the comparator CMP3 receives the sampling voltage Vs through a resistor R10, the inverting input end of the comparator CMP3 is used to receive the first voltage V1, the resistor R11 is connected between the third reference voltage Vref3 (for example, 5V) and the first voltage V1, and the resistor R12 is connected between the first voltage V1 and the ground. The cathode of the diode D14 is connected to the output end of the comparator CMP3, and the anode of the diode D14 is connected to the control end of the switch tube S1. The control signal Ctr1 of the switch tube S1 is connected to the control end of the switch tube S1 through a resistor R16. Among them, by configuring the third reference voltage Vref3, the resistor R11 and the resistor R12 make the voltage of the inverting input end of the comparator CMP3 the first voltage V1.

[0094] The driving circuit of the switch tube S1 also includes an inverting input terminal control circuit, which is used to pull down the inverting input terminal of the comparator CMP3 to a low level when the control signal Ctr3 of the switch tube S3 is at a high level. In one embodiment, the inverting input terminal control circuit includes a switch tube Q12, which is connected between the inverting input terminal of the comparator CMP3 and the ground, and the control terminal of the switch tube Q12 receives the control signal Ctr3 of the switch tube S3 via the resistor R17. The resistor R18 is connected between the control terminal of the switch tube Q12 and the ground. When the control signal Ctr3 is at a high level, the switch tube Q12 is turned on, and when the control signal Ctr3 is at a low level, the switch tube Q12 is turned off.

[0095] During 0-T0, the control signal Ctr3 is at a low level, the sampling voltage Vs is less than the first voltage V1, and the voltage at the non-inverting input terminal of the comparator CMP3 is less than the voltage at the inverting input terminal. Therefore, the comparator CMP3 outputs a low level, so the control terminal of the switch tube S1 is pulled low and the switch tube S1 is disconnected.

[0096] During T0-T1, the control signal Ctr3 is at a low level, the sampling voltage Vs is greater than the first voltage V1, and the voltage at the non-inverting input terminal of the comparator CMP3 is greater than the voltage at the inverting input terminal. Therefore, the comparator CMP3 outputs a high level, and the control signal Ctr1 is output to the switch tube S1, wherein the control signal Ctr1 is the second PWM signal PWM2 at this time.

[0097] During T1-T2, the control signal Ctr3 is at a low level, the sampling voltage Vs is less than the first voltage V1, and the voltage at the non-inverting input terminal of the comparator CMP3 is less than the voltage at the inverting input terminal. Therefore, the comparator CMP3 outputs a low level, the control terminal of the switch tube S1 is pulled low, and the switch tube S1 is disconnected.

[0098] During T2-T5, the control signal Ctr3 is at a high level, the inverting input terminal of the comparator CMP3 is pulled down to a low level, and the voltage at the non-inverting input terminal of the comparator CMP3 is greater than the voltage at the inverting input terminal. Therefore, the comparator CMP3 outputs a high level, and the control signal Ctr1 is output to the switch tube S1, wherein the control signal Ctr1 is the third PWM signal PWM3.

[0099] However, when the sampling voltage has ripples, the sampling voltage is unstable and has non-periodic changes. Therefore, in one switching cycle of the control signal Ctr1 of the switch tube S1, the switch tube S1 may be controlled to be turned on and off multiple times, affecting the normal operation of the circuit. Therefore, the present invention also provides a ripple control circuit.

[0100] The driving circuit of the switch tube S1 also includes a ripple control circuit, which is used to clamp the output of the comparator CMP3 at a low level or a high level within a switching cycle of the control signal Ctrl1. In one embodiment, the ripple control circuit includes a comparator CMP4, a non-inverting input terminal of the comparator CMP4 receives a fourth reference voltage Vref4 (for example, 5V) through a resistor R14, an inverting input terminal receives a control signal Ctr1 through a diode D13, and an output terminal is connected to the output terminal of CMP3. The resistor R13 is connected between the non-inverting input terminal and the output terminal of the comparator CMP4, and the resistor R15 is connected between the inverting input terminal of the comparator CMP2 and the ground.

[0101] Assuming that the resistance values ​​of the resistors R14 and R13 are the same, when the comparator CMP3 outputs a low level, the voltage at the non-inverting input terminal of CMP4 is the fourth reference voltage / 2 (for example, 2.5V), and at this time the control signal Ctr1 is a high level (when Ctr1 is a low level, the switch tube S1 is in a disconnected state, so there is no need to consider this situation), and the voltage at the non-inverting input terminal of the comparator CMP4 is less than the voltage at the inverting input terminal, so the comparator CMP4 outputs a low level, that is, the output of the comparator CMP3 is clamped to a low level, and even if the sampling voltage Vs fluctuates under the action of the ripple, it will not affect the output of the comparator CMP3.

[0102] When the comparator CMP3 outputs a high level, if the output of the comparator CMP3 jumps to a low level due to the presence of the ripple voltage, the comparator CMP4 will clamp the output of the comparator CMP3 to a low level until the next switching cycle of the control signal Ctr1. The comparator CMP4 ensures that even if the sampling voltage Vs fluctuates near the first voltage V1, a switching cycle will not occur, and the switch tube S1 is controlled to be turned on and off multiple times.

[0103] Among them, the fourth reference voltage Vref4, the resistor R14 and the resistor R13 are selected so that when the comparator CMP3 outputs a low level, the voltage at the non-inverting input terminal of CMP4 is less than the voltage at the inverting input terminal, and when the comparator CMP3 outputs a high level, the voltage at the non-inverting input terminal of CMP4 is greater than the voltage at the inverting input terminal.

[0104] In one embodiment, if the ripple of the sampling voltage can be removed by other means, the ripple control circuit can be omitted.

[0105] Fig.11 Shows Figure 1 The loss simulation results of the totem pole PFC circuit shown in Figure 1 are shown in Figure 2. The power supply voltage is 160V and the capacitor C BUS The voltage across the two ends is 360V, the load of PFC is 1KW, and the switch tubes S1 and S2 use the Sic Mos device C3M0045065K. When the driving method and driving circuit of the present invention are not used, the loss of the switch tube S2 during the freewheeling period is 12.19W through simulation analysis. Fig.12 The loss simulation results of the totem pole PFC synchronous rectification driving method of the present invention are shown. The simulation analysis shows that the loss of the switch tube S2 during the freewheeling period is 3.81W (the inductor current is greater than 5A, and the input synchronous rectification PWM).

[0106] The totem pole PFC synchronous rectification driving method and driving circuit of the present invention can reduce the loss of the switch tube during the freewheeling period and improve the efficiency of the system. In addition, the totem pole PFC synchronous rectification driving method and driving circuit of the present invention are simple to control. When the power supply passes through zero point or is lightly loaded, there is no situation where the DC bus discharges to the power supply, and the energy on the DC bus is not consumed, thereby improving the overall efficiency.

[0107] Although the present invention has been described through preferred embodiments, the present invention is not limited to the embodiments described herein but includes various changes and modifications that may be made without departing from the scope of the present invention.

Claims

1. A totem pole PFC synchronous rectification driving method, the totem pole PFC comprising a first branch having a first switch tube and a second switch tube connected in series and a second branch having a third switch tube and a fourth switch tube connected in series, the first branch and the second branch are connected in parallel, wherein: The driving method comprises: In the positive half cycle, the first PWM signal is first provided to the control end of the second switch tube, the fourth switch tube is turned on, and the first switch tube and the third switch tube are turned off. When the sampled voltage on the inductor is greater than the predetermined first voltage, the second PWM signal is provided to the control end of the first switch tube, wherein the second PWM signal is opposite to the first PWM signal; In the negative half cycle, the third PWM signal is first provided to the control end of the first switch tube, the third switch tube is turned on, and the second switch tube and the fourth switch tube are turned off. When the sampled voltage on the inductor is less than the predetermined second voltage, the fourth PWM signal is provided to the control end of the second switch tube, wherein the fourth PWM signal is opposite to the third PWM signal.

2. The totem pole PFC synchronous rectification driving method according to claim 1, wherein: The first voltage and the second voltage are dynamically adjusted according to the efficiency of the circuit system and the input current harmonics to maximize the efficiency.

3. A totem pole PFC synchronous rectification driving circuit, the totem pole PFC comprising a first branch having a first switch tube and a second switch tube connected in series and a second branch having a third switch tube and a fourth switch tube connected in series, the first branch and the second branch are connected in parallel, wherein: The driving circuit comprises: The first switch tube driving circuit includes: The first voltage comparison circuit includes a third comparator, which is used to output a first control signal to the control end of the first switch tube when the sampling voltage of the inductor is greater than the first voltage, and pull the control end of the first switch tube down to a low level when the sampling voltage is less than the first voltage; A first inverting input terminal control circuit, used for pulling down the inverting input terminal of the third comparator to a low level when the third control signal of the third switch tube is at a high level; The second switch tube driving circuit includes: The second voltage comparison circuit includes a first comparator, which is used to output a second control signal to the control end of the second switch tube when the sampling voltage is less than the second voltage, and pull the control end of the second switch tube down to a low level when the sampling voltage is greater than the second voltage; The second inverting input terminal control circuit is used to pull down the inverting input terminal of the first comparator to a low level when the fourth control signal of the fourth switch tube is at a high level.

4. The totem pole PFC synchronous rectification driving circuit according to claim 3, wherein: The non-inverting input terminal of the third comparator is used to receive the sampled voltage, and the inverting input terminal is used to receive the first voltage. The first voltage comparison circuit also includes: a tenth resistor connected between the non-inverting input terminal of the third comparator and the sampling voltage; A fourteenth diode is connected between the output end of the third comparator and the control end of the first switch tube; The sixteenth resistor is connected between the first control signal and the control end of the first switch tube.

5. The totem pole PFC synchronous rectification driving circuit according to claim 3, wherein: The first inverting input terminal control circuit further includes: A twelfth switch tube is connected between the inverting input terminal of the third comparator and the ground; A seventeenth resistor is connected between the control terminal of the twelfth switch tube and the third control signal; The eighteenth resistor is connected between the control end of the twelfth switch tube and the ground.

6. The totem pole PFC synchronous rectification driving circuit according to claim 3, wherein: The non-inverting input terminal of the first comparator is used to receive the second voltage, and the inverting input terminal is used to receive the sampled voltage. The second voltage comparison circuit also includes: A second resistor is connected between the inverting input terminal of the first comparator and the sampling voltage; A twelfth diode is connected between the output end of the first comparator and the control end of the second switch tube; The seventh resistor is connected between the second control signal and the control end of the second switch tube.

7. The totem pole PFC synchronous rectification driving circuit according to claim 3, wherein: The second inverting input terminal control circuit further includes: An eleventh switch tube is connected between the inverting input terminal of the first comparator and the ground; an eighth resistor, connected between the control terminal of the eleventh switch tube and the fourth control signal; The ninth resistor is connected between the control terminal of the eleventh switch tube and the ground.

8. The totem pole PFC synchronous rectification driving circuit according to claim 3, wherein: The first switch tube driving circuit also includes a first ripple control circuit, which is used to clamp the output of the third comparator within a switching cycle of the first control signal.

9. The totem pole PFC synchronous rectification driving circuit according to claim 8, wherein: The first ripple control circuit comprises: a fourth comparator, whose non-inverting input terminal is used to receive the fourth reference voltage, whose inverting input terminal is used to receive the first control signal, and whose output terminal is connected to the output terminal of the third comparator; a fourteenth resistor connected between the non-inverting input terminal of the fourth comparator and the fourth reference voltage; a thirteenth resistor connected between the non-inverting input terminal of the fourth comparator and the output terminal of the fourth comparator; a fifteenth resistor connected between the inverting input terminal of the fourth comparator and ground; Among them, the fourth reference voltage, the fourteenth resistor and the thirteenth resistor are selected so that when the third comparator outputs a low level, the voltage at the non-inverting input terminal of the fourth comparator is less than the voltage at the inverting input terminal, and when the third comparator outputs a high level, the voltage at the non-inverting input terminal of the fourth comparator is greater than the voltage at the inverting input terminal.

10. The totem pole PFC synchronous rectification driving circuit according to claim 3, wherein: The second switch tube driving circuit also includes a second ripple control circuit, which is used to clamp the output of the first comparator within a switching cycle of the second control signal.

11. The totem pole PFC synchronous rectification driving circuit according to claim 10, wherein: The second ripple control circuit comprises: A second comparator, whose non-inverting input terminal is used to receive a second reference voltage, whose inverting input terminal is used to receive a second control signal, and whose output terminal is connected to the output terminal of the first comparator; a fifth resistor connected between the non-inverting input terminal of the second comparator and the second reference voltage; A fourth resistor is connected between the non-inverting input terminal of the second comparator and the output terminal of the second comparator; a sixth resistor connected between the inverting input terminal of the second comparator and ground; Among them, the second reference voltage, the fourth resistor and the fifth resistor are selected so that when the first comparator outputs a low level, the voltage at the non-inverting input terminal of the second comparator is less than the voltage at the inverting input terminal, and when the first comparator outputs a high level, the voltage at the non-inverting input terminal of the second comparator is greater than the voltage at the inverting input terminal.

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