Control method, device, medium and product of DC-DC module

Abstract

The embodiment of the application relates to the technical field of digital signal processing, and discloses a control method, equipment, medium and product of a DC-DC module. The method comprises the following steps: sampling electrical parameters of the DC-DC module and judging, through a comparator circuit, whether a current working mode is a Buck mode or a Boost mode; calculating a deviation between an output voltage and a target voltage in real-time electrical parameters, generating a PWM duty cycle adjustment signal, and generating a plurality of interleaved PWM drive signals through a phase-shifting circuit; performing power distribution on the plurality of interleaved PWM drive signals, adjusting the conduction time of each switch tube, and obtaining a current-sharing control signal; and analyzing the real-time electrical parameters, the current working mode, the PWM duty cycle adjustment signal, the plurality of interleaved PWM drive signals and the current-sharing control signal, and obtaining a dynamic adjustment strategy. The method can at least solve the technical problem of low accuracy and efficiency of the control of the DC-DC module.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of digital signal processing, and particularly relates to a control method, device, medium and product of a DC-DC module. BACKGROUND

[0002] As a key component in power electronic systems, DC-DC converters are widely used in new energy generation, electric vehicles, aerospace, and other fields. Traditional DC-DC converter control methods mainly use fixed-frequency PWM control, sliding mode control, or predictive control techniques. These methods achieve stable output voltage by adjusting the on-time of the switching tube. With the development of power electronics technology, multi-phase parallel DC-DC converters have gradually become the mainstream choice for high-power applications due to their advantages such as current stress dispersion, uniform heat loss, and small output ripple. In multi-phase parallel systems, master-slave control, circulating current control, or distributed control strategies are often used to achieve current sharing among phases.

[0003] However, existing DC-DC converter control methods still have some shortcomings. First, in scenarios with frequent switching between operating modes, traditional control strategies are difficult to respond quickly, which can lead to output voltage fluctuations or system instability. Second, current sharing control in multi-phase parallel systems often relies on accurate current sampling, which not only increases system cost but also may introduce additional noise. In addition, fixed-parameter controllers are difficult to maintain optimal performance in the face of complex and variable load conditions and input voltage fluctuations. Finally, existing control methods are mostly designed for specific operating modes, lacking a unified control strategy for Buck and Boost modes, which limits the application of DC-DC converters under wide-range input-output conditions. SUMMARY

[0004] One object of the present application is to provide a control method, device, medium and product of a DC-DC module, at least to solve the technical problem of low accuracy and efficiency of DC-DC module control.

[0005] To achieve the above object, some embodiments of the present application provide the following aspects:

[0006] In a first aspect, some embodiments of this application also provide a control method for a DC-DC module, including: sampling electrical parameters of the DC-DC module to obtain real-time electrical parameters; analyzing the real-time electrical parameters and determining whether the current operating mode is Buck mode or Boost mode through a comparator circuit; calculating the deviation between the output voltage and the target voltage in the real-time electrical parameters and generating a PWM duty cycle adjustment signal through a PI controller; processing the PWM duty cycle adjustment signal and generating multiple interleaved PWM drive signals through a phase shifting circuit; distributing the power of the multiple interleaved PWM drive signals and adjusting the conduction time of each switch through a parallel current sharing controller to obtain a current sharing control signal; and comprehensively analyzing the real-time electrical parameters, the current operating mode, the PWM duty cycle adjustment signal, the multiple interleaved PWM drive signals, and the current sharing control signal through an adaptive control algorithm to obtain a dynamic adjustment strategy.

[0007] Secondly, some embodiments of this application also provide an electronic device, the electronic device comprising: one or more processors; and a memory storing computer program instructions, which, when executed, cause the processor to perform the steps of the method described above.

[0008] Thirdly, some embodiments of this application also provide a computer-readable medium having computer program instructions stored thereon, which can be executed by a processor to implement the method described above.

[0009] Fourthly, some embodiments of this application also provide a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of the method described above.

[0010] Compared with related technologies, the solution provided in this application samplees electrical parameters of the DC-DC module to obtain real-time electrical parameters, providing an accurate data foundation for subsequent control. Then, through analysis of these real-time electrical parameters and judgment by the comparator circuit, the current operating mode (Buck or Boost) can be accurately identified, laying the foundation for subsequent control strategy selection. After determining the operating mode, the method calculates the deviation between the output voltage and the target voltage and generates a PWM duty cycle adjustment signal through a PI controller, ensuring the stability and fast response of the output voltage. Subsequently, the PWM duty cycle adjustment signal is processed, and multiple interleaved PWM drive signals are generated through a phase-shifting circuit. This interleaved control technology effectively reduces output ripple and improves the overall performance of the system. In a multiphase parallel system, this method distributes power among the multiple interleaved PWM drive signals and uses a parallel current sharing controller to adjust the conduction time of each switch, thereby obtaining a current sharing control signal. This ensures the balanced operation of the multiphase system and reduces the stress on individual switches. Finally, an adaptive control algorithm was introduced to comprehensively analyze real-time electrical parameters, the current operating mode, PWM duty cycle adjustment signals, multi-channel interleaved PWM drive signals, and current sharing control signals to obtain a dynamic adjustment strategy. This adaptive control mechanism enables the system to adjust control parameters in real time according to changes in operating conditions, ensuring the optimal performance of the DC-DC module under various operating conditions. This achieves comprehensive, precise, and flexible control of the DC-DC module. Attached Figure Description

[0011] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0012] Figure 1 This is an exemplary flowchart of a control method for a DC-DC module according to some embodiments of this application;

[0013] Figure 2 This is a schematic diagram of the structure of an electronic device according to some embodiments of this application. Detailed Implementation

[0014] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0015] First Embodiment

[0016] The first embodiment of this application relates to a control method for a DC-DC module. For example... Figure 1 As shown, the method may include the following steps:

[0017] S101. Sample the electrical parameters of the DC-DC module to obtain real-time electrical parameters;

[0018] S102. Analyze the real-time electrical parameters and determine whether the current working mode is Buck mode or Boost mode through the comparator circuit.

[0019] S103. Calculate the deviation between the output voltage and the target voltage in the real-time electrical parameters, and generate a PWM duty cycle adjustment signal through the PI controller;

[0020] S104. Process the PWM duty cycle adjustment signal and generate multiple interleaved PWM drive signals through the phase shifting circuit;

[0021] S105. Power distribution is performed on the multi-channel interleaved PWM drive signals. The conduction time of each switch is adjusted by a parallel current sharing controller to obtain the current sharing control signal.

[0022] S106. By using an adaptive control algorithm, a dynamic adjustment strategy is obtained by comprehensively analyzing real-time electrical parameters, current operating mode, PWM duty cycle adjustment signal, multi-channel interleaved PWM drive signal and current sharing control signal.

[0023] Specifically, high-precision sampling of input voltage, output voltage, input current, and output current is performed. The sampling circuit uses a high-speed analog-to-digital converter to convert analog signals into digital signals. Subsequently, the sampled digital signals are low-pass filtered to eliminate high-frequency noise interference. Next, a moving average algorithm is used to smooth the filtered data, improving data stability. Finally, the smoothed data is calibrated and compensated to eliminate errors in the sampling circuit, obtaining accurate real-time electrical parameters. After obtaining the real-time electrical parameters, the control method analyzes these parameters and determines the current operating mode using a comparator circuit. Specifically, the ratio of input voltage to output voltage is compared; if the input voltage is greater than the output voltage, it is determined to be in Buck mode; otherwise, it is determined to be in Boost mode. To improve the accuracy of the judgment and the anti-interference capability, a comparison of input current and output current is also introduced as an auxiliary judgment criterion. The results of the voltage and current comparisons are combined through logical operations to obtain the final operating mode judgment result. To prevent frequent switching of operating modes, time delay and filtering are introduced to ensure the stability of the operating mode.

[0024] After determining the operating mode, the control method calculates the deviation between the output voltage and the target voltage and generates a PWM duty cycle adjustment signal through a PI controller. The PI controller consists of a proportional element and an integral element, where the proportional element is used for rapid response to voltage deviation, and the integral element is used to eliminate steady-state error. The output of the PI controller undergoes linear transformation and dead-time compensation to obtain the initial value of the PWM duty cycle. Finally, the duty cycle value is limited and quantized to obtain the final PWM duty cycle adjustment signal. Next, the control method processes the PWM duty cycle adjustment signal, generating multiple interleaved PWM drive signals through a phase-shifting circuit. First, the PWM signal is frequency-multiplied to obtain a high-frequency PWM reference signal. Then, the high-frequency reference signal undergoes phase decomposition and offset processing to generate multiple interleaved phase signals. These signals undergo waveform shaping, rising edge detection, and delay processing to form multiple interleaved PWM drive signals. Interleaved PWM technology can effectively reduce output voltage ripple and improve the overall system performance.

[0025] In a multiphase parallel system, the control method distributes power across multiple interleaved PWM drive signals and adjusts the conduction time of each switch via a parallel current-sharing controller to obtain the current-sharing control signal. First, each PWM signal is demodulated to obtain the conduction time data of each switch. Then, the average conduction time is calculated and compared with the conduction time of each switch to obtain the conduction time deviation. The deviation is adjusted using proportional-integral (PI) calculations to generate the current-sharing adjustment amount. Finally, the current-sharing adjustment amount is superimposed on the reference voltage of each PWM switch to achieve precise adjustment of the conduction time of each switch. Finally, the control method uses an adaptive control algorithm to comprehensively analyze real-time electrical parameters, the current operating mode, the PWM duty cycle adjustment signal, the multiple interleaved PWM drive signals, and the current-sharing control signal to obtain a dynamic adjustment strategy. The adaptive control algorithm first normalizes and extracts features from various parameters, then obtains preliminary adjustment parameters through data fusion and fuzzy inference. These parameters undergo adaptive adjustment and constraint processing to form a continuous adjustment curve. Finally, the adjustment curve is piecewise linearized and quantized to obtain the final dynamic adjustment strategy.

[0026] For example, consider a four-phase parallel DC-DC converter system with an input voltage of 48V and a target output voltage of 12V. At a certain moment, the sampled output voltage is 11.8V. The control method first determines that the operating mode is Buck mode. Then, it calculates the voltage deviation as 0.2V and generates a PWM duty cycle adjustment signal through the PI controller. Assuming the adjusted duty cycle is 25%, the phase-shifting circuit decomposes this signal into four PWM drive signals with a 90-degree phase difference. In current sharing control, it is found that the first current is slightly high, and its duty cycle is adjusted to 24.8% to achieve current sharing. Finally, the adaptive control algorithm fine-tunes the PI controller parameters according to the current operating state, optimizing the system response speed and stability. Through this series of precise control steps, the DC-DC module can maintain stable and efficient operation under various operating conditions.

[0027] In this embodiment, electrical parameters of the DC-DC module are sampled to obtain real-time electrical parameters, providing an accurate data foundation for subsequent control. Then, through analysis of these real-time electrical parameters and judgment by the comparator circuit, the current operating mode (Buck or Boost) can be accurately identified, laying the foundation for subsequent control strategy selection. After determining the operating mode, the method calculates the deviation between the output voltage and the target voltage and generates a PWM duty cycle adjustment signal through a PI controller, ensuring the stability and fast response of the output voltage. Subsequently, the PWM duty cycle adjustment signal is processed, and multiple interleaved PWM drive signals are generated through a phase-shifting circuit. This interleaved control technology effectively reduces output ripple and improves the overall system performance. In a multiphase parallel system, this method distributes power among the multiple interleaved PWM drive signals and uses a parallel current sharing controller to adjust the conduction time of each switch, thereby obtaining a current sharing control signal. This ensures the balanced operation of the multiphase system and reduces the stress on individual switches. Finally, an adaptive control algorithm was introduced to comprehensively analyze real-time electrical parameters, the current operating mode, PWM duty cycle adjustment signals, multi-channel interleaved PWM drive signals, and current sharing control signals to obtain a dynamic adjustment strategy. This adaptive control mechanism enables the system to adjust control parameters in real time according to changes in operating conditions, ensuring the optimal performance of the DC-DC module under various operating conditions. This achieves comprehensive, precise, and flexible control of the DC-DC module.

[0028] Second Embodiment

[0029] The second embodiment of this application relates to a control method for a DC-DC module. The second embodiment is an improvement upon the first embodiment, specifically in that: electrical parameters of the DC-DC module are sampled to obtain real-time electrical parameters, including:

[0030] (1) Connect the voltage sampling circuit and the current sampling circuit to the input and output terminals of the DC-DC module respectively to obtain the original sampling signal;

[0031] (2) Perform analog-to-digital conversion on the original sampled signal to obtain digital sampled data, and perform low-pass filtering on the digital sampled data to obtain the filtered digital signal;

[0032] (3) Perform moving average processing on the filtered digital signal to obtain smoothed voltage and current data, and perform calibration compensation on the smoothed voltage and current data to obtain calibrated voltage and current values.

[0033] (4) Calculate the effective values ​​of the calibrated voltage and current values ​​to obtain the effective voltage and current values ​​of the input and output, and perform abrupt change detection on the effective voltage and current values ​​to obtain the voltage and current change flag;

[0034] (5) Combine the effective voltage and current values ​​and voltage and current change flags to obtain real-time electrical parameters.

[0035] This application embodiment involves several sophisticated data acquisition and processing steps. First, voltage sampling circuits and current sampling circuits are connected to the input and output terminals of the DC-DC module, respectively, to obtain the raw sampled signals. Voltage sampling circuits typically employ a resistor divider network, while current sampling circuits commonly use Hall sensors or sampling resistors. The design of these sampling circuits needs to consider high common-mode voltage rejection and wide bandwidth characteristics to ensure accurate sampling signals under various operating conditions. After obtaining the raw sampled signals, analog-to-digital conversion (ADC) is performed to convert the continuous analog signal into a discrete digital signal. The selection of the ADC is crucial, requiring consideration of factors such as sampling rate, resolution, and conversion speed. For DC-DC modules, 12-bit or 16-bit ADCs are typically used, with sampling rates between 100kHz and 1MHz to balance sampling accuracy and system response speed. The converted digital sampled data is then subjected to low-pass filtering to remove high-frequency noise and interference. Commonly used low-pass filters include Butterworth filters or Chebyshev filters, with the filter cutoff frequency typically set to 1 / 10 to 1 / 5 of the switching frequency to effectively suppress switching noise without affecting the useful signal. The low-pass filtered digital signal is then processed by moving average to obtain smoothed voltage and current data. Moving average is a simple and effective digital smoothing technique that reduces random fluctuations by calculating the average of the most recent N sampling points. The choice of N requires a trade-off between smoothing effect and system response speed; for DC-DC modules, N is typically a value between 8 and 32. The smoothed data is then calibrated and compensated to obtain calibrated voltage and current values. The calibration and compensation process takes into account the gain error, bias error, and nonlinearity error of the sampling circuit, correcting the data with pre-measured calibration coefficients to ensure the accuracy of the measurement results.

[0036] The calibrated voltage and current values ​​are then calculated for RMS values ​​to obtain the effective voltage and current values ​​of the input and output. The RMS calculation uses the root mean square (RMS) method; for DC signals, the RMS value equals the average value; for signals with ripple, the RMS calculation reflects the signal's energy level. Simultaneously, abrupt changes in the effective voltage and current values ​​are detected to obtain voltage and current abrupt change flags. The abrupt change detection algorithm identifies rapid changes in voltage or current by comparing the difference between adjacent sampling points with a preset threshold, which is crucial for detecting load abrupt changes or input voltage fluctuations. Finally, the effective voltage and current values ​​and the voltage and current abrupt change flags are combined to obtain complete real-time electrical parameters. These parameters include the effective values ​​of input voltage, output voltage, input current, and output current, as well as the corresponding abrupt change flags. This comprehensive information provides a complete and accurate data foundation for subsequent control algorithms.

[0037] For example, suppose a DC-DC module operating in Buck mode has a rated input voltage of 48V, an output voltage of 12V, and a rated power of 500W. At a certain moment, the voltage sampling circuit acquires a raw input voltage signal of 47.8V, which is converted by a 16-bit ADC to obtain a digital value of 31130. This digital value is then low-pass filtered to remove high-frequency noise components. Next, it is smoothed using a 32-point moving average algorithm to obtain a more stable value of 31128. After compensation with a pre-calibrated calibration coefficient of 1.0006, the calibrated digital value is obtained as 31147. Finally, the effective value of the input voltage is calculated to be 47.95V. Simultaneously, a mutation detection algorithm compares the current value with the value of the previous sampling period and finds that the voltage change does not exceed a preset threshold of 0.5V, therefore no mutation flag is triggered. This process is also applied to the processing of output voltage, input current, and output current.

[0038] Third Embodiment

[0039] The third embodiment of this application relates to a control method for a DC-DC module. The third embodiment is an improvement upon the first embodiment, specifically in that it analyzes real-time electrical parameters and determines whether the current operating mode is Buck mode or Boost mode using a comparator circuit, including:

[0040] (1) Compare the input voltage and output voltage in the real-time electrical parameters to obtain the voltage ratio, and compare the voltage ratio with the preset threshold to obtain the preliminary working mode judgment result;

[0041] (2) Compare the input current and output current in the real-time electrical parameters to obtain the current ratio, and compare the current ratio with the preset threshold to obtain the auxiliary working mode judgment result;

[0042] (3) Perform a logical AND operation on the preliminary work mode judgment result and the auxiliary work mode judgment result to obtain the comprehensive work mode judgment result;

[0043] (4) The comprehensive working mode judgment result is processed by time delay to obtain the delayed working mode judgment result, and the delayed working mode judgment result is filtered to obtain the smoothed working mode judgment result.

[0044] (5) Perform threshold comparison on the smoothed working mode judgment results to obtain candidate working modes, and compare the candidate working modes with the working modes of the previous cycle to obtain the working mode switching flag.

[0045] (6) Perform edge detection on the working mode switching flag to obtain the switching trigger signal, and perform latching processing on the candidate working modes according to the switching trigger signal to obtain the current working mode, which is either Buck mode or Boost mode.

[0046] In this embodiment, the input voltage and output voltage in the real-time electrical parameters are compared to calculate the voltage ratio. This ratio is the primary basis for determining the operating mode, because in Buck mode, the output voltage is lower than the input voltage, while in Boost mode, the output voltage is higher than the input voltage. The calculated voltage ratio is then compared with a preset threshold, which is typically slightly greater than 1 to account for voltage measurement errors and fluctuations. The comparison result serves as a preliminary operating mode determination, providing a basis for subsequent judgments. To improve the accuracy and robustness of the judgment, the control method also introduces current comparison as an auxiliary judgment criterion. The input current and output current in the real-time electrical parameters are compared to obtain the current ratio. Ideally, the current ratio in Buck mode is less than 1, while the current ratio in Boost mode is greater than 1. This current ratio is also compared with a preset threshold to obtain an auxiliary operating mode judgment result. Current comparison can provide additional judgment criteria when the voltage comparison result is unclear, especially under light or heavy load conditions.

[0047] A logical AND operation is performed on the preliminary and auxiliary operating mode judgment results to obtain a comprehensive operating mode judgment result. The logical AND operation requires consistency between the voltage and current comparison results to arrive at a definitive operating mode judgment. This dual judgment mechanism significantly improves the reliability of the judgment and reduces the probability of misjudgment. Considering potential voltage and current fluctuations in actual operation, the control method applies a time delay to the comprehensive operating mode judgment result, resulting in a delayed judgment result. This time delay is typically implemented using a shift register, storing the judgment results from multiple consecutive sampling periods. The delayed result is then filtered to obtain a smoothed operating mode judgment result. The filtering can employ a simple majority voting method, where the mode judgment result that appears most frequently within a certain time window is adopted as the final result. This method effectively suppresses the impact of instantaneous fluctuations on the judgment result.

[0048] The smoothed operating mode determination result is then compared with thresholds to obtain candidate operating modes. This threshold comparison process is actually a hysteresis comparator, setting different thresholds for switching from Buck mode to Boost mode and from Boost mode to Buck mode to avoid frequent switching at mode boundaries. The candidate operating mode is compared with the operating mode of the previous cycle; if they are different, an operating mode switching flag is generated. Finally, edge detection is performed on the operating mode switching flag to obtain a switching trigger signal. Edge detection can capture the instantaneous change in operating mode, providing a timely response for subsequent control. Based on the switching trigger signal, the candidate operating mode is latched to obtain the current operating mode, which is then determined to be either Buck mode or Boost mode. The latching process ensures that the operating mode remains unchanged throughout a complete control cycle, providing stable operating mode information for other control components.

[0049] For example, suppose a DC-DC module has an input voltage of 48V, an output voltage of 24V, an input current of 10A, and an output current of 19A at a certain moment. First, the voltage ratio is calculated to be 0.5, which is less than the preset threshold of 1.05, initially indicating Buck mode. The current ratio is 1.9, which is greater than the preset threshold of 0.95, also indicating Buck mode. A logical AND operation is performed on both values ​​to obtain a comprehensive judgment result of Buck mode. This result is then processed with a 10ms time delay and a 5-point average filter to obtain a smoothed judgment result. Assuming that within the past 100ms, 80% of the time was judged as Buck mode and 20% as Boost mode, the final candidate operating mode is determined to be Buck mode. A mode switching flag is generated by comparing it with the Boost mode of the previous cycle. Edge detection captures this switching flag, triggering mode latching, and finally confirming the current operating mode as Buck mode.

[0050] Fourth embodiment

[0051] The fourth embodiment of this application relates to a control method for a DC-DC module. The fourth embodiment is an improvement upon the second embodiment, specifically in that: the deviation between the output voltage and the target voltage in real-time electrical parameters is calculated, and a PWM duty cycle adjustment signal is generated through a PI controller, including:

[0052] (1) Perform low-pass filtering on the output voltage in the real-time electrical parameters to obtain the filtered output voltage value, and calculate the difference between the filtered output voltage value and the target voltage to obtain the voltage deviation value;

[0053] (2) The voltage deviation value is amplified to obtain the amplified voltage deviation signal, and the amplified voltage deviation signal is limited to obtain the limited voltage deviation signal.

[0054] (3) Perform proportional calculation on the voltage deviation signal after limiting to obtain the proportional term output, and perform integral calculation on the voltage deviation signal after limiting to obtain the integral term output;

[0055] (4) Perform weighted summation on the proportional term output and the integral term output to obtain the PI controller output signal, and perform feedback compensation on the PI controller output signal to obtain the compensated control signal.

[0056] (5) Perform linear transformation on the compensated control signal to obtain the initial value of PWM duty cycle, and perform dead-zone compensation on the initial value of PWM duty cycle to obtain the compensated PWM duty cycle value.

[0057] (6) Limit the compensated PWM duty cycle value to obtain the limited PWM duty cycle value, and quantize the limited PWM duty cycle value to obtain the PWM duty cycle adjustment signal.

[0058] In this embodiment, the output voltage in the real-time electrical parameters is low-pass filtered to obtain the filtered output voltage value. The transfer function H(s) of the low-pass filter can be expressed as:

[0059]

[0060] Where, ω c Let be the cutoff angular frequency, and s be a complex frequency variable. This filtering process effectively removes high-frequency noise and improves the stability of subsequent control. The difference between the filtered output voltage and the target voltage is calculated to obtain the voltage deviation value e(t):

[0061] e(t) = V ref -V o (t)

[0062] Among them, V ref For the target voltage, V o (t) represents the filtered output voltage.

[0063] The voltage deviation value is amplified to obtain the amplified voltage deviation signal. The selection of the amplification factor K_a requires a trade-off between control accuracy and system stability. The amplified signal is then limited to obtain the limited voltage deviation signal to prevent excessive deviation from causing controller saturation. The limiting function can be expressed as:

[0064]

[0065] Among them, e lim (t) represents the deviation signal after amplitude limiting, e max For the maximum permissible deviation, K a It is the amplification factor, used to adjust the amplitude of the original deviation signal.

[0066] The voltage deviation signal after limiting is subjected to proportional and integral operations to obtain proportional and integral output terms, respectively. Feedback compensation is then applied to the PI controller output signal to obtain the compensated control signal. The output of the PI controller can be expressed as:

[0067]

[0068] Among them, K p K is the proportionality coefficient. i Let u(t) be the integral coefficient, u(t) be the output signal of the PI controller, and τ be the integral variable, representing all times from 0 to t. It is a dummy variable used to represent time during integration. Feedback compensation can improve the dynamic response characteristics of the system. The compensated control signal undergoes a linear transformation to obtain the initial value of the PWM duty cycle. The linear transformation can be expressed as:

[0069] D init =K d u(t)+D0

[0070] Among them, D init K is the initial value of the PWM duty cycle. d D0 is the transformation coefficient and D0 is the base duty cycle.

[0071] The initial PWM duty cycle value needs to undergo dead-time compensation to obtain the compensated PWM duty cycle value. Dead-time compensation can eliminate the influence of nonlinear characteristics during the turn-on and turn-off processes of the power switch. Finally, the compensated PWM duty cycle value is limited and quantized to obtain the final PWM duty cycle adjustment signal.

[0072] For example, suppose a Buck-type DC-DC module has a target output voltage of 12V, and the actual sampled output voltage is 11.8V. After a low-pass filter with a cutoff frequency of 1kHz, the filtered output voltage is 11.85V. The calculated voltage deviation is e(t) = 12 - 11.85 = 0.15V. Assume the amplification factor K... a If the value is 10, the amplified deviation signal is 1.5V. After a ±2V limiting process, the limiting deviation signal remains unchanged at 1.5V.

[0073] Set PI controller parameter K p =0.5, K i =10, then the proportional term output is 0.5*1.5=0.75, and the integral term output is assumed to be 0.5 (depending on past accumulated deviation). The PI controller output u(t)=0.75+0.5=1.25. After feedback compensation and linear transformation (assuming Kd=0.1, D0=0.5), the initial value of the PWM duty cycle Dinit=0.1*1.25+0.5=0.625 is obtained. Considering the dead time is 100ns and the switching period is 10μs, the duty cycle value after dead time compensation is 0.635. Finally, after limiting processing from 0.1 to 0.9 and 8-bit quantization (256 levels), the final PWM duty cycle adjustment signal is 163.

[0074] Fifth Embodiment

[0075] The fifth embodiment of this application relates to a control method for a DC-DC module. The fifth embodiment is an improvement upon the fourth embodiment, specifically in that: the PWM duty cycle adjustment signal is processed to generate multiple interleaved PWM drive signals via a phase-shifting circuit, including:

[0076] (1) The PWM duty cycle adjustment signal is digitized to obtain a digital PWM signal, and the digital PWM signal is frequency multiplied to obtain a high-frequency PWM reference signal.

[0077] (2) Perform phase decomposition on the high-frequency PWM reference signal to obtain multiple reference phase signals, and perform phase shift processing on the multiple reference phase signals to obtain multiple interleaved phase signals;

[0078] (3) The waveform of the multi-channel interleaved phase signal is shaped to obtain a square wave signal, and the rising edge of the square wave signal is detected to obtain the trigger time signal;

[0079] (4) Delay the trigger signal to obtain a delayed trigger signal, and perform pulse width modulation on the delayed trigger signal to obtain a modulated PWM signal;

[0080] (5) Perform dead-time insertion processing on the modulated PWM signal to obtain a PWM signal with dead time, and perform level conversion on the PWM signal with dead time to obtain a drive level signal;

[0081] (6) Buffer the drive level signal to obtain the buffered drive signal, and perform output isolation processing on the buffered drive signal to obtain multi-channel interleaved PWM drive signal.

[0082] In this embodiment, the PWM duty cycle adjustment signal is digitized to obtain a digital PWM signal. Digitization includes converting the analog signal to a digital signal, typically using a high-speed analog-to-digital converter (ADC). The digital PWM signal is then frequency-multiplied to obtain a high-frequency PWM reference signal. Frequency multiplication is usually achieved through a digital phase-locked loop (DPLL), increasing the frequency of the original PWM signal several times to increase control accuracy and reduce output ripple. The high-frequency PWM reference signal is then phase-decomposed to obtain multiple reference phase signals. Phase decomposition breaks down a high-frequency signal into multiple signals with fixed phase differences, typically implemented using a shift register or counter. For N-phase interleaved PWM, the phase difference is typically 360° / N. The multiple reference phase signals are then phase-shifted to obtain multiple interleaved phase signals. Phase-shifting further optimizes the phase relationship between the signals to minimize output ripple.

[0083] The multi-channel interleaved phase signals undergo waveform shaping to obtain a square wave signal. Waveform shaping typically includes adjusting the rising and falling edges to ensure fast signal transitions and low jitter. The square wave signal is then subjected to rising edge detection to obtain the trigger signal. Rising edge detection is usually implemented using a comparator or edge-triggered flip-flop to accurately pinpoint the start time of the PWM signal. The trigger signal is then delayed to obtain a delayed trigger signal. The purpose of the delay is to compensate for the turn-on delay of the drive circuit and power switching devices, typically implemented using a programmable delay line. The delayed trigger signal is then pulse-width modulated (PWM) to obtain the modulated PWM signal. Pulse-width modulation (PWM) is the process of adjusting the duration of the high-level signal based on the duty cycle calculated by the control algorithm.

[0084] The modulated PWM signal undergoes dead-time insertion to obtain a PWM signal with dead time. Dead time is a brief off-time introduced to prevent simultaneous conduction of the upper and lower bridge arm switches, typically ranging from tens to hundreds of nanoseconds. The PWM signal with dead time undergoes level conversion to obtain the drive level signal. Level conversion converts the logic level signal into the drive level required by the power switching devices, usually implemented using a level shifting circuit. The drive level signal is then buffered to obtain a buffered drive signal. Buffering provides sufficient drive capability to ensure rapid turn-on and turn-off of the power switching devices. Finally, the buffered drive signal undergoes output isolation to obtain a multi-channel interleaved PWM drive signal. Output isolation is typically implemented using optocouplers or digital isolators to isolate the control circuit and power circuit, improving the system's anti-interference capability and safety.

[0085] For example, consider a four-phase interleaved Buck DC-DC module with a base PWM frequency of 100kHz and a duty cycle of 40%. First, a 400kHz high-frequency PWM reference signal is obtained by quadrupling the frequency. Then, phase decomposition yields four reference phase signals with a 90° phase difference. Assuming an additional 5° phase offset is needed, the phases of the four interleaved phase signals are 0°, 95°, 190°, and 285°, respectively. After waveform shaping, these signals produce a square wave signal with a steep rising edge and a slow falling edge. The trigger signal interval obtained from rising edge detection is 2.5μs (1 / 400kHz). Considering the MOSFET turn-on delay of 50ns, the trigger signal is delayed by 50ns. The delayed trigger signal is then pulse-width modulated to obtain a PWM signal with a 40% duty cycle and a duration of 1μs.

[0086] After inserting a 200ns dead time, a PWM signal with dead time is obtained. Level conversion transforms the 0-3.3V logic level signal into a 0-12V drive level signal. After buffering, the rise and fall times of the drive signal are optimized to 20ns and 30ns, respectively. Finally, through optocoupler isolation, four electrically isolated interleaved PWM drive signals are obtained, which can directly drive the four power MOSFETs of the Buck converter.

[0087] Sixth Embodiment

[0088] The sixth embodiment of this application relates to a control method for a DC-DC module. The sixth embodiment is an improvement upon the first embodiment, specifically in that: power distribution is performed on the multi-channel interleaved PWM drive signals, and the conduction time of each switching transistor is adjusted by a parallel current sharing controller to obtain a current sharing control signal, including:

[0089] (1) Demodulate the multi-channel interleaved PWM drive signal to obtain the conduction time data of each switch, and normalize the conduction time data of each switch to obtain the normalized conduction time value.

[0090] (2) The normalized conduction time values ​​are weighted and averaged to obtain the average conduction time reference value. The difference between the average conduction time reference value and the normalized conduction time values ​​of each path is calculated to obtain the conduction time deviation value.

[0091] (3) Perform proportional-integral calculation on the conduction time deviation value to obtain the initial current equalization adjustment amount, and perform amplitude limiting processing on the initial current equalization adjustment amount to obtain the amplitude-limited current equalization adjustment amount;

[0092] (4) Quantize the current sharing regulation amount after the amplitude is limited to obtain the quantized current sharing regulation signal, and perform digital-to-analog conversion on the quantized current sharing regulation signal to obtain the analog current sharing regulation voltage;

[0093] (5) Amplify the simulated current sharing regulation voltage to obtain the amplified current sharing regulation voltage, and superimpose the amplified current sharing regulation voltage to obtain the PWM reference voltage after each channel is regulated.

[0094] (6) Compare and process the adjusted PWM reference voltage of each channel with the triangular wave carrier to obtain the adjusted PWM signal, and drive the adjusted PWM signal to obtain the current sharing control signal.

[0095] In this embodiment, the multi-channel interleaved PWM drive signals are demodulated to obtain the conduction time data of each switching transistor. The demodulation process employs a counter technique to record the high-level duration of each PWM signal. Subsequently, the conduction time data of each switching transistor is normalized to obtain normalized conduction time values. The normalization process can be expressed as:

[0096]

[0097] Among them, T n,i T is the normalized on-time value of the i-th path. i T represents the actual conduction time of the i-th path. max The maximum conduction time across all paths is given. A weighted average is calculated from the normalized conduction time values ​​to obtain the baseline average conduction time. The weighted average calculation formula is:

[0098]

[0099] Among them, T avg The average on-time reference value is given by Q, where Q is the number of parallel circuits and w is the number of parallel circuits. i Let be the weight coefficients of the i-th path, satisfying

[0100] Next, the difference between the average on-time reference value and the normalized on-time value of each channel is calculated to obtain the on-time deviation value:

[0101] ΔT i =T avg -T n,i

[0102] Where, ΔT i Let be the conduction time deviation value of the i-th path.

[0103] The initial current sharing adjustment is obtained by performing a proportional-integral (PI) calculation on the conduction time deviation. The PI calculation can be expressed as:

[0104]

[0105] Among them, U i (k) represents the initial current sharing adjustment of the i-th path during the k-th sampling, K x and K c These are the proportional and integral coefficients, respectively. The initial flow-sharing regulation is then limited to obtain the limited flow-sharing regulation, preventing over-regulation. The limiting process can be expressed as:

[0106]

[0107] Among them, U i,lim (k) is the current equalization adjustment amount after limiting, U max This represents the maximum allowable adjustment amount.

[0108] The current-sharing regulation value after limiting is quantized to obtain a quantized current-sharing regulation signal. The quantization process converts the continuous regulation value into a discrete digital signal. This quantized current-sharing regulation signal is then converted into an analog current-sharing regulation voltage via a digital-to-analog converter (DAC). The analog current-sharing regulation voltage is amplified to obtain an amplified current-sharing regulation voltage. This amplification process is typically implemented using an operational amplifier to match the voltage range of subsequent circuits.

[0109] The amplified current-sharing regulation voltage is superimposed on the original PWM reference voltage to obtain the regulated PWM reference voltage for each channel. The superposition process can be expressed as:

[0110] V pwm,i =V pwm,0 +K l U i,lim

[0111] Among them, V pwm,i V is the PWM reference voltage after adjustment for the i-th channel. pwm,0 K is the original PWM reference voltage. lThe superposition coefficient is used. The adjusted PWM reference voltages of each channel are compared with the triangular wave carrier wave to obtain the adjusted PWM signal. The comparison process uses a high-speed comparator; a high level is output when the reference voltage is higher than the triangular wave, and a low level is output otherwise. Finally, the adjusted PWM signal is processed to obtain the current sharing control signal, which is used to directly control the power switching transistors.

[0112] For example, consider a four-phase parallel Buck DC-DC module with a switching frequency of 100kHz. At a certain moment, the conduction times of the four switches are 4.5μs, 4.8μs, 4.6μs, and 4.7μs, respectively. After normalization, the normalized conduction time values ​​are 0.9375, 1.0000, 0.9583, and 0.9792. Assuming equal weights for the four switches, the average conduction time baseline is 0.9688. The calculated conduction time deviations for the four switches are 0.0313, -0.0312, 0.0105, and -0.0104, respectively.

[0113] Let the proportionality coefficient K x =0.5, integral coefficient K c =0.1. Assuming the previous integral values ​​were all 0, the initial current sharing adjustments are 0.0157, -0.0156, 0.0053, and -0.0052, respectively. After a limiting process of ±0.02, the current sharing adjustment remains unchanged. These adjustments are converted into analog voltages by a 12-bit DAC, ranging from 0 to 3.3V. Assuming an amplification factor of 2, the amplified current sharing adjustment voltage range is 0 to 6.6V. The original PWM reference voltage is 5V, and the superposition factor K... l If the value is 1, then the four adjusted PWM reference voltages are 5.1047V, 4.8953V, 5.0353V, and 4.9647V, respectively. These voltages are compared with a triangular wave carrier wave with a peak value of 10V to generate four PWM signals with slightly different duty cycles. After being processed by the drive circuit, these PWM signals are used to obtain current sharing control signals that can achieve current balancing.

[0114] Seventh Embodiment

[0115] The seventh embodiment of this application relates to a control method for a DC-DC module. The seventh embodiment is an improvement upon the sixth embodiment, specifically in that it uses an adaptive control algorithm to comprehensively analyze real-time electrical parameters, the current operating mode, the PWM duty cycle adjustment signal, the multi-channel interleaved PWM drive signal, and the current sharing control signal to obtain a dynamic adjustment strategy, including:

[0116] (1) Normalize the real-time electrical parameters, current working mode, PWM duty cycle adjustment signal, multi-channel interleaved PWM drive signal and current sharing control signal to obtain a normalized input vector, and extract features from the normalized input vector to obtain a feature vector;

[0117] (2) Perform data fusion processing on the feature vectors to obtain fused features, and perform fuzzification processing on the fused features to obtain a fuzzy input set;

[0118] (3) Perform fuzzy inference on the fuzzy input set to obtain the fuzzy output set, and perform defuzzification on the fuzzy output set to obtain the preliminary adjustment parameters;

[0119] (4) Adaptively adjust the initial adjustment parameters to obtain the adjusted parameters, and constrain the adjusted parameters to obtain the constrained adjustment parameters;

[0120] (5) Interpolate the constrained adjustment parameters to obtain a continuous adjustment curve, and perform piecewise linearization on the continuous adjustment curve to obtain a piecewise linear adjustment strategy.

[0121] (6) Quantize the piecewise linear adjustment strategy to obtain discrete adjustment instructions, and encode the discrete adjustment instructions to obtain a dynamic adjustment strategy.

[0122] In this embodiment, real-time electrical parameters, current operating mode, PWM duty cycle adjustment signal, multi-channel interleaved PWM drive signal, and current sharing control signal are normalized to obtain a normalized input vector. Normalization unifies data of different dimensions into the [0,1] interval, which is helpful for subsequent processing. The normalized input vector is then subjected to feature extraction to obtain a feature vector. Principal Component Analysis (PCA) is used for feature extraction to extract the most representative low-dimensional features from high-dimensional data, reducing data complexity. The feature vector is then subjected to data fusion processing to obtain fused features. Data fusion employs Dempster-Shafer evidence theory, comprehensively considering the reliability and conflict of multi-source information to form a more comprehensive description of the system state. The fused features are then fuzzified to obtain a fuzzy input set. The fuzzification process converts precise numerical values ​​into fuzzy sets, using membership functions to describe the uncertainty of the data.

[0123] The fuzzy input set enters the fuzzy inference stage, where inference is performed based on a pre-set fuzzy rule base to obtain a fuzzy output set. Fuzzy inference employs the Mamdani inference method, mapping inputs to outputs through IF-THEN rules. The fuzzy output set undergoes defuzzification to obtain preliminary adjustment parameters. Defuzzification uses the centroid method to convert the fuzzy set into precise numerical outputs. The preliminary adjustment parameters are then adaptively adjusted to obtain the adjusted parameters. Adaptive adjustment uses the recursive least squares (RLS) method, updating parameter estimates in real time based on system response. The adjusted parameters undergo constraint processing to obtain constrained adjustment parameters. Constraint processing ensures that the parameters remain within a reasonable range, avoiding over-adjustment that could lead to system instability.

[0124] The constrained adjustment parameters are interpolated to obtain a continuous adjustment curve. Cubic spline interpolation is used to generate a smooth, continuous curve between discrete points. The continuous adjustment curve is then piecewise linearized to obtain a piecewise linear adjustment strategy. Piecewise linearization simplifies the complex nonlinear curve into a multi-segment linear function, facilitating implementation by the actual controller. Finally, the piecewise linear adjustment strategy is quantized to obtain discrete adjustment commands. The quantization process converts the continuous adjustment strategy into a finite number of discrete levels to suit the digital control system. The discrete adjustment commands are then encoded to obtain the final dynamic adjustment strategy. Encoding converts the adjustment commands into an instruction format that the controller can directly execute.

[0125] For example, suppose a four-phase parallel Buck DC-DC module has an input voltage of 48V, a target output voltage of 12V, and a rated power of 1kW. At a certain moment, real-time electrical parameters show an output voltage of 11.8V, a total output current of 80A, and four-phase currents of 19.5A, 20.2A, 20.5A, and 19.8A, respectively. The current operating mode is Buck mode, the PWM duty cycle is 25%, and the phase difference between the four interleaved PWM drive signals is 90°. First, data normalization is performed, mapping parameters such as voltage, current, and duty cycle to the [0,1] interval. For example, the normalized output voltage is 0.983 (11.8 / 12), and the total current is 0.8 (80 / 100). After feature extraction, a 5-dimensional feature vector is obtained, containing output voltage deviation, total current percentage, phase current imbalance, PWM duty cycle, and operating mode indication.

[0126] Data fusion considers these five features to obtain a system status index. Fuzzification transforms this index into membership degrees for three fuzzy sets: "light load," "normal," and "heavy load." Assume the membership degrees are 0.1, 0.7, and 0.2, respectively. Fuzzy inference, based on preset rules such as "IF load normal AND voltage low THEN slightly increase duty cycle," derives a suggested fuzzy set for adjustment. Defuzzification yields preliminary adjustment parameters, such as a 1.2% increase in duty cycle. Adaptive adjustment considers the system's current response speed and stability, potentially adjusting the duty cycle increase to 1.5%. Constraint processing ensures the adjusted duty cycle does not exceed a 30% upper limit. Interpolation and piecewise linearization convert this adjustment into a piecewise function with different adjustment slopes across different load ranges.

[0127] Finally, quantization discretizes the continuous adjustment curve into 256 levels, which are then encoded to generate the final dynamic adjustment strategy, including PWM duty cycle adjustment instructions and current sharing control parameter update instructions. This dynamic adjustment strategy guides the controller to fine-tune the PWM signal and current sharing control in the next control cycle, gradually bringing the output voltage closer to the target value while optimizing the current distribution of each phase. Through this series of complex data processing and decision-making processes, the DC-DC module control method achieves intelligent adaptation and precise control under complex operating conditions.

[0128] The steps of the various methods described above are only for clarity. In practice, they can be combined into one step or some steps can be split into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this patent. Adding insignificant modifications or introducing insignificant designs to the algorithm or process, but without changing the core design of the algorithm and process, are also within the scope of protection of this patent.

[0129] Furthermore, some embodiments of this application also provide an electronic device. The electronic device can be various forms of digital computer, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, etc. The electronic device can also be various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices.

[0130] The electronic device includes: one or more processors; and a memory storing computer program instructions that, when executed, cause the processor to perform the steps of the methods provided in any one or more of the above embodiments. Figure 2 An exemplary structural diagram of the electronic device is disclosed. For example... Figure 2As shown, the electronic device includes one or more processors 1101, a memory 1102, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components are interconnected via different buses and can be mounted on a common motherboard or otherwise as required. The processors can process instructions executed within the electronic device, including instructions stored in or on memory to display graphical information of a GUI on an external input / output device (such as a display device coupled to the interface). In some other embodiments, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple electronic devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). The components, their connections and relationships, and their functions shown herein are merely examples and are not intended to limit the implementation of the present application described and / or claimed herein.

[0131] The electronic device may further include an input device 1103 and an output device 1104. The processor 1101, memory 1102, input device 1103, and output device 1104 may be connected via a bus or other means. Figure 2 Taking the example of a connection between China and Israel via a bus.

[0132] Input device 1103 can receive input numerical or character information, and generate key signal inputs related to user settings and function control of the electronic device, such as a touch screen, keypad, mouse, trackpad, touchpad, joystick, one or more mouse buttons, trackball, joystick, etc. Output device 1104 may include a display device, auxiliary lighting device (e.g., LED), and haptic feedback device (e.g., vibration motor). The display device may include, but is not limited to, a liquid crystal display (LCD), a light-emitting diode (LED) display, and a plasma display. In some embodiments, the display device may be a touch screen.

[0133] To provide interaction with the user, the electronic device can be a computer. The computer has: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0134] In this embodiment, a computer-readable medium stores a computer program / instructions that, when executed by a processor, implement the steps of the methods provided in any one or more of the above embodiments. This computer-readable medium may be included in the electronic device described in the above embodiments; or it may exist independently and not assembled into that device. The aforementioned computer-readable medium carries one or more computer-readable instructions.

[0135] The memory 1102 can serve as a non-transitory computer-readable storage medium, used to store non-transitory software programs, non-transitory computer-executable programs, and modules. The processor 1101 executes various functional applications and data processing of the server by running the non-transitory software programs, instructions, and modules stored in the memory 1102, thereby implementing the program instructions / modules corresponding to the methods provided in any one or more of the embodiments described above in this application.

[0136] The memory 1102 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the electronic device. Furthermore, the memory 1102 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory 1102 may optionally include memory remotely located relative to the processor 1101, and these remote memories can be connected to the electronic device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0137] It should be noted that the computer-readable medium described in this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this application, a computer-readable medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0138] Computer-readable media include both permanent and non-permanent, removable and non-removable media, which can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, read-only optical disc (CD-ROM), digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0139] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0140] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. For example, it can be implemented using an application-specific integrated circuit (ASIC), a general-purpose computer, or any other similar hardware device. In some embodiments, the software program of this application can be executed by a processor to implement the steps or functions described above. Similarly, the software program of this application (including related data structures) can be stored in a computer-readable recording medium, such as RAM memory, magnetic or optical drives, floppy disks, or similar devices. Additionally, some steps or functions of this application can be implemented in hardware, for example, as circuitry that works with a processor to perform the various steps or functions.

[0141] The computer program product provided in this application includes one or more computer programs / instructions. When executed by a processor, these computer programs / instructions generate, in whole or in part, the processes or functions described in this application. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., a solid-state disk (SSD)).

[0142] The flowcharts or block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of devices, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-specific system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0143] The scope of this application is defined by the appended claims rather than the foregoing description, and is therefore intended to encompass all variations falling within the meaning and scope of equivalents of the claims. No reference numerals in the claims should be construed as limiting the scope of the claims. Furthermore, it is clear that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units or devices recited in a device claim may also be implemented by a single unit or device in software or hardware. Terms such as "first," "second," etc., are used only for distinguishing descriptions and do not indicate any particular order, nor should they be construed as indicating or implying relative importance.

[0144] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily made by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims, and the above embodiments should be regarded as exemplary and non-limiting.

Claims

1. A control method for a DC-DC module, characterized in that, include: The electrical parameters of the DC-DC module are sampled to obtain real-time electrical parameters; The real-time electrical parameters are analyzed, and the comparator circuit determines whether the current operating mode is Buck mode or Boost mode, including: The input voltage and output voltage in the real-time electrical parameters are compared to obtain a voltage ratio, and the voltage ratio is compared with a preset threshold to obtain a preliminary working mode judgment result; The input current and output current in the real-time electrical parameters are compared to obtain the current ratio, and the current ratio is compared with a preset threshold to obtain the auxiliary working mode judgment result; Perform a logical AND operation on the preliminary working mode judgment result and the auxiliary working mode judgment result to obtain the comprehensive working mode judgment result; The comprehensive working mode judgment result is subjected to time delay processing to obtain the delayed working mode judgment result, and the delayed working mode judgment result is filtered to obtain the smoothed working mode judgment result. The smoothed working mode judgment result is compared with a threshold to obtain a candidate working mode, and the candidate working mode is compared with the working mode of the previous cycle to obtain a working mode switching flag. Edge detection is performed on the working mode switching flag to obtain a switching trigger signal, and the candidate working modes are latched according to the switching trigger signal to obtain the current working mode, which is either Buck mode or Boost mode. The deviation between the output voltage and the target voltage in the real-time electrical parameters is calculated, and a PWM duty cycle adjustment signal is generated by a PI controller. The PWM duty cycle adjustment signal is processed to generate multiple interleaved PWM drive signals through a phase shifting circuit; The power of the multi-channel interleaved PWM drive signals is distributed, and the conduction time of each switch is adjusted by a parallel current sharing controller to obtain the current sharing control signal; The adaptive control algorithm is used to comprehensively analyze the real-time electrical parameters, current operating mode, PWM duty cycle adjustment signal, multi-channel interleaved PWM drive signal and current sharing control signal to obtain a dynamic adjustment strategy.

2. The method according to claim 1, characterized in that, Electrical parameters are sampled from the DC-DC module to obtain real-time electrical parameters, including: A voltage sampling circuit and a current sampling circuit are connected to the input and output terminals of the DC-DC module, respectively, to obtain the original sampling signal; The original sampled signal is converted from analog to digital to obtain digital sampled data, and the digital sampled data is low-pass filtered to obtain a filtered digital signal. The filtered digital signal is processed by moving average to obtain smoothed voltage and current data, and the smoothed voltage and current data is calibrated and compensated to obtain calibrated voltage and current values. The effective values ​​of the calibrated voltage and current are calculated to obtain the effective voltage and current values ​​of the input and output, and abrupt changes are detected in the effective voltage and current values ​​to obtain voltage and current abrupt change flags. The real-time electrical parameters are obtained by combining the effective voltage and current values ​​and the voltage and current change flags.

3. The method according to claim 2, characterized in that, The deviation between the output voltage and the target voltage in the real-time electrical parameters is calculated, and a PWM duty cycle adjustment signal is generated through a PI controller, including: The output voltage in the real-time electrical parameters is subjected to low-pass filtering to obtain the filtered output voltage value, and the difference between the filtered output voltage value and the target voltage is calculated to obtain the voltage deviation value. The voltage deviation value is amplified to obtain an amplified voltage deviation signal, and the amplified voltage deviation signal is then limited to obtain a limited voltage deviation signal. The voltage deviation signal after limiting is proportionally calculated to obtain a proportional term output, and the voltage deviation signal after limiting is integrally calculated to obtain an integral term output. The proportional term output and the integral term output are weighted and summed to obtain the PI controller output signal, and the PI controller output signal is then subjected to feedback compensation to obtain the compensated control signal. The compensated control signal is linearly transformed to obtain the initial value of the PWM duty cycle, and the initial value of the PWM duty cycle is subjected to dead-time compensation processing to obtain the compensated PWM duty cycle value. The compensated PWM duty cycle value is subjected to amplitude limiting to obtain the amplitude-limited PWM duty cycle value, and the amplitude-limited PWM duty cycle value is subjected to quantization to obtain the PWM duty cycle adjustment signal.

4. The method according to claim 3, characterized in that, The PWM duty cycle adjustment signal is processed to generate multiple interleaved PWM drive signals through a phase-shifting circuit, including: The PWM duty cycle adjustment signal is digitized to obtain a digital PWM signal, and the digital PWM signal is frequency multiplied to obtain a high-frequency PWM reference signal. The high-frequency PWM reference signal is phase decomposed to obtain multiple reference phase signals, and the multiple reference phase signals are phase shifted to obtain multiple interleaved phase signals. The multi-channel interleaved phase signals are waveform shaped to obtain a square wave signal, and the rising edge of the square wave signal is detected to obtain the trigger time signal. The trigger time signal is delayed to obtain a delayed trigger signal, and the delayed trigger signal is pulse width modulated to obtain a modulated PWM signal. The modulated PWM signal is subjected to dead-time insertion processing to obtain a PWM signal with dead time, and the PWM signal with dead time is level-converted to obtain a drive level signal; The drive level signal is buffered to obtain a buffered drive signal, and the buffered drive signal is output isolated to obtain the multi-channel interleaved PWM drive signal.

5. The method according to claim 1, characterized in that, Power distribution is performed on the multi-channel interleaved PWM drive signals, and the conduction time of each switch is adjusted by a parallel current sharing controller to obtain the current sharing control signal, including: The multi-channel interleaved PWM drive signals are demodulated to obtain the conduction time data of each switch transistor, and the conduction time data of each switch transistor are normalized to obtain the normalized conduction time value. The normalized conduction time values ​​are weighted and averaged to obtain the average conduction time reference value. The difference between the average conduction time reference value and the normalized conduction time values ​​of each channel is calculated to obtain the conduction time deviation value. The conduction time deviation value is subjected to proportional-integral calculation to obtain the initial current sharing adjustment amount, and the initial current sharing adjustment amount is subjected to amplitude limiting to obtain the amplitude-limited current sharing adjustment amount. The current sharing regulation amount after the amplitude is limited is quantized to obtain a quantized current sharing regulation signal, and the quantized current sharing regulation signal is converted from digital to analog to obtain an analog current sharing regulation voltage. The simulated current sharing regulation voltage is amplified to obtain the amplified current sharing regulation voltage, and the amplified current sharing regulation voltage is superimposed to obtain the PWM reference voltage after regulation for each channel. The adjusted PWM reference voltages of each channel are compared with the triangular wave carrier to obtain the adjusted PWM signal, and the adjusted PWM signal is driven to obtain the current sharing control signal.

6. The method according to claim 5, characterized in that, By comprehensively analyzing the real-time electrical parameters, current operating mode, PWM duty cycle adjustment signal, multi-channel interleaved PWM drive signal, and current sharing control signal through an adaptive control algorithm, a dynamic adjustment strategy is obtained, including: The real-time electrical parameters, current operating mode, PWM duty cycle adjustment signal, multi-channel interleaved PWM drive signal and current sharing control signal are normalized to obtain a normalized input vector, and feature vectors are extracted from the normalized input vector to obtain a feature vector. The feature vectors are subjected to data fusion processing to obtain fused features, and the fused features are then subjected to fuzzification processing to obtain a fuzzy input set; Fuzzy inference is performed on the fuzzy input set to obtain a fuzzy output set, and the fuzzy output set is defuzzified to obtain preliminary adjustment parameters; The initial adjustment parameters are adaptively adjusted to obtain the adjusted parameters, and the adjusted parameters are constrained to obtain the constrained adjustment parameters. The constrained adjustment parameters are interpolated to obtain a continuous adjustment curve, and the continuous adjustment curve is then piecewise linearized to obtain a piecewise linear adjustment strategy. The piecewise linear adjustment strategy is quantized to obtain discrete adjustment commands, and the discrete adjustment commands are encoded to obtain the dynamic adjustment strategy.

7. An electronic device, characterized in that, The electronic device includes: One or more processors; and A memory storing computer program instructions, which, when executed, cause the processor to perform the steps of the method as described in any one of claims 1 to 6.

8. A computer-readable medium having a computer program / instructions stored thereon, characterized in that, When the computer program / instructions are executed by the processor, they implement the steps of the method according to any one of claims 1 to 6.

9. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by the processor, they implement the steps of the method according to any one of claims 1 to 6.

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