Switched capacitor converter circuit control time sequence method, device, equipment, medium and program product

Abstract

The invention provides a switched capacitor converter circuit control time sequence method, device and equipment, a medium and a program product, and the method comprises the steps: disconnecting a switch connected to a power end and an output end during the conversion from series connection to parallel connection, and cutting off a current path between the power end and the output end; the flying capacitors are sequentially connected in parallel between the output end and the ground from the output end; when parallel connection is converted into series connection, a current path between the flying capacitors and the output end is cut off firstly, then the flying capacitors are sequentially connected in series from the power end, and finally the power end is closed to be connected with the series switch of the uppermost flying capacitor, so that a series access from the power end to the output end is formed. According to the invention, the damage risk of the power tubes in the switched capacitor converter and the voltage withstanding requirement of part of the power tubes are reduced, and the conversion efficiency is further improved.

Description

Technical Field

[0001] The present invention relates to the technical field of switched capacitor converters, and in particular to a switched capacitor converter circuit control timing method, device, equipment, medium and program product. Background Art

[0002] With the booming development of portable and wearable electronic devices, Internet of Things technology and new energy vehicle markets, the demand for high-efficiency, small-size and wide-voltage input range power conversion solutions is becoming increasingly urgent. Switched capacitor converters have gradually become the focus of research due to their inherent advantages, such as no need for inductors, high conversion efficiency and flexible voltage regulation capabilities. Common topologies of switched capacitor converters include Dickson type, series-parallel type, doubler type and so on. Among these common switched capacitor converter topologies, the series-parallel switched capacitor converter (Switched Capacitor Converter, SCC) has the advantages of simple implementation and low capacitor cost, and has good application prospects.

[0003] like Figure 1 As shown, in the forward 4:1 working mode, when Q1 / Q2 / Q3 / Q4 is turned on, the flying capacitors CF1 / CF2 / CF3 are charged through the power terminal PMID, and the voltage on each flying capacitor is 1*VOUT. At this time, the voltage of the CP3 / CP2 / CP1 nodes is raised in sequence, which are 4*VOUT / 3*VOUT / 2*VOUT respectively; when Q5 / Q6 / Q7 / Q8 / Q9 / Q10 is turned on, the flying capacitors CF1 / CF2 / CF3 are discharged to VOUT, and the voltage of the CP3 / CP2 / CP1 nodes is 1*VOUT. In the process of serial-to-parallel conversion, the CP3 / CP2 / CP1 nodes will experience a voltage jump of 3*VOUT / 2*VOUT / 1*VOUT, and the voltage jump will be coupled to the gate end by the parasitic capacitance of the power tube, thereby causing a short spike in the gate-source voltage of the power tube, causing the power tubes that should not be turned on at the same time to be turned on at the same time for a short time. As shown in FIG. Figure 2 As shown, taking the CP1 and CN1 nodes as an example, when Q1 is turned on, the CP1 voltage jumps from 1*VOUT to 4*VOUT. If the Vgs of Q5 is coupled and causes it to be briefly turned on at this time, a low-resistance path from PMID through Q1 and Q5 to VOUT will be formed, generating a large peak current. The appearance of peak current will reduce the efficiency of the converter and there is a risk of damage to the power tube. When the CP1 voltage jump is too large, Q8 and Q2 also have the risk of punch-through. Similarly, CP2 and CN2 also have voltage jumps greater than 1*VOUT, and the power tubes connected to them also have the risk of punch-through.

[0004] In addition, during the serial-to-parallel conversion, Q2 / Q3 needs to withstand a voltage drop higher than 1*VOUT. Assume that the previous state of the converter is that Q5 / Q6 / Q7 / Q8 / Q9 / Q10 is turned on, the CP1 / CP2 / CP3 node voltages are all 1*VOUT, and the CN1 / CN2 / CN3 node voltages are all 0. When the state is switched, if Q4 is turned on first, the CP3 node voltage will reach 2*VOUT, and the CN2 node voltage is still 0 at this time, and Q3 needs to withstand a voltage drop of 2*VOUT. Similarly, after Q3 is turned on, Q2 needs to withstand a voltage drop of 3*VOUT, which will increase the voltage resistance requirements of the Q2 / Q3 power tubes. Summary of the invention

[0005] The present invention aims to provide a switching capacitor converter circuit control timing method to avoid the risk of short-term conduction from PMID to VOUT during series-parallel conversion of a series-parallel switching capacitor converter and the risk of some power tubes being subjected to voltages exceeding their normal working conditions.

[0006] The present invention provides a switching capacitor converter circuit control timing method, comprising:

[0007] When switching from the series state to the parallel state, the flying capacitors are connected in series as the starting state, and the switch connected to the power terminal PMID and the output terminal VOUT is first disconnected to cut off the current path between the power terminal PMID and the output terminal VOUT; then, starting from the output terminal VOUT side, the flying capacitors are connected in parallel between VOUT and the ground; this is repeated layer by layer, and finally all the flying capacitors can be connected in parallel to the output terminal VOUT;

[0008] When switching from the parallel state to the series state, first disconnect the switch connected to the upper plate or lower plate of each flying capacitor to cut off the current path from the flying capacitor to the output terminal VOUT; then start from the PMID side of the power end, connect the flying capacitors in series in sequence; this is repeated layer by layer, and finally all the flying capacitors are connected in series together; finally, close the series switch connected to the top flying capacitor on the PMID side of the power end to form a series path from the PMID side of the power end to the output terminal VOUT.

[0009] In some embodiments, when switching from a series state to a parallel state, after a flying capacitor is connected in parallel to the output terminal VOUT, it is necessary to ensure that the series switch connected to the upper plate of the flying capacitor is disconnected.

[0010] In some embodiments, when switching from a parallel state to a series state, before opening the series switch connected to the lower plate of the flying capacitor, it is necessary to ensure that the parallel switch connected to the lower plate of the flying capacitor is disconnected.

[0011] In a second aspect, the present invention provides a switched capacitor converter, which is an N:1 series-parallel switched capacitor converter or a 1:N series-parallel switched capacitor converter, and uses the method described in claims 1-3 to convert between the series state and the parallel state.

[0012] In a third aspect, the present invention provides a switching capacitor converter circuit control timing device, which is used to realize the conversion between the series state and the parallel state of the switching capacitor converter by controlling the states of each switch in the switching capacitor converter; the device comprises:

[0013] The first control module is used for executing the conversion from the series state to the parallel state, taking the flying capacitors in series as the starting state, first disconnecting the switch connected to the power terminal PMID and the output terminal VOUT, cutting off the current path between the power terminal PMID and the output terminal VOUT; then starting from the output terminal VOUT side, sequentially connecting the flying capacitors in parallel between VOUT and the ground; and in this way, recursively layer by layer, finally all the flying capacitors can be connected in parallel to the output terminal VOUT;

[0014] The second control module is used to switch from the parallel state to the series state. First, the switch connected to the upper plate or the lower plate of each flying capacitor is disconnected to cut off the current path from the flying capacitor to the output terminal VOUT; then, starting from the PMID side of the power terminal, the flying capacitors are connected in series in sequence; this is repeated layer by layer, and finally all the flying capacitors are connected in series together; finally, the series switch connected to the uppermost flying capacitor on the PMID side of the power terminal is closed to form a series path from the PMID side of the power terminal to the output terminal VOUT.

[0015] In some embodiments, when the first control module is used to execute the conversion from the series state to the parallel state, after a flying capacitor is connected in parallel to the output terminal VOUT, it is necessary to ensure that the series switch connected to the upper plate of the flying capacitor is disconnected.

[0016] In some embodiments, when the second control module is used to switch from the parallel state to the series state, before opening the series switch connected to the lower plate of the flying capacitor, it is necessary to ensure that the parallel switch connected to the lower plate of the flying capacitor is disconnected.

[0017] In a fourth aspect, the present invention provides an electronic device, comprising:

[0018] at least one processor; and a memory communicatively coupled to the at least one processor;

[0019] The memory stores instructions that can be executed by the at least one processor, and the at least one processor executes the above method by executing the instructions stored in the memory.

[0020] In a fifth aspect, the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium is used to store instructions, and when the instructions are executed, the above method is implemented.

[0021] In a sixth aspect, the present invention provides a computer program product, which, when called by a computer, enables the computer to execute the above method.

[0022] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0023] The present invention reduces the damage risk of power tubes in a switched capacitor converter and the withstand voltage requirement of some power tubes, and further improves the conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 The architecture diagram of a series-parallel switched capacitor converter with a 4:1 conversion ratio.

[0025] Figure 2 This is the timing diagram of a series-parallel switched capacitor converter with a 4:1 conversion ratio.

[0026] Figure 3 Schematic diagram of the N:1 series-parallel switched capacitor converter architecture and series and parallel states in an embodiment of the present invention.

[0027] Figure 4 Flow chart of a method for controlling a timing sequence of a switched capacitor converter circuit within one cycle of an N:1 series-parallel switched capacitor converter according to an embodiment of the present invention.

[0028] Figure 5 FIG. 4 is a switching timing diagram of each power tube in one cycle of a 4:1 series-parallel switched capacitor converter in an embodiment of the present invention.

[0029] Figure 6 Schematic diagram of key points of the process of switching from a parallel state to a series state of a 4:1 series-parallel switched capacitor converter in an embodiment of the present invention.

[0030] Figure 7 Schematic diagram of key points of the process of switching from a series state to a parallel state of a 4:1 series-parallel switched capacitor converter in an embodiment of the present invention.

[0031] Figure 8 Schematic diagram of the structure of a switching capacitor converter circuit control timing device in an embodiment of the present invention.

[0032] Fig. 9 The figure is a schematic diagram of the structure of an electronic device in an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0034] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] An embodiment of the present invention proposes a switching capacitor converter circuit control timing method, which is applicable to all N:1 or 1:N series-parallel switching capacitor converters and can effectively reduce the coupling effect and reduce the withstand voltage requirements of the series branch power tube when N is greater than or equal to 3.

[0036] Figure 3 It is a basic architecture of an N:1 series-parallel switched capacitor converter. In the N:1 series-parallel switched capacitor converter, a power terminal PMID is connected to an output terminal VOUT via N first switches S1 to S(N) and (N-1) flying capacitors CF1 to CF(N-1), and each of the first switches is alternately connected to a flying capacitor; the upper plate level of the (N-1) flying capacitors is correspondingly connected to the output terminal VOUT via second switches S(N+1) to S(2N-1), and the lower plate level of the (N-1) flying capacitors is correspondingly grounded via third switches S(2N) to S(3N-2).

[0037] Figure 3 The two states of the N:1 series-parallel switched capacitor converter are a series state in which all flying capacitors are connected in series between the power terminal PMID and the output terminal VOUT, and a parallel state in which all flying capacitors are connected in parallel between the output terminal VOUT and the ground. Figure 4 The flying capacitor switching sequence of an N:1 series-parallel switched capacitor converter in one cycle is given. Figure 3 The two state schematic diagrams in the switching capacitor converter circuit control timing method include:

[0038] When switching from the series state to the parallel state, the (N-1) flying capacitors are connected in series as the starting state, first disconnect the switches connected to the power terminal PMID and the output terminal VOUT, that is, the first switches S1 and S(N), and cut off the current path between the power terminal PMID and the output terminal VOUT; then, starting from the output terminal VOUT side, the flying capacitors are sequentially connected in parallel between VOUT and the ground, that is, the second switches S(N+1)~S(2N-1) and the third switches S(2N)~S(3N-2) are closed. After a flying capacitor is connected in parallel to the output terminal VOUT, it is necessary to ensure that the series switches connected to the upper plate of the flying capacitor, that is, the first switches S2~S(N-1), are disconnected to avoid the upper plate of the lower flying capacitor being short-circuited to the ground when the upper flying capacitor is connected in parallel to the output terminal VOUT. Each time the flying capacitor is connected in parallel to the output terminal VOUT, the potential of the upper plate of the flying capacitor will change from 2*VOUT to 1*VOUT, and the potential of all upper CP / CN nodes will change downward by 1*VOUT. By doing this recursively layer by layer, all (N-1) flying capacitors can eventually be connected in parallel to the output terminal VOUT, and the voltage of the CP / CN node can be guaranteed to change by only 1*VOUT each time it is switched, thereby reducing the risk of the power switch gate being coupled and causing the switch to be temporarily turned on.

[0039] When switching from the parallel state to the series state, it is necessary to first disconnect the switch connected to the upper plate or lower plate of each flying capacitor. The selection of the specific switch position needs to be determined in combination with the actual circuit. Here, the upper plate switch is disconnected as an example, that is, the second switch S(N+1)~S(2N-1), and the current path between the flying capacitor and the output terminal VOUT is cut off. Then, starting from the PMID side of the power end, the flying capacitors are connected in series in sequence. Before opening the series switch connected to the lower plate of the flying capacitor, that is, the first switch S2~S(N), it is necessary to ensure that the parallel switch connected to the lower plate of the flying capacitor is disconnected, that is, the third switch S(2N)~S(3N-2), to avoid the upper plate of the flying capacitor from being short-circuited to the ground. Each time the series connection of the flying capacitor is completed, the potential of the upper and lower plates will be raised by 1*VOUT. In this way, it is recursive layer by layer, and finally all (N-1) flying capacitors can be connected in series together, and it is ensured that each time the CP / CN node is switched, only 1*VOUT changes, reducing the risk of the power switch gate being coupled and causing the switch to be temporarily turned on. Finally, the series switch connected to the uppermost flying capacitor on the power terminal PMID side, ie, the first switch S1, is closed to form a series path from the power terminal PMID to the output terminal VOUT.

[0040] Taking the series-parallel switched capacitor converter with a conversion ratio of 4:1 as an example, the switches are all implemented by power tubes, such as Figure 5As shown in FIG. 1 , it is a complete power tube switching timing within a cycle, and it is defined that when the power end PMID is connected in series to the output end VOUT through three flying capacitors CF1 / CF2 / CF3, it is in a series state, and when the three flying capacitors are connected in parallel to the output end VOUT, it is in a parallel state.

[0041] When the switched capacitor converter switches from a parallel state to a series state, that is, the power tubes Q5 / Q6 / Q7 / Q8 / Q9 / Q10 change from on to off, and the power tubes Q1 / Q2 / Q3 / Q4 change from off to on, the flying capacitors CF1 / CF2 / CF3 are first connected in series from top to bottom, and finally the series path from the power end PMID to the output end VOUT is connected, thereby avoiding excessive jumps at the CP and CN nodes, and reducing the voltage drop borne by the power tubes in the series path during the conversion process. Figure 6 A schematic diagram of the key steps in the switching process of the switched capacitor converter from the parallel state to the series state is given. The specific process is described as follows:

[0042] Step 101, turn off the power tubes Q5 / Q6 / Q7, and cut off the discharge path between the three flying capacitors CF1 / CF2 / CF3 and the output terminal VOUT. At this time, the voltages of the CP1 / CP2 / CP3 nodes are all 1*VOUT, the voltages of the CN1 / CN2 / CN3 nodes are all 0, and the voltage drops on all power tubes except the power tube Q1 do not exceed 1*VOUT.

[0043] Step 102, when the power tubes Q5 / Q6 / Q7 are turned off, the power tube Q8 is turned off, the upper and lower plates of the flying capacitor CF1 are disconnected from the parallel path, and then the power tube Q2 is turned on. At this time, since the power tube Q9 is still not turned off, the flying capacitor CF1 and the flying capacitor CF2 form a series relationship, so the CP1 node voltage changes from 1*VOUT to 2*VOUT, and the CN1 node voltage changes from 0 to 1*VOUT, and only the power tube Q1 voltage drop is higher than 1*VOUT.

[0044] Step 103, the power tube Q9 is turned off, so that the series path formed by CF1 and CF2 is floating, and then the power tube Q3 is turned on. Similarly, because the power tube Q10 is not turned off, the voltage of the CP1 node becomes 3*VOUT, the voltage of the CN1 node becomes 2*VOUT, the voltage of the CP2 node becomes 2*VOUT, and the voltage of the CN2 node becomes 1*VOUT. At this time, the power tubes Q5 / Q8 need to withstand the voltage of 2*VOUT.

[0045] Step 104, next Q10 is turned off, making the series path formed by CF1 / CF2 / CF3 float, and then turning on the power tube Q4. All CP node and CN node voltages are raised by 1*VOUT, at which time the power tubes Q5 / Q8 need to withstand a voltage of 3*VOUT, and the power tubes Q6 / Q9 need to withstand a voltage of 2*VOUT.

[0046] When the switched capacitor converter switches from the series state to the parallel state, that is, the power tubes Q1 / Q2 / Q3 / Q4 switch from on to off, and the power tubes Q5 / Q6 / Q7 / Q8 / Q9 / Q10 switch from off to on, the three flying capacitors CF1 / CF2 / CF3 are connected in parallel to the output terminal VOUT in sequence, thereby avoiding excessive jumps at the CP node and the CN node. Figure 7 A schematic diagram of the key steps in the switching process of the switched capacitor converter from the series state to the parallel state is given. The specific process is described as follows:

[0047] Step 201, turn off the power tube Q1, and cut off the charging path from the power terminal PMID to the output terminal VOUT through the three flying capacitors CF1 / CF2 / CF3 in series. At this time, the voltages of all CP nodes and CN nodes remain unchanged, the power tubes Q5 / Q8 need to withstand a voltage of 3*VOUT, and the power tubes Q6 / Q9 need to withstand a voltage of 2*VOUT.

[0048] Step 202, turn off the power tube Q4, disconnect the CN3 node from the output terminal VOUT, then turn on the power tubes Q7 and Q10, and connect the flying capacitor CF3 in parallel to VOUT. Since the power tubes Q2 / Q3 are still turned on, the voltage across the flying capacitors CF1 and CF2 will shift down by 1*VOUT as a whole, and the power tubes Q5 / Q8 need to withstand a voltage of 2*VOUT.

[0049] Step 203, turn off the power tube Q3, disconnect the connection between the CN2 node and the CP3 node, then turn on the power tubes Q6 and Q9, and connect the flying capacitor CF2 to the output terminal VOUT in parallel. Similarly, since the power tube Q2 is still turned on, the voltage across the flying capacitor CF1 will shift down again by 1*VOUT, and at this time, only the power tube Q1 needs to withstand the voltage of 2*VOUT.

[0050] Step 204, turn off the power tube Q2, disconnect the connection between the CN1 node and the CP2 node, then turn on the power tubes Q5 and Q8, and connect the flying capacitor CF1 to the output terminal VOUT in parallel. At this time, the voltage across the flying capacitor CF1 will shift down again by 1*VOUT, and only the power tube Q1 needs to withstand the voltage of 3*VOUT.

[0051] In the above process, each time the switch jumps, the voltage change of all CP nodes and CN nodes will not exceed 1*VOUT, reducing the risk of coupling the power tube gate and causing the power end PMID to the output end VOUT to be temporarily turned on. At the same time, the power tube Q2 and the power tube Q3 do not need to withstand a voltage exceeding 1*VOUT, and a power tube with a smaller on-resistance (Ron,sp) can be selected to achieve higher efficiency with the same area. Taking the CP1 node and the CN1 node as an example, Figure 5 The switching waveforms of the CP1 node and the CN1 node are given in Figure 1, as well as the Vgs waveforms of the coupled power tubes Q5 / Q8 / Q2 when the voltage is converted. Since the voltage changes by 1*VOUT each time, the Figure 2 In the control sequence shown in FIG, although the coupling of Vgs occurs at most three times, the amplitude of each time is less than Figure 2 On the other hand, the smaller voltage change will have a relatively lower pull-down capability requirement for the power tube drive circuit, and is more friendly to the area and layout design of the drive circuit. At the same time, the power tubes Q2 and Q3 do not need to withstand a voltage exceeding 1*VOUT, and can use power tubes with smaller on-resistance (Ron,sp) to achieve higher efficiency under the same area. Taking VOUT=5V as an example, the withstand voltage of power tube Q2 drops from 3*VOUT(15V) to 1*VOUT(5V), and Ron can be reduced from 2.65mΩ*mm2 to 1.08mΩ*mm2; the withstand voltage of Q3 drops from 2*VOUT(10V) to 1*VOUT(5V), and Ron can be reduced from 2.17mΩ*mm2 to 1.08mΩ*mm2. Under the same area, the on-resistance is reduced by 2.45 times and 2 times respectively.

[0052] Based on the same technical concept, an embodiment of the present invention further provides a switching capacitor converter circuit control timing device, which is used to realize the conversion between the series state and the parallel state of the switching capacitor converter by controlling the states of each switch in the switching capacitor converter; Figure 8 As shown, the device comprises:

[0053] The first control module is used to execute the conversion from the series state to the parallel state, with (N-1) flying capacitors connected in series as the starting state, first disconnecting the switches connected to the power terminal PMID and the output terminal VOUT, namely the first switches S1 and S(N), and cutting off the current path from the power terminal PMID to the output terminal VOUT; then starting from the output terminal VOUT side, the flying capacitors are sequentially connected in parallel between VOUT and the ground, namely closing the second switches S(N+1)~S(2N-1) and the third switches S(2N)~S(3N-2), and after a flying capacitor is connected in parallel to the output terminal VOUT, it is necessary to ensure that the series switches connected to the upper plates of the flying capacitors, namely the first switches S2~S(N-1), are disconnected to avoid the upper plates of the flying capacitors in the lower layer being short-circuited to the ground when the flying capacitors in the upper layer are connected in parallel to the output terminal VOUT. Each time the flying capacitor is connected in parallel to the output terminal VOUT, the potential of the upper plate of the flying capacitor will change from 2*VOUT to 1*VOUT, and the potential of all upper CP / CN nodes will change downward by 1*VOUT. This is repeated layer by layer, and eventually all (N-1) flying capacitors can be connected in parallel to the output terminal VOUT, and the voltage of the CP / CN node can be guaranteed to change by only 1*VOUT each time the CP / CN node is switched, reducing the risk of the power switch gate being coupled and causing the switch to be temporarily turned on;

[0054] The second control module is used to switch from the parallel state to the series state. It is necessary to first disconnect the switch connected to the upper plate or lower plate of each flying capacitor. The selection of the specific switch position needs to be determined in combination with the actual circuit. Here, the upper plate switch is disconnected as an example, that is, the second switch S(N+1)~S(2N-1), which cuts off the current path between the flying capacitor and the output terminal VOUT. Then, starting from the power end PMID side, the flying capacitors are connected in series in sequence. Before opening the series switch connected to the lower plate of the flying capacitor, that is, the first switch S2~S(N), it is necessary to ensure that the parallel switch connected to the lower plate of the flying capacitor is disconnected, that is, the third switch S(2N)~S(3N-2), to avoid the upper plate of the flying capacitor from being short-circuited to the ground. After completing the series connection of the flying capacitor each time, the upper and lower plate potentials will be raised by 1*VOUT. In this way, all (N-1) flying capacitors can be connected in series, and the CP / CN node is guaranteed to change by only 1*VOUT each time it is switched, thereby reducing the risk of the power switch gate being coupled and causing the switch to be temporarily turned on. Finally, the series switch connected to the top flying capacitor on the power terminal PMID side, i.e., the first switch S1, is closed to form a series path from the power terminal PMID to the output terminal VOUT.

[0055] Based on the same technical concept, an embodiment of the present invention further provides an electronic device, which can implement the switching capacitor converter circuit control timing method flow provided in the above embodiment of the present application. In one embodiment, the electronic device can be a server, or a terminal device or other electronic device. Fig. 9 As shown, the electronic device may include:

[0056] At least one processor, and a memory connected to the at least one processor. The specific connection medium between the processor and the memory is not limited in the embodiment of the present invention. Fig. 9 The example in this article is that the processor and memory are connected through a bus. Fig. 9 The connections between other components are shown in bold lines, which are only for illustration and are not intended to be limiting. The bus can be divided into address bus, data bus, control bus, etc. Fig. 9 In the diagram, only one thick line is used, but this does not mean that there is only one bus or only one type of bus. Alternatively, a processor can also be called a controller, and there is no limitation on the name.

[0057] In an embodiment of the present invention, the memory stores instructions that can be executed by at least one processor, and the at least one processor can execute the switching capacitor converter circuit control timing method discussed above by executing the instructions stored in the memory. The processor can implement Fig. 9 The functions of each module in the device shown.

[0058] Among them, the processor is the control center of the device, which can use various interfaces and lines to connect the various parts of the entire control device, and monitor the device as a whole by running or executing instructions stored in the memory and calling data stored in the memory, various functions of the device and processing data.

[0059] In an optional design, the processor may include one or more processing units, and the processor may integrate an application processor and a modem processor, wherein the application processor mainly processes an operating system, a user interface, and application programs, and the modem processor mainly processes wireless communications. It is understandable that the modem processor may not be integrated into the processor. In some embodiments, the processor and the memory may be implemented on the same chip, and in some embodiments, they may also be implemented separately on separate chips.

[0060] The processor may be a general-purpose processor, such as a CPU, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, and may implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. A general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of a switching capacitor converter circuit control timing method disclosed in conjunction with the embodiments of the present invention may be directly embodied as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor.

[0061] As a non-volatile computer-readable storage medium, the memory can be used to store non-volatile software programs, non-volatile computer executable programs and modules. The memory may include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (Random Access Memory, RAM), static random access memory (Static Random Access Memory, SRAM), programmable read-only memory (Programmable Read Only Memory, PROM), read-only memory (Read Only Memory, ROM), electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), magnetic memory, disk, optical disk, etc. The memory is any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory in the embodiment of the present invention can also be a circuit or any other device that can realize a storage function, used to store program instructions and / or data.

[0062] By designing and programming the processor, the code corresponding to the method for controlling the timing sequence of a switched capacitor converter circuit introduced in the above embodiment can be fixed into the chip, so that the chip can perform the steps of the method for controlling the timing sequence of a switched capacitor converter circuit in the above embodiment when running. How to design and program the processor is a technology well known to those skilled in the art and will not be described in detail here.

[0063] Based on the same inventive concept, an embodiment of the present invention further provides a storage medium storing computer instructions. When the computer instructions are executed on a computer, the computer executes a switching capacitor converter circuit control timing method discussed above.

[0064] In some optional embodiments, the present application also provides various aspects of a switching capacitor converter circuit control timing method, which can also be implemented in the form of a program product, which includes a program code. When the program product is run on an apparatus, the program code is used to enable the control device to execute the steps of a switching capacitor converter circuit control timing method described above in this specification according to various exemplary embodiments of the present application.

[0065] It should be noted that, although several units or subunits of the device are mentioned in the above detailed description, this division is merely exemplary and not mandatory. In fact, according to the embodiments of the present application, the features and functions of two or more units described above can be embodied in one unit. Conversely, the features and functions of a unit described above can be further divided into multiple units to be embodied. In addition, although the operation of the method of the present application is described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in this specific order, or that all the operations shown must be performed to achieve the desired result. Additionally or alternatively, some steps can be omitted, multiple steps can be combined into one step for execution, and / or one step can be decomposed into multiple steps for execution.

[0066] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0067] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a server, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the process in the flowchart. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0068] Program code for performing the operations of the present application may be written using any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a stand-alone software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0069] Where a remote computing device is involved, the remote computing device may be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0070] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0071] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0072] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for controlling timing of a switched capacitor converter circuit, characterized in that: include: When switching from the series state to the parallel state, the flying capacitors are connected in series as the starting state, and the switch connected to the power terminal PMID and the output terminal VOUT is first disconnected to cut off the current path between the power terminal PMID and the output terminal VOUT; then, starting from the output terminal VOUT side, the flying capacitors are connected in parallel between VOUT and the ground; this is repeated layer by layer, and finally all the flying capacitors can be connected in parallel to the output terminal VOUT; When switching from the parallel state to the series state, first disconnect the switch connected to the upper plate or lower plate of each flying capacitor to cut off the current path from the flying capacitor to the output terminal VOUT; then start from the PMID side of the power end, connect the flying capacitors in series in sequence; this is repeated layer by layer, and finally all the flying capacitors are connected in series together; finally, close the series switch connected to the top flying capacitor on the PMID side of the power end to form a series path from the PMID side of the power end to the output terminal VOUT.

2. The method for controlling timing of a switched capacitor converter circuit according to claim 1, wherein: When switching from the series state to the parallel state, after a flying capacitor is connected in parallel to the output terminal VOUT, it is necessary to ensure that the series switch connected to the upper plate of the flying capacitor is disconnected.

3. The method for controlling timing of a switched capacitor converter circuit according to claim 1, wherein: When switching from a parallel state to a series state, before opening the series switch connected to the lower plate of the flying capacitor, ensure that the parallel switch connected to the lower plate of the flying capacitor is disconnected.

4. A switched capacitor converter, characterized in that: The switched capacitor converter is an N:1 series-parallel switched capacitor converter or a 1:N series-parallel switched capacitor converter, and the method according to claims 1 to 3 is used to convert between the series state and the parallel state.

5. A switching capacitor converter circuit control timing device, characterized in that: The device is used to realize the conversion between the series connection state and the parallel connection state of the switched capacitor converter by controlling the switch states of each switch in the switched capacitor converter; the device comprises: The first control module is used for executing the conversion from the series state to the parallel state, taking the flying capacitors in series as the starting state, first disconnecting the switch connected to the power terminal PMID and the output terminal VOUT, cutting off the current path between the power terminal PMID and the output terminal VOUT; then starting from the output terminal VOUT side, sequentially connecting the flying capacitors in parallel between VOUT and the ground; and in this way, recursively layer by layer, finally all the flying capacitors can be connected in parallel to the output terminal VOUT; The second control module is used to switch from the parallel state to the series state. First, the switch connected to the upper plate or the lower plate of each flying capacitor is disconnected to cut off the current path from the flying capacitor to the output terminal VOUT; then, starting from the PMID side of the power terminal, the flying capacitors are connected in series in sequence; this is repeated layer by layer, and finally all the flying capacitors are connected in series together; finally, the series switch connected to the uppermost flying capacitor on the PMID side of the power terminal is closed to form a series path from the PMID side of the power terminal to the output terminal VOUT.

6. The switch capacitor converter circuit control timing device according to claim 5, characterized in that: When the first control module is used to execute the conversion from the series state to the parallel state, after a flying capacitor is connected in parallel to the output terminal VOUT, it is necessary to ensure that the series switch connected to the upper plate of the flying capacitor is disconnected.

7. The switched capacitor converter circuit control timing device according to claim 5, characterized in that: The second control module is used to switch from the parallel state to the series state, and before opening the series switch connected to the lower plate of the flying capacitor, ensure that the parallel switch connected to the lower plate of the flying capacitor is disconnected.

8. An electronic device, characterized in that: include: at least one processor; and a memory communicatively coupled to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the at least one processor executes the method as described in any one of claims 1 to 3 by executing the instructions stored in the memory.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium is used to store instructions, and when the instructions are executed, the method according to any one of claims 1 to 3 is implemented.

10. A computer program product, characterized in that When the computer program product is called by a computer, the computer executes the method according to any one of claims 1 to 3.

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