Efficiency-enhanced two-stage driving stacked frequency quadrupler

Abstract

The invention discloses an efficiency enhanced two-stage driving stacked frequency quadrupler. The frequency quadrupler comprises a differential signal generating circuit, an orthogonal signal generating circuit and a double-push frequency multiplier, through the orthogonal signal generation circuit, the use of an inter-stage balun is avoided, the loss is reduced to the maximum extent, and the efficiency of the frequency multiplier is improved; the double-push-type frequency multiplier adopts a series structure, a series resonance circuit is added to the input end of the first-stage double-push-type frequency multiplier, the output power and the second harmonic suppression capability of a transistor are improved, the first stage is biased in A and B classes, and the output drives the source electrode and the grid electrode of the second-stage double-push-type frequency multiplier; the stacked dual-drive structure enables the driving power required by the second stage to the first stage to be reduced, and the transconductance is improved; the current is multiplexed through stacking, and the direct-current power consumption is reduced; the second-stage double-push frequency multiplier is biased in class C, so that the output power and the drain efficiency are improved. According to the invention, the characteristics of high drain electrode efficiency and good harmonic suppression capability and output power are embodied.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency integrated circuits, and in particular to an efficiency-enhanced two-stage drive stacked quadruple frequency multiplier. Background Art

[0002] The increased spatial resolution provided by millimeter-wave frequencies has driven the development of improved W-band (75-110 GHz) radar systems designed for applications such as automotive radar and vital sign detection. However, the quality of these radar systems depends on the spectral purity of the frequency synthesis circuits. Unfortunately, high-frequency oscillator circuits suffer from phase noise and tuning range degradation due to device parasitics, low-quality passive devices, and transistor gain reduction, making the oscillator circuit a major bottleneck in practical systems. Frequency multipliers alleviate these challenges by allowing the use of lower-frequency oscillators, whose output signals can be multiplied to the required high-frequency frequencies. However, the high output power requirements of radar applications can lead to heating issues in large-scale systems, requiring the investigation of energy-efficient solutions for radar transmitters.

[0003] A Chinese patent (CN114759879A) discloses a push-push based double and triple frequency multiplier. The structure in the above patent uses an interstage balun to drive the second-stage double-push structure, and the first-stage double-push structure obtains double frequency. Generally, a quadruple frequency multiplier is usually designed by stacking or cascading two double frequency multipliers. However, if the structure of the above technical solution is used to achieve quadruple frequency, since the output end of the PPD is single-ended and the input end of the PPD is differential, an interstage balun is usually required when the two-stage PPD is cascaded. These baluns will introduce additional losses, thereby affecting the signal efficiency, which is extremely unfavorable for the radar transmitter and causes a loss in transmission efficiency. In other words, a high-efficiency transmitter frequency multiplication scheme should minimize the frequency multiplication loss.

[0004] To this end, the present application provides a solution that avoids the use of an inter-stage balun to improve drain efficiency. Summary of the invention

[0005] The present invention discloses an efficiency-enhanced two-stage drive stacked quadruple frequency multiplier, wherein the two-stage drive stacked quadruple frequency multiplier circuit comprises: a differential signal generating circuit, an orthogonal signal generating circuit, and a double-push frequency multiplier;

[0006] The differential signal generating circuit has an input terminal RF Input on the left side and ports a and a on the right side. ′ ;

[0007] The orthogonal signal generating circuit is provided with ports b and c on the left side and ports d and d on the right side ′ 、e、e ′ ;

[0008] The double-push frequency multiplier comprises a first-stage double-push frequency multiplier and a second-stage double-push frequency multiplier;

[0009] The left side of the first-stage double-push frequency multiplier is provided with ports f and f ′ ,g,g ′ , ports h and j are set on the right;

[0010] The left side of the second-stage double-push frequency multiplier is provided with ports k and k ′ , set the port RF Output on the right;

[0011] The right port a of the differential signal generating circuit is connected to the left port b of the orthogonal signal generating circuit. ′ Connected to the left port c of the orthogonal signal generating circuit;

[0012] The right port d of the orthogonal signal generating circuit is connected to the left port f of the first-stage double-push frequency multiplier. ′ The right port e of the orthogonal signal generating circuit is connected to the left port f of the first stage double-push frequency multiplier. ′ Connect the right port of the orthogonal signal generating circuit to ′ The left side port of the first stage double push type frequency multiplier g ′ connect;

[0013] The right port h of the first-stage double-push frequency multiplier is connected to the second-stage double-push frequency multiplier k, and the right port j of the first-stage double-push frequency multiplier is connected to the second-stage double-push frequency multiplier k. ′ connect;

[0014] The double-push frequency multiplier of the two-stage driven stacked quadruple frequency multiplier adopts a series structure, a series resonant circuit is added to the input end of the first-stage double-push frequency multiplier, the output power and second harmonic suppression capability of the transistor are improved, the output of the first-stage double-push frequency multiplier is used to drive the source and gate of the second-stage double-push frequency multiplier, so that the driving power required by the second-stage double-push frequency multiplier for the first-stage double-push frequency multiplier is reduced, and the current is reused by stacking, thereby reducing the DC power consumption of the two-stage driven stacked quadruple frequency multiplier;

[0015] The first-stage double-push frequency multiplier is biased in class A and B, and the second-stage double-push frequency multiplier is biased in class C.

[0016] Preferably, the differential signal generating circuit includes a transformer TR1, a capacitor C1, and a capacitor C2;

[0017] The transformer TR1 includes ports a1, b1, c1, d1, and e1;

[0018] The output port a of the differential signal generating circuit is formed by connecting the d end of the transformer TR1 and one end of the capacitor C2; the port a ′ The c end of the transformer TR1 is connected to the other end of the capacitor C2; the a end of the transformer TR1 is connected to one end of the capacitor C1 as the input end RF Input of the frequency multiplier; the other end of the capacitor C1 is grounded; the b end and the e end of the transformer TR1 are grounded.

[0019] Preferably, the orthogonal signal generating circuit includes transformers TR2, TR3, capacitor C3, capacitor C4, resistor R1, resistor R2;

[0020] The transformer TR2 includes ports a2, b2, c2, and d2;

[0021] The transformer TR3 includes ports a3, b3, c3, and d3;

[0022] The output port d of the orthogonal signal generating circuit is connected to the input port f of the first-stage double-push frequency multiplier, and the port d' is connected to the input port g of the first-stage double-push frequency multiplier. The output port e of the orthogonal signal generating circuit is connected to the input port f' of the first-stage double-push frequency multiplier, and the port e' is connected to the input port g' of the first-stage double-push frequency multiplier. The port b of the orthogonal signal generating circuit is formed by connecting the a2 end of the transformer TR2 and one end of the capacitor C3, and the port c of the orthogonal signal generating circuit is formed by connecting the a2 end of the transformer TR3 and one end of the capacitor C4. Port d of the quadrature signal generating circuit is formed by connecting the d2 end of the transformer TR2 and the other end of the capacitor C3, and the port d' of the orthogonal signal generating circuit is the b2 port of the transformer TR2; the c2 end of the transformer TR2 is connected to one end of the resistor R1, and the other end of the resistor R1 is grounded; port e of the orthogonal signal generating circuit is formed by connecting the d3 end of the transformer TR3 and the other end of the capacitor C4, and the port e' is the b3 port of the transformer TR3, the c3 end of the transformer TR3 is connected to one end of the resistor R2, and the other end of the resistor R2 is grounded.

[0023] Preferably, the first stage double push type frequency multiplier comprises an inductor L1, an inductor L2, an inductor L3, an inductor L4, an inductor L5, an inductor L6, an inductor L7, an inductor L8, an NMOS tube M1, an NMOS tube M2, an NMOS tube M3, an NMOS tube M4, an NMOS tube M7, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a resistor R 10 , capacitor C5, capacitor C6, capacitor C7, capacitor C8, capacitor C9, capacitor C 10 , capacitor C 11 , capacitor C 12 , bias voltage Vbias1;

[0024] The first-stage double-push frequency multiplier is composed of two double-push frequency multipliers with series resonant circuits; the output port h of the first-stage double-push frequency multiplier is connected to the input port k of the second-stage double-push frequency multiplier; the output port j of the first-stage double-push frequency multiplier is connected to the input port k' of the second-stage double-push frequency multiplier; the port f is the left port of the inductor L1, the port f' is the left port of the inductor L2, the port g is the left port of the inductor L3, and the port g' is the left port of the inductor L4;

[0025] The port h is formed by connecting the drain of the NMOS tube M1 and the drain of the NMOS tube M2, and the port j is formed by connecting the drain of the NMOS tube M3 and the drain of the NMOS tube M4; the other end of the inductor L1 is connected to one end of the inductor L5, one end of the resistor R3 and one end of the capacitor C5; the other end of the inductor L2 is connected to one end of the inductor L6, one end of the resistor R4 and one end of the capacitor C6; the other end of the inductor L3 is connected to one end of the inductor L7, one end of the resistor R5 and one end of the capacitor C7; the other end of the inductor L4 is connected to one end of the inductor L8, one end of the resistor R6 and one end of the capacitor C8; the other end of the inductor L5 is connected to the other end of the inductor L6 and is grounded; the other end of the inductor L7 is connected to the other end of the inductor L8 and is grounded, the other end of the resistor R3 is connected to the other end of the resistor R4 and one end of the inductor L9 and is grounded, the other end of the resistor R5 is connected to the other end of the resistor R6 and the inductor L 10 The other end of the capacitor C5 is connected to one end of the capacitor C9 and one end of the resistor R7 and the gate of the NMOS tube M1, and the other end of the capacitor C6 is connected to the capacitor C 10 One end of the resistor R8 is connected to the gate of the NMOS tube M2, and the other end of the capacitor C9 is connected to the capacitor C 10 The other end of the capacitor C7 is connected to the other end of the inductor L9, and the other end of the capacitor C 11 One end of the resistor R9 is connected to the gate of the NMOS tube M3, and the other end of the capacitor C8 is connected to the capacitor C 12 One end and resistor R 10 One end of the capacitor C is connected to the gate of the NMOS tube M4. 11 The other end of the capacitor C 12 The other end and the inductor L 10 The other end of the resistor R7 is connected to the other end of the resistor R8 and the other end of the resistor R9 and the resistor R 10 The other end and resistor R 11 One end of the resistor R is connected to the gate of the NMOS tube M7 and the gate drain of the NMOS tube M7. 11The other end is the access end of the bias voltage Vbias1, and the source of the NMOS tube M7, the source of the NMOS tube M1, the source of the NMOS tube M2, the source of the NMOS tube M3, and the source of the NMOS tube M4 are grounded.

[0026] Preferably, the second-stage double-push frequency multiplier comprises: transmission line TL1, transmission line TL2, transmission line TL3, transmission line TL4, transmission line TL5, transmission line TL6, transmission line TL7, transmission line TL8, transmission line TL9, transmission line TL 10 , Transmission Line TL 11 , capacitor C 13 , capacitor C 14 , capacitor C 15 , capacitor C 16 , capacitor C 17 , NMOS tube M5, NMOS tube M6, bias voltage Vbias2;

[0027] The second-stage double-push frequency multiplier is composed of a double-push frequency multiplier with a cross-coupling structure. Port k of the second-stage double-push frequency multiplier is a port of the transmission line TL1, and port k' is a port of the transmission line TL4. The other end of the transmission line TL1 is connected to one end of the transmission line TL2 and one end of the transmission line TL3. The other end of the transmission line TL2 is connected to the capacitor C 13 One end of the capacitor C 13 The other end of the transmission line TL4 is connected to one end of the transmission line TL5 and one end of the transmission line TL6, and the other end of the transmission line TL5 is connected to the capacitor C 14 One end of the capacitor C 14 The other end of the transmission line TL3 is connected to one end of the transmission line TL7 and the gate of the NMOS tube M5 and the source of the NMOS tube M6; the other end of the transmission line TL7 is connected to the capacitor C 15 One end of the capacitor C is connected as the access end of the bias voltage Vbias2. 15 The other end of the transmission line TL6 is connected to one end of the transmission line TL8 and the gate of the NMOS tube M6 and the source of the NMOS tube M5. The other end of the transmission line TL8 is connected to the capacitor C 16 One end of the capacitor C is connected as the access end of the bias voltage Vbias2. 16 The other end of the NMOS tube M5 is grounded, the drain of the NMOS tube M6 is connected to one end of the transmission line TL9, and the other end of the transmission line TL9 is connected to the transmission line TL 10 One end of the transmission line TL 11 One end of the transmission line TL 10 The other end of the capacitor C17 One end of the capacitor C is connected as the access end of the power supply voltage. 17 The other end of the transmission line TL is grounded. 11 The other end serves as the output end RF Output of the quadruple frequency multiplier.

[0028] Compared with the prior art, the technical solution of this application has the following technical effects:

[0029] The two-stage driven stacked quadruple frequency multiplier of the present invention adds an orthogonal signal generating circuit to replace the use of the inter-stage balun, thereby minimizing the loss and improving the peak drain efficiency of the frequency multiplier. A series resonant circuit is added to the input end of the first-stage double-push frequency multiplier to improve the output power and second harmonic suppression capability of the transistor. The first-stage double-push frequency multiplier is biased in Class A and Class B. A stacked dual-drive structure is adopted between the first and second stages to reduce the driving power required by the second stage for the first stage, and current is reused by stacking, thereby reducing the DC power consumption of the frequency multiplier. The second-stage double-push frequency multiplier is biased in Class C, so that the output power and drain efficiency are further improved.

[0030] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application so that it can be implemented in accordance with the contents of the specification, and to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the following is a detailed description of the preferred embodiments of the present application in conjunction with the accompanying drawings as follows.

[0031] Based on the detailed description of the specific embodiments of the present application in combination with the accompanying drawings below, those skilled in the art will become more aware of the above and other objects, advantages and features of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings without creative work. In all drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, each element or part is not necessarily drawn according to the actual scale.

[0033] Figure 1 is a circuit diagram of a quadruple frequency multiplier of the present invention;

[0034] Figure 2 is the input matching characteristic S of the present invention 11 Schematic diagram;

[0035] Figure 3 The output matching characteristic S of the present invention22 Schematic diagram;

[0036] Figure 4 It is a schematic diagram of the relationship between the output power and the input power of the present invention at 88GHz;

[0037] Figure 5 It is a schematic diagram of the relationship between conversion gain and input power at 88 GHz of the present invention;

[0038] Figure 6 It is a schematic diagram of efficiency and input power of the present invention at 88 GHz;

[0039] Figure 7 It is a schematic diagram of the output power of the present invention at an input power of 5.3dBm;

[0040] Figure 8 It is a schematic diagram of the peak efficiency of the present invention at an input power of 5.3dBm;

[0041] Fig. 9 It is a schematic diagram of harmonic suppression of the present invention at an input power of 5.3dBm. DETAILED DESCRIPTION

[0042] To make the purpose, technical scheme and advantages of the embodiment of the present application clearer, the technical scheme in the embodiment of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiment of the present application. Obviously, the described embodiment is a part of the embodiment of the present application, rather than all of the embodiments. In the following description, specific details such as specific configuration and components are provided only to help fully understand the embodiments of the present application. Therefore, it should be clear to those skilled in the art that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present application. In addition, for clarity and brevity, the description of known functions and structures is omitted in the embodiment.

[0043] It should be understood that the references to "one embodiment" or "this embodiment" throughout the specification mean that the specific features, structures, or characteristics associated with the embodiment are included in at least one embodiment of the present application. Therefore, the references to "one embodiment" or "this embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0044] In addition, the present application may repeat reference numerals and / or letters in different examples. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate the relationship between the various embodiments and / or settings discussed.

[0045] The term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, B exists alone, and A and B exist at the same time. The term " / and" in this article describes another type of association object relationship, indicating that there can be two relationships. For example, A / and B can mean: A exists alone, and A and B exist alone. In addition, the character " / " in this article generally indicates that the previous and next associated objects are in an "or" relationship.

[0046] The term "at least one" in this article is merely a description of the association relationship of associated objects, indicating that there may be three relationships. For example, at least one of A and B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0047] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusions.

[0048] Example 1

[0049] This embodiment mainly describes an efficiency-enhanced two-stage drive stacked quadruple frequency multiplier, such as Figure 1 As shown, the two-stage drive stacked quadruple frequency multiplier circuit includes: a differential signal generating circuit, an orthogonal signal generating circuit, and a double-push frequency multiplier;

[0050] The left side of the differential signal generation circuit is set with the input terminal RF Input, and the right side is set with ports a and a ′ ;

[0051] The orthogonal signal generating circuit has ports b and c on the left and ports d and d on the right. ′ 、e、e ′ ;

[0052] The double-push frequency multiplier comprises a first-stage double-push frequency multiplier and a second-stage double-push frequency multiplier;

[0053] The left side of the first-stage double-push frequency multiplier is provided with ports f and f ′ ,g,g ′ , ports h and j are set on the right;

[0054] The left side of the second-stage double-push frequency multiplier is provided with ports k and k ′ , set the port RF Output on the right;

[0055] The right port a of the differential signal generating circuit is connected to the left port b of the orthogonal signal generating circuit. The right port a of the differential signal generating circuit ′ Connected to the left port c of the orthogonal signal generating circuit;

[0056] The right port d of the orthogonal signal generating circuit is connected to the left port f of the first-stage double-push frequency multiplier. ′ Connected to the left port g of the first-stage double-push frequency multiplier; the right port e of the orthogonal signal generating circuit is connected to the left port f of the first-stage double-push frequency multiplier ′ Connect the right port of the orthogonal signal generating circuit to ′ The left side port of the first stage double push type frequency multiplier g ′ connect;

[0057] The right port h of the first-stage double-push frequency multiplier is connected to the second-stage double-push frequency multiplier k, and the right port j of the first-stage double-push frequency multiplier is connected to the second-stage double-push frequency multiplier k. ′ connect;

[0058] The double-push frequency multiplier of the two-stage drive stacked quadruple frequency multiplier adopts a series structure, a series resonant circuit is added to the input end of the first-stage double-push frequency multiplier, the output power and second harmonic suppression capability of the transistor are improved, the output of the first-stage double-push frequency multiplier is used to drive the source and gate of the second-stage double-push frequency multiplier, so that the driving power required by the second-stage double-push frequency multiplier for the first-stage double-push frequency multiplier is reduced, and the current is reused by stacking, thereby reducing the DC power consumption of the two-stage drive stacked quadruple frequency multiplier;

[0059] The first-stage double-push frequency multiplier is biased in class A and B, and the second-stage double-push frequency multiplier is biased in class C.

[0060] Further, the differential signal generating circuit includes a transformer TR1, a capacitor C1, and a capacitor C2;

[0061] The transformer TR1 includes ports a1, b1, c1, d1, and e1;

[0062] The output port a of the differential signal generating circuit is formed by connecting the d end of the transformer TR1 and one end of the capacitor C2; port a ′ The c end of the transformer TR1 is connected to the other end of the capacitor C2; the a end of the transformer TR1 is connected to one end of the capacitor C1 as the input end RF Input of the frequency multiplier; the other end of the capacitor C1 is grounded; the b end and the e end of the transformer TR1 are grounded.

[0063] Further, the orthogonal signal generating circuit includes transformers TR2, TR3, capacitor C3, capacitor C4, resistor R1, resistor R2;

[0064] Transformer TR2 includes ports a2, b2, c2, and d2;

[0065] Transformer TR3 includes ports a3, b3, c3, d3;

[0066] The output port d of the orthogonal signal generating circuit is connected to the input port f of the first-stage double-push frequency multiplier, and the port d' is connected to the input port g of the first-stage double-push frequency multiplier. The output port e of the orthogonal signal generating circuit is connected to the input port f' of the first-stage double-push frequency multiplier, and the port e' is connected to the input port g' of the first-stage double-push frequency multiplier. The port b of the orthogonal signal generating circuit is formed by connecting the a2 end of the transformer TR2 and one end of the capacitor C3, and the port c of the orthogonal signal generating circuit is formed by connecting the a2 end of the transformer TR3 and one end of the capacitor C4. ; Port d of the orthogonal signal generating circuit is formed by connecting the d2 end of the transformer TR2 and the other end of the capacitor C3, and the port d' of the orthogonal signal generating circuit is the b2 port of the transformer TR2; the c2 end of the transformer TR2 is connected to one end of the resistor R1, and the other end of the resistor R1 is grounded; port e of the orthogonal signal generating circuit is formed by connecting the d3 end of the transformer TR3 and the other end of the capacitor C4, and port e' is the b3 port of the transformer TR3, the c3 end of the transformer TR3 is connected to one end of the resistor R2, and the other end of the resistor R2 is grounded.

[0067] Furthermore, the first-stage double-push frequency multiplier includes an inductor L1, an inductor L2, an inductor L3, an inductor L4, an inductor L5, an inductor L6, an inductor L7, an inductor L8, an NMOS tube M1, an NMOS tube M2, an NMOS tube M3, an NMOS tube M4, an NMOS tube M7, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a resistor R 10 , capacitor C5, capacitor C6, capacitor C7, capacitor C8, capacitor C9, capacitor C 10 , capacitor C 11 , capacitor C 12 , bias voltage Vbias1;

[0068] The first-stage double-push frequency multiplier is composed of two double-push frequency multipliers with series resonant circuits; the output port h of the first-stage double-push frequency multiplier is connected to the input port k of the second-stage double-push frequency multiplier; the output port j of the first-stage double-push frequency multiplier is connected to the input port k' of the second-stage double-push frequency multiplier; the port f is the left port of the inductor L1, the port f' is the left port of the inductor L2, the port g is the left port of the inductor L3, and the port g' is the left port of the inductor L4;

[0069] Port h is formed by connecting the drain of NMOS tube M1 and the drain of NMOS tube M2, and port j is formed by connecting the drain of NMOS tube M3 and the drain of NMOS tube M4; the other end of inductor L1 is connected to one end of inductor L5, one end of resistor R3 and one end of capacitor C5; the other end of inductor L2 is connected to one end of inductor L6, one end of resistor R4 and one end of capacitor C6; the other end of inductor L3 is connected to one end of inductor L7, one end of resistor R5 and one end of capacitor C7; the other end of inductor L4 is connected to one end of inductor L8, one end of resistor R6 and one end of capacitor C8; the other end of inductor L5 is connected to the other end of inductor L6 and grounded; the other end of inductor L7 is connected to the other end of inductor L8 and grounded, the other end of resistor R3 is connected to the other end of resistor R4 and one end of inductor L9 and grounded, the other end of resistor R5 is connected to the other end of resistor R6 and the other end of inductor L7. 10 The other end of capacitor C5 is connected to one end of capacitor C9, one end of resistor R7 and the gate of NMOS tube M1, and the other end of capacitor C6 is connected to capacitor C 10 One end of the resistor R8 is connected to the gate of the NMOS tube M2, and the other end of the capacitor C9 is connected to the capacitor C 10 The other end of the capacitor C7 is connected to the other end of the inductor L9, and the other end of the capacitor C 11 One end of the resistor R9 is connected to the gate of the NMOS tube M3, and the other end of the capacitor C8 is connected to the capacitor C 12 One end and resistor R 10 One end of the capacitor is connected to the gate of the NMOS tube M4, and the capacitor C 11 The other end of the capacitor C 12 The other end and the inductor L 10 The other end of the resistor R7 is connected to the other end of the resistor R8 and the other end of the resistor R9 and the resistor R 10 The other end and resistor R 11 One end of the resistor R is connected to the gate of the NMOS tube M7 and the gate drain of the NMOS tube M7. 11 The other end is the access end of the bias voltage Vbias1, and the source of the NMOS tube M7, the source of the NMOS tube M1, the source of the NMOS tube M2, the source of the NMOS tube M3, and the source of the NMOS tube M4 are grounded.

[0070] Furthermore, the second-stage double-push frequency multiplier includes: transmission line TL1, transmission line TL2, transmission line TL3, transmission line TL4, transmission line TL5, transmission line TL6, transmission line TL7, transmission line TL8, transmission line TL9, transmission line TL 10 , Transmission Line TL 11 , capacitor C 13 , capacitor C 14 , capacitor C15 , capacitor C 16 , capacitor C 17 , NMOS tube M5, NMOS tube M6, bias voltage Vbias2;

[0071] The second-stage double-push frequency multiplier is composed of a double-push frequency multiplier with a cross-coupling structure. Port k of the second-stage double-push frequency multiplier is a port of the transmission line TL1, port k' is a port of the transmission line TL4, the other end of the transmission line TL1 is connected to one end of the transmission line TL2 and one end of the transmission line TL3, and the other end of the transmission line TL2 is connected to the capacitor C 13 One end of the capacitor C 13 The other end of the transmission line TL4 is connected to one end of the transmission line TL5 and one end of the transmission line TL6, and the other end of the transmission line TL5 is connected to the capacitor C 14 One end of the capacitor C 14 The other end of the transmission line TL3 is connected to the ground, the other end of the transmission line TL7 is connected to the gate of the NMOS tube M5 and the source of the NMOS tube M6; the other end of the transmission line TL7 is connected to the capacitor C 15 One end of the capacitor C is connected as the input end of the bias voltage Vbias2. 15 The other end of the transmission line TL6 is connected to one end of the transmission line TL8 and the gate of the NMOS tube M6 and the source of the NMOS tube M5. The other end of the transmission line TL8 is connected to the capacitor C 16 One end of the capacitor C is connected as the input end of the bias voltage Vbias2. 16 The other end of the NMOS tube M5 is grounded, the drain of the NMOS tube M6 is connected to one end of the transmission line TL9, and the other end of the transmission line TL9 is connected to the transmission line TL 10 One end of the transmission line TL 11 One end of the transmission line TL 10 The other end of the capacitor C 17 One end of the capacitor is connected as the power supply voltage access terminal, and the capacitor C 17 The other end of the transmission line TL is grounded. 11 The other end serves as the output end RF Output of the quadruple frequency multiplier.

[0072] This embodiment adds an orthogonal signal generating circuit to replace the inter-stage balun, thereby minimizing the loss and improving the efficiency of the frequency multiplier. The frequency multiplier adopts a two-stage double-push frequency multiplier cascade structure, and a series resonant circuit is added to the input end of the first stage. The output power and second harmonic suppression capability of the transistor are improved. The output of the first stage is used to drive the source and gate of the second stage, so that the driving power required by the second stage for the first stage is reduced, and the current is reused by stacking, thereby reducing the DC power consumption of the frequency multiplier. At the same time, the first-stage double-push frequency multiplier is biased in class AB, and the second-stage double-push frequency multiplier is also biased in class C, and the output power and drain efficiency are further improved.

[0073] Example 2

[0074] This embodiment is based on Embodiment 1 and describes in detail a simulation experiment of an efficiency-enhanced two-stage drive stacked quadruple frequency multiplier, specifically including:

[0075] The two-stage drive stacked quadruple frequency multiplier is composed of a differential signal generating circuit and an orthogonal generating circuit and a two-stage double-push frequency multiplier, wherein the differential signal generating circuit is composed of a transformer TR1, and the signal is also converted into a differential signal when input matching is achieved, and the orthogonal generating circuit is composed of two transformers TR2 and TR3 with feedforward capacitors, and the differential signal is converted into four signals with a phase difference of 90°, wherein the feedforward capacitor can ensure that the transformer performs fine phase control, and achieves an accurate phase shift of 90° between output signals, and also avoids the use of inter-stage baluns, thereby minimizing losses and improving the efficiency of the quadruple frequency multiplier;

[0076] A series resonant circuit is added to the input end of the first-stage double-push frequency multiplier, which improves the output power of the transistor and short-circuits the second harmonic to the ground through the resonant circuit, thereby improving the second harmonic suppression capability. At the same time, a shunt Q-reducing resistor is added to the resonator to expand the matching bandwidth between the orthogonal generation circuit and the double-push frequency multiplier. In order to effectively drive the second-stage double-push frequency multiplier, the first-stage double-push frequency multiplier is biased in class AB, while the second-stage double-push frequency multiplier is biased in class C for efficiency. The first-stage double-push frequency multiplier is designed to drive the gate and source of the second stage. This stacked dual-drive structure reduces the driving power required by the second stage for the first stage, and current reuse is achieved through stacking, thereby reducing the DC power consumption of the frequency multiplier, while the output power and drain efficiency are further improved.

[0077] In the simulation experiment, the circuit of the two-stage driven stacked quadruple frequency multiplier is designed with a 90nm CMOS process, a power supply voltage of 3V, an operating frequency covering 83-95GHz, an overall circuit power consumption of 50mW, a peak output power of 6.8dBm, a conversion gain of 2.2dB, a peak drain efficiency of 10.3%, and harmonic suppression greater than 31dBc.

[0078] like Figure 1 As shown, the key parameters of the circuit are: C1 = 186fF, C2 = 160fF, C 3，4 =142fF, C 5，6，7，8 =1pF, C 9，10，11，12 =148fF, C 13，14 =320fF, C 15，16，17 =10pF;

[0079] L ab1 =L cd1 =90pH, k1=0.75, L ab2 =L cd2 =L ab3 =L cd3 =253pH, k2=k3=0.66, L1=L2=L3=L4=120pH,

[0080] L5=L6=L7=L8=360pH, L9=L 10 =40pH, R1=R2=25Ω, R3=R4=R6=R6=100Ω, R7=R8=R9=R 10 =10kΩ,

[0081] Wm1=Wm2=Wm3=Wm4=Wm7=24um, Wm5=Wm6=30um;

[0082] TL1=TL4=50Ω / 26°, TL2=TL5=50Ω / 33°, TL3=TL6=30Ω / 24°, TL7=TL8=30Ω / 90°, TL9=35Ω / 28°, TL 10 =50Ω / 8°, TL 11 =35Ω / 20°;

[0083] like Figure 2 As shown, the input matching characteristic S of the present invention is given. 11 Simulation results show that in the 20-24 GHz frequency band, S 11 All less than -10dB;

[0084] like Figure 3 As shown, the output matching characteristic S of the present invention is given. 22 Simulation results show that in the 83-95GHz frequency band, S 22 All less than -10dB;

[0085] like Figure 4 As shown in the figure, the simulation results of the relationship between output power and input power at 88GHz are given. When the input power is greater than 5.2dBm, the output power basically remains stable at 6.8dBm.

[0086] like Figure 5 As shown in the figure, the simulation results of the relationship between conversion gain and input power at 88GHz are given. When the input power is 5.3dBm, the conversion gain reaches a maximum of 2.2dB;

[0087] like Figure 6 As shown, the simulation results of the relationship between drain efficiency and input power at 88GHz are given. When the input power is 5.3dBm, the drain efficiency reaches a maximum of 10.2%;

[0088] like Figure 7 As shown, the simulation results of the output power when the input power is 5.3dBm are given. The output power varies from 3 to 6.8dBm in the 83-95GHz frequency band, and the maximum value of 6.8dBm is achieved at the center frequency.

[0089] like Figure 8 As shown, the simulation results of the peak drain efficiency at an input power of 5.3dBm are given. The output power varies from 8.3% to 10.3% in the 83-95GHz band, and the maximum value of 10.3% is achieved at the center frequency.

[0090] like Fig. 9 As shown, the simulation results of harmonic suppression when the input power is 5.3dBm are given. In the frequency band of 83-95GHz, the fundamental wave suppression is 46dBc, the second harmonic suppression is 31dBc, and the third harmonic suppression is 35dBc.

[0091] Table 1 Parameter performance comparison

[0092]

[0093] The existing technology is: BH Ku, H Chung, GM Rebeiz.A Milliwatt-Level 70-110 GHzFrequencyQuadrupler With>30 dBc Harmonic Rejection[J].IEEE TRANSACTIONS ONMICROWAVETHEORY AND TECHNIQUES, 2020, 68(5): 1697-1705.

[0094] As can be seen from Table 1, since the frequency doubler of the present invention adds an orthogonal signal generating circuit, the use of an inter-stage balun is avoided, the loss is minimized and the peak drain efficiency of the frequency doubler is improved, so that the present invention has a significant advantage in efficiency performance, compared with the conventional cascade double frequency multiplication scheme of the prior art. In addition, the output power and power consumption of the present invention are also significantly better than the prior art, which makes the present invention a high-efficiency quadruple frequency multiplier advantage solution suitable for W-band transmitters.

[0095] This embodiment introduces in detail a simulation test of an efficiency-enhanced two-stage driven stacked quadruple frequency multiplier. Through the simulation test results, it is found that the frequency multiplier of the present invention avoids the use of inter-stage baluns, minimizes losses and improves the peak drain efficiency of the frequency multiplier, presents significant advantages in efficiency performance, and becomes a high-efficiency quadruple frequency multiplier advantage solution suitable for W-band transmitters.

[0096] The above are only preferred embodiments of the present invention, which do not limit the scope of protection of the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any changes, modifications, replacements, integrations and parameter changes to these embodiments within the spirit and principles of the present invention through conventional substitutions or without departing from the principles and spirit of the present invention fall within the scope of protection of the present invention.

Claims

1. An efficiency-enhanced two-stage drive stacked quadruple frequency multiplier, characterized in that: The two-stage drive stacked quadruple frequency multiplier circuit comprises: a differential signal generating circuit, an orthogonal signal generating circuit, and a double-push frequency multiplier; The differential signal generating circuit has an input terminal RF Input on the left side and ports a and a on the right side. ′ ; The orthogonal signal generating circuit is provided with ports b and c on the left side and ports d and d on the right side ′ 、e、e ′ ; The double-push frequency multiplier comprises a first-stage double-push frequency multiplier and a second-stage double-push frequency multiplier; The left side of the first-stage double-push frequency multiplier is provided with ports f and f ′ ,g,g ′ , ports h and j are set on the right; The left side of the second-stage double-push frequency multiplier is provided with ports k and k ′ , set the port RF Output on the right; The right port a of the differential signal generating circuit is connected to the left port b of the orthogonal signal generating circuit. ′ Connected to the left port c of the orthogonal signal generating circuit; The right port d of the orthogonal signal generating circuit is connected to the left port f of the first-stage double-push frequency multiplier. ′ Connected to the left port g of the first-stage double-push frequency multiplier; the right port e of the orthogonal signal generating circuit is connected to the left port f of the first-stage double-push frequency multiplier ′ Connect the right port of the orthogonal signal generating circuit to ′ The left side port of the first stage double push type frequency multiplier g ′ connect; The right port h of the first-stage double-push frequency multiplier is connected to the second-stage double-push frequency multiplier k, and the right port j of the first-stage double-push frequency multiplier is connected to the second-stage double-push frequency multiplier k. ′ connect; The double-push frequency multiplier of the two-stage driven stacked quadruple frequency multiplier adopts a series structure, a series resonant circuit is added to the input end of the first-stage double-push frequency multiplier, the output power and second harmonic suppression capability of the transistor are improved, the output of the first-stage double-push frequency multiplier is used to drive the source and gate of the second-stage double-push frequency multiplier, so that the driving power required by the second-stage double-push frequency multiplier for the first-stage double-push frequency multiplier is reduced, and the current is reused by stacking, thereby reducing the DC power consumption of the two-stage driven stacked quadruple frequency multiplier; The first-stage double-push frequency multiplier is biased in class A and B, and the second-stage double-push frequency multiplier is biased in class C.

2. The efficiency-enhanced two-stage drive stacked quadruple frequency multiplier according to claim 1, characterized in that: The differential signal generating circuit includes a transformer TR1, a capacitor C1, and a capacitor C2; The transformer TR1 includes ports a1, b1, c1, d1, and e1; The output port a of the differential signal generating circuit is formed by connecting the d end of the transformer TR1 and one end of the capacitor C2; the port a ′ The c end of the transformer TR1 is connected to the other end of the capacitor C2; the a end of the transformer TR1 is connected to one end of the capacitor C1 as the input end RF Input of the frequency multiplier; the other end of the capacitor C1 is grounded; the b end and the e end of the transformer TR1 are grounded.

3. The efficiency-enhanced two-stage drive stacked quadruple frequency multiplier according to claim 1, characterized in that: The orthogonal signal generating circuit includes transformers TR2, TR3, capacitor C3, capacitor C4, resistor R1, resistor R2; The transformer TR2 includes ports a2, b2, c2, and d2; The transformer TR3 includes ports a3, b3, c3, and d3; The output port d of the orthogonal signal generating circuit is connected to the input port f of the first-stage double-push frequency multiplier, and the port d' is connected to the input port g of the first-stage double-push frequency multiplier. The output port e of the orthogonal signal generating circuit is connected to the input port f' of the first-stage double-push frequency multiplier, and the port e' is connected to the input port g' of the first-stage double-push frequency multiplier. The port b of the orthogonal signal generating circuit is formed by connecting the a2 end of the transformer TR2 and one end of the capacitor C3, and the port c of the orthogonal signal generating circuit is formed by connecting the a2 end of the transformer TR3 and one end of the capacitor C4. Port d of the quadrature signal generating circuit is formed by connecting the d2 end of the transformer TR2 and the other end of the capacitor C3, and port d' of the orthogonal signal generating circuit is the v2 port of the transformer TR2; the c2 end of the transformer TR2 is connected to one end of the resistor R1, and the other end of the resistor R1 is grounded; port e of the orthogonal signal generating circuit is formed by connecting the d3 end of the transformer TR3 and the other end of the capacitor C4, and port e' is the b3 port of the transformer TR3, the c3 end of the transformer TR3 is connected to one end of the resistor R2, and the other end of the resistor R2 is grounded.

4. The efficiency-enhanced two-stage drive stacked quadruple frequency multiplier according to claim 1, characterized in that: The first stage double push type frequency multiplier comprises an inductor L1, an inductor L2, an inductor L3, an inductor L4, an inductor L5, an inductor L6, an inductor L7, an inductor L8, an NMOS tube M1, an NMOS tube M2, an NMOS tube M3, an NMOS tube M4, an NMOS tube M7, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a resistor R 10 , capacitor C5, capacitor C6, capacitor C7, capacitor C8, capacitor C9, capacitor C 10 , capacitor C 11 , capacitor C 12 , bias voltage Vbias1; The first-stage double-push frequency multiplier is composed of two double-push frequency multipliers with series resonant circuits; the output port h of the first-stage double-push frequency multiplier is connected to the input port k of the second-stage double-push frequency multiplier; the output port j of the first-stage double-push frequency multiplier is connected to the input port k' of the second-stage double-push frequency multiplier; the port f is the left port of the inductor L1, the port f' is the left port of the inductor L2, the port g is the left port of the inductor L3, and the port g' is the left port of the inductor L4; The port h is formed by connecting the drain of the NMOS tube M1 and the drain of the NMOS tube M2, and the port j is formed by connecting the drain of the NMOS tube M3 and the drain of the NMOS tube M4; the other end of the inductor L1 is connected to one end of the inductor L5, one end of the resistor R3 and one end of the capacitor C5; the other end of the inductor L2 is connected to one end of the inductor L6, one end of the resistor R4 and one end of the capacitor C6; the other end of the inductor L3 is connected to one end of the inductor L7, one end of the resistor R5 and one end of the capacitor C7; the other end of the inductor L4 is connected to one end of the inductor L8, one end of the resistor R6 and one end of the capacitor C8; the other end of the inductor L5 is connected to the other end of the inductor L6 and is grounded; the other end of the inductor L7 is connected to the other end of the inductor L8 and is grounded, the other end of the resistor R3 is connected to the other end of the resistor R4 and one end of the inductor L9 and is grounded, the other end of the resistor R5 is connected to the other end of the resistor R6 and the inductor L 10 The other end of the capacitor C5 is connected to one end of the capacitor C9 and one end of the resistor R7 and the gate of the NMOS tube M1, and the other end of the capacitor C6 is connected to the capacitor C 10 One end of the resistor R8 is connected to the gate of the NMOS tube M2, and the other end of the capacitor C9 is connected to the capacitor C 10 The other end of the capacitor C7 is connected to the other end of the inductor L9, and the other end of the capacitor C 11 One end of the resistor R9 is connected to the gate of the NMOS tube M3, and the other end of the capacitor C8 is connected to the capacitor C 12 One end and resistor R 10 One end of the capacitor C is connected to the gate of the NMOS tube M4. 11 The other end of the capacitor C 12 The other end and the inductor L 10 The other end of the resistor R7 is connected to the other end of the resistor R8 and the other end of the resistor R9 and the resistor R 10 The other end and resistor R 11 One end of the resistor R is connected to the gate of the NMOS tube M7 and the gate drain of the NMOS tube M7. 11 The other end is the access end of the bias voltage Vbias1, and the source of the NMOS tube M7, the source of the NMOS tube M1, the source of the NMOS tube M2, the source of the NMOS tube M3, and the source of the NMOS tube M4 are grounded.

5. The efficiency-enhanced two-stage drive stacked quadruple frequency multiplier according to claim 1, characterized in that: The second-stage double-push frequency multiplier includes: transmission line TL1, transmission line TL2, transmission line TL3, transmission line TL4, transmission line TL5, transmission line TL6, transmission line TL7, transmission line TL8, transmission line TL9, transmission line TL 10 , Transmission Line TL 11 , capacitor C 13 , capacitor C 14 , capacitor C 15 , capacitor C 16 , capacitor C 17 , NMOS tube M5, NMOS tube M6, bias voltage Vbias2; The second-stage double-push frequency multiplier is composed of a double-push frequency multiplier with a cross-coupling structure. Port k of the second-stage double-push frequency multiplier is a port of the transmission line TL1, and port k' is a port of the transmission line TL4. The other end of the transmission line TL1 is connected to one end of the transmission line TL2 and one end of the transmission line TL3. The other end of the transmission line TL2 is connected to the capacitor C 13 One end of the capacitor C 13 The other end of the transmission line TL4 is connected to one end of the transmission line TL5 and one end of the transmission line TL6, and the other end of the transmission line TL5 is connected to the capacitor C 14 One end of the capacitor C 14 The other end of the transmission line TL3 is connected to one end of the transmission line TL7 and the gate of the NMOS tube M5 and the source of the NMOS tube M6; the other end of the transmission line TL7 is connected to the capacitor C 15 One end of the capacitor C is connected as the access end of the bias voltage Vbias2. 15 The other end of the transmission line TL6 is connected to one end of the transmission line TL8 and the gate of the NMOS tube M6 and the source of the NMOS tube M5. The other end of the transmission line TL8 is connected to the capacitor C 16 One end of the capacitor C is connected as the access end of the bias voltage Vbias2. 16 The other end of the NMOS tube M5 is grounded, the drain of the NMOS tube M6 is connected to one end of the transmission line TL9, and the other end of the transmission line TL9 is connected to the transmission line TL 10 One end of the transmission line TL 11 One end of the transmission line TL 10 The other end of the capacitor C 17 One end of the capacitor C is connected as the access end of the power supply voltage. 17 The other end of the transmission line TL is grounded. 11 The other end serves as the output end RF Output of the quadruple frequency multiplier.

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