High-linearity broadband passive mixer

Abstract

The high-linearity broadband passive mixer comprises an RF impedance matching network, an IF impedance matching network, an LO pre-driver, a stacked LO driver and a switch core, a radio frequency signal enters from the P3 port and the P4 port, enters the RF impedance matching network, is transmitted to the A port and the B port through the X port and the Y port, enters the switch core, and finally is transmitted to the E port and the F port, and enters the IF impedance matching network; a local oscillator signal enters from the P1 port and the P2 port, enters the LO pre-driver, is transmitted through the H port and the Z port, enters the switch core through the double-path stacked LO driver, reaches the IF impedance matching network through the E port and the F port, and finally outputs an IF signal through the P5 port and the P6 port. According to the invention, the working frequency range is 7 GHz to 20 GHz, the RF impedance matching network adopts a hybrid coupling structure, the IF impedance matching network adopts a low-pass four-order LC structure, and the LO pre-driver and the stacked LO driver are cascaded to realize the ultrahigh linearity, low power consumption and ultra-wideband performance of an IF signal.

Description

Technical Field

[0001] The invention relates to the technical field of radio frequency wireless communication, and in particular to a high-linearity broadband passive mixer. Background Art

[0002] A passive mixer is an RF device whose core function is to combine two signals of different frequencies (usually an input RF signal and a local oscillator signal) to produce a new frequency component without the need for an external power supply to provide gain. Wideband communication systems are gaining more and more attention today due to the demand for higher data rates, especially in the FR3 band for 7-20 GHz 5G communications. These systems use wideband RF front-ends to support multi-band operation and inter-band carrier aggregation. However, these functions are achieved at the expense of a large amount of unfiltered interference, which imposes strict linearity requirements on the components in the RF signal path. In digital beamforming arrays, wideband low-noise amplifiers amplify the interference signal, resulting in a greatly increased interference signal level at the mixer input. In RF beamforming arrays, the situation is slightly better because before the mixer, the out-of-beam blocking interference is usually attenuated after the beam is combined, reducing the interference to the subsequent mixer. Nevertheless, for arrays with a large number of elements or jammers in the main beam, the main signal and interference signal power levels at the mixer input can be very large. Therefore, large signal linearity (IP1dB) and small signal linearity (IIP3) are critical for mixers deployed in broadband systems (especially base stations). The use of these solutions will inevitably cause interference to the broadband system in the new FR3 band. Therefore, providing high-linearity broadband passive mixers for the new 5G communication FR3 band has become particularly commercially valuable and technically significant.

[0003] Looking back, traditional technologies mostly use double-balanced mixers or single-balanced mixers. For example, a Chinese patent (CN118381472A) discloses a high harmonic suppression mixer, and provides an active mixer based on a single-balanced structure design, including an NMOS tube Q1, HBT tubes Q2 and Q3, and a resistor R 1～3 ; The local oscillator signal is isolated through HBT tubes Q2 and Q3 to reduce the interference of the local oscillator signal on the output signal; however, the use of HBT tubes Q2 and Q3 will change with temperature, resulting in unstable static operating points. At the same time, the active structure in the above technology has poor linearity and a bandwidth of only 6GHz, which cannot meet the high linearity requirements of the broadband system in the new 5G communication FR3 band.

[0004] Therefore, the existing mixers have poor linearity and low bandwidth, and are unable to meet the high linearity requirements of the broadband system in the new 5G communication FR3 band, thereby restricting the overall performance of the mixer. To this end, the present invention provides a high-linearity broadband passive mixer with ultra-high linearity and ultra-wideband advantages. Summary of the invention

[0005] The invention discloses a high linearity broadband passive mixer, comprising: an RF impedance matching network, an IF impedance matching network, an LO pre-driver, a stacked LO driver, and a switch core;

[0006] Ports P3, P4 and ports A, B are arranged on both sides of the RF impedance matching network; the RF impedance matching network includes: a capacitor C m , capacitor C s , capacitor C a 、Inductance L p 、Inductance L s 、Inductance L d 、Inductance L a ;

[0007] Ports P5, P6 and ports E, F are arranged on both sides of the IF impedance matching network; the IF impedance matching network comprises: capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, inductor L1, inductor L2, inductor L3, inductor L4;

[0008] Ports A and B and ports C and D are arranged on both sides of the switch core; the switch core includes switches S1, S2, S3, and S4, which have the same switch structure; the switch structure includes: NMOS tube M s1 、NMOS tube M s2 , capacitor C c , capacitor C d , resistor R g , resistor R n ;

[0009] Ports P1, P2 and ports H, Z are arranged on both sides of the LO pre-driver; the LO pre-driver comprises an upper and lower link LO pre-driver, and the upper and lower link LO pre-drivers have the same structure; the LO pre-driver comprises: a PMOS tube M1, a PMOS tube M2, a PMOS tube M3, an NMOS tube M4, an NMOS tube M5, an NMOS tube M6, a capacitor C b 、Inductance L g , resistor R d ;

[0010] The stacked LO driver is provided with ports G and S; the stacked LO driver includes stacked LO drivers for upper and lower links, and the stacked LO drivers have the same structure; the stacked LO driver includes: a PMOS tube M p1 、PMOS tube M p2 、PMOS tube M p3 、NMOS tube M n1 、NMOS tube M n2 、NMOS tube Mn3 , capacitor C p1 , capacitor C p2 , capacitor C p3 , capacitor C n1 , capacitor C n2 , capacitor C n3 ;

[0011] The port X in the RF impedance matching network is connected to the A terminal of the switch core, and the Y terminal in the RF impedance matching network is connected to the B terminal of the switch core;

[0012] The C end of the switch core is connected to the E end of the IF impedance matching network, the D end of the switch core is connected to the F end of the IF impedance matching network, and the P5 and P6 ports of the IF impedance matching network output IF signals;

[0013] The P1 and P2 terminals of the LO pre-driver receive the local oscillator signal, the H terminal of the LO pre-driver is connected to the G terminal of the stacked LO driver, the Z terminal of the LO pre-driver is connected to the S terminal of the stacked LO driver, and the output local oscillator signal of the stacked LO driver is connected to the switch core S 1～4 The input terminal connection of

[0014] Ports P3 and P4 in the RF impedance matching network receive RF input signals, and the RF signals enter the RF impedance matching network from ports P3 and P4, and are converted and output into two signals through the XY port; one signal passes through port A through switch S1 and the other signal passes through port B through switch S3 to port C, and finally merges at port E; one signal passes through port A through switch S2 and the other signal passes through port B through switch S4 to port D, and finally merges at port F; the two signals enter the IF impedance matching network through port EF, and finally output the IF signal through ports P5 and P6;

[0015] The local oscillator signal enters through ports P1 and P2, is divided into two signals and enters the upper and lower link LO pre-drivers to ports H and Z, and then the two signals enter the upper and lower link stacked LO drivers through ports G and S respectively, obtain the local oscillator signal, and enter the switch S in the switch core 1～4 as the local oscillator signal input.

[0016] Preferably, the capacitor C in the RF impedance matching network m One end of the inductor L p The C terminal is connected to the P3 port and serves as an input terminal of the RF impedance matching network. The capacitor C m The other end of the inductor L s The D end is connected and serves as the output port X of the RF impedance matching network. The inductor L p The a terminal and the inductor Ld The e-end is connected to the inductor L p The a terminal and the inductor L s The b-end is coupled, the inductor L s The b terminal and the inductor L a The f terminal is connected to ground, the inductor L d The g terminal and the inductor L a The h-terminal coupling, the capacitor C a One end of the inductor L d The g end is connected to the P4 port and serves as another input end of the RF impedance matching network. The capacitor C a The other end of the inductor L a The h end is connected and serves as the other output port Y of the RF impedance matching network. The capacitor C s One end of the capacitor C m One end and the inductor L s The b terminal is connected to the capacitor C s The other end of the capacitor C a The other end and the inductor L a The h end of the connection.

[0017] Preferably, one end of the capacitor C1 in the IF impedance matching network is connected to one end of the inductor L1, connected to port E, and serves as an input end of the IF impedance matching network, the other end of the capacitor C1 is connected to one end of the capacitor C4 and grounded, the other end of the capacitor C4 is connected to one end of the inductor L3, connected to port F, and serves as another input end of the IF impedance matching network, the other end of the inductor L3 is connected to one end of the capacitor C5 and one end of the inductor L4, the other end of the inductor L1 is connected to one end of the capacitor C2 and one end of the inductor L2, the other end of the capacitor C2 is connected to the other end of the capacitor C5 and grounded, the other end of the inductor L2 is connected to one end of the capacitor C3, connected to port P5, and serves as an output end of the IF impedance matching network, the other end of the capacitor C3 is connected to one end of the capacitor C6 and grounded, the other end of the capacitor C6 is connected to the other end of the inductor L4, and connected to port P6.

[0018] Preferably, the inductor L in the LO pre-driver g One end of the inductor is connected to the port P1 / P2 and serves as the input of the LO pre-driver. g The other end of the capacitor C b One end of the capacitor C b The other end of the resistor R d One end of the capacitor C b The other end is connected to the gate end of the NMOS tube M4 and the gate end of the PMOS tube M1. dThe other end is connected to the drain end of the NMOS tube M4 and the drain end of the PMOS tube M1, the source end of the NMOS tube M4 is grounded, the source end of the PMOS tube M1 is connected to the power supply voltage 1.2V, and the resistor R d The other end is connected to the gate end of the NMOS tube M5 and the gate end of the PMOS tube M2, the drain end of the NMOS tube M5 is connected to the drain-gate end of the PMOS tube M2, the source end of the NMOS tube M5 is grounded, the source end of the PMOS tube M2 is connected to the power supply voltage 1.2V, the drain end of the NMOS tube M5 is connected to the gate end of the NMOS tube M6 and the gate end of the PMOS tube M3, the drain end of the PMOS tube M2 is connected to the gate end of the NMOS tube M6 and the gate end of the PMOS tube M3, the source end of the NMOS tube M6 is grounded, the source end of the PMOS tube M3 is connected to the power supply voltage 1.2V, the drain end of the NMOS tube M6 is connected to the drain-gate end of the PMOS tube M3, connected to the port H / Z, and serves as the output end of the LO pre-driver.

[0019] Preferably, the stacked LO driver PMOS tube M p1 The source terminal is connected to the power supply voltage 5V, and the PMOS tube M p1 The drain terminal and the PMOS tube M p2 The source end is connected to the PMOS tube M p1 Gate terminal and capacitor C p1 One end of the capacitor C p1 The other end of the capacitor C p2 One end of the capacitor C p2 The other end is connected to the PMOS tube M p2 The gate terminal is connected to the PMOS tube M p2 The drain terminal and the PMOS tube M p3 The source end is connected to the PMOS tube M p3 The drain terminal and NMOS tube M n3 The drain terminal is connected and serves as the stacked LO driver output terminal V out , the capacitor C p3 One end of the capacitor C p2 One end and capacitor C n3 One end is connected to the stacked LO driver input terminal V in , the capacitor C p3 The other end is connected to the PMOS tube M p3 The gate terminal is connected to the capacitor C n3 One end of the capacitor C n2 One end of the capacitor C n3 The other end is connected to the NMOS tube M n3 The gate terminal is connected to the NMOS tube M n3 The source end and NMOS tube M n3 The drain terminal is connected to the capacitor C n2 One end of the capacitor Cn1 One end of the capacitor C n2 The other end is connected to the NMOS tube M n2 The gate terminal is connected to the NMOS tube M n2 The source end and NMOS tube M n1 The drain terminal is connected to the capacitor C n1 The other end is connected to the NMOS tube M n1 The gate terminal is connected to the NMOS tube M n1 The source terminal is grounded.

[0020] Preferably, the capacitor C in the switch core c One end of the capacitor C d One end is connected to the LO signal, the capacitor C c The other end is connected to the NMOS tube M s1 Gate terminal and resistor R g One end of the capacitor C d The other end is connected to the NMOS tube M s2 Gate terminal and resistor R n One end of the resistor R n The other end of the resistor R g The other end is connected to the power supply voltage V g , the NMOS tube M s1 The source terminal is connected to IN and serves as the input terminal of the switch. The NMOS tube M s1 The drain terminal and NMOS tube M s2 The source end is connected to the NMOS tube M s2 The drain terminal is connected to OUT and serves as the output terminal of the switch.

[0021] Compared with the prior art, the technical solution of this application has the following technical effects:

[0022] The CMOS integrated passive mixer provided by the present invention has significant advantages of miniaturization and high integration, making it more ideal for broadband system applications in the new 5G communication FR3 band. CMOS technology has strong compatibility with digital circuits, which facilitates the realization of logical control of multi-phase digital clocks, reduces manufacturing costs, and enhances market competitiveness. The performance advantages of ultra-wideband and ultra-high linearity enable the CMOS integrated passive mixer to be adjusted according to different application requirements and adapt to various frequency communication requirements. These characteristics make it increasingly popular in modern wireless communication systems.

[0023] The present invention utilizes that the switching core consists of four switches configured in a double-balanced structure, and each switch is composed of two NMOS devices stacked in series, which improves the breakdown voltage between the source and drain, achieving a greater RF signal voltage processing capacity; by designing a small Cc and ensuring that Cc < Cgate (the equivalent parasitic capacitance of the transistor gate), a quasi-floating effect of the gate is achieved. In this way, when a large RF signal enters the source, part of it is coupled to the gate, and the equivalent floating gate will track the large signal at the source and drain. As a result, the effective gate-source and gate-drain voltages are reduced, reducing the distortion risk of the transistor; the impedance matching networks for RF and IF also achieve the effect of changing the RF / IF impedance, that is, converting the 50Ω impedance at the RF and IF ports into 20Ω when looking from the source and drain of the mixer transistor to the RF and IF ports. The reduced impedance decreases the voltage signal swing at the source and drain, reducing the degree of distortion.

[0024] The stacked LO driver structure of the present invention extends the frequency range of the local oscillator driver, enabling the mixer to cover a wideband frequency range. The solution of the present invention is a passive mixer structure, which is easy to implement silicon-based integration and has the advantages of small size and low cost.

[0025] The above description is only an overview of the technical solution of the present application. In order to be able to understand the technical means of the present application more clearly, so as to be implemented in accordance with the content of the specification, and in order to make the above and other purposes, features and advantages of the present application more obvious and understandable, the following describes the preferred embodiments of the present application in detail in conjunction with the drawings as follows.

[0026] Based on the following detailed description of the specific embodiments of the present application in conjunction with the drawings, those skilled in the art will understand the above and other purposes, advantages and features of the present application more clearly. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to actual scale.

[0028] Figure 1 is the architecture diagram of the present invention;

[0029] Figure 2 is the schematic diagram of the RF impedance matching network circuit of the present invention;

[0030] Figure 3 is the schematic diagram of the IF impedance matching network circuit of the present invention;

[0031] Figure 4 Schematic diagram of the LO pre-driver circuit of the present invention;

[0032] Figure 5 is a schematic diagram of a stacked LO driver circuit of the present invention;

[0033] Figure 6 The switch S of the present invention 1～4 Circuit diagram;

[0034] Figure 7 It is a schematic diagram of down-conversion loss of the present invention;

[0035] Figure 8 It is a schematic diagram of the input power 1-dB compression point of the present invention;

[0036] Fig. 9 It is a schematic diagram of IIP3 of the present invention;

[0037] Fig.10 This is a schematic diagram of the IIP3 efficiency of the present invention;

[0038] Fig.11 Schematic diagram of power consumption of the present invention. DETAILED DESCRIPTION

[0039] To make the purpose, technical scheme and advantages of the embodiment of the present application clearer, the technical scheme in the embodiment of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiment of the present application. Obviously, the described embodiment is a part of the embodiment of the present application, rather than all of the embodiments. In the following description, specific details such as specific configuration and components are provided only to help fully understand the embodiments of the present application. Therefore, it should be clear to those skilled in the art that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present application. In addition, for clarity and brevity, the description of known functions and structures is omitted in the embodiment.

[0040] It should be understood that the references to "one embodiment" or "this embodiment" throughout the specification mean that the specific features, structures, or characteristics associated with the embodiment are included in at least one embodiment of the present application. Therefore, the references to "one embodiment" or "this embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0041] In addition, the present application may repeat reference numerals and / or letters in different examples. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate the relationship between the various embodiments and / or settings discussed.

[0042] The term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, B exists alone, and A and B exist at the same time. The term " / and" in this article describes another type of association object relationship, indicating that there can be two relationships. For example, A / and B can mean: A exists alone, and A and B exist alone. In addition, the character " / " in this article generally indicates that the previous and next associated objects are in an "or" relationship.

[0043] The term "at least one" in this article is merely a description of the association relationship of associated objects, indicating that there may be three relationships. For example, at least one of A and B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0044] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusions.

[0045] Example 1

[0046] This embodiment mainly describes a high linearity broadband passive mixer, such as Figure 1 As shown, it includes: an RF impedance matching network, an IF impedance matching network, an LO pre-driver, a stacked LO driver, and a switch core;

[0047] Ports P3, P4 and ports A, B are set on both sides of the RF impedance matching network; the RF impedance matching network includes: capacitor C m , capacitor C s , capacitor C a 、Inductance L p 、Inductance L s 、Inductance L d 、Inductance L a ;

[0048] Ports P5, P6 and ports E, F are arranged on both sides of the IF impedance matching network; the IF impedance matching network includes: capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, inductor L1, inductor L2, inductor L3, inductor L4;

[0049] Ports A and B and ports C and D are set on both sides of the switch core; the switch core includes switches S1, S2, S3, and S4, and the switch structure is the same; the switch structure includes: NMOS tube M s1 、NMOS tube M s2 , capacitor C c, capacitor C d , resistor R g , resistor R n ;

[0050] Ports P1, P2 and ports H, Z are arranged on both sides of the LO pre-driver; the LO pre-driver includes upper and lower link LO pre-drivers, and the upper and lower link LO pre-drivers have the same structure; the LO pre-driver includes: PMOS tube M1, PMOS tube M2, PMOS tube M3, NMOS tube M4, NMOS tube M5, NMOS tube M6, capacitor C b 、Inductance L g , resistor R d ;

[0051] The stacked LO driver sets ports G and S; the stacked LO driver includes upper and lower link stacked LO drivers, and the stacked LO driver has the same structure; the stacked LO driver includes: a PMOS tube M p1 、PMOS tube M p2 、PMOS tube M p3 、NMOS tube M n1 、NMOS tube M n2 、NMOS tube M n3 , capacitor C p1 , capacitor C p2 , capacitor C p3 , capacitor C n1 , capacitor C n2 , capacitor C n3 ;

[0052] Port X in the RF impedance matching network is connected to the A terminal of the switch core, and the Y terminal in the RF impedance matching network is connected to the B terminal of the switch core;

[0053] The C end of the switch core is connected to the E end of the IF impedance matching network, the D end of the switch core is connected to the F end of the IF impedance matching network, and the P5 and P6 ports of the IF impedance matching network output IF signals;

[0054] The P1 and P2 terminals of the LO pre-driver receive the local oscillator signal, the H terminal of the LO pre-driver is connected to the G terminal of the stacked LO driver, the Z terminal of the LO pre-driver is connected to the S terminal of the stacked LO driver, and the output local oscillator signal of the stacked LO driver is connected to the switch core S 1～4 The input terminal connection of

[0055] Ports P3 and P4 in the RF impedance matching network receive RF input signals. The RF signals enter the RF impedance matching network from ports P3 and P4, and are converted and output into two signals through the XY port; one signal passes through port A through switch S1 and the other signal passes through port B through switch S3 to port C, and finally merges at port E; one signal passes through port A through switch S2 and the other signal passes through port B through switch S4 to port D, and finally merges at port F; the two signals enter the IF impedance matching network through port EF, and finally output the IF signal through ports P5 and P6;

[0056] The local oscillator signal enters through ports P1 and P2, and is divided into two signals that enter the upper and lower link LO pre-drivers to ports H and Z. Then the two signals enter the upper and lower link stacked LO drivers through ports G and S respectively, obtain the local oscillator signal, and enter the switch S in the switch core. 1～4 as the local oscillator signal input.

[0057] Further, if Figure 2 As shown, the capacitor C in the RF impedance matching network m One end of the inductor L p The c-end of the capacitor is connected to the P3 port and serves as an input end of the RF impedance matching network. m The other end of the inductor L s The d end is connected to the output port X of the RF impedance matching network, and the inductor L p The a terminal and the inductor L d The e-end is connected to the inductor L p The a terminal and the inductor L s The b-end coupling, inductor L s The b terminal and the inductor L a The f end is connected to the ground, and the inductor L d The g terminal and the inductor L a The h-end coupling, capacitor C a One end of the inductor L d The g end of the capacitor is connected to the P4 port and serves as another input end of the RF impedance matching network. a The other end of the inductor L a The h end is connected to the other output port Y of the RF impedance matching network, and the capacitor C s One end of the capacitor C m One end and the inductor L s The b terminal is connected to the capacitor C s The other end of the capacitor C a The other end and the inductor L a The h end of the connection.

[0058] Further, if Figure 3As shown, one end of the capacitor C1 in the IF impedance matching network is connected to one end of the inductor L1, connected to port E, and serves as an input end of the IF impedance matching network, the other end of the capacitor C1 is connected to one end of the capacitor C4 and grounded, the other end of the capacitor C4 is connected to one end of the inductor L3, connected to port F, and serves as another input end of the IF impedance matching network, the other end of the inductor L3 is connected to one end of the capacitor C5 and one end of the inductor L4, the other end of the inductor L1 is connected to one end of the capacitor C2 and one end of the inductor L2, the other end of the capacitor C2 is connected to the other end of the capacitor C5 and grounded, the other end of the inductor L2 is connected to one end of the capacitor C3, connected to port P5, and serves as an output end of the IF impedance matching network, the other end of the capacitor C3 is connected to one end of the capacitor C6 and grounded, the other end of the capacitor C6 is connected to the other end of the inductor L4, and connected to port P6.

[0059] Further, if Figure 4 As shown, the inductor L in the LO pre-driver g One end of the inductor is connected to port P1 / P2 and serves as the input of the LO pre-driver. g The other end of the capacitor C b One end of the capacitor C b The other end of the resistor R d One end of the capacitor C b The other end is connected to the gate end of NMOS tube M4 and the gate end of PMOS tube M1, and the resistor R d The other end is connected to the drain end of NMOS tube M4 and the drain end of PMOS tube M1, the source end of NMOS tube M4 is grounded, the source end of PMOS tube M1 is connected to the power supply voltage 1.2V, and the resistor R d The other end is connected to the gate end of NMOS tube M5 and the gate end of PMOS tube M2, the drain end of NMOS tube M5 is connected to the drain-gate end of PMOS tube M2, the source end of NMOS tube M5 is grounded, the source end of PMOS tube M2 is connected to the power supply voltage 1.2V, the drain end of NMOS tube M5 is connected to the gate end of NMOS tube M6 and the gate end of PMOS tube M3, the drain end of PMOS tube M2 is connected to the gate end of NMOS tube M6 and the gate end of PMOS tube M3, the source end of NMOS tube M6 is grounded, the source end of PMOS tube M3 is connected to the power supply voltage 1.2V, the drain end of NMOS tube M6 is connected to the drain-gate end of PMOS tube M3, connected to port H / Z, and serves as the output end of LO pre-driver.

[0060] Further, if Figure 5 As shown, the stacked LO driver PMOS tube M p1 The source terminal is connected to the power supply voltage 5V, the PMOS tube M p1 The drain terminal and the PMOS tube M p2 Source connection, PMOS tube M p1 Gate terminal and capacitor C p1One end of the capacitor C p1 The other end of the capacitor C p2 One end of the capacitor C p2 The other end is connected to the PMOS tube M p2 Gate connection, PMOS tube M p2 The drain terminal and the PMOS tube M p3 Source connection, PMOS tube M p3 The drain terminal and NMOS tube M n3 The drain terminal is connected and serves as the stacked LO driver output terminal V out , capacitor C p3 One end of the capacitor C p2 One end and capacitor C n3 One end is connected to the stacked LO driver input terminal V in , capacitor C p3 The other end is connected to the PMOS tube M p3 Gate terminal connection, capacitor C n3 One end of the capacitor C n2 One end of the capacitor C n3 The other end is connected to the NMOS tube M n3 Gate connection, NMOS tube M n3 The source end and NMOS tube M n3 Drain connection, capacitor C n2 One end of the capacitor C n1 One end of the capacitor C n2 The other end is connected to the NMOS tube M n2 Gate connection, NMOS tube M n2 The source end and NMOS tube M n1 Drain connection, capacitor C n1 The other end is connected to the NMOS tube M n1 Gate connection, NMOS tube M n1 The source terminal is grounded.

[0061] Further, if Figure 6 As shown, the capacitor C in the switch core c One end of the capacitor C d One end is connected to the LO signal, capacitor C c The other end is connected to the NMOS tube M s1 Gate terminal and resistor R g One end of the capacitor C d The other end is connected to the NMOS tube M s2 Gate terminal and resistor R n Connect one end of the resistor R n The other end of the resistor R g The other end is connected to the power supply voltage V g , NMOS tube M s1The source terminal is connected to IN and serves as the input terminal of the switch. The NMOS tube M s1 The drain terminal and NMOS tube M s2 Source connection, NMOS tube M s2 The drain terminal is connected to OUT and serves as the output terminal of the switch.

[0062] This embodiment shows that the CMOS integrated passive mixer has significant advantages of miniaturization and high integration, making it more ideal for broadband system applications in the new 5G communication FR3 band. CMOS technology is highly compatible with digital circuits, which facilitates the logical control of multi-phase digital clocks, reduces manufacturing costs, and enhances market competitiveness. The performance advantages of ultra-wideband and ultra-high linearity enable the CMOS integrated passive mixer to be adjusted according to different application requirements and adapt to various frequency communication requirements.

[0063] Example 2

[0064] This embodiment is based on Embodiment 1 and describes in detail an optimization solution of a high linearity broadband passive mixer, which specifically includes:

[0065] The RF impedance matching network adopts a hybrid coupling (magnetic and capacitive) structure to achieve high bandwidth and low insertion loss, such as Figure 2 As shown in the figure, the magnetic coupling is designed with a low K value to increase the self-resonant frequency (SRF), while the feedforward capacitor network (Cm) is used to further expand the bandwidth. On the other hand, the IF impedance matching network is optimized for the 3-7GHz operating frequency and is designed as a low-pass fourth-order LC network with a structure as shown in the figure. Figure 3 As shown in the figure, a wider bandwidth and out-of-band spurious harmonic suppression are obtained; wherein, at the RF and IF nodes, two impedance step-down matching networks (MN) are used to reduce the 50Ω standard impedance of the external RF and IF ports to a lower impedance of 20Ω at the source and drain of the switching transistor core looking at the external RF and IF ports. This low impedance can effectively improve linearity. The IF impedance matching network can also be placed inside the mixer package or on the printed circuit board, depending on the high or low IF band.

[0066] LO pre-driver Figure 4 As shown, this structure provides a 2-stage pre-driver to generate a rail-to-rail signal to drive the stacked LO driver; this signal is usually used to drive a load with higher power, such as a local oscillator (LO) driver, which is used to generate a stable oscillation signal in a wireless communication system; the pre-driver is a small power amplifier used to drive the main power amplifier, and they can increase the amplitude of the signal to ensure that there is enough power to drive the subsequent power amplifier. The two-stage pre-driver is designed here, which means that the signal will be amplified twice to ensure that sufficient driving capability is provided to the stacked local oscillator driver.

[0067] The stacked LO driver, as Figure 5 shown, shows a stacked LO driver composed of three layers of NMOS devices and three layers of PMOS devices, with an operating voltage of 5V. The input signal is applied to all MOS devices within the stack, rather than only to the bottommost and topmost devices. Compared with the traditional driver, in the high (low) input signal state of the improved design, M n2 and M n3 (M p2 and M p3 ) have a higher V gs (V sg ), thus reducing the on-resistance of the MOS devices. Therefore, the driver can maintain a rail-to-rail output swing at a higher frequency, effectively ensuring the bandwidth characteristics of the mixer. At the same time, due to the faster transition time at the output end of the driver, a higher mixer IIP3 can be achieved. In addition, when M n2 and M n3 (M p2 and M p3 ) devices are in the off state, the M n2 and M n3 (M p2 and M p3 ) on the improved driver have a lower V gs (V sg ), thus reducing the leakage current and improving the driver efficiency. Secondly, by operating the pre-driver from a 1.2V instead of the standard 1V power supply to drive the stacked LO driver with a larger voltage swing, a better on-off switch is achieved. Although the higher power supply voltage and larger load capacitance will increase the power consumption of the pre-driver, since the power consumption of the pre-driver is very small, the increase in the total power consumption is negligible.

[0068] The switch core, as Figure 6 shown, consists of four switches configured in a double-balanced structure. Each switch is composed of two NMOS devices stacked in series, which can achieve a higher voltage handling capacity and improve the linearity of the switch core. The equivalent on-resistance of a single NMOS transistor is 3 - 4Ω, effectively reducing the insertion loss. To further improve the linearity of the mixer, the capacitor used to couple the LO to the NMOS gate is designed to be relatively small (Cc < Cgate), forming a quasi-floating gate that can track the source and drain voltages and reduce the effective V gs / V gd to improve the mixer linearity. If Cc is too small, it will be at the cost of a higher driving local oscillator signal strength. Therefore, the optimized results after comprehensive consideration are shown in the following table;

[0069]

[0070] A high linearity broadband passive mixer provided in this embodiment is implemented using 45nm SOI technology, consumes less than 430mW of power, and has an operating frequency covering the 7-20GHz new 5G communication FR3 band. At a radio frequency of 7-20GHz, the analog conversion insertion loss of the mixer at different LO and IF=3GHz values ​​is 8-11.7dB, IP1dB is 20.3-25.1dBm, and IIP3 is 23.5-36dBm. The specific values ​​of the component parameters are as described in the above table;

[0071] like Figure 7 As shown, the simulation results of the down-conversion loss when the intermediate frequency is 3 GHz are given. It can be seen that in the RF frequency spacing range of 7-20 GHz, the down-conversion loss is 8-11.7 dB;

[0072] like Figure 8 As shown, when the intermediate frequency is 3GHz, the simulation results of IP1dB show that in the RF frequency spacing range of 7-20GHz, the IP1dB is 20.3-25.1dB;

[0073] like Fig. 9 As shown in the figure, the simulation results of IIP3 are given when the intermediate frequency is 3GHz. It can be seen that in the RF frequency range of 7-20GHz, the IIP3 is 23.5-36dBm; IIP3 efficiency (dB) is defined as the difference between IIP3 (dBm) and power consumption (dBm), which shows the efficiency of the mixer in achieving specific intermodulation performance;

[0074] like Fig.10 As shown, the IIP3 efficiency is shown, where the IF is set to 3 GHz. When the RF frequency is 7-13 GHz, the IIP3 efficiency of the mixer is 5-19 dB. As the LO frequency increases, the IIP3 efficiency drops to ≈0 dB at 20 GHz.

[0075] like Fig.11 As shown in the figure, the power consumption result diagram of the mixer is given, and the results show that the power consumption is less than 430mW in the LO frequency spacing range of 7-20GHz.

[0076] Through comparative analysis of the above optimization schemes, it can be seen that the superior linearity and bandwidth characteristics of the present invention are very suitable for the high linearity receiving application field of modern phased arrays.

[0077] The above are only preferred embodiments of the present invention, which do not limit the scope of protection of the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any changes, modifications, replacements, integrations and parameter changes to these embodiments within the spirit and principles of the present invention through conventional substitutions or without departing from the principles and spirit of the present invention fall within the scope of protection of the present invention.

Claims

1. A high linearity broadband passive mixer, characterized in that: include: RF impedance matching network, IF impedance matching network, LO pre-driver, stacked LO driver, switch core; Ports P3, P4 and ports A, B are arranged on both sides of the RF impedance matching network; the RF impedance matching network includes: a capacitor C m , capacitor C s , capacitor C a 、Inductance L p 、Inductance L s 、Inductance L d 、Inductance L a ; Ports P5, P6 and ports E, F are arranged on both sides of the IF impedance matching network; the IF impedance matching network comprises: capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, inductor L1, inductor L2, inductor L3, inductor L4; Ports A and B and ports C and D are arranged on both sides of the switch core; the switch core includes switches S1, S2, S3, and S4, which have the same switch structure; the switch structure includes: NMOS tube M s1 、NMOS tube M s2 , capacitor C c , capacitor C d , resistor R g , resistor R n ; Ports P1, P2 and ports H, Z are arranged on both sides of the LO pre-driver; the LO pre-driver comprises an upper and lower link LO pre-driver, and the upper and lower link LO pre-drivers have the same structure; the LO pre-driver comprises: a PMOS tube M1, a PMOS tube M2, a PMOS tube M3, an NMOS tube M4, an NMOS tube M5, an NMOS tube M6, a capacitor C b 、Inductance L g , resistor R d ; The stacked LO driver is provided with ports G and S; the stacked LO driver includes stacked LO drivers for upper and lower links, and the stacked LO drivers have the same structure; the stacked LO driver includes: a PMOS tube M p1 、PMOS tube M p2 、PMOS tube M p3 、NMOS tube M n1 、NMOS tube M n2 、NMOS tube M n3 , capacitor C p1 , capacitor C p2 , capacitor C p3 , capacitor C n1 , capacitor C n2 , capacitor C n3 ; The port X in the RF impedance matching network is connected to the A terminal of the switch core, and the Y terminal in the RF impedance matching network is connected to the B terminal of the switch core; The C end of the switch core is connected to the E end of the IF impedance matching network, the D end of the switch core is connected to the F end of the IF impedance matching network, and the P5 and P6 ports of the IF impedance matching network output IF signals; The P1 and P2 terminals of the LO pre-driver receive the local oscillator signal, the H terminal of the LO pre-driver is connected to the G terminal of the stacked LO driver, the Z terminal of the LO pre-driver is connected to the S terminal of the stacked LO driver, and the output local oscillator signal of the stacked LO driver is connected to the switch core S 1～4 The input terminal connection of Ports P3 and P4 in the RF impedance matching network receive RF input signals, and the RF signals enter the RF impedance matching network from ports P3 and P4, and are converted and output into two signals through the XY port; one signal passes through port A through switch S1 and the other signal passes through port B through switch S3 to port C, and finally merges at port E; one signal passes through port A through switch S2 and the other signal passes through port B through switch S4 to port D, and finally merges at port F; the two signals enter the IF impedance matching network through port EF, and finally output the IF signal through ports P5 and P6; The local oscillator signal enters through ports P1 and P2, is divided into two signals and enters the upper and lower link LO pre-drivers to ports H and Z, and then the two signals enter the upper and lower link stacked LO drivers through ports G and S respectively, obtain the local oscillator signal, and enter the switch S in the switch core 1～4 as the local oscillator signal input.

2. A high linearity broadband passive mixer according to claim 1, characterized in that: The RF impedance matching network capacitor C m One end of the inductor L p The C terminal is connected to the P3 port and serves as an input terminal of the RF impedance matching network. The capacitor C m The other end of the inductor L s The D end is connected and serves as the output port X of the RF impedance matching network. The inductor L p The a terminal and the inductor L d The e-end is connected to the inductor L p The a terminal and the inductor L s The b-end is coupled, the inductor L s The b terminal and the inductor L a The f terminal is connected to ground, the inductor L d The g terminal and the inductor L a The h-terminal coupling, the capacitor C a One end of the inductor L d The g end is connected to the P4 port and serves as another input end of the RF impedance matching network. The capacitor C a The other end of the inductor L a The h end is connected and serves as the other output port Y of the RF impedance matching network. The capacitor C s One end of the capacitor C m One end and the inductor L s The b terminal is connected to the capacitor C s The other end of the capacitor C a The other end and the inductor L a The h end of the connection.

3. A high linearity broadband passive mixer according to claim 2, characterized in that: One end of the capacitor C1 in the IF impedance matching network is connected to one end of the inductor L1, connected to port E, and serves as an input end of the IF impedance matching network. The other end of the capacitor C1 is connected to one end of the capacitor C4 and grounded. The other end of the capacitor C4 is connected to one end of the inductor L3, connected to port F, and serves as another input end of the IF impedance matching network. The other end of the inductor L3 is connected to one end of the capacitor C5 and one end of the inductor L4. The other end of the inductor L1 is connected to one end of the capacitor C2 and one end of the inductor L2. The other end of the capacitor C2 is connected to the other end of the capacitor C5 and grounded. The other end of the inductor L2 is connected to one end of the capacitor C3, connected to port P5, and serves as an output end of the IF impedance matching network. The other end of the capacitor C3 is connected to one end of the capacitor C6 and grounded. The other end of the capacitor C6 is connected to the other end of the inductor L4 and connected to port P6.

4. A high linearity broadband passive mixer according to claim 2, characterized in that: The LO pre-driver inductor L g One end of the inductor is connected to the port P1 / P2 and serves as the input of the LO pre-driver. g The other end of the capacitor C b One end of the capacitor C b The other end of the resistor R d One end of the capacitor C b The other end is connected to the gate end of the NMOS tube M4 and the gate end of the PMOS tube M1. d The other end is connected to the drain end of the NMOS tube M4 and the drain end of the PMOS tube M1, the source end of the NMOS tube M4 is grounded, the source end of the PMOS tube M1 is connected to the power supply voltage 1.2V, and the resistor R d The other end is connected to the gate end of the NMOS tube M5 and the gate end of the PMOS tube M2, the drain end of the NMOS tube M5 is connected to the drain-gate end of the PMOS tube M2, the source end of the NMOS tube M5 is grounded, the source end of the PMOS tube M2 is connected to the power supply voltage 1.2V, the drain end of the NMOS tube M5 is connected to the gate end of the NMOS tube M6 and the gate end of the PMOS tube M3, the drain end of the PMOS tube M2 is connected to the gate end of the NMOS tube M6 and the gate end of the PMOS tube M3, the source end of the NMOS tube M6 is grounded, the source end of the PMOS tube M3 is connected to the power supply voltage 1.2V, the drain end of the NMOS tube M6 is connected to the drain-gate end of the PMOS tube M3, connected to the port H / Z, and serves as the output end of the LO pre-driver.

5. A high linearity broadband passive mixer according to claim 1, characterized in that: The stacked LO driver PMOS tube M p1 The source terminal is connected to the power supply voltage 5V, and the PMOS tube M p1 The drain terminal and the PMOS tube M p2 The source end is connected to the PMOS tube M p1 Gate terminal and capacitor C p1 One end of the capacitor C p1 The other end of the capacitor C p2 One end of the capacitor C p2 The other end is connected to the PMOS tube M p2 The gate terminal is connected to the PMOS tube M p2 The drain terminal and the PMOS tube M p3 The source end is connected to the PMOS tube M p3 The drain terminal and NMOS tube M n3 The drain terminal is connected and serves as the stacked LO driver output terminal V out , the capacitor C p3 One end of the capacitor C p2 One end and capacitor C n3 One end is connected to the stacked LO driver input terminal V in , the capacitor C p3 The other end is connected to the PMOS tube M p3 The gate terminal is connected to the capacitor C n3 One end of the capacitor C n2 One end of the capacitor C n3 The other end is connected to the NMOS tube M n3 The gate terminal is connected to the NMOS tube M n3 The source end and NMOS tube M n3 The drain terminal is connected to the capacitor C n2 One end of the capacitor C n1 One end of the capacitor C n2 The other end is connected to the NMOS tube M n2 The gate terminal is connected to the NMOS tube M n2 The source end and NMOS tube M n1 The drain terminal is connected to the capacitor C n1 The other end is connected to the NMOS tube M n1 The gate terminal is connected to the NMOS tube M n1 The source terminal is grounded.

6. A high linearity broadband passive mixer according to claim 1, characterized in that: The switch core capacitor C c One end of the capacitor C d One end is connected to the LO signal, the capacitor C c The other end is connected to the NMOS tube M s1 Gate terminal and resistor R g One end of the capacitor C d The other end is connected to the NMOS tube M s2 Gate terminal and resistor R n One end of the resistor R n The other end of the resistor R g The other end is connected to the power supply voltage V g , the NMOS tube M s1 The source terminal is connected to IN and serves as the input terminal of the switch. The NMOS tube M s1 The drain terminal and NMOS tube M s2 The source end is connected to the NMOS tube M s2 The drain terminal is connected to OUT and serves as the output terminal of the switch.

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