Class D amplifier with multiple independent output stages

Abstract

The invention relates to a class D amplifier with multiple independent output stages. A method for improving a broadband common mode rejection ratio (CMRR) in a class D amplifier includes: matching a first ratio and a second ratio in a first trimming manner; the class D amplifier includes an integrator coupled to differential first and second paths; the first ratio is a ratio of the feedback resistance to the input resistance in the first path; the second ratio is a ratio of the feedback resistance to the input resistance in the second path; matching the first RC time constant and the second RC time constant in a second trim manner after matching the first ratio and the second ratio in the first trim manner; r of the first RC time constant is a resistance having a first matching ratio, and C of the first RC time constant is an integrating capacitance in the first path; the other R of the second RC time constants is a resistance having a second matching ratio, and the other C of the second RC time constants is an integrating capacitance in the second path.

Description

[0001] This application is a divisional application of the Chinese patent application with application number "201880086254.6", application date "November 8, 2018", and invention name "Class D amplifier with multiple independent output stages" Background Art

[0002] Reducing the power consumption of audio amplifiers is very desirable, especially for devices with limited battery capacity due to system constraints, such as portable devices. In the past, various solutions have been introduced to help reduce the power consumption of audio amplifiers, whether at the system level or at the circuit level. Examples of previous solutions are included below. First, a class D output stage is used to replace the class AB output stage to improve medium to high power efficiency by reducing the IR drop loss of the output stage. Second, a class DG or class H power amplifier is introduced to provide sufficient power for the class D output stage, so that the switching capacitance loss of the class D output stage is minimized, and thus the low power efficiency is improved. Third, a linear amplifier is then introduced to drive a speaker load in an idle state, where the switching loss of the class D amplifier is completely removed and the idle power efficiency is improved. Fourth, driver field effect transistor (FET) segmentation is used to further reduce the switching capacitance loss for idle to low power efficiency by reducing the number of active parts in the driver FET. Fifth, a lower switching frequency in the idle state is used to reduce switching losses. Sixth, dynamic biasing is performed according to the output power level to reduce circuit static power. Seventh, noise gating is employed to shut down the Class D amplifier when the output power level is below a threshold.

[0003] In certain user applications, the recent pursuit is to not perform noise gating, but to put the amplifier in full-throttle state in the idle state, so that intermittent white background noise and / or any other significant performance differences (e.g., bimodal idle channel noise (ICN) and total harmonic distortion plus noise (THDN)) can be avoided. Therefore, another round of loss reduction is needed for idle low-power operation relative to the prior art solutions, where the goal is to reduce the total chip power consumption by about half. Summary of the invention

[0004] In one embodiment, the present disclosure provides a class D amplifier with a low power consumption mode. The class D amplifier includes a first independent output stage and a second independent output stage, which receive a corresponding first level power supply voltage and a second level power supply voltage for driving a load coupled to an output terminal of the class D amplifier during a corresponding first operating mode and a second operating mode. The class D amplifier also includes a bypass switch that can be controlled to disconnect the second output stage from the output terminal during the first operating mode and connect the second output stage to the output terminal during the second operating mode. The first operating mode and the second operating mode are selected based on the output power level of the class D amplifier.

[0005] In another embodiment, the present disclosure provides a method for operating a Class D amplifier with a low power consumption mode. The method includes providing a first independent output stage and a second independent output stage, which receive a corresponding first level power supply voltage and a second level power supply voltage, for driving a load coupled to an output terminal of the Class D amplifier during a corresponding first operating mode and a second operating mode, and controlling a bypass switch to disconnect the second output stage from the output terminal during the first operating mode, and connect the second output stage to the output terminal during the second operating mode. The first operating mode and the second operating mode are selected based on the output power level of the Class D amplifier.

[0006] In yet another embodiment, the present disclosure provides a method for improving a broadband common mode rejection ratio (CMRR) in a class D amplifier. The method includes matching a first ratio and a second ratio in a first trimming manner, and after matching the first ratio and the second ratio in the first trimming manner, matching a first RC time constant and a second RC time constant in a second trimming manner. The class D amplifier includes an integrator coupled to a differential first path and a second path. The first ratio is a ratio of a feedback resistor to an input resistor in the first path. The second ratio is a ratio of a feedback resistor to an input resistor in the second path. R of the first RC time constant is a resistor having a first matching ratio, and C of the first RC time constant is an integral capacitor in the first path. Another R of the second RC time constant is a resistor of a second matching ratio, and another C of the second RC time constant is an integral capacitor in the second path.

[0007] In yet another embodiment, the present disclosure provides a class D amplifier comprising an integrator coupled to a differential first path and a second path. The first path and the second path each include a feedback resistor, an input resistor, and an integral capacitor. The first ratio is the ratio of the feedback resistor to the input resistor in the first path, and the second ratio is the ratio of the feedback resistor to the input resistor in the second path. The first ratio and the second ratio can be matched in a first trimming manner. R of the first RC time constant is the resistance of the first matching ratio, and C of the first RC time constant is the integral capacitor in the first path, and another R of the second RC time constant is the resistance of the second matching ratio, and another C of the second RC time constant is the integral capacitor in the second path. The first RC time constant and the second RC time constant can be matched in a second trimming manner.

[0008] In yet another embodiment, the present disclosure provides a method performed by a class D amplifier having a quantizer and a driver stage. The quantizer and the driver stage have a combined gain. The method includes, for each of a plurality of power rails of the class D amplifier: sensing a voltage value of the power rail and determining a ramp amplitude based on the sensed voltage value. The method also simultaneously includes: switching the driver stage from using a first power rail of the plurality of power rails to using a second power rail of the plurality of power rails, and switching the quantizer from using a ramp amplitude associated with the first power rail to using a ramp amplitude associated with the second power rail, so that the combined gain is constant.

[0009] In yet another embodiment, the present disclosure provides a method for reducing distortion in a class D amplifier having a driver stage operable in multiple modes with different corresponding output impedances. The method includes sensing a current at a load of the class D amplifier. The method also includes determining an IR drop of a corresponding output impedance of the driver stage based on the sensed current. The method also includes adding the IR drop to an output of a loop filter of the class D amplifier to compensate for the corresponding output impedance of the driver stage.

[0010] A first embodiment of the present disclosure is a method and system for providing a high performance, low power mode for a class D amplifier. For a class D amplifier, a multi-rail output stage and corresponding pre-drivers for the output stage from different levels of supply voltages are interconnected using bypass switches. The bypass switches are controlled in a manner such that a load of the class D amplifier is powered by only one of the different levels of supply voltages. The single and only one of the different levels of supply voltages is selected based on a target output power level of the class D amplifier.

[0011] A second embodiment of the present disclosure is a method and system for reducing distortion in a class D amplifier having an output stage whose output impedance can vary. Current is sensed at a load of the class D amplifier. Based on the sensed current, an IR drop of the entire output stage is determined for the corresponding output impedance. The IR drop is added to the output of the loop filter of the class D amplifier to compensate for the corresponding output impedance of the output stage. In addition, based on the sensed current, the position of the load current zero crossing is determined, and the output impedance is allowed to vary at the position of the load current zero crossing. Alternatively, the position of the load voltage zero crossing is determined, and the output impedance is allowed to vary at the position of the load voltage zero crossing.

[0012] A third embodiment is a method and system for improving a broadband common mode rejection ratio (CMRR) in a class D amplifier. High precision trimming is used to match the ratio of feedback resistance to input resistance between a first pair of differential paths. High precision trimming is used to match the RC time constant between a second pair of differential paths around a first integrator, where R of the RC time constant is the total resistance of the feedback resistance in parallel with the input resistance, and C of the RC time constant is the integrating capacitance of the associated first integrator.

[0013] A fourth embodiment is a method and system for providing a glitch-free transition between power rails for a class D amplifier, so that the output stage of the class D amplifier has a constant gain. The voltage value of each power rail is preferably sensed in parallel or simultaneously. Based on the sensed voltage value of each power rail, a corresponding ramp amplitude is determined for each power rail. Based on the power rail used by the output stage, a corresponding ramp amplitude is used so that the gain of the output stage is constant.

[0014] The first embodiment can improve system power efficiency near idle and low output power levels by reducing power consumption of internal circuits and losses associated with total output capacitance (e.g., parasitic capacitance and external electromagnetic interference (EMI) capacitance). The second, third, and fourth embodiments can maintain circuit performance (i.e., THDN, pop-click, etc.) to achieve an overall practical Class-D audio amplifier that achieves low noise, low distortion, and optimal power efficiency covering a 0-100% output power range. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1A is an illustration of an example personal audio device.

[0016] Figure 1B is a block diagram of selected components of an example audio IC for a personal audio device.

[0017] Figure 2 is a block diagram of selected components of an example Class D amplifier.

[0018] Figure 3 It is shown Figure 2 A block diagram of an embodiment of the various parts of a Class D amplifier.

[0019] Figure 4 is shown with multiple parallel output stages and associated pre-drivers Figure 3 A block diagram of an embodiment of a driver stage of a Class D amplifier.

[0020] Figure 5 is shown with a dual output stage Figure 3 A circuit diagram of an embodiment of a driver stage.

[0021] Figure 6 is a timing diagram illustrating the timing of transitions from LV mode to HV mode and back to LV mode according to one embodiment of a dual output stage Class-D amplifier.

[0022] Figure 7 is a timing diagram illustrating mode transitions between dual output stages according to one embodiment of a dual output stage Class-D amplifier.

[0023] Figure 8 is a diagram showing a Class D amplifier with dual parallel output stages Figure 3 A block diagram of an alternative embodiment of a driver stage.

[0024] Fig. 9 is a conceptual block diagram illustrating an IR drop compensation circuit for use in a class-D amplifier having multiple different power supply level output stages according to an embodiment.

[0025] Fig.10 It is shown Figure 2 A block diagram of an embodiment of a portion of a Class D amplifier.

[0026] Fig.11 According to the embodiment Figure 3 Simplified resistor mismatch model of a Class D amplifier section.

[0027] Fig.12 is shown with dual parallel output stages Figure 3 A block diagram of an alternative embodiment of a driver stage.

[0028] Fig.13 Is shown around Figure 3 FIG. 1 is a diagram of an embodiment of a calibration circuit of a first integrator INT1 of a class-D amplifier and a calibration method for improving wideband CMRR / PSRR.

[0029] Fig.14 It is shown Fig.13 A circuit diagram of an alternative embodiment of a portion of a Class D amplifier calibration circuit.

[0030] Fig.15 It is shown that the use Fig.13 A flow chart of a method for calibrating a resistor ratio using a calibration circuit.

[0031] Fig.16 is a conceptual block diagram of an embodiment of a dual supply sensing circuit for generating a ramp, illustrating the ability of the ramp amplitude to shift instantaneously as the operating mode of the output stage changes.

[0032] Fig.17 is shown with three output stages Figure 3 A circuit diagram of an embodiment of a driver stage. DETAILED DESCRIPTION

[0033] Reference now Figure 1A , a diagram of an exemplary personal audio device 1 is shown according to an embodiment of the present disclosure. Figure 1A There is depicted a personal audio device 1 coupled to headphones 3 in the form of a pair of earbud speakers 8A and 8B. Figure 1A The headset 3 depicted in the figure is merely an example, and it should be understood that the personal audio device 1 can be used in conjunction with a variety of audio transducers including, but not limited to, headphones, earbuds, in-ear headphones, and external speakers. Plug 4 may provide electrical terminals for connecting the headset 3 to the personal audio device 1. The personal audio device 1 may use a touch screen 2 to provide a display to the user and receive user input, or a standard liquid crystal display (LCD) may be combined with various buttons, sliders, and / or knobs disposed on the front and / or sides of the personal audio device 1. Similarly, Figure 1A As shown, the personal audio device 1 may include an audio integrated circuit (IC) 9 for generating analog audio signals for transmission to the headphone 3 and / or another audio transducer (e.g., a speaker). Embodiments of a class D amplifier having multiple independently selectable load driving output stages to achieve reduced power consumption and methods and circuits for maintaining high audio performance when transitioning power supply operating modes between the multiple independent output stages are described. Although embodiments are described in the context of a personal audio device, other embodiments for other audio applications are contemplated.

[0034] Reference now Figure 1B , a block diagram showing selected components of an example audio IC 9 of a personal audio device according to an embodiment of the present disclosure. In some embodiments, the example audio IC 9 may be used to implement Figure 1A Audio IC 9. Figure 1B As shown, a microcontroller core 18 (eg, a digital signal processor or "DSP") may supply a digital audio input signal DIG_IN to a digital-to-analog converter (DAC) 14, which may convert the digital audio input signal into an analog input signal V INDAC 14 can convert the analog signal V IN Supplied to amplifier 16, which can amplify or attenuate the analog input signal V IN To provide audio output signal V OUT , the audio output signal V OUT Speakers, headphone transducers, line level signal outputs, and / or other suitable outputs may be operated.Microcontroller 18 may perform various functions described herein associated with transitioning of power supply operating modes between the various output stages of amplifier 16.

[0035] Reference now Figure 2 , a block diagram of selected components of an example class D amplifier 22 according to an embodiment of the present disclosure is shown. Preferably, the class D amplifier 22 is a pulse width modulation (PWM) amplifier. In some embodiments, the example class D amplifier 22 can be used to implement Figure 1B Amplifier 16. Figure 2 As shown, the example Class D amplifier 22 may include a digital modulator subsystem 24 and an analog PWM modulator 26. In one embodiment, the digital modulator subsystem 24 is a digital closed loop PWM modulator (DCL_PWMM).

[0036] The class D amplifier 22 can be configured to operate in an analog closed-loop mode through the use of an analog PWM modulator 26. In the analog closed-loop mode, the input signal V IN The analog PWM modulator 26 may receive its input from the digital modulator 24 and may utilize the analog PWM modulator 26 so that the output of the analog PWM modulator 26 received and driven by the driver stage 34 is driven as the output signal V OUT The driver stage 34 may include a plurality of output switches configured to generate an output signal V from the modulation signal generated by the analog PWM modulator 26. OUT The output signal V from the driver stage 34 OUT It is provided to the input of an analog PWM modulator 26 in a feedback loop.

[0037] An embodiment of a digital input Class D audio amplifier incorporating the various features described herein to improve performance can have a total power consumption of ~15mW, evenly divided between the digital, analog, and Class D drivers. Conventionally, losses on the digital and analog circuit portions are determined by circuit scale and key circuit performance considerations (e.g., noise, THD, and MIP), which are typically optimized so that little further improvement can be made within tight specifications. On the other hand, losses on the Class D driver are primarily driven by device characteristics (e.g., transistor thresholds, unit FET Rdson (resistance drain-source conduction), FET parasitic capacitance, etc.). Therefore, if the losses are attributed to the selected device manufacturing process, there is typically little room for improving efficiency.

[0038] In many portable devices, for example, an audio amplifier capable of delivering 8 Watts peak to an 8 Ohm load requires a 12V supply; therefore, a high voltage (HV) pre-driver is required to drive the output HV device. In most cases, the support circuitry driving the HV FETs may consume more HV supply power than the power consumption of the HV FETs themselves (e.g., speaker supply voltage VDD_SPK=12V). A detailed example is shown in Table 1 below, where it is assumed that the HV driver (pre-driver and output stage) is in standby mode. If a completely independent low voltage (LV) driver (pre-driver and output stage) is incorporated, CASE #4 depicts the lowest power loss scenario, an embodiment of which is described below.

[0039]

[0040]

[0041] Table 1 - Output stage power loss details

[0042] It can be observed from Table 1 that, as described in the embodiments of the present disclosure, an advantageous power saving scheme has at least two, but not limited to, two independently powered Class D output stages: an HV output stage and an LV output stage, which are interconnected by a set of bypass switches between the output nodes to alternatively provide power to the speaker load according to the output power level. For another example, a third output stage independently powered by a medium voltage (MV) power supply can be further introduced to fill the deliverable output power gap between the HV and LV stages. Advantageously, each independent output stage and its associated pre-driver are in the same power domain, i.e., powered by the same power supply, and all unused output stages and associated pre-drivers are turned off to achieve maximum (max) power saving from the associated power domain.

[0043] Reference now Figure 3 , showing Figure 222. The analog PWM modulator 26 (eg, Figure 2 ) receives digital input signal D IN (For example, from Figure 2 The digital PWM modulator 24) provides its output to the driver stage 34 (e.g., Figure 2 The analog PWM modulator 26 includes a digital-to-analog converter (DAC) that receives a digital input signal D IN , and provides the analog differential output to the loop filter 302. Figure 3 In an embodiment of the invention, the loop filter 302 includes a first integrator INT1 and a second integrator INT2 connected in series. Embodiments with loop filters of different orders are envisioned. The loop filter 302 passes baseband frequency content (e.g., audio signals from 20 Hz to 20 kHz) and suppresses higher frequency content, which includes out-of-band noise and signals near the carrier frequency (e.g., PWM switching frequency, such as 800 kHz) and its harmonics. The output of the loop filter 302 is provided to a quantizer 304, which compares its input signal with a ramp voltage to generate a differential PWM output provided to the driver stage 34. In one embodiment, the loop filter 302 in combination with the quantizer 304 can be used as a delta-sigma modulator. The driver stage 34 provides a differential output to the load 332. The differential load output is fed back to the input of the loop filter 302 and is added to the corresponding portion of the differential output of the DAC to provide a closed loop.

[0044] Reference now Figure 4 , showing Figure 34 is a block diagram of an embodiment of a driver stage 34 of a Class-D amplifier 22 having multiple parallel output stages and associated pre-drivers. The driver stage 34 receives three different supply voltages: HV_SUPPLY (e.g., 12V from a boost converter), MV_SUPPLY (e.g., 4.3V from a battery), and LV_SUPPLY (e.g., 1.8V from a buck converter). The HV_SUPPLY is provided to an HV pre-driver 402 and an HV Class-D output stage 404, which is driven by the HV pre-driver 402. The MV_SUPPLY is provided to an MV pre-driver 412 and an MV Class-D output stage 414 driven by the MV pre-driver 412, and to a bypass and HV blocking circuit 416 coupled to the MV Class-D output stage 414. LV_SUPPLY is provided to the LV pre-driver 422 and the LV class D output stage 424 driven by the LV pre-driver 422, and is provided to the bypass and HV blocking circuit 426 coupled to the LV class D output stage 424. Each of the HV class D output stage 404, the MVD class output stage 414, and the LV class D output stage 424 generates a differential output signal to drive the load 332, the terminals of which are coupled to the corresponding nodes OUT_M and OUT_P. As described in more detail below, the control logic monitors the output power level. Based on the output power level, the control logic controls the bypass and HV blocking circuit 416 / 426 to enable one of the pre-driver / output stage pairs (HV402 / 404, MV 412 / 414, or LV 422 / 424) to power the load 332, and the control logic turns off the other pre-driver / output stage pairs (HV 402 / 404, MV 412 / 414, and / or LV 422 / 424).

[0045] Figure 4 The power savings of the embodiments can be attributed to many factors other than the quiescent current cutoff of the unused HV output stage from the HV power supply. Another significant power saving lies in the switching losses of the parasitic capacitance (CAPS) around the output stage, including the total output capacitance Coss of the output transistors, the stray capacitance on the printed circuit board (PCB), the total input capacitance Ciss of the output transistors, and all parasitic capacitances switched at the PWM frequency inside the pre-driver. In addition, in certain specific applications, where an EMI capacitor must be placed on both driver output nodes (e.g., OUT_P and OUT_M), large power losses can be observed in the EMI capacitor (e.g., nanofarads) when the EMI capacitor is switched between the HV power supply and ground. However, by introducing a LV output stage, this type of loss can be greatly reduced. For example, a total 2nF capacitance flipping at a frequency of 400KHz will consume:

[0046] 1.2^2*400K*2n=1.152mW@1.2V, and

[0047] 4.3^2*400K*2n=14.792mW@4.3V, and

[0048] 12^2*400K*2n=115.2mW@12V.

[0049] It can be observed that a larger separation between the HV power supply and the LV power supply will result in more power saving in the LV power supply idle / low power state compared to the same type of losses on the HV power supply.

[0050] Reference now Figure 5 , shows a dual output stage Figure 3 A circuit diagram of an embodiment of the driver stage 34 is shown. Figure 4 As shown in , load 332 is coupled to OUT_P and OUT_M. Figure 5 Shows Figure 4 1 and 2. An example of an HV output stage 404, an LV output stage 424, and a bypass and HV blocking circuit 426 of FIG. 1 is shown. The HV output stage 404 includes an HVP portion and an HVN portion. The HVP portion includes a pair of p-channel HV FETs (HVP) whose sources are coupled to HV_SUPPLY and whose drains are coupled to OUT_M and OUT_P, respectively. The HVN portion includes a pair of n-channel HV FETs (HVN) whose sources are coupled to ground and whose drains are coupled to OUT_M and OUT_P, respectively. The LV output stage 424 includes an LVP portion and an LVN portion. The LVP portion includes a pair of p-channel LV FETs (LVP) whose sources are coupled to LV_SUPPLY. The drain of one of the LV p-channel FETs (LVP) is coupled to the bypass and HV blocking circuit 426 via node A, and the drain of the other of the low voltage p-channel FETs (LVP) is coupled to the bypass and HV blocking circuit 426 via node B. The LVN section includes a pair of n-channel LV FETs (LVN) whose sources are coupled to ground. The drain of one n-channel LV FET (LVN) is coupled to the bypass and HV blocking circuit 426 via node A, and the drain of the other n-channel low voltage FET (LVN) is coupled to the bypass and HV blocking circuit 426 via node B. Figure 5 As shown by the thick lines on the drains of HVP and HVN in FIG, these FETs can withstand higher voltages and consume more power than the LVP FET and LVN FET. That is, advantageously, the LVP FET and LVN FET consume much less power than the HVP FET and HVN FET. The gates of the HVP FET and HVN FET can be driven by an HV pre-driver (e.g., Figure 4The gates of the LVP FET and the LVN FET may be driven by an LV pre-driver with a differential PWM signal (e.g., Figure 4 When class D amplifier 22 is in LV mode, HVP and HVN (and the associated HV pre-driver 402) are turned off to substantially reduce power consumption; conversely, when class D amplifier 22 is in HV mode, LVP and LVN (and the associated LV pre-driver 422) are turned off. In one embodiment, HVP, HVN, LVP, and LVN are turned off by placing HVP, HVN, LVP, and LVN in a high impedance state (e.g., driving a high value into the gates of HVP and LVP and driving a low value into the gates of HVN and LVN), and pre-drivers 402 / 422 are turned off by biasing them with very little current, which places them in a low power consumption state.

[0051] The bypass and HV blocking circuit 426 includes a first clamp circuit 502, a first capacitor C1, and a first buffer 504, each coupled between node A and a floating voltage VFLOAT at the cathode of a diode, the anode of which is coupled to a power supply voltage node VP (e.g., a battery). The output of the first buffer 504 is coupled to the gate of a first high voltage n-channel FET HVN_bypass1 used as an interconnect switch or bypass switch to selectively couple node A to node OUT_M. The bypass and HV blocking circuit 426 also includes a second clamp 512, a second capacitor C2, and a second buffer 514, each coupled between node B and the floating voltage VFLOAT. The output of the second buffer 514 is coupled to the gate of a second high voltage n-channel FET HVN_bypass2 used as an interconnect switch or bypass switch to selectively couple node B to node OUT_P. When HVP is turned on, the bypass switches HVN_bypass1 and HVN_bypass2 are also used to protect the LVP FET and LVN FET from the high voltage supplied from HV_SUPPLY through HVP.

[0052] The HV output stage 404 and the LV output stage 424 are constructed to be in different power domains and have different types of devices. The bypass switches HVN_bypass1 and HVN_bypass2 (collectively referred to as bypass switches HVN_bypass) are of HV type. When the bypass switch HVN_bypass is enabled, the LV output stage 424 is connected to the output load 332, and when the bypass switch HVN_bypass is disabled, they block the swing from the LV output stage 424 to the output load 332. The control of the bypass switch HVN_bypass is static based on the power envelope detection of the output signal. The bypass switch HVN_bypass is powered by a local floating voltage supply VFLOAT. The floating voltage VFLOAT is generated by a bootstrap circuit (e.g., capacitors C1 and C2), and the floating voltage VFLOAT is periodically replenished via the current I_cp whenever the low-side switch LVN of the LV output stage 424 is enabled, such as Figure 5 shown.

[0053] During the mode transition between two output stages (e.g., 404 and 424), the “make before break” rule is followed regardless of the direction in which the operation mode is transitioned. For example, in a central edge modulation (CEM) scheme, the optimal mode transition point is located at the beginning of the PWM cycle, which is initiated by the CEM start pulse. More specifically, to comply with this rule, the optimal position is the start of the phase when both low-side switches HVN and LVN are enabled, when the output stages 404 and 424 share a ground return. The transition timing is as follows Figure 6 shown.

[0054] Reference now Figure 6 , shows an example of a dual output stage Class D amplifier (e.g., Figure 5 1 is a timing diagram of the transition timing from LV mode to HV mode and back to LV mode for one embodiment of a driver stage 34 of FIG. 1 . Examples of differential output signal waveforms are shown as separate OUT_P and OUT_M waveforms (indicated by solid and dashed lines, respectively). A series of CEM start pulses (CSP1, CSP2, CSP3, CSP4, CSP5) are shown, each of which initiates a PWM cycle.

[0055] After reset, both the HV output stage 404 and the LV output stage 424 are disabled. More specifically, the HV PMOS FET (HVP) and HV NMOS FET (HVN) in the HV output stage 404 and the LV PMOS FET (LVP) and bypass switch HVN_bypass in the LV output stage 424 are disabled, and only the LV NMOS FET (LVN) is enabled. During steady state operation, the HV FET will switch to deliver power to the speaker load 332, or the LV FET (through the enabled bypass switch HVN_bypass) will switch to deliver power to the speaker load 332. At the beginning of the PWM cycle indicated by the CEM start pulse, the control logic (not shown) performs a switch or transition from the HV output stage 404 to the LV output stage 424 (i.e., the operating mode is changed from HV mode to LV mode) or a switch or transition from the LV output stage 424 to the HV output stage 404 (i.e., the operating mode is changed from LV mode to HV mode). For example, at Figure 6 , a transition from LV mode to HV mode is performed at the second CEM start pulse CSP2, and a transition from HV mode to LV mode is performed at the fourth CEM start pulse CSP4. When transitioning from HV mode to LV mode, the control signal HV_ENABLE for enabling HVN remains valid, the control signal LV_ENABLE for enabling LVN is set to valid, and the bypass switch HVN_bypass is turned on to provide a second ground path for the load current passing through LVN, followed by setting the control signal HV_ENABLE to invalid to disable HVN in the HV output stage 404 to disconnect HVP and HVN from the loop. Similarly, when transitioning from LV mode to HV mode, the control signal LV_ENABLE for enabling LVN remains valid, the control signal HV_ENABLE for enabling HVN is set to valid to provide a second ground path for the load current, followed by closing the bypass switch HVN_bypass to disconnect LVP and LVN from the loop. The time for the amplifier 22 to operate in each respective mode of HV or LV may be long, such as many PWM cycles. That is, depending on changes in the required power level of the output signal, the transition between the HV mode and the LV mode may occur infrequently relative to the PWM period.

[0056] The "make before break" rule involving limited overlap between the HVN and LVN ground paths ensures that the load current can always find a current return path, so that voltage spikes at mode transitions are avoided. The overlap period is preferably as short as possible so that any sudden changes in the return path impedance do not cause noticeable voltage spikes across the load; therefore, THDN degradation is minimized. Figure 6As shown, advantageously, the control logic performs the mode transition at the beginning of the PWM cycle and when both the HVN FET and / or the LVN FET are turned on (i.e., both terminals of the load 332 are connected to a shared power rail, such as ground) and both the HVP FET and the LVP FET are turned off. This avoids large voltage swings that might otherwise occur, which could cause voltage glitches across the load 332 and lead to THDN degradation. For example, if a transition from HV mode to LV mode is performed at the third CEM start pulse CSP3, a swing from the HV_SUPPLY voltage to the LV_SUPPLY voltage might be seen on the load 332.

[0057] Reference now Figure 7 , shows an example of a dual output stage Class D amplifier (e.g., Figure 5 A timing diagram of mode transition between dual output stages of an embodiment of an amplifier 22). Figure 6 The timing diagram of shows the timing of mode transitions at a micro level (ie, at the level of switching output signal frequency (eg, hundreds of kHz)) in order to minimize THDN degradation; however, Figure 7 The timing diagram shows the timing of mode transitions at a macro level, i.e., at a baseband input signal frequency level (e.g., tens of kHz in the audio range), so as to minimize THDN degradation. As long as the desired output power is above a first threshold (thresh_hipower), the HV output stage 404 is enabled and the LV output stage 424 is disabled, and if the desired output power is below a second threshold (thresh_lopower), the LV output stage 424 is enabled and the HV output stage 404 is disabled. Inactive output devices (e.g., HVP and HVN or LVP and LVN) and associated pre-driver circuits (e.g., HV pre-driver 402 or LV pre-driver 422) are powered off to reduce the quiescent bias current to a minimum. The interval between the two thresholds (i.e., thresh_hipower and thresh_lopower) is designed to avoid oscillatory switching between the HV output stage 404 and the LV output stage 424. In one embodiment, before performing a transition from the HV mode to the LV mode (at Figure 7 The required output power must remain below the low power threshold thresh_lopower for a delay (e.g., Figure 7The delay is used as a time-based hysteresis mechanism to reduce overly frequent transitions between modes. In one embodiment, an optional lookahead buffer (e.g., Tbuf_opt) is inserted into the data path, which can be used to determine the optimal out-transition location (transition from LV mode to HV mode), for example, at the last voltage zero crossing (VZC) before the desired output power rises above the high power threshold thresh_hipower. That is, the data path can buffer the output signal long enough to detect that the desired output power is above the high power threshold thresh_hipower, and still remember the most recent last VZC for THDN optimized transition from LV mode to HV mode. In one embodiment, if the lookahead buffer depth is insufficient to determine the optimal out-transition location, the obligated out-transition point is set to valid (i.e., transition from LV mode to HV mode). In one embodiment, the current zero crossing (IZC) is detected instead of the VZC and used as the location for the operating mode transition.

[0058] Reference now Figure 8 , shows a Class D amplifier having dual parallel output stages (e.g., Figure 2 Amplifier 22) Figure 3 A block diagram of an alternative embodiment of the driver stage 34 is shown. Figure 8 The embodiments of Figure 4 The embodiments are similar and like numbered elements are similar. Figure 8 In the embodiment of the present invention, the class D amplifier 22 further includes a power supply voltage buffer amplifier 802 inside the audio IC 9 including the class D amplifier 22. The power supply voltage buffer amplifier 802 receives an external power supply voltage EXT_SUPPLY that can be provided from the system level. For example, the power supply voltage EXT_SUPPLY outside the audio IC 9 Figure 1A The power supply of the personal audio device 1 (e.g., 12V boost, 4.3V battery, 1.8V analog voltage rail) can provide an external supply voltage EXT_SUPPLY to the amplifier 22. Figure 8 In the embodiment of FIG. 8 , the supply voltage buffer amplifier 802 uses the external supply voltage EXT_SUPPLY to generate LV_SUPPLY provided to the LV pre-driver 422, the LV class D output stage 424, and the bypass and HV blocking circuit 426. Figure 8Only the generation of LV_SUPPLY is shown, but the supply voltage buffer amplifier 802 can also generate supply voltages of other levels (e.g., MV_SUPPLY). In one embodiment, the supply voltage buffer amplifier 802 generates a supply voltage of a level different from the received level, for example, the supply voltage buffer amplifier 802 can receive a 1.8V level and generate a supply voltage of a 1.0V level. In one embodiment, the supply voltage buffer amplifier 802 includes a low dropout (LDO) voltage regulator.

[0059] Differential Mode Errors and Solutions During HV / LV Stage Switching

[0060] The main differential errors caused by output stage mode switching include the following factors: quantizer gain mismatch; propagation delay mismatch between HV and LV paths; signal-related propagation delay on the quantizer; output stage impedance mismatch. The first two factors can be calibrated during product testing. The third factor can be minimized by using high-gain, high-bandwidth (BW) comparators. The fourth factor is explained below.

[0061] Given the finite impedance of the driver stage 34, the voltage applied to the speaker load 332 will be different from the nominal voltage measured from the power supply (e.g., HV_SUPPLY, MV_SUPPLY, LV_SUPPLY). For example, a 0.1 ohm Rdson (e.g., the Rdson of the output stage FET) will result in a 0.1V IR drop when a current of 1A flows through the load 332; therefore, the voltage seen by the load 322 after Rdson is 0.1V less than the supply voltage. The theoretical duty cycle expression for the output stage is given by equation (1).

[0062]

[0063] In formula (1), SVint2 represents a system variable, which is Figure 3 Vramp represents the average value of the output voltage V_INT2 of the second integrator INT2 of the loop filter 302 of the class D amplifier 22. Figure 3The amplitude of the ramp voltage used by the quantizer 304 to generate the PWM output signal. Vo represents the average output voltage provided to the load 332. IL represents the load current. Rds_tot represents the total Rdson of the output stage (e.g., 404 and 424, and HVN_BYPASS1 and HVN_BYPASS2 when in LV mode). Vspk represents the power supply voltage (e.g., HV_SUPPLY, MV_SUPPLY, or LV_SUPPLY). In order not to disturb SVint2 when the power supply voltage Vspk is suddenly reduced (e.g., from 12V to 1.2V) and the ramp amplitude Vramp is scaled by the same amount, the product IL*Rds_tot needs to remain constant in order to match the impedance from the HV output stage to the LV output stage when the load current IL is not zero. On the other hand, even in the case of impedance mismatch, the transition occurs at the load current zero crossing, and the product IL*Rds_tot will be zero. Current zero crossing detection can be performed (e.g., for finding Figure 7 The "optimal out-of-phase transition point" in the input signal (i.e., the "optimal out-of-phase transition point") and impedance matching are both used to minimize the residual error given by each term (see equation (2) below). Additionally, the current zero-crossing detection can be replaced by voltage zero-crossing detection at a low frequency (e.g., audio baseband frequency). Replacing current zero-crossings with voltage zero-crossings can result in a smaller phase difference, which can be traded for less circuit complexity.

[0064] If the load current is available, an IR drop compensation circuit can be built around the output stage (e.g. Fig. 9 The circuit 900 of FIG. 1 is used to further reduce the IL*Rds_tot error during the mode transition. The total error voltage can be expressed by formula (2).

[0065] Total error voltage = IL*(Rds_tot_HV–Rds_tot_LV)*LPF(s)*Δgain_ircomp(2)

[0066] In equation (2), Rds_tot_HV represents the total Rdson of the HV output stage 404, and Rds_tot_LV represents the total Rdson of the LV output stage 424. LPF(s) represents a low pass filter (LPF) along the load current sensing path (e.g., Fig. 9 The factor Δgain_ircomp is the gain difference between the inverse of the combined gain of the quantizer 304 and the driver stage 34 in HV mode and LV mode. The combined gain of the quantizer 304 and the driver stage 34 (e.g., 10) is defined as the ratio of the supply voltage Vspk (e.g., HV_SUPPLY or LV_SUPPLY) to the ramp voltage Vramp.

[0067] Since the total error after applying IR drop compensation is the product of multiple terms (as described above for equation (2) and below for Fig. 9 As described above, even when each term is not zero, the total error after IR compensation may be very close to zero. Therefore, advantageously, when IR drop compensation is adopted, the circuit requirements can be more relaxed, and the spurs on the second integrator INT2 can be well controlled to be minimized.

[0068] Reference now Fig. 9 , which shows an example of a method for operating a plurality of output stages (e.g., Figure 4 HV output stage 404 and LV output stage 424) of a class D amplifier (e.g., Figure 2 A conceptual block diagram of an IR drop compensation circuit 900 used in an amplifier 22). A low pass filter (LPF) 902 receives a sensed load current I SNS (ie, through load 332). LPF 902 may be necessary, especially when the sensed load current I SNS When there is noise, LPF 902 provides its output to the inverse 904, which multiplies the output of LPF 902 by Figure 3 The inverse of the gain of the quantizer 304. In one embodiment, the gain of the quantizer 304 varies depending on whether the amplifier 22 is operating in the HV mode or the LV mode. The first multiplier 906 and the second multiplier 908 multiply the output of the inverse 904 by Rds(HV_tot) and Rds(LV_tot), respectively, and provide their respective products to the multiplexer 912, which selects one of its inputs based on the control input mode_sel, which indicates the operating mode (i.e., HV mode or LV mode). Rds(HV_tot) and Rds(LV_tot) are measured values ​​of the total Rdson of the HV output stage 404 and the LV output stage 424, respectively. The output of the multiplexer 912 is added to the adding element 914 by the adding element 914. Figure 3 The output voltage V_INT2 of the second integrator INT2 is added to generate a compensation voltage V_INT2_compensated. The compensation voltage V_INT2_compensated is provided to a sample-and-hold circuit (SAH) 916, which provides its output to the quantizer 304. Advantageously, the adding element 914 is ( Fig.10 The addition is performed after the integrating capacitor around the second integrator INT2 and is therefore not remembered by the integrating capacitor.

[0069] Reference now Fig.10 , showing Figure 2 A block diagram of an embodiment of a portion of a Class-D amplifier 22 is shown. Fig.10In many ways similar to Figure 3 .However, Fig. 9 The IR drop compensation circuit 900 receives the sensed load current I SNS The output of the IR drop compensation circuit 900 is provided to a summing element, which sums the output voltage V_INT2 of the second integrator INT2 and provides the sum to the quantizer 304 .

[0070] The embodiments described herein operate to minimize errors caused by mode transitions between output stages, such as glitches caused by IR drops. If errors still occur, the loop of amplifier 22 will attempt to correct the errors. However, advantageously, a Fig. 9 The IR drop compensation circuit 900 is used to reduce the error that needs to be corrected.

[0071] It is not necessary to correct the polarity of the load current for the correction factor. However, it may be necessary to compensate for the relative amount not stored by the compensation loop filter 302 whenever there is a mode transition.

[0072] Output glitches due to common-mode output voltage step changes and countermeasures

[0073] The resistor and capacitor mismatch between the two differential paths around the speaker amplifier 22 may cause the differential output value of the amplifier 22 (e.g., the difference between OUT_P and OUT_M) to have a certain dependence on the output common-mode voltage (VCMO) of the amplifier 22. The output common-mode voltage VCMO is the average value of the differential output voltage of OUT_P and OUT_M within the CEM-based PWM cycle, and is also half of the average power supply voltage Vspk within the CEM-based PWM cycle. At any time when the output common-mode voltage VCMO changes (e.g., due to a transition from HV mode to LV mode or vice versa), an output DC offset due to the resistor mismatch will be observed, and a transient glitch due to the RC time constant mismatch of the first integrator INT1 will be observed.

[0074] Reference now Fig.11 , showing a schematic diagram of a method according to an embodiment Figure 3 A simplified resistor mismatch model of part 22 of a class-D amplifier. Fig.11 Examples include Figure 3 The first integrator INT1 of FIG. 1 is shown, and the remaining stages (i.e., the second integrator INT2, the quantizer 304, and the driver stage 34) are shown as the rest of the loop 1102. On the differential input to the first integrator, i.e., on the differential m and p paths, a virtual ground Vx is shown. The first integrating capacitor C1m is connected on its m path between the input and the output of the first integrator INT1, and the second integrating capacitor C1p is connected on its p path between the input and the output of the first integrator INT1.

[0075] The differential output voltage VOD (i.e., the difference between OUT_P and OUT_M) is Fig.11 The output common-mode voltage VCMO is fed back from the rest of the loop 1102 to the first summing element, which also receives the output common-mode voltage VCMO and provides its sum to the feedback resistor Rfbm of the m-path. The other side of the m-path feedback resistor Rfbm is connected to the m-path input of the first integrator INT1. The differential input voltage VID (i.e., Figure 3 The differential outputs of the DACs are Fig.11 The output common mode voltage VCMO is provided to the second summing element, which also receives the input common mode voltage VCMI and provides its sum to the input resistor Rsm of the m-path. The other side of the m-path input resistor Rsm is connected to the m-path input of the first integrator INT1. The p-path feedback resistor Rfbp receives the output common mode voltage VCMO and provides its output to the p-path input of the first integrator INT1. The p-path input resistor Rsp receives the input common mode voltage VCMI and provides its output to the p-path input of the first integrator INT1.

[0076] exist Fig.11 In the simplified model of , the circuit components Rfbp, Rsp and C1p along the p-path are considered as references. Due to the mismatch in the values ​​of the corresponding components of the p-path, the corresponding components along the m-path are shown to have errors, more specifically, the value of Rfbm=Rfbp*(1+εfb), the value of Rsm=Rsp*(1+εs), and the value of C1m=C1p*(1+εc1). It can be observed from the following formulas (3) and (4) that in order to make the dependence of the virtual ground Vx of the first integrator INT1 on the output common-mode voltage VCMO zero, εs must be set equal to εtot, which shows that for infinite CMRR, the resistance ratio on both sides must be matched.

[0077]

[0078] The audible glitch energy in the band can be controlled by avoiding sudden increases, as required by the pop-click specification threshold. Avoiding sudden increases can be achieved by a supply voltage buffer amplifier that can smoothly move the supply voltage Vspk of the output stage between the HV and LV domains, such as Fig.12 shown.

[0079] Reference now Fig.12 , shows a dual parallel output stage Figure 3 A block diagram of an alternative embodiment of the driver stage 34 is shown. Fig.12 The embodiments of Figure 4, and like numbered components are similar. In one embodiment, the high supply voltage and the low supply voltage HV_SUPPLY and LV_SUPPLY can be provided from the system level. For example, the audio IC 9 is external to Figure 1A The power supply of the personal audio device 1 (e.g., 12V boost, 4.3V battery, 1.8V analog voltage rail) can provide different supply voltages EXT_HV_SUPPLY and EXT_LV_SUPPLY to the amplifier 22. Fig.12 In the embodiment of the present invention, the class D amplifier 22 also includes a power supply voltage buffer amplifier 1202 inside the audio IC 9 including the class D amplifier 22. Fig.12 In an embodiment of the present invention, the supply voltage buffer amplifier 1202 receives external HV and LV supply voltages EXT_HV_SUPPLY and EXT_LV_SUPPLY and uses them to generate HV_SUPPLY, which is provided to the HV pre-driver 402 and the HV class D output stage 404. When a transition from HV mode to LV mode is desired, the supply voltage buffer amplifier 1202 smoothly moves the supply voltage HV_SUPPLY from its normal high level (e.g., 12V) to an LV level (e.g., 4.3V or 1.8V). Once the HV_SUPPLY rail is about to provide the same voltage level as the LV_SUPPLY rail, the control logic causes a transition from the HV output stage 404 driving the load 332 to the LV output stage 424 driving the load 332. In order to make the HV to LV transition, preferably, the control logic turns on LVN and LVP and the bypass switches HVN_BYPASS1 and HVN_BYPASS2, and then switches the HV output stage 404 to the LV level as described above. Figure 6 The make-before-break approach described places HVP and HVN in a high impedance state (and turns off the HV pre-driver 402). When a transition from LV mode to HV mode is desired, the supply voltage buffer amplifier 1202 smoothly moves the supply voltage HV_SUPPLY from the LV level (e.g., 4.3V or 1.8V) to its normal high level (e.g., 12V). Once the HV_SUPPLY rail is about to provide a high voltage level, the control logic causes a transition from the LV output stage 424 driving the load 332 to the HV output stage 404 driving the load 332. In order to make the LV to HV transition, the control logic preferably turns on HVP and HVN, and then performs the same operation as described above with respect to Figure 6 The make-before-break approach puts LVN and LVP into a high impedance state (and turns off LV pre-driver 422) and turns off bypass switches HVN_BYPASS1 HVN_BYPASS2 and HVN_BYPASS2. In one embodiment, supply voltage buffer amplifier 1202 includes a low dropout (LDO) voltage regulator.

[0080] Fig.12One disadvantage of the solution is that it may require additional area, power, and bill of materials (BOM) count penalties. On the other hand, removing the power buffer 802 may require compensation immediately at the input or output of the speaker amplifier 22. Unfortunately, such compensation is not compatible with baseband signals that contain significant out-of-band noise (OOBN). Therefore, an embodiment of improving the common-mode rejection ratio / power supply rejection ratio (CMRR / PSRR) of the speaker amplifier 22 is described below, so that the common-mode signal can be locally suppressed as much as possible. In one embodiment, VCMO is half of the power supply voltage Vspk; therefore, PSRR and CMRR are directly related.

[0081] Reference now Fig.13 , showing Figure 3 An embodiment of a calibration circuit 1302 around the first integrator INT1 of the class-D amplifier 22 and a calibration method for improving broadband CMRR / PSRR. Theoretical calculations show that to achieve a PSRR of 90 dB and a THDN of ~80 dB, the mismatch between the differential p and m paths of the resistance ratio of the feedback resistor Rfb and the input resistor Rs must be less than 0.003%, and the RC time constant mismatch between the differential p and m paths around the first integrator INT1 must be less than 0.1%.

[0082] You can refer to Fig.11 A simplified resistor mismatch model is used to understand Fig.13 Calibration circuit 1302. Fig.13A calibration circuit 1302 around the first integrator INT1 is shown, the calibration circuit 1302 including a p-path trimming resistor array Rcalp and an m-path trimming resistor array Rcalm for trimming the ratio RFB / RS of the feedback to input resistance of one or both of the P-path and the M-path so that the P-path and the M-path ratios are matched. The calibration circuit 1302 also includes an m-path trimming capacitor array C1calm and a p-path trimming capacitor array C1calp for matching the RC time constants of the m-path and the p-path. In one embodiment, the trimming resistor arrays Rcalp and Rcalm include resistor trimming arrays that can be programmed with different code values ​​to specify different resistance values ​​during calibration. In another embodiment, one or more of the input resistors Rsp and Rsm and the feedback resistors Rfbp and Rfbm can be laser trimmed to a desired value during calibration, in which case the trimming resistor arrays Rcalp and Rcalm may not be present. In one embodiment, the RC time constant trimming capacitor arrays C1calm and C1calp include trimming capacitor arrays that can be programmed with different code values ​​to specify different capacitance values ​​during calibration. In another embodiment, one or more of the integrating capacitances C1m and C1p may be laser trimmed to a desired value during calibration, in which case there may be no RC time constant trimming C1calm and C1calp.

[0083] The differential output paths of the first integrator INT1 are shown as INT1_OP and INT1_OM, each of which is connected to ground via a corresponding capacitor CL. Figure 3 The output section of the DAC is Fig.13, an inverter INV is shown receiving a PWM input signal. The DAC is biased by a DAC reference voltage VDAC and ground, as is the inverter INV. The DAC output has a differential output resistance on its differential output path, which is an m-path input resistance Rsm connected to the m-path input of the first integrator INT1, and a p-path input resistance Rsp connected to the p-path input of the first integrator INT1. The m-path feedback resistance Rfbm is connected between the m-path load output OUT_M and the m-path input of the first integrator INT1, and the p-path feedback resistance Rfbp is connected between the p-path load output OUT_P and the p-path input of the first integrator INT1. The p-path trimming resistor array Rcalp is connected between the DAC reference voltage VDAC and ground to alternating sides of the p-path input of the first integrator INT1, and the m-path trimming resistor array Rcalm is connected between the DAC reference voltage VDAC and ground to alternating sides of the m-path input of the first integrator INT1. One side of the m-path trimming capacitor array C1calm is connected to the m-path input of the first integrator INT1, and the other side is selectively connected to the differential outputs INT1_OM and INT1_OP of the first integrator INT1 through corresponding switches. One side of the p-path trimming capacitor array C1calp is connected to the p-path input of the first integrator INT1, and the other side is selectively connected to the differential outputs INT1_OM and INT1_OP of the first integrator INT1 through corresponding switches.

[0084] To maximize the PSRR and minimize the performance drift before and after calibration, both trimming circuits are fully differentially arranged around the first integrator INT1, and the virtual ground Vx of the first integrator INT1 is configured not to contact any PN junction of the FET switch or any nonlinear devices such as metal oxide semiconductor field effect transistor (MOSFET) capacitors, which have high voltage / temperature coefficients.

[0085] The RC time constant trimming capacitor arrays C1calp and C1calm that do not require balanced differential RC time constants are cross-connected (rather than short-circuited around themselves) to the other side of the output node of the first integrator INT1, as shown in FIG. Fig.13 As shown, the trimmed capacitor array has low impedance.

[0086] The trim resistor array configuration is static and complementary. That is, the trim resistor arrays Rcalp and Rcalm do not interact with the main PWM DAC resistors (in Fig.13In contrast, the trimming resistor arrays Rcalp and Rcalm are wired through N / PFET switches (not shown) to contact ground or DAC reference voltage VDAC, which also has low impedance, leaving the other end of the trimming resistor arrays Rcalp and Rcalm, which is the virtual ground Vx of the first integrator INT1, uncontaminated. For each trimming code, the resistances of the pull-up and pull-down portions of the trimming resistor arrays are designed to be the same, resulting in zero current into the virtual ground Vx. The complementary trimming resistor arrays are equivalent to two single resistors placed in parallel with the input resistors Rsm and Rsp (DAC output resistors). By sizing the trimming resistor arrays Rcalp and Rcalm to be N times larger than the main input resistors Rsp and Rsm, where N is a number at least greater than 1, much higher trimming accuracy is achieved without the tiny least significant bit (LSB) resistors required in the direct trimming method.

[0087] For example, when the nominal Rcal resistor is set to one hundred (100) times the input resistors Rsm and Rsp, and the trim LSB is 0.1%, the effective trim resolution can be as fine as 0.003%, achieving a CMRR better than 90dB. In one embodiment, the trim range is + / -0.1%.

[0088] The calibration process consists of two steps: resistor ratio trimming, followed by RC time constant trimming, i.e., capacitor trimming. After calibration, the speaker modulator has good broadband CMRR, thus minimizing fluctuations in the output stage power supply.

[0089] Reference now Fig.14 , showing Fig.13 1302 of the Class D amplifier 22. Fig.14 In the embodiment, Fig.13 As in the embodiment of the present invention, one side of the m-path trimming capacitor array C1calm is coupled to the m-path input terminal of the first integrator INT1, and the other side is selectively coupled to the m-path output terminal INT1_OM of the first integrator INT1 through a switch. Fig.14 In the embodiment of the present invention, the switch is a bipolar single throw switch, which can be thrown to couple the other side of the m-path trimming capacitor array C1calm to the output of the buffer BUF (e.g., a unity gain operational amplifier), and the input of the buffer BUF is coupled to the m-path input of the first integrator INT1. Similarly, one side of the p-path trimming capacitor array C1calp is coupled to the p-path input of the first integrator INT1, and the other side is selectively coupled to the p-path output INT1_OP of the first integrator INT1 through the switch. However, in Fig.14In an embodiment of the present invention, the switch is a bipolar single throw switch that can be thrown to couple the other side of the p-path trimming capacitor array C1calp to the output of a buffer BUF (e.g., a unity gain operational amplifier), the input of which is coupled to the p-path input of the first integrator INT1. Either of the two switches can be thrown to couple the other side of its associated RC time constant trimming capacitor array C1cal to its associated buffer BUF so as to produce a zero potential across the RC time constant trimming capacitor array C1cal to effectively remove any influence of the RC time constant trimming capacitor array C1cal from the amplifier 22. The advantage of removing the RC time constant trimming capacitor array C1cal in this manner is that it reduces the PN junction area attached to the virtual ground Vx of the first integrator INT1 (e.g., from a MOSFET used as a switch in the trimming capacitor array), which makes the trimming performance less susceptible to process / temperature / voltage variations.

[0090] Reference now Fig.15 , shows the example for use Fig.13 1502. Operation begins at block 1502.

[0091] At block 1502 , the amplifier 22 is set to closed loop operation with zero input and the output DC offset voltage is recorded as a reference. Operation proceeds to block 1504 .

[0092] At block 1504 , the HV / LV mode is switched once to check if the resulting DC offset voltage has changed from the previously captured value. Operation proceeds to block 1506 .

[0093] At block 1506, the resistor trim code is adjusted using a binary search algorithm, and the resulting output offset voltage is saved as a reference for the next iteration before the next mode switch. This step is repeated until the binary search algorithm converges to the minimum DC offset difference between the modes. The resulting final code is the optimal code to obtain the desired CMRR. Operation proceeds to block 1508.

[0094] At block 1508, steps 1502 to 1506 are repeated for each gain tap. In this manner, a resistance ratio optimal trimming code may be found.

[0095] RC time constant trimming is used to remove transient glitches originating from periodic common mode switching at the class D driver stage 34. In theory, only one calibration is required. Preferably, the entire trimming code space is swept to obtain the best code that produces the smallest transient glitches. During the trimming process, periodic mode switching is forced to expose the time constant difference between the differential p and m paths of the first integrator INT1, and spectrum analysis (e.g., Fast Fourier Transform (FFT)) can be used to evaluate the pulse energy with glitches in the band with high resolution.

[0096] Glitch-free transitions between power rails in a Class-D amplifier incorporating dual-path power rail sensing

[0097] To minimize the change in power stage gain associated with supply voltage changes, the quantizer gain, set by the ramp amplitude, must be proportional to the supply voltage. Ideally, as the final stage supply moves, the duty cycle output of the quantizer moves accordingly. Therefore, as long as this supply feed-forward is perfectly implemented, the amplifier feedback loop does not need to react.

[0098] Unfortunately, the sensing network may have a limited bandwidth. The supply voltage feed forward concept may only work up to a certain frequency, beyond which the path latency is too large, making the DC operating point (DCOP) set by the supply feed forward path inaccurate. As a result, the loop undergoes a DCOP settling procedure, which is the root cause of supply transient glitches. A more difficult situation exists when a sudden step transient occurs at the ultimate supply, which requires an immediate response to the ramp amplitude. Since no circuit has infinite bandwidth, embodiments are described in which a second path is included to address this situation.

[0099] Reference now Fig.16 , shows a conceptual block diagram of an embodiment of a dual power supply sensing circuit 1602 for ramp generation, illustrating the ability of the ramp amplitude to move instantaneously as the operating mode of the output stage changes. The first current-to-voltage conversion block 1604H converts HV_SUPPLY to an HV current received by the first gain adjustment block 1606H. The second current-to-voltage conversion block 1604L converts LV_SUPPLY to an LV current received by the second gain adjustment block 1606L. The first and / or second gain adjustment blocks 1606L and 1606H calibrate the received corresponding conversion currents to match each other and provide them to the multiplexer 1608. The multiplexer 1608 selects one of its inputs based on the control input HV / LV selection indicating the current operating mode. The selected calibration current is provided to the ramp generator 1612, which generates a ramp, and the comparator of the quantizer 304 compares the ramp with the output of the loop filter 302, and the result is provided to the driver stage 34 to drive the load 332.

[0100] If available from Fig.16 Conceptually, there is a HV path and a LV path through the quantizer 304. The HV path is used by the quantizer 304 in HV mode, and the LV path is used by the quantizer 304 in LV mode. The HV path and the HV output stage 404 of the quantizer 304 have a combined HV gain, and the LV path and the LV output stage 424 of the quantizer have a combined LV gain. The combined HV gain and the combined LV gain are calibrated to match (e.g., within a few percent) so that any changes in the open-loop transfer function of the speaker amplifier 22 are minimized when the operating mode is changed. Therefore, glitches associated with changes in the open-loop transfer function caused by the difference between the combined HV gain and the combined LV gain can be minimized or removed. In addition, the optimal location for making the operating mode change to minimize the possible effects of the combined HV gain and LV gain mismatch is when the output voltage of the differential driver stage 34 is zero, which can be detected as a zero duty cycle crossing of the output of the quantizer 304. Therefore, a VZC detection circuit (eg, a phase detector) based on the local output of the quantizer 304 may be employed for timely detection.

[0101] The timing of the power switching is also critical for a glitch-free transition, as it must not disturb the current duty cycle generation. Therefore, the best point to make a power change is at the beginning of the PWM cycle, which occurs immediately when both terminals of the load 332 are connected to the power rail shared by both the HV output stage 404 and the LV output stage 424, as shown in Fig.16 The transition shown in the lower portion of is made at the bottom of the ramp, which corresponds to the CEM start pulse that starts the PWM cycle. Advantageously, making a power change at the beginning of a PWM cycle can be precisely coordinated in a single chip design, with the start of the PWM cycle occurring immediately when both terminals of the load 332 are connected to the power rail shared by both the HV output stage 404 and the LV output stage 424.

[0102] Reference now Fig.17 , shows a diagram showing a three output stage Figure 3 A circuit diagram of an embodiment of the driver stage 34 is shown. Fig.17 The embodiments of Figure 5 The embodiments are similar and like numbered elements are similar. However, Fig.17 Embodiments also include Figure 44 and bypass and HV blocking circuit 416. The MV output stage 414 includes an MVP portion and an MVN portion. The MVP portion includes a pair of p-channel MV FETs (MVP) whose sources are coupled to MV_SUPPLY. The drain of one of the MV p-channel FETs (MVP) is coupled to the bypass and HV blocking circuit 416 via node C, and the drain of the other of the medium voltage p-channel FETs (MVP) is coupled to the bypass and HV blocking circuit 416 via node D. The MVN portion includes a pair of n-channel MV FETs (MVN) whose sources are coupled to ground. The drain of one of the n-channel MV FETs (MVN) is coupled to the bypass and HV blocking circuit 416 via node C, and the drain of the other of the n-channel medium voltage FETs (MVN) is coupled to the bypass and HV blocking circuit 416 via node D. The gates of the MVP FET and the MVN FET can be driven by an MV pre-driver (e.g., Figure 4 The gates of the MVP FET and the MVN FET may be driven by a MV pre-driver (eg, Figure 4 When the class-D amplifier 22 is in the MV mode, HVP and HVN (and the associated HV pre-driver 402) and LVP and LVN (and the associated LV pre-driver 422) are turned off to substantially reduce power consumption.

[0103] Although not in Fig.17 , but the bypass and HV blocking circuit 416 includes a third clamp, a third capacitor, and a third buffer, each coupled between node C and a floating voltage at the cathode of a diode, the anode of which is similar to Figure 5 4 is coupled to a supply voltage node (e.g., a battery) in the manner shown for bypass and HV blocking circuit 426 in FIG. 4. The output of the third buffer is coupled to the gate of a third high voltage n-channel FET HVN_bypass3, which serves as an interconnect switch or bypass switch, to selectively couple node C to node OUT_M. Although not shown, bypass and HV blocking circuit 416 also includes a fourth clamp, a fourth capacitor, and a fourth buffer, each coupled between node D and the floating voltage. The output of the fourth buffer is coupled to the gate of a fourth high voltage n-channel FET HVN_bypass4, which serves as an interconnect switch or bypass switch, to selectively couple node D to node OUT_P. When HVP is turned on, bypass switches HVN_bypass3 and HVN_bypass4 are also used to protect MVP FET and MVN FET from the high voltage provided by HV_SUPPLY through HVP.

[0104] The MV output stage 414 is constructed in a different power domain and using different types of devices than the HV output stage 404 or the LV output stage 424. The bypass switches HVN_bypass3 and HVN_bypass4 (collectively referred to as bypass switches HVN_bypass) are of the HV type. When the bypass switches HVN_bypass are enabled, the MV output stage 414 is connected to the output load 332, and when the bypass switches HVN_bypass are disabled, they block the swing from the MV output stage 414 to the output load 332. The control of the bypass switches HVN_bypass is static based on power envelope detection of the output signal. The bypass switches HVN_bypass are powered by a local floating voltage supply. The floating voltage is controlled by a power supply similar to that described with respect to Figure 5 The bootstrap circuit produces.

[0105] Similar to the above Figure 6 As described, during a mode transition between the MV output stage 414 and one of the two other output stages (eg, 404 and 424), the “make before break” rule is followed regardless of which direction the operating mode is transitioning.

[0106] It should be understood, especially by those of ordinary skill in the art who have benefited from this disclosure, that the various operations described herein (especially in conjunction with the accompanying drawings) may be implemented by other circuits or other hardware components. Unless otherwise indicated, the order in which each operation of a given method is performed may be changed, and the various elements of the systems shown herein may be added, reordered, combined, omitted, modified, etc. The present disclosure is intended to encompass all such modifications and changes, and therefore, the above description should be considered illustrative rather than restrictive.

[0107] Similarly, although the present disclosure is directed to specific embodiments, certain modifications and changes may be made to those embodiments without departing from the scope and coverage of the present disclosure. In addition, any benefits, advantages, or solutions to problems described herein with respect to specific embodiments are not intended to be interpreted as key, required, or essential features or elements.

[0108] Other similar embodiments with the benefit of this disclosure will be apparent to those of ordinary skill in the art, and such embodiments should be considered to be included herein. All examples and conditional language listed herein are intended for teaching purposes to help readers understand the present disclosure and the concepts made by the inventors to further develop the art, and are interpreted as not being limited to such specifically listed examples and conditions.

[0109] The present disclosure includes all changes, substitutions, variations, alterations and modifications to the example embodiments herein that would be understood by a person of ordinary skill in the art. Similarly, the appended claims cover all changes, substitutions, variations, alterations and modifications to the example embodiments herein that would be understood by a person of ordinary skill in the art, where appropriate. In addition, references in the appended claims to a device or system adapted to, arranged to, enabled, configured to, enabled, operable or operable to perform a specific function, or a component of a device or system, include the device, system or component, whether or not it or the specific function is activated, turned on, or unlocked, as long as the device, system or component is so adjusted, arranged, capable, configured, enabled, operable or operable.

Claims

1. A method for improving a broadband common mode rejection ratio (CMRR) in a class D amplifier, comprising: matching the first ratio and the second ratio in a first trimming manner; wherein the class D amplifier comprises an integrator coupled to a differential first path and a second path; wherein the first ratio is a ratio of a feedback resistor to an input resistor in the first path; wherein the second ratio is a ratio of a feedback resistance to an input resistance in the second path; After matching the first ratio and the second ratio in the first trimming manner, matching the first RC time constant and the second RC time constant in the second trimming manner; wherein R of the first RC time constant is a resistor having a first matching ratio, and C of the first RC time constant is an integral capacitor in the first path; and The other R of the second RC time constant is a resistor with a second matching ratio, and the other C of the second RC time constant is an integral capacitor in the second path.

2. The method according to claim 1, in, The first trimming method includes trimming at least one resistor array in at least one of the first path and the second path; and The second trimming method includes trimming at least one capacitor array in at least one of the first path and the second path.

3. The method according to claim 2, in, The matching the first ratio and the second ratio includes trimming the at least one resistor array to change the input resistance and an equivalent resistance of the at least one resistor array.

4. The method according to claim 2, in, The at least one resistor array is static with respect to a pulse width modulated (PWM) input signal that switches input resistances in the differential first and second paths.

5. The method according to claim 2, in, The at least one resistor array is coupled to a virtual ground of the integrator.

6. The method according to claim 5, further comprising: in, The at least one capacitor array includes a first capacitor array in the first path and a second capacitor array in the second path; wherein the first capacitor array and the second capacitor array include switches for trimming according to a second manner; wherein the class D amplifier comprises a first buffer in the first path and a second buffer in the second path, the first buffer and the second buffer are both coupled to a virtual ground of the integrator; and One of the first buffer and the second buffer is operated to generate a zero potential on one of the first capacitor array and the second capacitor array to reduce a PN junction area attached to a virtual ground of the integrator.

7. The method according to claim 1, in, The first trimming method includes using a laser to trim one or more of the feedback resistor and the input resistor to match the first ratio and the second ratio; and The second trimming method includes using a laser to trim one or more capacitors in the integral capacitor to match the first RC time constant and the second RC time constant.

8. A class D amplifier, comprising: an integrator coupled to the differential first path and the second path; Wherein, the first path and the second path both include a feedback resistor, an input resistor and an integral capacitor; wherein the first ratio is a ratio of feedback resistance to input resistance in the first path, and the second ratio is a ratio of feedback resistance to input resistance in the second path; wherein the first ratio and the second ratio can be matched in a first trimming manner; wherein R of the first RC time constant is a resistor having a first matching ratio, and C of the first RC time constant is an integral capacitor in the first path, and another R of the second RC time constant is a resistor having a second matching ratio, and another C of the second RC time constant is an integral capacitor in the second path; and The first RC time constant and the second RC time constant can be matched in a second trimming manner.

9. The class D amplifier of claim 8, further comprising: At least one resistor array in at least one of the first path and the second path, which can be trimmed according to the first trimming method; as well as At least one capacitor array in at least one of the first path and the second path can be trimmed according to the second trimming method.

10. The class D amplifier according to claim 9, in, The at least one resistor array is trimmable to change the input resistance and an equivalent resistance of the at least one resistor array to match the first ratio and the second ratio.

11. The class D amplifier according to claim 10, in, The at least one resistor array is static with respect to a pulse width modulated (PWM) input signal that switches input resistances in the differential first and second paths.

12. The class D amplifier according to claim 11, in, The at least one resistor array is coupled to a virtual ground of the integrator.

13. The class D amplifier of claim 12, further comprising: in, The at least one capacitor array includes a first capacitor array in the first path and a second capacitor in the second path; wherein the first capacitor array and the second capacitor array include switches for trimming according to a second manner; a first buffer in the first path and a second buffer in the second path, the first buffer and the second buffer being coupled to a virtual ground of the integrator; and The first buffer and the second buffer are operable to generate a zero potential on the first capacitor array and the second capacitor array to reduce a PN junction area attached to a virtual ground of the integrator.

14. The class D amplifier according to claim 8, in, The first trimming manner includes using a laser to trim one or more of the feedback resistor and the input resistor to match the first ratio and the second ratio; and The second trimming method includes using a laser to trim one or more of the integral capacitors to match the first RC time constant and the second RC time constant.

15. A method performed by a class D amplifier having a quantizer and a driver stage, wherein: The quantizer and the driver stage have a combined gain, the method comprising: For each of the plurality of power rails of the Class-D amplifier: sensing a voltage value of the power rail; and determining a ramp amplitude based on the sensed voltage value; at the same time: switching the driver stage from using a first power rail of the plurality of power rails to using a second power rail of the plurality of power rails; and The quantizer is switched from using a ramp amplitude associated with the first power rail to using a ramp amplitude associated with the second power rail to make the combined gain constant.

16. The method according to claim 15, further comprising: in, The driver stage includes a plurality of independent output stages receiving respective supply voltages from the plurality of power rails for driving a load of the class-D amplifier; and wherein the switching of the driver stage from using a first power rail of the plurality of power rails to using a second power rail of the plurality of power rails and the switching of the quantizer from using a ramp amplitude associated with the first power rail to using a ramp amplitude associated with the second power rail are performed at the beginning of a pulse width modulation (PWM) cycle, the beginning of the pulse width modulation (PWM) cycle occurring when both terminals of the load are connected to a power rail shared by the plurality of independent output stages.

17. The method according to claim 16, further comprising: include: in, The quantizer and the driver stage have a plurality of combined gains corresponding to the plurality of output levels; as well as Each of the plurality of combined gains is calibrated so that the plurality of combined gains match.

18. The method according to claim 15, further comprising: detecting a zero duty cycle crossing at an output of the quantizer; and wherein the switching of the driver stage from using a first power rail of the plurality of power rails to using a second power rail of the plurality of power rails and the switching of the quantizer from using a ramp amplitude associated with the first power rail to using a ramp amplitude associated with the second power rail are performed at the detected zero duty cycle crossing.

19. A class D amplifier comprising: Accepts multiple power rails of different voltages; Quantizer; as well as Driver stage; wherein the quantizer and the driver stage have a combined gain; The circuit is configured as: For each of the plurality of power rails of the Class-D amplifier: sensing a voltage value of the power rail; and determining a ramp amplitude based on the sensed voltage value; at the same time: switching the driver stage from using a first power rail of the plurality of power rails to using a second power rail of the plurality of power rails; and The quantizer is switched from using a ramp amplitude associated with the first power rail to using a ramp amplitude associated with the second power rail to make the combined gain constant.

20. The class D amplifier according to claim 19, in, The driver stage includes a plurality of independent output stages receiving respective supply voltages from the plurality of power rails for driving a load of the class-D amplifier; and wherein the switching of the driver stage from using a first power rail of the plurality of power rails to using a second power rail of the plurality of power rails and the switching of the quantizer from using a ramp amplitude associated with the first power rail to using a ramp amplitude associated with the second power rail are performed at the beginning of a pulse width modulation (PWM) cycle, the beginning of the pulse width modulation (PWM) cycle occurring when both terminals of the load are connected to a power rail shared by the plurality of independent output stages.

21. The class D amplifier according to claim 20, in, The quantizer and the driver stage have a plurality of combined gains corresponding to the plurality of output levels; and One or more of the plurality of combined gains are calibrable such that the plurality of combined gains match.

22. The class D amplifier of claim 19, further comprising: circuitry configured to detect a zero duty cycle crossing at an output of the quantizer; and wherein the switching of the driver stage from using a first power rail of the plurality of power rails to using a second power rail of the plurality of power rails and the switching of the quantizer from using a ramp amplitude associated with the first power rail to using a ramp amplitude associated with the second power rail are performed at the detected zero duty cycle crossing.

23. A method for reducing distortion in a class D amplifier having a driver stage capable of operating in multiple modes having different respective output impedances, the method comprising: sensing a current at a load of the class-D amplifier; determining an IR drop of a corresponding output impedance of the driver stage based on the sensed current; as well as The IR drop is added to the loop filter output of the class-D amplifier to compensate for the corresponding output impedance of the driver stage.

24. The method according to claim 23, further comprising: determining a location of a load current zero crossing based on the sensed current; as well as At the determined location, the class-D amplifier is changed to operate in a different one of the plurality of modes having a different corresponding output impedance.

25. The method of claim 23, further comprising: Sense the position of the load voltage zero crossing; as well as At the sensed position, the class-D amplifier is changed to operate in a different one of the plurality of modes having a different corresponding output impedance.

26. A class D amplifier comprising: a loop filter having an output terminal; a driver stage capable of operating in multiple modes having different corresponding output impedances; as well as The circuit is configured as: sensing a current at a load of the class-D amplifier; determining an IR drop of a corresponding output impedance of the driver stage based on the sensed current; and The IR drop is added to the loop filter output to compensate for the corresponding output impedance of the driver stage.

27. The class D amplifier of claim 26, in, The output impedance of the driver stage is variable at zero crossings of the sensed load current.

28. The class D amplifier of claim 26, in, The output impedance of the driver stage is variable at zero crossings of the sensed load voltage.

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