Clock phase automatic correction method and device
By building an automatic clock correction system, the digital acquisition module, test computer and test computer are used to automatically adjust the phase of the clock signal, solving the problem of data transmission abnormalities caused by clock offset in the digital circuit, realizing automatic clock phase correction, and improving the accuracy and compatibility of correction.
Patent Information
- Application Number
- CN202411629116.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-15
- Publication Date
- 2025-03-25
AI Technical Summary
In high-digital digital circuits, offset of clock signals may lead to abnormal data transmission, and the prior art requires active clock phase correction, which is complicated and not automated.
A clock phase automatic correction method and device are provided. By building an automatic clock calibration system, the digital acquisition module, test computer and test computer are used to automatically adjust the phase of the clock signal to make it have a fixed phase relationship with the reference clock.
The automated process of automatic clock phase correction is realized, which simplifies correction operations, improves compatibility, and improves the accuracy and robustness of corrections through the iterative correction process.
Smart Images
Figure CN119696555A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of electronic information technology, and in particular relates to a clock phase automatic correction method and device. Background Art
[0002] With the advancement of technology, the frequency range of electronic devices is constantly expanding. In high-frequency digital circuits, parallel data may be transmitted abnormally due to clock offset during transmission. Usually, active clock phase correction is required to solve this clock offset. Summary of the invention
[0003] The purpose of the present invention is to provide a method and device for automatic correction of clock phase in view of the above-mentioned problems, so as to realize the automation of the correction process. The device can quickly realize automatic correction of the clock. The correction operation using the device is simple and has strong compatibility.
[0004] The above purpose is achieved through the following technical solutions:
[0005] The present invention first provides a clock phase automatic correction method, the method comprising the following steps:
[0006] S1. Build a clock automatic correction system, including a digital acquisition module, a test computer, and a test host computer;
[0007] S2. When the phase of clock signal 1 needs to be corrected, first select a clock in the digital acquisition module as the correction reference, correct the phase of clock signal 1 so that it has a fixed phase relationship with the reference clock, and the host computer sends the configuration parameters of clock signal 1 and the reference clock;
[0008] S3. The host computer controls the signal source to transmit the reference signal into the digital acquisition module. The digital acquisition module uses the clock signal 1 and the reference clock to collect the reference signal, adjust the reference signal frequency in steps, and record the reference signal data collected by the clock signal 1 and the reference clock at all frequencies;
[0009] The host computer processes the reference signal data collected by the clock signal 1 and the reference clock, extracts the phase information of the collected reference signal data at the set frequency, subtracts the phase information of the two channels to obtain a frequency-phase curve, fits the frequency-phase curve to obtain the slope of the curve, calculates the phase difference between the clock signal 1 and the reference clock according to the slope of the curve, calculates the difference based on the ideal result and the configuration parameters sent in step 2, and resends the configuration parameters;
[0010] S4. Iterative correction process: Iterate the correction process of steps 2-3 two or three times until the expected correction effect is achieved.
[0011] Furthermore, the specific method of step S2 is as follows:
[0012] Assuming that the initial phase of the reference clock is 0, that is, the clock signal is 0, its expression is:
[0013] C0(t)=sin(2π·f clk ·t)
[0014] Where C0(t) represents the output signal of clock signal 0, f clk represents the reference clock frequency, and t represents the time parameter;
[0015] When the initial phase of clock signal 1 relative to the reference signal is When , it is expressed as:
[0016]
[0017] Here, C1(t) represents the output signal representing clock signal 1.
[0018] Furthermore, the specific method of step S3 is as follows:
[0019] The reference signal emitted by the signal source is expressed as:
[0020]
[0021] Among them, S0(t) represents the output signal of the signal source, represents the initial phase of the signal source, f sig is the reference signal frequency;
[0022] After sampling and signal processing the reference signal using the above two clocks, the phases of the sampled signals are:
[0023]
[0024] in, Indicates the phase of the reference signal after sampling and signal processing by clock signal 0. Indicates the phase of the reference signal after sampling and signal processing by clock signal 1;
[0025] when When , the term containing t disappears and becomes a constant, and the uncertain The term is also eliminated, so Finally, the phase of clock signal 1 is obtained:
[0026]
[0027] The above formula is affected by the actual acquisition accuracy and the physical characteristics of the device. The single frequency point measurement error is large. In order to further eliminate the error, the above formula is expressed as:
[0028]
[0029] Using multiple groups of f sig Signal Fit the function and find the slope K. Finally, the phase of clock signal 1 can be obtained as:
[0030]
[0031] According to the obtained phase Select the correction target phase positioning as 0, that is, synchronize with the reference clock or fix any specified phase difference with the reference clock, calculate the new configuration parameters and issue them, until the obtained Meets calibration requirements.
[0032] The present invention also provides a clock phase automatic correction device, which is used to implement the above-mentioned clock phase automatic correction method. The device includes a digital acquisition module, a test computer, and a test host computer. The test host computer is embedded with the clock phase automatic correction method software described in one of claims 1-3.
[0033] Compared with the prior art, the present invention has the following significant advantages:
[0034] 1. The present invention can automatically complete the calibration process through the host computer;
[0035] 2. The present invention includes a host computer, a test system, and a complete system of the device under test;
[0036] 3. The present invention is based on a correction algorithm and readback data, and the correction process can be iterated to verify the correction effect. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] Figure 1 This is a working block diagram of the clock phase automatic correction device proposed by the present invention. DETAILED DESCRIPTION
[0038] The present invention is further described in detail below in conjunction with the accompanying drawings.
[0039] Figure 1 The figure shows the working block diagram of the clock phase automatic correction device. The modules implemented by the present invention include a digital acquisition module, a test computer, test software (including high-speed clock phase automatic correction software) and corresponding test cables, power supplies, signal sources and other equipment. The specific implementation steps are as follows:
[0040] Step 1: Build an automatic correction device system, including a digital acquisition module, a test computer, a test host computer (including high-speed clock phase automatic correction software) and corresponding test instruments, etc.;
[0041] Step 2: When the phase of clock signal 1 needs to be corrected, first select a clock in the acquisition module as the correction reference (assuming its initial phase is 0). By correcting the phase of clock signal 1, it has a fixed phase relationship with the reference clock. The host computer sends the configuration parameters of clock signal 1 and the reference clock.
[0042] Step 3: The host computer controls the signal source to transmit the reference signal into the digital acquisition module. The digital acquisition module uses the clock signal 1 and the reference clock to respectively collect the reference signal, adjusts the reference signal frequency in steps, and records the reference signal data collected by the clock signal 1 and the reference clock at all frequencies.
[0043] The host computer processes the data, extracts the phase information of the collected signal at the set frequency, subtracts the phase information of the two channels to obtain the frequency-phase curve, fits the curve to obtain the slope of the curve, calculates the phase difference between clock signal 1 and the reference clock based on the slope, and calculates the difference based on the ideal result and the configuration parameters sent in step 2. Resend the configuration parameters.
[0044] Step 4: Iterate the correction process. Iterate the correction process of steps 2-3 two or three times until the desired correction effect is achieved.
[0045] The specific implementation principles in steps 2 and 3 are as follows:
[0046] Assuming that the initial phase of the reference clock is 0, that is, the clock signal is 0, its expression is:
[0047] C0(t)=sin(2π·f clk ·t)
[0048] Where C0(t) represents the output signal of clock signal 0, f clk represents the reference clock frequency, and t represents the time parameter;
[0049] When the initial phase of clock signal 1 relative to the reference signal is When , it is expressed as:
[0050]
[0051] Here, C1(t) represents the output signal representing clock signal 1.
[0052] The reference signal emitted by the signal source is expressed as:
[0053]
[0054] Among them, S0(t) represents the output signal of the signal source, represents the initial phase of the signal source, f sig is the reference signal frequency;
[0055] After sampling and signal processing the reference signal using the above two clocks, the phases of the sampled signals are:
[0056]
[0057] in, Indicates the phase of the reference signal after sampling and signal processing by clock signal 0. Indicates the phase of the reference signal after sampling and signal processing by clock signal 1;
[0058] when When , the term containing t disappears and becomes a constant, and the uncertain The term is also eliminated, so Finally, the phase of clock signal 1 is obtained:
[0059]
[0060] The above formula is affected by the actual acquisition accuracy and the physical characteristics of the device. The single frequency point measurement error is large. In order to further eliminate the error, the above formula is expressed as:
[0061]
[0062] Using multiple groups of f sig Signal Fit the function and find the slope K. Finally, the phase of clock signal 1 can be obtained as:
[0063]
[0064] According to the obtained phase Select the correction target phase positioning as 0, that is, synchronize with the reference clock or fix any specified phase difference with the reference clock, calculate the new configuration parameters and issue them, until the obtained Meets calibration requirements.
[0065] Through the above steps, the clock phase correction process can be realized. The correction can be automatically completed by the host computer, and the correction process is iterated at the same time, which increases the accuracy and robustness of the automatic correction system. Its main features are that any correction target phase can be set, phase correction between channels of any clock frequency can be achieved, and the correction device itself will not become a bottleneck for phase correction accuracy (the accuracy is only limited by the limit accuracy of the module being corrected itself).
Claims
1. A clock phase automatic correction method, characterized in that: The method comprises the following steps: S1. Build a clock automatic correction system, including a digital acquisition module, a test computer, and a test host computer; S2. When the phase of clock signal 1 needs to be corrected, first select a clock in the digital acquisition module as the correction reference, correct the phase of clock signal 1 so that it has a fixed phase relationship with the reference clock, and the host computer sends the configuration parameters of clock signal 1 and the reference clock; S3. The host computer controls the signal source to transmit the reference signal into the digital acquisition module. The digital acquisition module uses the clock signal 1 and the reference clock to collect the reference signal, adjust the reference signal frequency in steps, and record the reference signal data collected by the clock signal 1 and the reference clock at all frequencies; The host computer processes the reference signal data collected by the clock signal 1 and the reference clock, extracts the phase information of the collected reference signal data at the set frequency, subtracts the phase information of the two channels to obtain a frequency-phase curve, fits the frequency-phase curve to obtain the slope of the curve, calculates the phase difference between the clock signal 1 and the reference clock according to the slope of the curve, calculates the difference based on the ideal result and the configuration parameters sent in step 2, and resends the configuration parameters; S4. Iterative correction process: Iterate the correction process of steps 2-3 two or three times until the expected correction effect is achieved.
2. A clock phase automatic correction method according to claim 1, characterized in that: The specific method of step S2 is as follows: Assuming that the initial phase of the reference clock is 0, that is, the clock signal is 0, its expression is: C0(t)=sin(2π·f clk ·t) Where C0(t) represents the output signal of clock signal 0, f clk represents the reference clock frequency, and t represents the time parameter; When the initial phase of clock signal 1 relative to the reference signal is When , it is expressed as: Here, C1(t) represents the output signal representing clock signal 1.
3. The method for automatic clock phase correction according to claim 2, characterized in that: The specific method of step S3 is as follows: The reference signal emitted by the signal source is expressed as: Among them, S0(t) represents the output signal of the signal source, represents the initial phase of the signal source, f sig is the reference signal frequency; After sampling and signal processing the reference signal using the above two clocks, the phases of the sampled signals are: in, Indicates the phase of the reference signal after sampling and signal processing by clock signal 0. Indicates the phase of the reference signal after sampling and signal processing by clock signal 1; when When , the term containing t disappears and becomes a constant, and the uncertain The term is also eliminated, so Finally, the phase of clock signal 1 is obtained: The above formula is affected by the actual acquisition accuracy and the physical characteristics of the device. The single frequency point measurement error is large. In order to further eliminate the error, the above formula is expressed as: Using multiple groups of f sig Signal Fit the function and find the slope K. Finally, the phase of clock signal 1 can be obtained as: According to the obtained phase Select the correction target phase positioning as 0, that is, synchronize with the reference clock or fix any specified phase difference with the reference clock, calculate the new configuration parameters and send them down until the obtained Meets calibration requirements.
4. A clock phase automatic correction device, characterized in that: The device is used to implement the clock phase automatic correction method described in any one of claims 1-3. The device includes a digital acquisition module, a test computer, and a test host computer. The test host computer is embedded with the clock phase automatic correction method software described in any one of claims 1-3.