Semiconductor module

Abstract

A semiconductor module according to the present invention includes: first and second switching elements that operate complementarily; a high-potential-side drive circuit including a first driver capable of adjusting an output to the first gate; and a low-potential-side drive circuit including a second driver capable of adjusting an output to the second gate. The high-potential-side drive circuit includes: a first level shift unit that outputs to a first driver; a shift register; a low-voltage-side setting value storage unit; a write signal generation unit; a second level shift unit which, in accordance with the write signal, shifts the held information of the low-voltage-side setting value holding unit to a high potential; a high-voltage-side setting value storage unit; and a decoder that varies the output current capability of the first driver in accordance with the recording of the high-voltage-side setting value storage unit.

Description

Technical Field

[0001] The present invention relates to a semiconductor module, and in particular, to a semiconductor module having a power transistor and a drive circuit for driving the power transistor built therein. Background Art

[0002] A semiconductor module is known that has a built-in MPU (micro processing unit) having a function of generating a PWM (pulse width modulation) signal. The semiconductor module internally generates a PWM signal for controlling a switching device based on a signal from an external controller.

[0003] On the other hand, there is the following problem, namely, in order to be able to change the operating characteristics of the semiconductor module, it is necessary to communicate between the external controller and the internal controller, receive data for the change from the outside, and also need to receive a trigger signal that specifies the timing of the change from the outside. Terminals are required for this, and the module cannot be miniaturized.

[0004] In this regard, Japanese Patent Application Laid-Open No. 2020-205702 discloses a semiconductor module whose operating characteristics can be changed.

[0005] On the other hand, in the structure shown in Japanese Patent Publication No. 2020-205702, a period (dV / dt period) during which the voltage in the high voltage region of the driving device driving the complementary driven power transistor changes sharply and a negative potential period due to undershoot occurs. During this period, the voltage level conversion (level shift circuit) for signal transmission of the set value cannot achieve signal transmission, and the driving capability setting cannot become a normal value, wherein the set value sets the driving capability. Summary of the invention

[0006] The present invention is made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor module capable of performing normal driving capability setting.

[0007] One aspect of the present invention comprises: a first switching element and a second switching element, which are connected in series between a first potential and a second potential lower than the first potential and operate complementarily; a high potential side driving circuit, which includes a first driver, the first driver is connected to a first gate of the first switching element, the first driver can adjust the output to the first gate; and

[0008] The low potential side driving circuit includes a second driver connected to the second gate of the second switching element, and the second driver can adjust the output to the second gate. The high potential side driving circuit includes: terminals, which respectively receive data communication signals sent from an external controller, namely, a driving signal, a data signal, a clock signal, and an enable signal; a first level shifter, which level-shifts the driving signal to a high potential and outputs it to the first driver; a shift register, which is composed of a plurality of flip-flops connected in cascade, records the data signal in the flip-flop according to the clock signal and the enable signal, and shifts the recorded data to the first level each time the data signal is stored in the flip-flop. to an adjacent trigger; a low-voltage side setting value storage unit, which records the recorded contents of multiple triggers of the first shift register according to the enable signal extraction; a write signal generating unit, which generates a write signal based on the drive signal and the enable signal; a second level shifting unit, which level-shifts the stored information of the low-voltage side setting value storage unit to a high potential according to the write signal; a high-voltage side setting value storage unit, which is connected via the second level shifting unit and records the same information as the information recorded in the low-voltage side setting value storage unit; and a decoder, which is used to make the output current capacity of the first driver variable according to the record of the high-voltage side setting value storage unit.

[0009] The above and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a diagram for explaining the outline of the structure of the semiconductor module according to the first embodiment.

[0011] Figure 2 This is a diagram for explaining the circuit configuration of the first level shifter 10 according to the first embodiment.

[0012] Figure 3 This is a diagram for explaining the configuration of the driver 30 and the shift register unit 38 according to the first embodiment.

[0013] Figure 4 This is a diagram for explaining the configuration of the high-voltage side set value storage unit 16 and the second level shift unit 18 according to the first embodiment.

[0014] Figure 5 This is a diagram for explaining setting information stored in the controller (MCU) 2 according to the first embodiment.

[0015] Figure 6 This is a diagram for explaining a timing chart of output of write signal TM1 according to the first embodiment.

[0016] Figure 7 This is another diagram for explaining the timing chart of the output of the write signal TM1 according to the first embodiment.

[0017] Figure 8 This is a diagram for explaining the outline of the structure of a semiconductor module according to the second embodiment.

[0018] Fig. 9 This is a diagram for explaining a timing chart of output of write signal TM1 according to the second embodiment.

[0019] Fig.10 This is a diagram for explaining the outline of the structure of a semiconductor module according to the third embodiment.

[0020] Fig.11 This is a diagram for explaining the outline of the structure of a semiconductor module according to the fourth embodiment.

[0021] Fig.12 This is a diagram for explaining the configuration of the high-voltage side set value storage unit 16A and the second level shift unit 18A according to the fourth embodiment.

[0022] Fig.13 This is a diagram for explaining the outline of the structure of a semiconductor module according to the fifth embodiment.

[0023] Fig.14 This is a diagram for explaining the configuration of the high-voltage side set value storage unit 16B, the second level shift unit 18B, and the low-voltage side shift register unit 21 according to the fifth embodiment.

[0024] Fig.15 This is a diagram for explaining a timing chart of output of write signal TM1 according to the fifth embodiment.

[0025] Fig.16 This is another diagram for explaining the timing chart of the output of the write signal TM1 according to the fifth embodiment.

[0026] Fig.17 This is a diagram for explaining the outline of the structure of a semiconductor module according to the sixth embodiment. DETAILED DESCRIPTION

[0027] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, the same reference numerals are given to the same or corresponding parts in the drawings, and the description thereof will not be repeated in principle.

[0028] Implementation Method 1

[0029] Figure 1 FIG. 2 is a diagram for explaining the schematic structure of the semiconductor module according to the first embodiment. Figure 1, the semiconductor module includes power transistors (switching elements) Q1, Q2, and a driving circuit for driving the gates of the power transistors Q1, Q2. The power transistor Q1 is arranged between the high potential HV and the output node OUT. The power transistor Q2 is arranged between the output node OUT and the ground potential VSS side. The driving circuit includes a high potential side output capacity variable gate device HVIC (high potential side driving circuit) and a low potential side output capacity variable gate device LVIC (low potential side driving circuit). The high potential side output capacity variable gate device HVIC is arranged corresponding to the gate of the power transistor Q1. The low potential side output capacity variable gate device LVIC is arranged corresponding to the gate of the power transistor Q2. The power transistors Q1, Q2 are complementarily operated by the gate drive of the high potential side output capacity variable gate device HVIC and the low potential side output capacity variable gate device LVIC. As an example, the output node OUT is connected to a motor or the like as a load.

[0030] The controller (MCU) 2 outputs a data communication signal for driving the power transistors Q1 and Q2 to the high potential side output capability variable gate device HVIC and the low potential side output capability variable gate device LVIC. The high potential side output capability variable gate device HVIC and the low potential side output capability variable gate device LVIC drive the power transistors Q1 and Q2, respectively, according to the data communication signal from the controller 2. The high potential side output capability variable gate device HVIC has input terminals HIN, SI, CK, and EN. In addition, the high potential side output capability variable gate device HVIC has an output terminal HO. The input terminal HIN receives a high potential side drive signal from the controller 2. The input terminal SI receives a data signal from the controller 2. The input terminal CK receives a clock signal from the controller 2. The input terminal EN receives an enable signal from the controller 2. The output terminal HO is connected to the gate of the power transistor Q1.

[0031] The high potential side output capability variable gate device HVIC includes a first level shifting unit 10 for level-shifting a high potential side driving signal to a high potential, a write signal generating unit 24, a shift register unit 22, a low voltage side setting value storage unit 20, a second level shifting unit 18, a high voltage side setting value storage unit 16, a decoder 14 and a driver 12.

[0032] The shift register section 22 is composed of a plurality of DT flip-flops connected in cascade. The shift register section 22 records the input data signal according to the data signal, the clock signal and the enable signal, and moves (shifts) the data signal to the adjacent DT flip-flop. In this example, the 3-bit data signal (D1 to D3) is stored in the shift register section 22 and output to the low voltage side set value storage section 20.

[0033] The low voltage side set value storage unit 20 stores the information stored in the shift register unit 22 in accordance with the enable signal. Specifically, the low voltage side set value storage unit 20 stores the information stored in the shift register unit 22 in accordance with the fall or rise of the enable signal.

[0034] The second level shifter 18 level-shifts the data signal, which is 3-bit information stored in the low-voltage side set value storage unit 20 , to a high potential in accordance with the write signal TM1 generated by the write signal generator 24 .

[0035] The high-voltage side set value storage unit 16 stores information of the 3-bit data signal ( D1 to D3 ) level-shifted by the second level shift unit 18 .

[0036] The decoder 14 performs decoding processing based on the data signals ( D1 to D3 ) stored in the high-voltage side set value storage unit 16 , and outputs the decoding processing to the driver 12 .

[0037] In this example, a high voltage region HVR is shown, in which the first level shifter 10 and part of the second level shifter 18 , the driver 12 , the decoder 14 , and the high voltage side set value storage section 16 are provided.

[0038] The write signal generating section 24 outputs a write signal TM1 based on the high potential side drive signal and the enable signal.

[0039] The low potential side output capability variable gate device LVIC has input terminals LIN, SIL, CKL, and ENL. In addition, the low potential side output capability variable gate device LVIC has an output terminal LO. The input terminal LIN receives a low potential side drive signal from the controller 2. The input terminal SIL receives a data signal from the controller 2. The input terminal CKL receives a clock signal from the controller 2. The input terminal ENL receives an enable signal from the controller 2. The output terminal LO is connected to the gate of the power transistor Q2.

[0040] The low potential side output capability variable gate device LVIC includes a shift register section 38 , a set value storage section 36 , a decoder 34 , and a driver 30 .

[0041] The shift register section 38 is composed of a plurality of DT flip-flops connected in cascade. The shift register section 38 records the input data signal according to the data signal, the clock signal and the enable signal, and moves (shifts) the data signal to the adjacent DT flip-flop. In this example, the 3-bit data signal (D1 to D3) is stored in the shift register section 38 and output to the set value storage section 36.

[0042] The set value storage unit 36 ​​stores the information stored in the shift register unit 38 in accordance with the enable signal. The set value storage unit 36 ​​stores the information stored in the shift register unit 38 in accordance with the fall or rise of the enable signal.

[0043] The decoder 34 performs decoding processing based on the data signals ( D1 to D3 ) stored in the setting value storage unit 36 ​​, and outputs the decoding processing to the driver 30 .

[0044] In this example, the following situation is described: the information recorded in the low voltage side setting value storage unit 20 is transmitted to the high voltage side setting value storage unit 16 by the write signal TM1 generated by the write signal generating unit 24 based on the high potential side drive signal and the enable signal, thereby avoiding the period of rapid voltage change (dV / dt period) and the negative voltage period of the high voltage region HVR during which the second level shifting unit 18 cannot achieve signal transmission and communicating.

[0045] Figure 2 FIG. 2 is a diagram for explaining the circuit configuration of the first level shifter 10 according to the first embodiment. Figure 2 The first level shifter 10 includes an on-off one-shot pulse circuit 100 , high withstand voltage MOS transistors 102 , 104 , an SR flip-flop 106 , inverters 114 , 116 , diodes 112 , 118 , and resistors 108 , 110 .

[0046] The on-off one-shot pulse circuit 100 outputs a one-shot pulse when turned on / off (when the input signal rises / falls). The on-off one-shot pulse circuit 100 outputs a one-shot pulse to the gate of the high-withstand voltage MOS transistor 102 when turned on (when the input signal rises). The on-off one-shot pulse circuit 100 outputs a one-shot pulse to the gate of the high-withstand voltage MOS transistor 104 when turned off (when the input signal falls). Node N0 is connected to terminal VB. The floating power supply 120 is connected between terminal VB and terminal VS. Terminal VSS connected to the ground potential GND is connected to node N1. High-withstand voltage MOS transistors 102 and 104 are connected in parallel between node N0 and node N1. Resistor element 108 is provided between the source side of the high-withstand voltage MOS transistor 102 and node N0. Resistor element 110 is provided between the source side of the high-withstand voltage MOS transistor 104 and node N0. The anode side of the diode 112 is connected to the terminal VS which is the intermediate potential, and the cathode side is connected to the connection node between the resistor 108 and the high withstand voltage MOS transistor 102. The anode side of the diode 118 is connected to the terminal VS which is the intermediate potential, and the cathode side is connected to the connection node between the resistor 110 and the high withstand voltage MOS transistor 104. The diodes 112 and 118 clamp the cathode voltage to a voltage drop from the voltage of the terminal VS to the VF voltage of the diode, and adjust it not to exceed the withstand voltage of the inverters 114 and 116 and the resistors 108 and 110.

[0047] When the high withstand voltage MOS transistor 102 is turned off, the potential of the connection node between the resistor element 108 and the high withstand voltage MOS transistor 102 is set to a high potential. Therefore, the output signal of the inverter 114 is set to an "L" level. Similarly, when the high withstand voltage MOS transistor 104 is turned off, the potential of the connection node between the resistor element 110 and the high withstand voltage MOS transistor 104 is set to a high potential. Therefore, the output signal of the inverter 116 is set to an "L" level.

[0048] When the high-voltage MOS transistor 102 is driven (turned on), the potential of the connection node between the resistor element 108 and the high-voltage MOS transistor 102 decreases. In conjunction with this, the output signal of the inverter 114 is set to the "H" level. Similarly, when the high-voltage MOS transistor 104 is driven (turned on), the potential of the connection node between the resistor element 110 and the high-voltage MOS transistor 104 decreases. Therefore, the output signal of the inverter 116 is set to the "H" level.

[0049] The on-off one-shot pulse circuit 100 outputs a one-shot pulse when it is on (when the input signal rises). As a result, the high-voltage MOS transistor 102 is turned on. As a result, the connection node with the resistor element 108 becomes an "L" level, and the inverter 114 outputs an "H" level. That is, the RS flip-flop is set to "1". The on-off one-shot pulse circuit 100 outputs a one-shot pulse when it is off (when the input signal falls). As a result, the high-voltage MOS transistor 104 is turned on. As a result, the connection node with the resistor element 110 becomes an "L" level, and the inverter 116 outputs an "H" level. That is, the RS flip-flop is reset to "0".

[0050] With this configuration, the driving signal input to the on / off one-shot pulse circuit 100 is level-shifted to a high potential and stored in the RS flip-flop 106. The RS flip-flop 106 outputs the stored data signal from the terminal D0OUT.

[0051] Figure 3 1 is a diagram for explaining the configuration of the driver 30 and the shift register unit 38 according to the first embodiment. Figure 3 The shift register section 38 is formed by cascading a plurality of flip-flops (DT-FF) 200 to 202 to form a shift register. The data signal input from the input terminal SIL is input to the D input of the starting flip-flop 200, and the Q output of the starting flip-flop 200 is input to the D input of the next-stage flip-flop 201. The Q output of the next-stage flip-flop 201 is input to the D input of the next-stage flip-flop 202. The Q outputs of the flip-flops 200 to 202 are output to the set value storage section 36 as data D3, D2, and D1.

[0052] The clock signal input from the input terminal CKL is input to the clock inputs of all the flip-flops 200 to 202. The data signal input in accordance with the clock input is transferred to the flip-flop of the next stage and is stored in the flip-flop of the next stage.

[0053] The setting value storage unit 36 ​​includes a plurality of flip-flops (DT-FF) 203 to 205. The output of the flip-flop 200, i.e., data D3, is input to the D input of the flip-flop 203. The output of the flip-flop 201, i.e., data D2, is input to the D input of the flip-flop 204. The output of the flip-flop 202, i.e., data D1, is input to the D input of the flip-flop 205. The enable signal input from the input terminal ENL is input to the clock inputs of all the flip-flops 203 to 205.

[0054] Therefore, the flip-flops 203 to 205 of the setting value storage unit 36 ​​store the Q outputs of the flip-flops 200 to 202, i.e., data D3, D2, and D1, according to the enable signal input from the input terminal ENL, and output them to the decoder 34. The setting value storage unit 36 ​​stores 3-bit information (D1 to D3). The decoder 34 decodes the 3-bit information into an 8-pattern signal.

[0055] The driver 30 has a plurality of drivers DD connected in parallel to the gate of the power transistor Q2. All of the plurality of drivers DD except one are connected to the gate of the power transistor Q2 via a switch SW, and the connection and disconnection to the gate of the power transistor Q2 are controlled by turning the switch SW on and off. The on / off control of the switch SW is controlled by the Q output of the flip-flops 200 to 202, i.e., the set value. The decoder 34 decodes the 3-bit information of the set value storage unit 36 ​​into an 8-mode signal, and performs on / off control of the switch SW.

[0056] The switch SW of the driver 30 is turned on according to the 8-mode signal output from the decoder 34. If the number of switches SW of the driver 30 is increased, the number of drivers DD driving the power transistor Q2 can be increased. Therefore, the driving capability of the driver 30 can be improved. As described above, the driving capability can be variably set according to the set value. In addition, although Figure 3 1 and 2 have been described with reference to the configuration of the driver 30 of the low potential side output capability variable gate device LVIC. However, the configurations of the shift register unit 22 and the driver 12 of the high potential side output capability variable gate device HVIC are also the same.

[0057] Figure 4 FIG. 2 is a diagram for explaining the configuration of the high voltage side set value storage unit 16 and the second level shift unit 18 according to the first embodiment. Figure 4 The high voltage side set value storage unit 16 includes a plurality of flip-flops 106A to 106C.

[0058] The second level shift unit 18 includes a plurality of flip-flops (DT-FF) 101A to 101C, on / off single-shot pulse circuits 100A to 100C, high-voltage MOS transistors 102A to 102C, 104A to 104C, SR flip-flops 106A to 106C, inverters 114A to 114C, 116A to 116C, diodes 112A to 112C, 118A to 118C, and resistors 108A to 108C, 110A to 110C.

[0059] The flip-flop 101A is triggered by the write signal TM1 and stores the data D3 stored in the low voltage side set value storage unit 20. The flip-flop 101B is triggered by the write signal TM1 and stores the data D2 stored in the low voltage side set value storage unit 20. The flip-flop 101C is triggered by the write signal TM1 and stores the data D1 stored in the low voltage side set value storage unit 20.

[0060] The on-off one-shot pulse circuit 100A outputs a one-shot pulse when the data D3 is turned on / off (when the input signal rises / falls). The on-off one-shot pulse circuit 100A outputs a one-shot pulse to the gate of the high-withstand voltage MOS transistor 102A when turned on (when the input signal rises). The on-off one-shot pulse circuit 100A outputs a one-shot pulse to the gate of the high-withstand voltage MOS transistor 104A when turned off (when the input signal falls). Node N0 is connected to terminal VB. The floating power supply 120 is connected between terminal VB and terminal VS. Terminal VSS connected to the ground potential GND is connected to node N1. High-withstand voltage MOS transistors 102A and 104A are connected in parallel between node N0 and node N1. Resistor element 108A is provided between the source side of the high-withstand voltage MOS transistor 102A and node N0. Resistor element 110A is provided between the source side of the high-withstand voltage MOS transistor 104A and node N0. The anode side of the diode 112A is connected to the terminal VS which is the intermediate potential, and the cathode side is connected to the connection node between the resistor element 108A and the high withstand voltage MOS transistor 102A. The anode side of the diode 118A is connected to the terminal VS which is the intermediate potential, and the cathode side is connected to the connection node between the resistor element 110A and the high withstand voltage MOS transistor 104A.

[0061] When the high withstand voltage MOS transistor 102A is turned off, the potential of the connection node between the resistor element 108A and the high withstand voltage MOS transistor 102A is set to a high potential. Therefore, the output signal of the inverter 114A is set to an "L" level. Similarly, when the high withstand voltage MOS transistor 104A is turned off, the potential of the connection node between the resistor element 110A and the high withstand voltage MOS transistor 104A is set to a high potential. Therefore, the output signal of the inverter 116A is set to an "L" level.

[0062] When the high-voltage MOS transistor 102A is driven (turned on), the potential of the connection node between the resistor element 108A and the high-voltage MOS transistor 102A decreases. In association with this, the output signal of the inverter 114A is set to the "H" level. Similarly, when the high-voltage MOS transistor 104A is driven (turned on), the potential of the connection node between the resistor element 110A and the high-voltage MOS transistor 104A decreases. Therefore, the output signal of the inverter 116A is set to the "H" level.

[0063] The on-off one-shot pulse circuit 100A outputs a one-shot pulse when the data D3 is turned on (when the input signal rises). As a result, the high-voltage MOS transistor 102A is turned on. As a result, the connection node with the resistor element 108A becomes an "L" level, and the inverter 114A outputs an "H" level. That is, the RS flip-flop is set to "1". The on-off one-shot pulse circuit 100A outputs a one-shot pulse when the data D3 is turned off (when the input signal falls). As a result, the high-voltage MOS transistor 104A is turned on. As a result, the connection node with the resistor element 110A becomes an "L" level, and the inverter 116A outputs an "H" level. That is, the RS flip-flop 106A is reset to "0".

[0064] With this configuration, the data D3 input to the on / off one-shot pulse circuit 100A is level-shifted to a high potential and stored in the RS flip-flop 106A. The RS flip-flop 106A outputs the stored data signal from the terminal D3OUT.

[0065] The on-off one-shot pulse circuit 100B outputs a one-shot pulse when the data D2 is turned on / off (when the input signal rises / falls). The on-off one-shot pulse circuit 100B outputs a one-shot pulse to the gate of the high-withstand voltage MOS transistor 102B when turned on (when the input signal rises). The on-off one-shot pulse circuit 100B outputs a one-shot pulse to the gate of the high-withstand voltage MOS transistor 104B when turned off (when the input signal falls). Node N0 is connected to terminal VB. The floating power supply 120 is connected between terminal VB and terminal VS. Terminal VSS connected to the ground potential GND is connected to node N1. High-withstand voltage MOS transistors 102B and 104B are connected in parallel between node N0 and node N1. Resistor element 108B is provided between the source side of the high-withstand voltage MOS transistor 102B and node N0. Resistor element 110B is provided between the source side of the high-withstand voltage MOS transistor 104B and node N0. The anode side of the diode 112B is connected to the terminal VS which is the intermediate potential, and the cathode side is connected to the connection node between the resistor element 108B and the high withstand voltage MOS transistor 102B. The anode side of the diode 118B is connected to the terminal VS which is the intermediate potential, and the cathode side is connected to the connection node between the resistor element 110B and the high withstand voltage MOS transistor 104B.

[0066] When the high withstand voltage MOS transistor 102B is turned off, the potential of the connection node between the resistor element 108B and the high withstand voltage MOS transistor 102B is set to a high potential. Therefore, the output signal of the inverter 114B is set to an "L" level. Similarly, when the high withstand voltage MOS transistor 104B is turned off, the potential of the connection node between the resistor element 110B and the high withstand voltage MOS transistor 104B is set to a high potential. Therefore, the output signal of the inverter 116B is set to an "L" level.

[0067] When the high-voltage MOS transistor 102B is driven (turned on), the potential of the connection node between the resistor element 108B and the high-voltage MOS transistor 102B decreases. In association with this, the output signal of the inverter 114B is set to the "H" level. Similarly, when the high-voltage MOS transistor 104B is driven (turned on), the potential of the connection node between the resistor element 110B and the high-voltage MOS transistor 104B decreases. Therefore, the output signal of the inverter 116B is set to the "H" level.

[0068] The on-off one-shot pulse circuit 100B outputs a one-shot pulse when the data D2 is turned on (when the input signal rises). As a result, the high-voltage MOS transistor 102B is turned on. As a result, the connection node with the resistor element 108B becomes an "L" level, and the inverter 114B outputs an "H" level. That is, the RS flip-flop is set to "1". The on-off one-shot pulse circuit 100B outputs a one-shot pulse when the data D2 is turned off (when the input signal falls). As a result, the high-voltage MOS transistor 104B is turned on. As a result, the connection node with the resistor element 110B becomes an "L" level, and the inverter 116B outputs an "H" level. That is, the RS flip-flop is reset to "0".

[0069] With this configuration, the data D2 input to the on / off one-shot pulse circuit 100B is level-shifted to a high potential and stored in the RS flip-flop 106B. The RS flip-flop 106B outputs the stored data signal from the terminal D2OUT.

[0070] The on-off one-shot pulse circuit 100C outputs a one-shot pulse when the data D1 is turned on / off (when the input signal rises / falls). The on-off one-shot pulse circuit 100C outputs a one-shot pulse to the gate of the high-withstand voltage MOS transistor 102C when turned on (when the input signal rises). The on-off one-shot pulse circuit 100C outputs a one-shot pulse to the gate of the high-withstand voltage MOS transistor 104C when turned off (when the input signal falls). Node N0 is connected to terminal VB. The floating power supply 120 is connected between terminal VB and terminal VS. Terminal VSS connected to the ground potential GND is connected to node N1. High-withstand voltage MOS transistors 102C and 104C are connected in parallel between node N0 and node N1. Resistor element 108C is provided between the source side of the high-withstand voltage MOS transistor 102C and node N0. Resistor element 110C is provided between the source side of the high-withstand voltage MOS transistor 104C and node N0. The anode side of the diode 112C is connected to the terminal VS at the intermediate potential, and the cathode side is connected to the connection node between the resistor element 108C and the high withstand voltage MOS transistor 102C. The anode side of the diode 118C is connected to the terminal VS at the intermediate potential, and the cathode side is connected to the connection node between the resistor element 110C and the high withstand voltage MOS transistor 104C.

[0071] When the high-voltage MOS transistor 102C is turned off, the potential of the connection node between the resistor element 108C and the high-voltage MOS transistor 102C is set to a high potential. Therefore, the output signal of the inverter 114C is set to an "L" level. Similarly, when the high-voltage MOS transistor 104C is turned off, the potential of the connection node between the resistor element 110C and the high-voltage MOS transistor 104C is set to a high potential. Therefore, the output signal of the inverter 116C is set to an "L" level.

[0072] When the high-voltage MOS transistor 102C is driven (turned on), the potential of the connection node between the resistor element 108C and the high-voltage MOS transistor 102C decreases. In association with this, the output signal of the inverter 114C is set to the "H" level. Similarly, when the high-voltage MOS transistor 104C is driven (turned on), the potential of the connection node between the resistor element 110C and the high-voltage MOS transistor 104C decreases. Therefore, the output signal of the inverter 116C is set to the "H" level.

[0073] The on-off one-shot pulse circuit 100C outputs a one-shot pulse when the data D1 is turned on (when the input signal rises). As a result, the high-voltage MOS transistor 102C is turned on. As a result, the connection node with the resistor element 108C becomes an "L" level, and the inverter 114C outputs an "H" level. That is, the RS flip-flop is set to "1". The on-off one-shot pulse circuit 100C outputs a one-shot pulse when the data D1 is turned off (when the input signal falls). As a result, the high-voltage MOS transistor 104C is turned on. As a result, the connection node with the resistor element 110C becomes an "L" level, and the inverter 116C outputs an "H" level. That is, the RS flip-flop is reset to "0".

[0074] With this configuration, the data D1 input to the on / off one-shot pulse circuit 100C is level-shifted to a high potential and stored in the RS flip-flop 106C. The RS flip-flop 106C outputs the stored data signal from the terminal D1OUT.

[0075] Figure 5 This is a diagram for explaining the setting information stored in the controller (MCU) 2 according to the first embodiment. Figure 5 A driving force table is provided in the memory of the controller (MCU) 2. For example, a plurality of setting value data for defining the driving capabilities of the drivers of the high potential side output capability variable gate device HVIC (upper gate) and the low potential side output capability variable gate device LVIC (lower gate) are stored.

[0076] In this example, the set value data of the driving capability of the driver stores data P1 and P2 for the driver on the upper arm side, and stores data P3 and P4 for the driver on the lower arm side.

[0077] Furthermore, although “other 1” that specifies other capabilities in addition to the driving capabilities of the driver is exemplified, this is not particularly limited in this embodiment.

[0078] The controller 2 uses the driving force table to read data as needed, and stores the data in the shift register section 22 of the high potential side output capability variable gate device HVIC (upper gate) and the shift register section 38 of the low potential side output capability variable gate device LVIC (lower gate).

[0079] Thereby, the driving capabilities of the driver 12 and the driver 30 can be made variable.

[0080] On the other hand, as described above, there may be a period (dV / dt period) in which the voltage in the high voltage region in the driving device driving the complementarily driven power transistor changes rapidly and a negative potential period due to undershoot.

[0081] During this period, the voltage level conversion (level shift circuit) for signal transmission of the set value for setting the driving capability cannot achieve signal transmission, and the driving capability setting cannot become a normal value.

[0082] The write signal generating section 24 according to Embodiment 1 adjusts the output timing of the write signal TM1 according to the high potential side driving signal. The above-mentioned problem can be avoided by performing signal transmission according to the timing of the write signal TM1.

[0083] Figure 6 FIG. 2 is a diagram for explaining a timing chart of output of a write signal TM1 according to the first embodiment. Figure 6 At time T0, when the enable signal falls (or rises), the recorded contents of the multiple triggers of the shift register unit 22 are extracted and recorded in the low-voltage side setting value storage unit 20, and then at time T1, the low-potential side drive signal of the input terminal LIN falls.

[0084] At time T2, a gate signal of “L” level is output from the output terminal LO, and the power transistor Q2 is turned off.

[0085] Next, at time T3, the high potential side drive signal of the input terminal HIN rises complementarily. Next, at time T4, a gate signal of "H" level is output from the output terminal HO, and the power transistor Q1 is turned on.

[0086] Along with this, the potential of the connection node between the power transistor Q1 and the power transistor Q2 rises during the period from time T5 to time T6. Along with this, a period (dV / dt period) occurs during which the voltage of the high voltage region HVR of the high potential side output capacity variable gate device HVIC changes rapidly. During this period, signal transmission may not be achieved in the voltage level conversion (level shift circuit), and normal setting may not be performed.

[0087] Therefore, in the first embodiment, at time T7 after the period of rapid change, write signal generating section 24 causes write signal TM1 to rise.

[0088] Thus, the data signals (D1 to D3) stored in the low voltage setting value storage unit 20 are stored in the high voltage setting value storage unit 16 via the second level shift unit 18. After being converted into 8-mode signals by the decoder 14, the driving capability of the driver 12 is changed.

[0089] After the high potential side drive signal from the input terminal HIN rises, the write signal generating unit 24 outputs the write signal TM1 after the delay time DL1 until the gate signal from the output terminal HO rises, the delay time DL2 until the power transistor Q1 is turned on, and the voltage change (dV / dt) of the high voltage region HVR caused by the power transistor Q1 being turned on. Thus, it is possible to avoid the period during which the voltage level conversion (level shift circuit) cannot achieve signal transmission and record it in the high voltage side setting value storage unit 16. After the high potential side drive signal from the input terminal HIN rises, the write signal generating unit 24 outputs the write signal TM1 after a prescribed period. The prescribed period is set to be a period longer than the total period of the delay times DL1, DL2 and the prescribed period of change (dV / dt).

[0090] Figure 7 This is another diagram for explaining the timing chart of the output of the write signal TM1 according to the first embodiment. Figure 7 At time T0, the recorded contents of the multiple triggers of the shift register unit 22 are extracted and recorded in the low-voltage side setting value storage unit 20 at the timing of the fall (or rise) of the enable signal, and then, at time T11, the high-potential side drive signal of the input terminal HIN falls.

[0091] At time T12, a gate signal of “L” level is output from the output terminal HO, and the power transistor Q1 is turned off.

[0092] Next, at time T13, the low potential side drive signal of the input terminal LIN rises complementarily. Next, at time T14, a gate signal of "H" level is output from the output terminal LO, and the power transistor Q2 is turned on.

[0093] Along with this, the potential of the connection node between the power transistor Q1 and the power transistor Q2 drops sharply during the period from time T15 to time T16. Along with this, a period (VS negative potential period) occurs during which the voltage of the high voltage region HVR of the high potential side output capacity variable gate device HVIC changes sharply. During this period, the voltage of the high voltage region HVR is a negative voltage, so signal transmission may not be achieved in the voltage level conversion (level shift circuit), and normal setting may not be performed.

[0094] Therefore, in the first embodiment, at time T17 after the period in which the voltage of the high voltage region HVR of the high potential side output capability variable gate device HVIC becomes a negative voltage, the write signal generating section 24 raises the write signal TM1 .

[0095] Thus, the data signals (D1 to D3) stored in the low voltage setting value storage unit 20 are stored in the high voltage setting value storage unit 16 via the second level shift unit 18. After being converted into 8-mode signals by the decoder 14, the driving capability of the driver 12 is changed.

[0096] The write signal generating unit 24 outputs the write signal TM1 after the high potential side drive signal falls, the delay time DL3 until the gate signal from the output terminal HO falls, the dead time (DEAD TIME) set so that the power transistors Q1 and Q2 are not turned on at the same time, the delay time DL4 from the rise of the low potential side drive signal to the rise of the gate signal from the output terminal LO, the delay time DL5 until the power transistor Q2 is turned on, and the period when the high voltage region HVR generated by the power transistor Q2 turning on becomes a negative voltage. Thus, it is possible to avoid the period in which the voltage level conversion (level shift circuit) cannot perform signal transmission and record it in the high voltage side set value storage unit 16. The write signal generating unit 24 outputs the write signal TM1 after a predetermined period after the high potential side drive signal from the input terminal HIN falls. The predetermined period is set to a period longer than the total period of the delay times DL3, DL4, DL5, the dead time (DEAD TIME) and the VS negative potential period.

[0097] Implementation Method 2

[0098] Figure 8 FIG. 2 is a diagram for explaining the outline of the structure of a semiconductor module according to Embodiment 2. Figure 8The semiconductor module according to the second embodiment is different from the semiconductor module according to the first embodiment in that the signal of the output terminal LO of the low potential side output capability variable gate device LVIC (low potential side drive circuit) is set as the input of the high potential side output capability variable gate device HVIC (high potential side drive circuit). Specifically, the high potential side output capability variable gate device HVIC is newly provided with an input terminal LOS. The input terminal LOS receives the input of the signal of the output terminal LO of the low potential side output capability variable gate device LVIC (low potential side drive circuit).

[0099] In addition, the write signal generating section 24 is changed to a write signal generating section 24A. The write signal generating section 24A outputs a write signal TM1 based on the high potential side drive signal, the low potential side drive signal, and the enable signal.

[0100] Fig. 9 FIG. 2 is a diagram for explaining a timing chart of output of a write signal TM1 according to the second embodiment. Fig. 9 At time T20, the recorded contents of the multiple triggers of the shift register unit 22 are extracted and recorded in the low-voltage side setting value storage unit 20 at the timing of the fall (or rise) of the enable signal, and then, at time T21, the high-potential side drive signal of the input terminal HIN falls.

[0101] At time T22, a gate signal of “L” level is output from the output terminal HO, and the power transistor Q1 is turned off.

[0102] Next, at time T23, the low potential side drive signal of the input terminal LIN rises complementarily. Next, at time T24, a gate signal of "H" level is output from the output terminal LO, and the power transistor Q2 is turned on.

[0103] Along with this, during the period from time T25 to time T26, a period occurs in which the voltage of the high voltage region HVR of the high potential side output capacity variable gate device HVIC becomes a negative voltage.

[0104] In this example, at time T27 after the period of the negative voltage, write signal generating section 24A causes write signal TM1 to rise.

[0105] Thus, the data signals (D1 to D3) stored in the low voltage setting value storage unit 20 are stored in the high voltage setting value storage unit 16A via the second level shift unit 18A. After being converted into 8-mode signals by the decoder 14, the driving capability of the driver 12 is changed.

[0106] The write signal generating unit 24A outputs the write signal TM1 after the delay time DL5 from the rise of the gate signal output from the output terminal LO until the power transistor Q2 is turned on, and the high voltage region HVR generated by the power transistor Q2 turning on becomes a negative voltage. Thus, it is possible to avoid the period during which the voltage level conversion (level shift circuit) cannot perform signal transmission and record it in the high voltage side setting value storage unit 16. The write signal generating unit 24 outputs the write signal TM1 after a predetermined period after the rise of the low potential side drive signal from the input terminal LOS. The predetermined period is set to a period longer than the total period of the delay time DL5 and the VS negative potential period.

[0107] In addition, regarding the rise of the high potential side drive signal, Figure 6 The contents described are the same.

[0108] With the configuration according to the second embodiment, it is possible to more accurately avoid the period during which the voltage level conversion (level shift circuit) cannot perform signal transmission and record the signal in the high voltage side set value storage unit 16 .

[0109] Implementation 3

[0110] Fig.10 FIG. 2 is a diagram for explaining the outline of the structure of a semiconductor module according to Embodiment 3. Fig.10 The semiconductor module involved in the third embodiment is different from the semiconductor module involved in the second embodiment in that the write signal TM1 of the high potential side output capability variable gate device HVIC (high potential side drive circuit) is set as the input of the low potential side output capability variable gate device LVIC (low potential side drive circuit). Specifically, the high potential side output capability variable gate device HVIC newly sets the output terminal TOUT. In addition, the low potential side output capability variable gate device LVIC newly sets the input terminal TIN. The input terminal TIN receives the input of the write signal TM1 via the output terminal TOUT of the high potential side output capability variable gate device HVIC (high potential side drive circuit).

[0111] The low potential side output capability variable gate device LVIC has a two-layer structure of the setting value storage unit. Specifically, the setting value storage unit 36 ​​is replaced with a first setting value storage unit 36A and a second setting value storage unit 36B.

[0112] The first set value storage unit 36A stores the information stored in the shift register unit 38 in response to the enable signal.

[0113] The second set value storage unit 36B further stores the information stored in the first set value storage unit 36A in accordance with the write signal TM1.

[0114] With this configuration, the setting value information of the low potential side output capability variable gate device LVIC is updated at the same timing as the setting value information of the high potential side output capability variable gate device HVIC (high potential side drive circuit) is updated according to the write signal TM1.

[0115] In the structures involved in the above-mentioned embodiments 1 and 2, there is a situation where only the information of the setting value of the low-potential side output capability variable gate device LVIC is updated, but with the structure involved in this embodiment 3, the information of the setting value is updated by the same write signal TM1, so the adjustment of the driving capability can be performed at the same time, and the change can be efficient.

[0116] Implementation 4

[0117] Fig.11 FIG. 2 is a diagram for explaining the outline of the structure of a semiconductor module according to Embodiment 4. Fig.11 The semiconductor module according to the fourth embodiment is different from the semiconductor module according to the third embodiment in that the second level shifter 18 is replaced by a second level shifter 18A. The semiconductor module according to the fourth embodiment is different in that the high voltage side setting value storage unit 16 is replaced by a high voltage side setting value storage unit 16A.

[0118] The second level shifter 18A is composed of a pulse generator 230 and a plurality of high withstand voltage MOS transistors. In this example, four high withstand voltage MOS transistors are included.

[0119] Fig.12 FIG. 2 is a diagram for explaining the configuration of the high voltage side set value storage unit 16A and the second level shift unit 18A according to the fourth embodiment. Fig.12 The high voltage side set value storage unit 16A includes a plurality of flip-flops (DT-FF) 205A to 205C.

[0120] The second level shifter 18A includes a pulse generator 230 , a delay circuit 220 , voltage-resistant MOS transistors 202A to 202D, inverters 204 , 214A to 214C, diodes 212A to 212D, resistors 210A to 210D, and AND circuits 201A to 201C.

[0121] The pulse generating unit 230 generates and outputs a one-shot pulse signal using the write signal TM1 as a trigger, and the delay circuit 220 outputs a signal obtained by delaying the one-shot pulse signal to the gate of the withstand voltage MOS transistor 202A.

[0122] The AND circuit 201A outputs an AND logic operation result based on the single pulse signal generated by the pulse generating unit 230 and the data D3 stored in the low voltage side set value storing unit 20 to the gate of the withstand voltage MOS transistor 202B.

[0123] Node N0 is connected to terminal VB. Floating power supply 120 is connected between terminal VB and terminal VS. Terminal VSS connected to ground potential GND is connected to node N1. High withstand voltage MOS transistors 202A and 202B are connected in parallel between node N0 and node N1. Resistor 210A is arranged between the source side of high withstand voltage MOS transistor 202A and node N0. Resistor 210B is arranged between the source side of high withstand voltage MOS transistor 202B and node N0. The anode side of diode 212A is connected to terminal VS which becomes an intermediate potential, and the cathode side is connected to the connection node between resistor 210A and high withstand voltage MOS transistor 202A. The anode side of diode 212B is connected to terminal VS which becomes an intermediate potential, and the cathode side is connected to the connection node between resistor 210B and high withstand voltage MOS transistor 202B.

[0124] The AND circuit 201B outputs an AND logic operation result based on the single pulse signal generated by the pulse generating unit 230 and the data D2 stored in the low voltage side set value storing unit 20 to the gate of the withstand voltage MOS transistor 202C.

[0125] The high withstand voltage MOS transistors 202C and 202D are connected in parallel between the node N0 and the node N1. The resistor element 210C is provided between the source side of the high withstand voltage MOS transistor 202C and the node N0. The resistor element 210D is provided between the source side of the high withstand voltage MOS transistor 202D and the node N0. The anode side of the diode 212C is connected to the terminal VS which becomes the intermediate potential, and the cathode side is connected to the connection node between the resistor element 210C and the high withstand voltage MOS transistor 202C. The anode side of the diode 212D is connected to the terminal VS which becomes the intermediate potential, and the cathode side is connected to the connection node between the resistor element 210D and the high withstand voltage MOS transistor 202D.

[0126] When the high-voltage MOS transistor 202C is turned off, the potential of the connection node between the resistor element 210C and the high-voltage MOS transistor 202C is set to a high potential. Therefore, the output signal of the inverter 214B is set to an "L" level. When the high-voltage MOS transistor 202C is driven (turned on), the potential of the connection node between the resistor element 210C and the high-voltage MOS transistor 202C decreases. Along with this, the output signal of the inverter 214B is set to an "H" level.

[0127] When the high withstand voltage MOS transistor 202D is turned off, the potential of the connection node between the resistor element 210D and the high withstand voltage MOS transistor 202D is set to a high potential. Therefore, the output signal of the inverter 214C is set to an "L" level. When the high withstand voltage MOS transistor 202D is driven (turned on), the potential of the connection node between the resistor element 210D and the high withstand voltage MOS transistor 202D decreases. Along with this, the output signal of the inverter 214C is set to an "H" level.

[0128] The AND circuit 201C outputs an AND logic operation result obtained based on the single pulse signal generated by the pulse generating unit 230 and the data D1 stored in the low voltage side set value storing unit 20 to the gate of the withstand voltage MOS transistor 202D.

[0129] The high withstand voltage MOS transistors 202B to 202D are driven based on the one-shot pulse of the pulse generating unit 230 and the data D3 to D1 stored in the low voltage side set value storage unit 20. In addition, the signal that becomes the trigger of the flip-flops 205A to 205C is driven according to the delay signal of the delay circuit 220. Therefore, data "1" or "0" is set in the flip-flops 205A to 205C based on the data D3 to D1.

[0130] With this configuration, the data D3 to D1 input to the second level shifter 18A are level-shifted to a high potential and stored in the flip-flops 205A to 205C. The flip-flops 205A to 205C output the stored data signals from the terminals D3OUT to D1OUT.

[0131] On the other hand, in the case of the structure of the high voltage side set value storage unit 16A according to the fourth embodiment, it can be composed of four high withstand voltage MOS transistors. The number of high withstand voltage MOS transistors is reduced, the number of components is reduced, and the layout structure is also simplified.

[0132] In this example, a three-bit structure is described, but the structure can be simplified even when the number of bits is increased to multiple bits.

[0133] Implementation method 5

[0134] Fig.13 FIG. 2 is a diagram for explaining the outline of the structure of a semiconductor module according to Embodiment 5. Fig.13The semiconductor module involved in the fifth embodiment is different from the semiconductor module involved in the fourth embodiment in that the structures of the second level shifter 18A and the high voltage side setting value storage unit 16A are changed. Specifically, the difference is that the high voltage side setting value storage unit 16A is replaced by the high voltage side setting value storage unit 16B, and the number of bits is changed to an 8-bit structure. Eight DT flip-flops are provided. The difference is that the second level shifter 18A is replaced by the second level shifter 18B. The second level shifter 18B includes a high voltage side shift register unit 17.

[0135] Furthermore, a clock generating section 19 that generates an internal clock INCK, a low-voltage side shift register section 21 that operates according to the internal clock INCK of the clock generating section 19 , and a counter 15 are provided.

[0136] In addition, the difference is that the variable gate device LVIC for the low potential side output capability is also expanded from 3 bits to 8 bits. The write signal generating unit 24A outputs the write signal TM1 to the clock generating unit 19. The clock generating unit 19 generates the internal clock INCK according to the write signal TM1. The low voltage side shift register unit 21 sequentially stores the data signal stored in the low voltage side setting value storing unit 20 according to the internal clock INCK, and forwards it to the high voltage side shift register unit 17 as the forwarding signal D.

[0137] The high-voltage side shift register section 17 receives the input of the signal after the level conversion via the high withstand voltage MOS transistor. Specifically, the high-voltage side shift register section 17 receives and stores the input of the signal after the level conversion of the forwarding signal D according to the internal clock INCK. The information stored in the low-voltage side shift register section 21 is transferred to the high-voltage side shift register section 17 according to the internal clock INCK.

[0138] The counter 15 counts the internal clock INCK and outputs a control signal CT at a predetermined counting timing.

[0139] Specifically, until all the information stored in the low-voltage side setting value storage unit 20 is transferred from the low-voltage side shift register unit 21 to the high-voltage side shift register unit 17, the number of counts of the internal clock INCK needs to be 8. The counter 15 outputs the control signal CT when the internal clock INCK is counted 8 times. The 8 DT flip-flops of the high-voltage side setting value storage unit 16B store the information of the high-voltage side shift register unit 17 according to the control signal CT.

[0140] The low potential side output capability variable gate device LVIC has a two-layer structure of the setting value storage unit. Specifically, the setting value storage unit 36 ​​is replaced by a first setting value storage unit 36A and a second setting value storage unit 36B.

[0141] The first set value storage unit 36A stores the information stored in the shift register unit 38 in accordance with the enable signal. The second set value storage unit 36B further stores the information stored in the first set value storage unit 36A in accordance with the control signal CT.

[0142] With this structure, even when the number of bits is expanded, there is no need to increase the number of high-voltage MOS transistors, and the number of high-voltage MOS transistors can be reduced, the number of components can be reduced, and the layout structure can also be simplified.

[0143] Fig.14 This is a diagram for explaining the configuration of the high voltage side set value storage unit 16B, the second level shift unit 18B, and the low voltage side shift register unit 21 according to the fifth embodiment. Fig.14 The high voltage side set value storage unit 16B has a plurality of flip-flops 203, 204, ... .

[0144] The second level shifter 18B includes a high-side shift register section 17, high-withstand voltage MOS transistors 202A to 202C, diodes 212A to 212C, resistors 210A to 210C, and inverters 214A to 214C.

[0145] The low-voltage side shift register section 21 has a plurality of flip-flops 240, 241, ... connected in cascade connection. The plurality of flip-flops 240, 241, ... receive the input of the internal clock INCK and sequentially forward the stored data to the flip-flops of the subsequent stage. In this example, the low-voltage side shift register section 21 has 8 flip-flops, and sequentially outputs the stored data as the forwarding signal D to the high-voltage side shift register section 17 according to the input of the internal clock INCK.

[0146] The forwarding signal D is input to the gate of the high withstand voltage MOS 202C. The internal clock INCK is input to the gate of the high withstand voltage MOS 202B. The control signal CT of the counter 15 is input to the gate of the high withstand voltage MOS 202A. The node N0 is connected to the terminal VB. The floating power supply 120 is connected between the terminal VB and the terminal VS. The terminal VSS connected to the ground potential GND is connected to the node N1. The high withstand voltage MOS transistors 202A, 202B, and 202C are connected in parallel between the node N0 and the node N1. The resistance element 210A is arranged between the source side of the high withstand voltage MOS transistor 202A and the node N0. The resistance element 210B is arranged between the source side of the high withstand voltage MOS transistor 202B and the node N0. The resistance element 210C is arranged between the source side of the high withstand voltage MOS transistor 202C and the node N0. The anode side of the diode 212A is connected to the terminal VS at the intermediate potential, and the cathode side is connected to the connection node between the resistor 210A and the high withstand voltage MOS transistor 202A. The inverter 214A outputs a clock input to the high voltage side set value storage unit 16B according to the signal of the connection node.

[0147] The anode side of the diode 212B is connected to the terminal VS which becomes the intermediate potential, and the cathode side is connected to the connection node between the resistor element 210B and the high withstand voltage MOS transistor 202B. The inverter 214B outputs the clock input of the high-voltage side shift register section 17 according to the signal of the connection node. The anode side of the diode 212C is connected to the terminal VS which becomes the intermediate potential, and the cathode side is connected to the connection node between the resistor element 210C and the high withstand voltage MOS transistor 202C. The inverter 214C outputs the data input of the high-voltage side shift register section 17 according to the signal of the connection node.

[0148] With this configuration, the data D sequentially transferred from the low-voltage side shift register section 21 is level-shifted to a high potential and transferred to the high-voltage side shift register section 17 .

[0149] The high-voltage side shift register section 17 sequentially stores the transfer signal D sequentially transferred from the low-voltage side shift register section 21 in eight flip-flops in accordance with the internal clock INCK and the transfer signal D.

[0150] The data stored in the high-voltage side shift register section 17 is stored in the high-voltage side set value storage section 16B in accordance with the control signal CT of the counter 15 .

[0151] In addition, although the structure of 8 bits is described in this example, the structure is also simplified when the number of bits is further expanded to multiple bits.

[0152] Fig.15FIG. 2 is a diagram for explaining a timing chart of output of a write signal TM1 according to Embodiment 5. Fig.15 At time T30, the recorded contents of the multiple triggers of the shift register unit 22 are extracted and recorded in the low-voltage side setting value storage unit 20 at the timing of the fall (or rise) of the enable signal, and then, at time T31, the low-potential side drive signal of the input terminal LIN falls.

[0153] At time T32, a gate signal of “L” level is output from the output terminal LO, and the power transistor Q2 is turned off.

[0154] Next, at time T33, the high potential side drive signal of the input terminal HIN rises complementarily. Next, at time T34, a gate signal of "H" level is output from the output terminal HO, and the power transistor Q1 is turned on.

[0155] Along with this, the potential of the connection node between the power transistor Q1 and the power transistor Q2 rises during the period from time T35 to time T36. Along with this, a period (dV / dt period) occurs during which the voltage of the high voltage region HVR of the high potential side output capacity variable gate device HVIC changes rapidly. During this period, signal transmission may not be achieved in the voltage level conversion (level shift circuit), and normal setting may not be performed.

[0156] Therefore, in the fifth embodiment, at time T37 after the period of rapid change, write signal generating section 24 causes write signal TM1 to rise.

[0157] The clock generating unit 19 outputs the internal clock INCK at time T38 in response to the input of the write signal TM1. In response to this, the low-voltage side shift register unit 21 transfers the transfer signal D to the high-voltage side shift register unit 17 in response to the internal clock INCK. The high-voltage side shift register unit 17 sequentially stores the transfer signal D in response to the internal clock INCK.

[0158] The counter 15 counts the internal clock INCK and outputs the control signal CT after counting eight times at time T39. The high voltage side set value storage unit 16B stores the data stored in the high voltage side shift register unit 17 in the flip-flop according to the control signal CT.

[0159] Thus, the data signals (D1 to D8) stored in the low voltage side setting value storage unit 20 are stored in the high voltage side setting value storage unit 16 via the low voltage side shift register unit 21 and the high voltage side shift register unit 17. Then, after being converted into a 256-mode signal by the decoder 14, the driving capability of the driver 12 is changed.

[0160] The write signal generating unit 24 outputs the write signal TM1 after the rise of the high potential side drive signal from the input terminal HIN, after the delay time DL1 until the gate signal from the output terminal HO rises, the delay time DL2 until the power transistor Q1 is turned on, and the voltage change (dV / dt) of the high voltage region HVR caused by the power transistor Q1 being turned on. Thus, it is possible to avoid the period during which the voltage level conversion (level shift circuit) cannot achieve signal transmission and record it in the high voltage side setting value storage unit 16B. The write signal generating unit 24 outputs the write signal TM1 after the predetermined period after the rise of the high potential side drive signal from the input terminal HIN. The predetermined period is set to be a period longer than the total period of the delay times DL1, DL2 and the predetermined period of change (dV / dt).

[0161] Fig.16 This is another diagram for explaining the timing chart of the output of the write signal TM1 according to the fifth embodiment. Fig.16 At time T40, the recorded contents of the multiple triggers of the shift register unit 22 are extracted and recorded in the low-voltage side setting value storage unit 20 at the timing of the fall (or rise) of the enable signal, and then, at time T41, the high-potential side drive signal of the input terminal HIN falls.

[0162] At time T42, a gate signal of "L" level is output from the output terminal HO, and the power transistor Q1 is turned off. Next, at time T43, the low potential side drive signal of the input terminal LIN rises complementarily. Next, at time T44, a gate signal of "H" level is output from the output terminal LO, and the power transistor Q2 is turned on.

[0163] Along with this, the potential of the connection node between the power transistor Q1 and the power transistor Q2 drops sharply during the period from time T45 to time T46. Along with this, a period (VS negative potential period) during which the voltage of the high voltage region HVR of the high potential side output capacity variable gate device HVIC changes sharply occurs. During this period, since the voltage of the high voltage region HVR is a negative voltage, signal transmission may not be achieved in the voltage level conversion (level shift circuit), and normal setting may not be performed.

[0164] Therefore, in the fifth embodiment, at time T47 after the period in which the voltage of the high voltage region HVR of the high potential side output capability variable gate device HVIC becomes a negative voltage, the write signal generating section 24 causes the write signal TM1 to rise.

[0165] The clock generating unit 19 outputs the internal clock INCK at time T48 in response to the input of the write signal TM1. In response to this, the low-voltage side shift register unit 21 transfers the transfer signal D to the high-voltage side shift register unit 17 in response to the internal clock INCK. The high-voltage side shift register unit 17 sequentially stores the transfer signal D in response to the internal clock INCK.

[0166] The counter 15 counts the internal clock INCK and outputs the control signal CT after counting eight times at time T49. The high voltage side set value storage unit 16B stores the data stored in the high voltage side shift register unit 17 in the flip-flop according to the control signal CT.

[0167] Thus, the data signals (D1 to D8) stored in the low voltage side setting value storage unit 20 are stored in the high voltage side setting value storage unit 16 via the low voltage side shift register unit 21 and the high voltage side shift register unit 17. Then, after being converted into a 256-mode signal by the decoder 14, the driving capability of the driver 12 is changed.

[0168] The write signal generating unit 24A outputs the write signal TM1 after the delay time DL5 from the rise of the gate signal outputted from the output terminal LO to the turn-on of the power transistor Q2, and the period during which the high voltage region HVR generated by the turn-on of the power transistor Q2 becomes a negative voltage. Thus, it is possible to avoid the period during which the voltage level conversion (level shift circuit) cannot perform signal transmission and record it in the high voltage side setting value storage unit 16. The write signal generating unit 24A outputs the write signal TM1 after a predetermined period after the rise of the low potential side drive signal from the input terminal LOS. The predetermined period is set to a period longer than the total period of the delay time DL5 and the negative potential period of VS.

[0169] According to the structure involved in the fifth embodiment, even when the number of bits is increased, the number of high-voltage MOS transistors is reduced, the number of components is reduced, and the layout structure is also simplified.

[0170] Implementation 6

[0171] Fig.17 FIG. 2 is a diagram for explaining the outline of the structure of a semiconductor module according to Embodiment 6. Fig.17 The semiconductor module according to the sixth embodiment is different from the semiconductor module according to the first embodiment in that the power transistors (switching elements) Q1 and Q2 are replaced with SiC-MOSFETs QA1 and QA2.

[0172] The other structures are the same. It can also be applied to SiC-MOSFET. Although the Vth fluctuation of SiC-MOSFET is large and the individual fluctuation of output characteristics is also large, by adjusting the output capacity of the driver by using the structure involved in the above-mentioned embodiment, the fluctuation as a semiconductor module can be suppressed. In addition, it can also be applied to other embodiments.

[0173] For each embodiment disclosed this time, it is also envisioned that it can be appropriately combined and implemented within the scope of non-contradiction. It should be considered that the embodiments disclosed this time are illustrative in all aspects, rather than restrictive. The scope of the present invention is not indicated by the above description but by the claims, and is intended to include all changes within the meaning and scope equivalent to the claims.

Claims

1. A semiconductor module comprising: a first switching element and a second switching element connected in series between a first potential and a second potential lower than the first potential and operating in a complementary manner; a high potential side driving circuit including a first driver connected to a first gate of the first switching element and capable of adjusting an output to the first gate; as well as a low potential side driving circuit including a second driver connected to a second gate of the second switching element and capable of adjusting an output to the second gate, The high potential side driving circuit comprises: Terminals, which respectively receive data communication signals sent from an external controller, namely, a drive signal, a data signal, a clock signal, and an enable signal; a first level shifter that performs level shifting on the driving signal toward a high potential and outputs the driving signal to the first driver; a first shift register, which is composed of a plurality of flip-flops connected in cascade, records a data signal in the flip-flops according to the clock signal and the enable signal, and moves the recorded data to an adjacent flip-flop each time the data signal is stored in the flip-flop; a low voltage side set value storage unit that extracts and records the recorded contents of the plurality of flip-flops of the first shift register according to the enable signal; a write signal generating unit that generates a write signal based on the drive signal and the enable signal; a second level shifting unit for level-shifting the stored information of the low voltage side set value storing unit to a high potential according to the write signal; a high voltage side set value storage unit connected via the second level shift unit and recording the same information as the information recorded in the low voltage side set value storage unit; and The first decoder is configured to make the output current capacity of the first driver variable according to the record of the high voltage side set value storage unit.

2. The semiconductor module according to claim 1, wherein: The write signal generating unit activates the write signal after a predetermined period of time has elapsed in response to a rise or fall of the drive signal.

3. The semiconductor module according to claim 2, wherein: The write signal generating section receives the output of the drive signal of the low potential side drive circuit, and makes the write signal active based on the output of the drive signal.

4. The semiconductor module according to claim 1, wherein: The low potential side driving circuit comprises: Terminals, which respectively receive data communication signals sent from an external controller, namely, a second drive signal, a second data signal, a second clock signal, and a second enable signal; a second shift register, which is composed of a plurality of flip-flops connected in cascade, and records a second data signal in the flip-flops according to the second clock signal and the second enable signal, and shifts the recorded data to an adjacent flip-flop each time the second data signal is stored in the flip-flops; a first set value storage unit that extracts and records the recorded contents of the plurality of flip-flops of the second shift register according to the second enable signal; a second setting value storage unit that records the same information as that of the first setting value storage unit in response to the write signal; and A second decoder is used to make the output current capacity of the second driver variable according to the record of the second setting value storage unit.

5. The semiconductor module according to claim 1, wherein: The second level shifter includes: a pulse generating unit that outputs the stored information of the low voltage side setting value storing unit as a one-shot pulse signal according to the write signal; as well as a plurality of high withstand voltage transistors driven according to the outputs of the pulse generating units, The high-voltage side set value storage unit includes a plurality of flip-flop circuits connected to the high withstand voltage transistor, and the plurality of flip-flop circuits record the same information as that of the low-voltage side set value storage unit.

6. The semiconductor module according to claim 1, wherein: The invention also comprises a low-voltage side shift register, which is composed of a plurality of flip-flops connected in cascade, and records the data signal of the low-voltage side setting value storage unit in the flip-flop according to an internal clock signal, and moves the recorded data to an adjacent flip-flop each time the data signal is stored in the flip-flop. The second level shifter includes: A high-voltage side shift register, which is composed of a plurality of flip-flops connected in cascade, and records the data signal of the low-voltage side shift register in the flip-flop according to the internal clock signal, and whenever the data signal is stored in the flip-flop, the recorded data is moved to an adjacent flip-flop; as well as A plurality of high withstand voltage transistors are arranged between the low voltage side shift register and the high voltage side shift register, and are driven according to the internal clock signal and the data signal of the low voltage side shift register.

7. The semiconductor module according to any one of claims 1 to 6, wherein: The first switching element and the second switching element correspond to SiC MOSFETs.

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