Gate driver circuit, motor driving device using same, and electronic device

Abstract

A gate driver circuit for driving an N-type power transistor constituting a switching circuit includes: a high level line on which a voltage higher than a source of the power transistor is generated; a conduction transistor configured to supply a current to a gate of the power transistor; a turn-off transistor configured to sink a current from a gate of the power transistor; and a control circuit in which the on-transistor includes a plurality of transistors connected between a gate of the power transistor and a high level line, and in which the control circuit controls on / off states of the plurality of transistors such that when the power transistor is on, the on-transistor has a first driving capability in a first period, and when the power transistor is on, the on-transistor has a second driving capability in a second period. A second driving capability lower than the first driving capability is provided in the second period, and a third driving capability higher than the second driving capability is provided in the third period.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based upon and claims the benefit of priority from Japanese patent application No. 2023-159106, filed on September 22, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a gate driver circuit. Background Art

[0004] Half-bridge circuits, H-bridge circuits, and three-phase bridge circuits (hereinafter collectively referred to as bridge circuits) using power transistors are widely used in motor driver circuits, DC / DC converters, power conversion devices, and the like.

[0005] Figure 1 is a circuit diagram of a bridge circuit 10. The bridge circuit 10 includes an upper arm 12 and a lower arm 14 connected in series between a power supply terminal and a ground terminal. The upper arm 12 includes a high-side transistor MH and a freewheeling diode Di connected in parallel. The lower arm 14 includes a low-side transistor ML and a freewheeling diode Di connected in parallel. An inductor (coil) L1 serving as a load is connected to the output terminal of the bridge circuit 10.

[0006] The bridge circuit 10 can take the following states: state φ1, in which both the high-side transistor MH and the low-side transistor ML are off (high impedance state), state φ2, in which the high-side transistor MH is on and the low-side transistor ML is off (high output state), and state φ3, in which the high-side transistor MH is off and the low-side transistor ML is on (low output state). For each of the states φ1 to φ3, there is a current supply state and a current sink state, in which the current I is output from the bridge circuit 10. OUT (current flows to the right in the figure). In the current absorption state, the bridge circuit 10 absorbs the current I OUT (Current flows to the left in the diagram).

[0007] [Prior art literature]

[0008] [Patent Document]

[0009] Patent Document 1: Japanese Patent Publication No. 2018-82575 Summary of the invention

[0010] As a survey Figure 1 As a result of the bridge circuit shown in , the present disclosure has recognized the following problems.

[0011] Consider the transition from the high impedance state φ1 to the high output state φ2 in the current supply state. In state φ1, the output current I OUTThe current is supplied to the load via the flyback diode Di of the lower arm 14 (current supply). The output voltage V in the state φ1 OUT is −Vf. Vf is the forward voltage of the freewheeling diode Di.

[0012] In state φ2, the output current I of the bridge circuit 10 is OUT flows through the high-side transistor MH. In addition, the reverse recovery current I rc The output current I flows from the cathode to the anode in the freewheeling diode Di of the lower arm 14 on the opposite side. OUT and reverse recovery current I rc All flow through the high-side transistor MH. This state is equivalent to through-current flow. When the through-current flows, the output voltage V of the bridge circuit 10 OUT becomes unstable and ringing occurs. Ringing is undesirable because it may cause unwanted radiation.

[0013] In view of the above-mentioned problems, an exemplary object of an embodiment of the present disclosure is to provide a gate driver circuit capable of suppressing a through current and ringing caused by a reverse recovery current of an opposite-side freewheeling diode.

[0014] One aspect of the present disclosure provides a gate driver circuit for driving an N-type power transistor constituting a switching circuit. The gate driver circuit includes a high-level line on which a voltage higher than the source of the power transistor is generated, a turn-on transistor configured to supply current to the gate of the power transistor, a turn-off transistor configured to absorb current from the gate of the power transistor, and a control circuit configured to control the turn-on transistor and the turn-off transistor. The turn-on transistor includes a plurality of transistors connected between the gate of the power transistor and the high-level line. The control circuit controls the on / off state of the plurality of transistors so that when the power transistor is turned on, the turn-on transistor has a first driving capability in a first time period, a second driving capability lower than the first driving capability in a second time period, and a third driving capability higher than the second driving capability in a third time period.

[0015] Any combination of the above-described components and mutual substitution between the components or expressions of the present disclosure in methods, apparatuses, systems, etc. are also effective as aspects of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure.

[0017] Figure 1 It is the circuit diagram of a bridge circuit.

[0018] Figure 2 is a circuit diagram of a switching circuit according to an embodiment.

[0019] Figure 3 is a circuit diagram of a gate driver circuit according to an embodiment.

[0020] Figure 4 yes Figure 3 The operating waveform of the gate driver circuit is shown.

[0021] Figure 5 is a circuit diagram of a driving circuit including a gate driver circuit.

[0022] Figure 6 is a circuit diagram of a conduction circuit according to Modification 1.

[0023] Figure 7 is a circuit diagram of a conduction circuit according to Modification 2.

[0024] Figure 8 It is shown Figure 7 The waveform diagram of the operation (simulation results) of the conducting circuit is shown.

[0025] Fig. 9 is the circuit diagram of the driving circuit.

[0026] Fig.10 is a circuit diagram of a motor driving device including a switching circuit according to an embodiment. DETAILED DESCRIPTION

[0027] Reference will now be made in detail to various embodiments, examples of which are shown in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without these specific details. In other cases, well-known methods, processes, systems, and components are not described in detail in order to avoid unnecessarily obscuring aspects of the various embodiments.

[0028] (Overview of Embodiments)

[0029] An overview of some exemplary embodiments of the present disclosure will be described. This overview is intended to provide a simplified explanation of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a preface to the detailed description below, and is not intended to limit the scope of the present invention or disclosure. For convenience, the term "one embodiment" may be used to refer to one embodiment (example or modification) or multiple embodiments (example or modification) disclosed in this specification.

[0030] This summary is not an exhaustive overview of all conceivable embodiments and is not intended to identify key elements of all embodiments or delineate the scope of some or all aspects. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to a more detailed description that is presented later.

[0031] A gate driver circuit according to one embodiment drives an N-type power transistor constituting a switch circuit. The gate driver circuit includes a high-level line on which a voltage higher than the source of the power transistor is generated, a turn-on transistor configured to supply current to the gate of the power transistor, a turn-off transistor configured to absorb current from the gate of the power transistor, and a control circuit for controlling the turn-on transistor and the turn-off transistor. The turn-on transistor includes a plurality of transistors connected between the gate of the power transistor and the high-level line. The control circuit controls the on / off state of the plurality of transistors so that when the power transistor is turned on, the turn-on transistor has a first capability in a first time period, a second capability lower than the first capability in a second time period, and a third capability higher than the second capability in a third time period.

[0032] The current driving capability (also referred to as driving capability or capability) of the on-state transistor is the sum of the driving capabilities of the transistors in the on-state among the plurality of transistors, and the driving capability of each transistor is defined by W / L (gate width / gate length). In the first to third time periods, the current flowing through the on-state transistor is defined by the driving capability of the on-state transistor.

[0033] According to the above configuration, a driving current having a first current amount is supplied to the gate of the power transistor during a first period until the power transistor is turned on, thereby increasing the gate voltage. Then, after the power transistor is turned on, during a second period in which the reverse recovery current can flow through the freewheeling diode of the relative arm, the driving current supplied to the gate of the power transistor is reduced to slowly turn on the power transistor while keeping the on-resistance of the power transistor large. This makes it possible to suppress the through current and ringing caused by the reverse recovery current of the freewheeling diode of the relative arm. Subsequently, during a third period in which the reverse recovery current is unlikely to flow, the amount of current supplied to the gate increases more than during the second period, thereby shortening the turn-on time of the power transistor and reducing power consumption. In addition, during the first and second periods, the first current mirror circuit operates, and the input current amount of the first current mirror circuit is switched so that when switching to the second period, the current supplied to the gate changes slowly. This makes it possible to further reduce power consumption.

[0034] In one embodiment, the third capability may be higher than the first capability. That is, the current supplied to the gate of the power transistor in the third period may be higher than the current supplied to the gate of the power transistor in the first period and the second period. After the influence of the reverse recovery characteristics of the freewheeling diode of the relative arm becomes smaller, the amount of current supplied to the gate of the power transistor increases, thereby reducing the on-resistance of the power transistor in a short time and improving the efficiency of the bridge circuit.

[0035] In one embodiment, the plurality of transistors may include at least one transistor assigned to the first transistor group and at least one transistor assigned to the second transistor group. The control circuit may fix at least one transistor assigned to the second transistor group to an off state in the second period without changing the on / off state of at least one transistor assigned to the first transistor group in the first period to the third period. In the second period, only the transistors included in the first transistor group may be turned on. Therefore, when the first period is changed to the second period and when the second period is changed to the third period, only one of the turning on and off of the transistor occurs. This makes it possible to suppress the discontinuity of the current.

[0036] In one embodiment, the control circuit can control the on / off state of the plurality of transistors so that the on transistor has a fourth capability higher than the third capability in the fourth period. This makes it possible to fix the power transistor to the on state.

[0037] In one embodiment, the multiple transistors may have the same size.

[0038] In one embodiment, the plurality of transistors may have binary weighted sizes.

[0039] In one embodiment, the gate driver circuit may further include a first sensor that compares the gate-source voltage of the power transistor to a first threshold voltage. The control circuit may perform a transition to a second time period in response to a change in the output of the first sensor during the first time period. By monitoring the gate-source voltage of the power transistor, the magnitude of the drive current may be changed in conjunction with a transition of the power transistor from an off state to an on state. The first threshold voltage may be equal to, higher than, or lower than the gate threshold of the MOSFET.

[0040] In one embodiment, the first sensor can be shared with a high-side turn-off sensor that detects the turn-off of the high-side transistor. This makes it possible to reduce the drive current before the high-side transistor is turned on. In addition, an increase in circuit area can be suppressed.

[0041] In one embodiment, the gate driver circuit may further include a second sensor that compares the output voltage of the switch circuit with a second threshold voltage. The control circuit may perform a transition to a third period in response to a change in the output of the second sensor in the second period. By monitoring the output voltage, it may be detected that the influence of the reverse recovery characteristics of the freewheeling diode of the relative arm has become smaller.

[0042] In one embodiment, the gate driver circuit may further include a third sensor that compares the output voltage of the switch circuit with a third threshold voltage. The control circuit may perform a transition to a fourth period in response to a change in the output of the third sensor during the third period.

[0043] In one embodiment, the gate driver circuit can be integrated on a single semiconductor substrate. The term "integrated" includes the case where all components of the circuit are formed on the semiconductor substrate, and the case where the main components of the circuit are integrated and some resistors, capacitors, etc. used to adjust the circuit constants can be set outside the semiconductor substrate. By integrating the circuit on a single chip, the circuit area can be reduced and the characteristics of the circuit elements can be kept uniform.

[0044] According to one embodiment, a motor drive circuit includes a bridge circuit, a high-side driver and a low-side driver, the bridge circuit includes a high-side transistor and a low-side transistor, the high-side driver is any one of the above-mentioned gate driver circuits that drives the high-side transistor as a power transistor, and the low-side driver is any one of the above-mentioned gate driver circuits that drives the low-side transistor as a power transistor.

[0045] An electronic device according to one embodiment includes a motor and the above-mentioned motor driving device configured to drive the motor.

[0046] (Example)

[0047] The preferred embodiments will be described below with reference to the accompanying drawings. The same or equivalent components, parts and processes shown in each of the accompanying drawings are represented by similar reference numerals, and repeated descriptions are appropriately omitted. In addition, the embodiments are exemplary rather than restrictive. All features and combinations thereof described in the embodiments are not necessarily necessary for the present disclosure.

[0048] In the present disclosure, the expression “a state in which component A is connected to component B” includes a case in which component A and component B are directly physically connected, or even a case in which component A and component B are indirectly connected via any other component that does not affect the electrical connection state between component A and component B or does not impair the function and effect achieved by the combination of component A and component B.

[0049] Similarly, “a state in which component C is installed between component A and component B” includes a state in which component A and component C or component B and component C are indirectly connected through any other component that does not affect the electrical connection state between component A and component C or component B and component C or does not impair the function and effect achieved by the combination of component A and component C or component B and component C, as well as a state in which component A and component C or component B and component C are directly connected.

[0050] Figure 2 is a circuit diagram of a switch circuit 100 according to an embodiment. The switch circuit 100 includes a bridge circuit 110 and a drive circuit 200. Although only a configuration of one phase of the switch circuit 100 is shown here, the switch circuit 100 may be a three-phase circuit or an H-bridge circuit.

[0051] The bridge circuit 110 includes an upper arm 112 disposed between a power supply line (input line) 102 and an output terminal (output line) 104, and a lower arm 114 disposed between the output line 104 and a ground line 106. The upper arm 112 includes a high-side transistor MH and a flyback diode (freewheel diode) Di connected in parallel. The lower arm 114 includes a low-side transistor ML and a flyback diode Di connected in parallel. In the present embodiment, the high-side transistor MH and the low-side transistor ML are N-channel MOSFETs, and the body diode of each of them also serves as a flyback diode Di.

[0052] The drive circuit 200 controls the upper arm 112 and the lower arm 114 of the bridge circuit 110. The drive circuit 200 switches between three states: a high impedance state φ1 in which both the upper arm 112 and the lower arm 114 are turned off, a high output state φ2 in which the upper arm 112 is turned on and the lower arm 114 is turned off, and a low output state φ3 in which the upper arm 112 is turned off and the lower arm 114 is turned on. The output current I flows from the output line 104 of the bridge circuit 110 to the inductor L1 as a load. OUT The direction of is taken as positive, and the opposite direction is taken as negative. For each of the three states φ1 to φ3, there is an output current I OUT For the positive (current supply) state φ1A to φ3A and the output current I OUT The state of φ1B to φ3B is negative (current sinking).

[0053] The driving circuit 200 is a functional IC including a control circuit 210, a high-side driver circuit 220, and a low-side driver circuit 260, and is integrated on a single semiconductor substrate. The control circuit 210 selects one of the states φ1 to φ3 according to the load state of the bridge circuit 110, and generates control signals HGCTL and LGCTL corresponding to each of the states φ1 to φ3. In state φ1, both the high-side control signal HGCTL and the low-side control signal LGCTL are at an off level (e.g., a low level). In state φ2, the high-side control signal HGCTL is at an on level (e.g., a high level), and the low-side control signal LGCTL is at an off level. In state φ3, the high-side control signal HGCTL is at an off level, and the low-side control signal LGCTL is at an on level.

[0054] The high-side driver circuit 220 receives the high-side control signal HGCTL at the input node IN. The output node OUT is connected to the gate of the high-side transistor MH via the high-side gate pin HG. When the high-side control signal HGCTL changes from the off level to the on level, the high-side driver circuit 220 drives the current I HG_ON Supplied to the gate of the high-side transistor MH, thereby increasing the gate-source voltage V of the high-side transistor MH GSWhen the high-side control signal HGCTL changes from the on level to the off level, the high-side driver circuit 220 draws a driving current I from the gate of the high-side transistor MH. HG_OFF , thereby reducing the gate-source voltage V GS And turn off the high-side transistor MH.

[0055] When the high-side transistor MH is turned on, the high-side driver circuit 220 can select a plurality of operation modes, one of which is referred to as a first mode. In the first mode, the high-side driver circuit 220 changes the drive current I supplied to the gate of the high-side transistor MH in a plurality of stages according to the state of the bridge circuit 110. HG_ON .

[0056] In the first mode, the high-side driver circuit 220 outputs a driving current I having a first current amount I1 during a first period T1 after the high-side control signal HGCTL is changed from an off level to an on level. HG_ON , outputting a driving current I having a second current amount I2 smaller than the first current amount I1 during a second period T2 after the first period T1. HG_ON And during a third period T3 after the second period T2, a driving current I having a third current amount I3 greater than the first current amount I1 and the second current amount I2 is output. HG_ON .

[0057] The high-side driver circuit 220 is configured to operate in a second mode in addition to the first mode. In the second mode, the driving current I generated by the high-side driver circuit 220 HG_ON The waveform of is different from the waveform in the first mode. Specifically, in the second mode, from the time when the high-side control signal HGCTL changes from the off level to the on level to the time when the state transition of the bridge circuit 110 is completed, the driving current I HG_ON The constant amount Ic has a value greater than the second current amount I2. The constant amount Ic may be greater than any one of the first to third current amounts I1 to I3.

[0058] The low-side driver circuit 260 receives the low-side control signal LGCTL at the input node IN. The output node OUT is connected to the gate of the low-side transistor ML via the low-side gate pin LG. When the low-side control signal LGCTL changes from the off level (e.g., low level) to the on level (high level), the low-side driver circuit 260 drives the current I LG_ON Supplied to the gate of the low-side transistor ML, raising the gate-source voltage V of the low-side transistor ML GSWhen the low-side control signal LGCTL changes from the on level to the off level, the low-side driver circuit 260 draws a driving current I from the gate of the low-side transistor ML. LG_OFF , reducing the gate-source voltage V GS , and turns off the low-side transistor ML.

[0059] Similar to the high-side driver circuit 220 , the low-side driver circuit 260 is configured to be switchable between a first mode and a second mode.

[0060] In the first mode, the low-side driver circuit 260 changes the driving current I supplied to the gate of the low-side transistor ML in multiple stages according to the state of the bridge circuit 110. LG_ON .

[0061] In the first mode, the low-side driver circuit 260 outputs a driving current I having a fourth current amount I4 during a fourth period T4 after the low-side control signal LGCTL is changed from an off level to an on level. LG_ON , outputting a driving current I having a fifth current amount I5 smaller than the fourth current amount I4 during a fifth period T5 after the fourth period T4. LG_ON And during a sixth period T6 after the fifth period T5, a driving current I having a sixth current amount I6 greater than the fourth current amount I4 and the fifth current amount I5 is output. LG_ON .

[0062] In the second mode, the driving current I generated by the low-side driver circuit 260 LG_ON The waveform of is different from that in the first mode. Specifically, in the second mode, from the time when the low-side control signal LGCTL changes from the off level to the on level to the time when the state transition of the bridge circuit 110 is completed, the driving current I LG_ON The constant amount Id has a value greater than the fifth current amount I5. The constant amount Id may be greater than any one of the fourth to sixth current amounts I4 to I6.

[0063] The above is the configuration of the switch circuit 100. Next, the operation of the switch circuit 100 will be described.

[0064] First, the operation of the high-side driver circuit 220 will be described. The high-side driver circuit 220 operates in a first mode when a reverse recovery current of the freewheeling diode of the lower arm 114 can be generated, and operates in a second mode when a reverse recovery current of the freewheeling diode of the lower arm 114 is not generated.

[0065] Specifically, the high-side driver circuit 220 turns off the high-side transistor MH and the low-side transistor ML and the current I OUTWhen the state φ1A supplied via the freewheeling diode Di of the lower arm 114 is turned on (supply high), the operation is performed in the first mode.

[0066] In addition, the high-side driver circuit 220 turns off the high-side transistor MH and turns off the current I OUT The low-side transistor ML operates in the first mode when the state of the sink is turned on (sink high).

[0067] Figure 3 4 is a circuit diagram of a gate driver circuit 400 according to an embodiment. Figure 2 The high-side driver circuit 220 shown in FIG. 1 and drives the N-type high-side transistor MH forming the upper arm.

[0068] The conduction circuit 410 is configured to provide a conduction current I HG_ON , the high-side transistor MH is an N-type power transistor. The shutdown circuit 420 is configured to sink a current I from the gate of the high-side transistor MH. HG_OFF .

[0069] The conduction circuit 410 includes a conduction transistor SW1. The conduction transistor SW1 is configured to have a variable driving capability S. Specifically, the conduction transistor SW1 includes a plurality of transistors MP1 to MPn connected in parallel (between the gate of the high-side transistor MH and the high-level line 412). The transistors MP1 to MPn are configured to be able to switch between a conduction state and an off state independently. The driving capability S of the conduction transistor SW1 can be adjusted according to the number of transistors in the conduction state among the transistors MP1 to MPn.

[0070] The driving capability of the i-th (i=1, 2, . . . , n) transistor MPi is determined by the aspect ratio W / L of the gate width W and the gate length L. Therefore, the driving capability of the turned-on transistor SW1 is the sum of the driving capabilities of the turned-on transistors.

[0071] In this embodiment, it is assumed that the W / L (ie, driving capability) of the plurality of transistors MP1 to MPn are all equal. Therefore, when m of the n transistors (1≤m≤n) are turned on, the driving capability of the turned-on transistor SW1 is m times the driving capability of one transistor.

[0072] The control circuit 210 generates a control signal HGCTL indicating states of the turn-on transistor SW1 and the turn-off transistor SW2 . Specifically, the control circuit 210 is configured to control the turn-on / off states of the plurality of transistors MP1 to MPn with respect to the turn-on transistor SW1 .

[0073] In the first mode, the control circuit 210 operates in the following sequence including the first to fourth periods T1 to T4 in response to an instruction to turn on the high-side transistor MH.

[0074] The capability of the turn-on transistor SW1 is set so that the turn-on transistor SW1 operates in a saturation region during the first period T1 to the third period T3. During the fourth period T4, the turn-on transistor SW1 is considered to operate in a linear region.

[0075] (i) First period T1

[0076] During the first period T1, the capability of the pass transistor SW1 is set to the first capability S1. Therefore, the current flowing through the pass transistor SW1 does not depend on the drain-source voltage, but is determined by the gate-source voltage and the current capability. During the first period T1, the current I having the first current amount I1 HG_ON is supplied to the gate of the high-side transistor MH.

[0077] (ii) Second period T2

[0078] During the second period T2, the capability of the turn-on transistor SW1 is set to a second capability S2 lower than the first capability S1. During the second period T2, the current I having the second current amount I2 smaller than the first current amount I1 HG_ON is supplied to the gate of the high-side transistor MH.

[0079] (iii) Third period T3

[0080] During the third period T3, the capacity of the turn-on transistor SW1 is set to a third capacity S3 higher than the second capacity S2. The third capacity S3 may be higher or lower than the first capacity S1, but is assumed to be higher than the first capacity S1. During the third period T3, the current I having the third current amount I3 greater than the first current amount I1 and the second current amount I2 HG_ON is supplied to the gate of the high-side transistor MH.

[0081] (iv) Fourth period T4

[0082] During the fourth period T4 , the capacity of the turn-on transistor SW1 is set to a fourth capacity S4 , which is higher than the first capacity S1 , the second capacity S2 , and the third capacity S3 .

[0083] For example, when n=5, control may be performed such that m=2 in the first period T1 , m=1 in the second period, m=4 in the third period, and m=5 in the fourth period.

[0084] Figure 4 yes Figure 3The operation waveform diagram of the gate driver circuit 400 is shown in FIG. The control signal CTRL is a logic signal indicating the state of the bridge circuit 110. LGS is the gate voltage (gate-source voltage) of the low-side transistor ML. V HG is the gate voltage of the high-side transistor MH, and V OUT is the source voltage, i.e., the output voltage of the high-side transistor MH. V HGS is the gate-source voltage of the high-side transistor MH, and is V HG With V OUT The potential difference between.

[0085] Before time t0, the control signal CTRL is at a low level, the high-side transistor MH is turned off, the low-side transistor ML is turned on, and the output voltage V OUT It is low voltage (0V).

[0086] Figure 4 1 shows the operation in the current supply mode. Before time t0, the negative current I ML flows through the low-side transistor ML.

[0087] At time t0, the control signal CTRL transitions to a high level. Therefore, the low-side driver circuit 260 reduces the gate voltage V of the low-side transistor ML. LG And turn off the low-side transistor ML.

[0088] At time t1, when the gate voltage V LG becomes lower than the fourth threshold voltage V th4 , the high-side driver circuit 220 becomes effective.

[0089] In the first period T1, m=2 transistors are turned on, and the turned-on transistor SW1 has a first capacity S1. At this time, the current I with the first current amount I1 HG_ON is supplied to the gate of the high-side transistor MH.

[0090] Then, when the gate-source voltage V HGS At time t2, the voltage V th1 , the period changes to the second period T2. In the second period T2, m=1 transistors are turned on, and the turned-on transistor SW1 has a second capacity S2. At this time, the current I with the second current amount I2 HG_ON is supplied to the gate of the high-side transistor MH. Since the second current I2 is less than the first current I1, the gate-source voltage V HGS The rising rate of the gate-source voltage V HGS rate of rise.

[0091] Then, when the output voltage V OUT At time t3, the voltage V th2 , the period changes to the third period T3. In the third period T3, m=4 transistors are turned on, and the turned-on transistor SW1 has a third capacity S3. At this time, the current I with the third current amount I3 HG_ON is supplied to the gate of the high-side transistor MH. The third current amount I3 is greater than the first current amount I1 and the second current amount I2, and the gate-source voltage V HGS The rate of ascent increases.

[0092] Then, when the output voltage V OUT At time t4, the input voltage V IN The third threshold voltage V th3 , the period changes to the fourth period T4. In the fourth period T4, m=5 transistors are turned on, the conduction transistor SW1 has the maximum fourth capacity S4, and the conduction transistor SW1 is in a fully turned-on state. When the conduction transistor SW1 is in a fully turned-on state, the gate voltage V HG is fixed to a high level voltage, and the high-side transistor MH is fixed to a strongly on state.

[0093] The operation of the switching circuit 100 has been described above.

[0094] According to the switch circuit 100, during the first period T1, the driving current I having the first current amount I1 HG_ON is supplied to the gate of the high-side transistor MH until the high-side transistor MH is turned on, thereby increasing the gate voltage V HG Then, during the second period T2 after the high-side transistor MH is turned on and the reverse recovery current can flow through the freewheeling diode of the lower arm, the driving current I supplied to the gate of the high-side transistor MH is HG_ON The current is reduced to the second current amount I2, and the high-side transistor MH is gradually turned on while maintaining a large on-resistance. This makes it possible to suppress the through current and ringing caused by the reverse recovery current of the freewheeling diode of the arm on the opposite side of the upper arm (i.e., the lower arm) as the drive target of the drive circuit 200.

[0095] Subsequently, in the third period T3 in which the reverse recovery current is unlikely to flow, the drive current I supplied to the gate of the high-side transistor MH is HG_ON The third current amount I3 is increased to be greater than the driving current in the second period T2, thereby shortening the turn-on time of the high-side transistor MH and reducing power consumption.

[0096] In addition, the driving current I supplied to the gate of the high-side transistor MH in the third period T3 is HG_ONis greater than the first current amount I1 in the first period T1. Therefore, the on-resistance of the high-side transistor MH can be reduced in a short period of time, thereby further improving the efficiency of the bridge circuit.

[0097] Next, a configuration example of the shutdown circuit 420 will be described.

[0098] Figure 5 2 is a circuit diagram of a drive circuit 200A including a gate driver circuit 400A. The gate driver circuit 400A includes a turn-on circuit 410A and a turn-off circuit 420A.

[0099] The configuration of the conduction circuit 410A is similar to Figure 3 The configuration shown in .

[0100] The shutdown circuit 420A includes a shutdown transistor SW2. The shutdown transistor SW2 includes a plurality of transistors MN1 to MNn connected in parallel. The number n of transistors MN constituting the shutdown transistor SW2 may be the same as or different from the number n of transistors MP constituting the conduction transistor SW1.

[0101] The transistors MN1 to MNn are configured to be independently switchable between an on state and an off state. The driving capability S of the off transistor SW2 can be adjusted according to the number of transistors in the on state among the transistors MN1 to MNn.

[0102] According to the shutdown circuit 420A, when the high-side transistor MH is turned off, the driving current I generated by the shutdown circuit 420A HG_OFF can be changed in stages, like the drive current I when turning on the high-side transistor MH HG_ON Same.

[0103] Next, a modified example of the conduction circuit 410 will be described.

[0104] (Revision 1)

[0105] Figure 6 is a circuit diagram of a conduction circuit 410 according to Modification Example 1.

[0106] The capabilities (sizes) of the plurality of transistors MP1 to MPn constituting the turn-on transistor SW1 may be weighted in binary. Specifically, the W / L ratios of the transistors MP1, MP2, ..., MPn may satisfy the following relationship: 1:2: ...:2 n-1 .

[0107] When n=5, the W / L ratios of the five transistors MP1 to MP5 are as follows: 1:2:4:8:16.

[0108] A control example in this case is shown below.

[0109] (i) First period T1

[0110] MP1=OFF

[0111] MP2 = On

[0112] MP3=off

[0113] MP4=off

[0114] MP5=off

[0115] The capability of turning on the transistor SW1 during the first period T1 is W / L=2.

[0116] (ii) Second period T2

[0117] MP1=conduction

[0118] MP2=off

[0119] MP3=off

[0120] MP4=off

[0121] MP5=off

[0122] The capability of turning on the transistor SW1 during the second period T2 is W / L=1.

[0123] (iii) Third period T3

[0124] MP1=OFF

[0125] MP2=off

[0126] MP3=off

[0127] MP4=off

[0128] MP5 = conduction

[0129] The capability of turning on the transistor SW1 during the third period T3 is W / L=16.

[0130] (iv) Fourth period T4

[0131] MP1=conduction

[0132] MP2 = On

[0133] MP3 = conduction

[0134] MP4 = On

[0135] MP5 = conduction

[0136] The capability of turning on the transistor SW1 during the fourth period T4 is W / L=31.

[0137] (Revision 2)

[0138] Figure 7 is a circuit diagram of a conduction circuit 410 according to Modification Example 2.

[0139] The capabilities (sizes) of the plurality of transistors MP1 to MPn constituting the pass transistor SW1 are weighted in binary. In this example, n=5, and the W / L ratios of the transistors MP1, MP2, ..., MP5 may satisfy the following relationship: 1:2:2:4:8.

[0140] Among the plurality of transistors MP1 to MP5, transistors MP1 and MP2 are assigned to the first transistor group, and transistors MP3 to MP5 are assigned to the second transistor group. The state of the first transistor group is fixed in the first time period T1 to the third time period T3. For example, transistor MP1 is fixed to the off state, and transistor MP2 is fixed to the on state. The second current amount I2 in the second time period T2 can be set by combining the states of the two transistors MP1 and MP2. In the second time period T2, all transistors MP3 to MP5 included in the second transistor group are fixed to the off state.

[0141] In the first period T1 , the third period T3 , and the fourth period T4 , the transistors MP3 to MP5 included in the second transistor group are switched on and off.

[0142] A control example in this case is shown below.

[0143] (i) First period T1

[0144] MP1=OFF

[0145] MP2 = On

[0146] MP3=off

[0147] MP4 = On

[0148] MP5=off

[0149] The capability of turning on the transistor SW1 during the first period T1 is W / L=6.

[0150] (ii) Second period T2

[0151] MP1=OFF

[0152] MP2 = On

[0153] MP3=off

[0154] MP4=off

[0155] MP5=off

[0156] The capability of turning on the transistor SW1 during the second period T2 is W / L=2.

[0157] (iii) Third period T3

[0158] MP1=OFF

[0159] MP2 = On

[0160] MP3=off

[0161] MP4=off

[0162] MP5 = conduction

[0163] The capability of turning on the transistor SW1 during the third period T3 is W / L=10.

[0164] (iv) Fourth period T4

[0165] MP1=OFF

[0166] MP2 = On

[0167] MP3 = conduction

[0168] MP4 = On

[0169] MP5 = conduction

[0170] The capability of turning on the transistor SW1 during the fourth period T4 is W / L=16.

[0171] Figure 8 It is shown Figure 7 The operation (simulation result) of the conduction circuit 410 is shown in FIG.

[0172] In this configuration, the second current amount I2 of the second period T2 can be set in three stages.

[0173] In addition, at the transition from the first period T1 to the second period T2, no transistor is turned on, but only turned off. In addition, at the transition from the second period T2 to the third period T3, no transistor is turned off, but only turned on.

[0174] If there are both on and off at the transition from the first period T1 to the second period T2 or from the second period T2 to the third period T3, discontinuity of current may occur when the timing of on and off is not aligned. Modification 2 can solve this problem.

[0175] In the fourth period T4 , the transistor MP1 may be turned on.

[0176] Fig. 9is a circuit diagram of the driving circuit 200 . The driving circuit 200 may include a first sensor 202 , a second sensor 204 , a third sensor 206 , and a low-side shutdown sensor 208 .

[0177] The low-side shutdown sensor 208 detects the shutdown of the low-side transistor ML. The low-side shutdown sensor 208 compares the gate-source voltage of the low-side transistor ML with the fourth threshold voltage V th4 When the control circuit 210 detects the turn-off of the low-side transistor ML based on the output of the low-side turn-off sensor 208 , the control circuit 210 performs a transition to the first period T1 .

[0178] The first sensor 202 measures the gate-source voltage V of the high-side transistor MH. GS With the first threshold voltage V th1 The threshold voltage V of the MOSFET can be used for comparison. GS（th） To set the first threshold voltage V th1 .

[0179] In many cases, a high-side shutdown sensor that detects the shutdown of the high-side transistor MH is provided in the driving circuit 200. The output of the high-side shutdown sensor is referenced by the control circuit 210. The control circuit 210 monitors the output of the high-side shutdown sensor and performs a transition of the low-side control signal LGCTL to the on-level after the high-side transistor MH is clearly turned off. Therefore, the high-side transistor MH and the low-side transistor ML can be prevented from being turned on at the same time, and a through current is prevented.

[0180] When the driving circuit 200 includes a high-side turn-off sensor, the first sensor 202 may be shared with the high-side turn-off sensor, thereby reducing the circuit area.

[0181] In the first period T1, when the output of the first sensor 202 changes, that is, when the gate-source voltage V GS Exceeds the first threshold voltage V th1 , the high-side driver circuit 220 performs a transition to the second period T2. th1 is set to be lower than the MOSFET threshold voltage V GS（th） When the high-side driver circuit 220 is turned on, the high-side driver circuit 220 may transition to the second period T2 before the high-side transistor MH is turned on. When the response delay is large, the high-side driver circuit 220 performs the transition to the second period T2 simultaneously with the turning on or slightly after the turning on.

[0182] By monitoring the gate-source voltage V GS , the driving current I can be changed in combination with the transition of the high-side transistor MH from the off state to the on state HG_ON The amplitude.

[0183] The second sensor 204 outputs the output voltage V of the output line 104 OUT With the second threshold voltage V th2 The high-side driver circuit 220 performs a transition to the third period T3 in response to the change in the output of the second sensor 204 in the second period T2. By monitoring the output voltage V OUT , it can be detected that the influence of the reverse recovery characteristics of the freewheeling diode Di of the lower arm 114 has become smaller.

[0184] The driving circuit 200 may be provided with a sensor (voltage monitoring circuit) which outputs a voltage V OUT is compared with a threshold voltage which is greater than the input voltage V IN Low preset value in order to detect the output voltage V OUT The completion of the transition from the low level to the high level, or for other purposes. In this case, by also using the voltage monitoring circuit as the second sensor 204, the increase in the circuit area can be suppressed.

[0185] The third sensor 206 outputs a voltage V OUT With the input voltage set at V IN The third threshold voltage near V th3 The control circuit 210 refers to the output of the third sensor 206, and when the output voltage V OUT Exceeds the third threshold voltage V th3 , a transition to the fourth period T4 is performed.

[0186] Next, the configuration and operation of the low-side driver circuit 260 will be described. The low-side driver circuit 260 may be configured in the same manner as the high-side driver circuit 220.

[0187] The low-side driver circuit 260 operates in the first mode when a reverse recovery current of the freewheeling diode of the upper arm 112 can be generated, and operates in the second mode when the reverse recovery current of the freewheeling diode of the upper arm 112 is not generated.

[0188] Specifically, the low-side driver circuit 260 turns off the high-side transistor MH and the low-side transistor ML and the current I OUT When the state φ1B absorbed by the freewheeling diode Di of the upper arm 112 is turned on (absorption is reduced), the operation is performed in the first mode.

[0189] In addition, the low-side driver circuit 260 turns on the low-side transistor ML from the high-side transistor MH, turns off the low-side transistor ML, and supplies the current I OUTIn the case of a conductive state (supply reduction), it operates in the second mode.

[0190] (Application example)

[0191] Next, a description will be given of applications of the switch circuit 100. The switch circuit 100 can be suitably used in a motor drive circuit.

[0192] Fig.10 is a circuit diagram of a motor driving device 300 including the switching circuit 100 according to the embodiment. The motor driving device 300 drives a three-phase motor 302 as a load, and controls the rotation state thereof.

[0193] The motor drive device 300 includes a bridge circuit 110 and a drive circuit 200. The bridge circuit 110 is a three-phase inverter and has phase legs of U-phase, V-phase, and W-phase. Each phase leg has an upper arm and a lower arm.

[0194] The drive circuit 200 includes a control circuit 210, high-side driver circuits 220U to 220W, and low-side driver circuits 260U to 260W. The control circuit 210 generates control signals indicating states of six arms constituting the bridge circuit 110 based on the state of the three-phase motor 302 as a load.

[0195] The high-side driver circuits 220U to 220W are configured with the architecture of the above-described high-side driver circuit 220. The low-side driver circuits 260U to 260W are configured with the architecture of the above-described low-side driver circuit 260.

[0196] Although a three-phase motor is used as an example here, a single-phase motor may also be used. In this case, the bridge circuit 110 is an H-bridge circuit.

[0197] Next, the application of the motor driving device 300 will be described. The motor driving device 300 can be used to control the spindle motor of a hard disk or the lens driving motor of an imaging device. Alternatively, the motor driving device 300 can be used to drive the driving motor or paper feeding motor of a printer. Alternatively, the motor driving device 300 can be used to drive the motor in an electric vehicle, a hybrid vehicle, etc.

[0198] The embodiments are merely examples, and those skilled in the art will appreciate that various modifications may be made to the combination of individual components and individual processing steps, and these modifications also fall within the scope of the disclosure or the present invention. Such modifications will be described below.

[0199] (Revision 1)

[0200] In the embodiment, the bridge circuit 110 is configured with discrete components. However, the present disclosure is not limited thereto. The bridge circuit 110 may be integrated into the driving circuit 200 .

[0201] (Revision 2)

[0202] The upper arm 112 and the lower arm 114 may be formed of IGBTs (Insulated Gate Bipolar Transistors).

[0203] (Revision 3)

[0204] In an embodiment, both the high-side driver circuit 220 and the low-side driver circuit 260 are capable of selecting multiple modes. However, only one of them may be configured to be mode controllable.

[0205] (Revision 4)

[0206] Applications of the switching circuit 100 are not limited to the motor drive device 300. For example, the switching circuit 100 can be appropriately used for a switching regulator (DC / DC converter), various power conversion devices (inverters and converters), an inverter for turning on a discharge lamp, a digital audio amplifier, etc. Therefore, the switching circuit 100 can be used for consumer devices including electronic devices and home appliances, vehicles or vehicle-mounted components, and industrial vehicles or industrial machinery.

[0207] The embodiments described using specific terms merely illustrate the principles and applications of the present disclosure, and many modifications and changes in arrangements are permitted in the embodiments without departing from the spirit of the present disclosure as defined in the claims.

[0208] (Supplementary explanation)

[0209] The following techniques are disclosed in this specification.

[0210] (Supplementary Note 1)

[0211] A gate driver circuit for driving an N-type power transistor constituting a switch circuit, comprising:

[0212] a high level line on which a voltage higher than a source of the power transistor is generated;

[0213] a pass transistor configured to supply current to a gate of the power transistor;

[0214] a turn-off transistor configured to sink current from the gate of the power transistor; and

[0215] a control circuit configured to control the turn-on transistor and the turn-off transistor,

[0216] wherein the conducting transistor comprises a plurality of transistors connected between the gate of the power transistor and the high level line, and

[0217] The control circuit controls the on / off state of the multiple transistors so that when the power transistor is turned on, the on transistor has a first driving capability in a first time period, a second driving capability lower than the first driving capability in a second time period, and a third driving capability higher than the second driving capability in a third time period.

[0218] (Supplementary Note 2)

[0219] The gate driver circuit according to Supplementary note 1, wherein the third driving capability is higher than the first driving capability.

[0220] (Supplementary Note 3)

[0221] The gate driver circuit according to Supplementary Note 1 or 2, wherein the plurality of transistors include at least one transistor assigned to the first transistor group and at least one transistor assigned to the second transistor group, and

[0222] The control circuit fixes the at least one transistor assigned to the second transistor group to an off state during the second period, while changing from the first period to the third period without changing the on / off state of the at least one transistor assigned to the first transistor group.

[0223] (Supplementary Note 4)

[0224] The gate driver circuit according to any one of Supplementary Notes 1 to 3, wherein the control circuit controls the on / off states of the plurality of transistors so that the on transistors have a fourth driving capability higher than the third driving capability in a fourth period.

[0225] (Supplementary Note 5)

[0226] The gate driver circuit according to any one of Supplementary Notes 1 to 4, wherein the plurality of transistors have the same size.

[0227] (Supplementary Note 6)

[0228] The gate driver circuit according to any one of Supplementary Notes 1 to 4, wherein the plurality of transistors have binary weighted sizes.

[0229] (Supplementary Note 7)

[0230] The gate driver circuit according to any one of Supplementary Notes 1 to 6, further comprising a first sensor configured to compare a gate-source voltage of the power transistor with a first threshold voltage,

[0231] Wherein the control circuit performs a transition to the second period in response to a change in the output of the first sensor during the first period.

[0232] (Supplementary Note 8)

[0233] The gate driver circuit according to any one of Supplementary Notes 1 to 7, further comprising a second sensor configured to compare an output voltage of the switch circuit with a second threshold voltage,

[0234] The control circuit performs the transition to the third period in response to a change in the output of the second sensor during the second period.

[0235] (Supplementary Note 9)

[0236] The gate driver circuit according to Supplementary Note 4, further comprising a third sensor configured to compare the output voltage of the switch circuit with a third threshold voltage,

[0237] The control circuit performs a transition to the fourth period in response to a change in the output of the third sensor during the third period.

[0238] (Supplementary Note 10)

[0239] The gate driver circuit according to any one of Supplementary Notes 1 to 9, wherein the gate driver circuit is integrated on a single semiconductor substrate.

[0240] (Supplementary Note 11)

[0241] A motor driving device, comprising:

[0242] a bridge circuit comprising a high-side transistor and a low-side transistor;

[0243] a high-side driver, which is the gate driver circuit described in any one of Supplementary Notes 1 to 9, configured to drive the high-side transistor as the power transistor; and

[0244] A low-side driver is the gate driver circuit described in any one of Supplementary Notes 1 to 9, the low-side driver being configured to drive the low-side transistor as the power transistor.

[0245] (Supplementary Note 12)

[0246] An electronic device, comprising:

[0247] Motors; and

[0248] The motor driving device according to Supplementary Note 11 is configured to drive the motor.

[0249] Although certain embodiments have been described, these embodiments are presented only as examples and are not intended to limit the scope of the present disclosure. In fact, the embodiments described herein may be embodied in various other forms. In addition, various omissions, substitutions, and changes may be made to the forms of the embodiments described herein without departing from the spirit of the present disclosure. The attached claims and their equivalents are intended to cover these forms or modifications that fall within the scope and spirit of the present disclosure.

[0250] Description of Reference Numerals

[0251] 100: switch circuit, 102: power line, 104: output line, 106: ground line, 110: bridge circuit, 112: upper arm, 114: lower arm, MH: high-side transistor, ML: low-side transistor, Di: freewheeling diode, 200: drive circuit, 202: first sensor, 204: second sensor, 206: third sensor, 208: low-side shutdown sensor, 210: control circuit, 220: high-side driver circuit, 260: low-side driver circuit, 300: motor drive device, 302: three-phase motor, 400: gate driver circuit, 410: turn-on circuit, 412: high-level line, SW1: turn-on transistor, SW2: turn-off transistor, 420: turn-off circuit

Claims

1. A gate driver circuit for driving an N-type power transistor constituting a switch circuit, comprising: a high level line on which a voltage higher than a source of the power transistor is generated; a pass transistor configured to supply current to a gate of the power transistor; a turn-off transistor configured to sink current from the gate of the power transistor; as well as a control circuit configured to control the turn-on transistor and the turn-off transistor, wherein the conducting transistor comprises a plurality of transistors connected between the gate of the power transistor and the high level line, and The control circuit controls the on / off state of the multiple transistors so that when the power transistor is turned on, the on transistor has a first driving capability in a first time period, a second driving capability lower than the first driving capability in a second time period, and a third driving capability higher than the second driving capability in a third time period. 2 . The gate driver circuit according to claim 1 , wherein the third driving capability is higher than the first driving capability.

3. The gate driver circuit according to claim 1 , wherein the plurality of transistors include at least one transistor assigned to a first transistor group and at least one transistor assigned to a second transistor group, and The control circuit fixes the at least one transistor assigned to the second transistor group to an off state during the second period, and does not change the on / off state of the at least one transistor assigned to the first transistor group from the first period to the third period.

4. The gate driver circuit according to any one of claims 1 to 3, wherein the control circuit controls the on / off states of the plurality of transistors so that the on transistors have a fourth driving capability higher than the third driving capability in a fourth period.

5. The gate driver circuit according to any one of claims 1 to 3, wherein the plurality of transistors have the same size.

6. The gate driver circuit of any one of claims 1 to 3, wherein the plurality of transistors have binary weighted sizes.

7. The gate driver circuit according to any one of claims 1 to 3, further comprising a first sensor configured to compare a gate-source voltage of the power transistor with a first threshold voltage, Wherein the control circuit performs a transition to the second period in response to a change in the output of the first sensor during the first period.

8. The gate driver circuit according to any one of claims 1 to 3, further comprising a second sensor configured to compare the output voltage of the switch circuit with a second threshold voltage, The control circuit performs the transition to the third period in response to a change in the output of the second sensor during the second period.

9. The gate driver circuit according to claim 4, further comprising a third sensor configured to compare the output voltage of the switch circuit with a third threshold voltage, The control circuit performs a transition to the fourth period in response to a change in the output of the third sensor during the third period.

10. The gate driver circuit according to any one of claims 1 to 3, the gate driver circuit being integrated on a single semiconductor substrate.

11. A motor drive device, comprising: a bridge circuit comprising a high-side transistor and a low-side transistor; a high-side driver, the high-side driver being a gate driver circuit according to any one of claims 1 to 3, the high-side driver being configured to drive the high-side transistor as the power transistor; as well as A low-side driver, the low-side driver being a gate driver circuit according to any one of claims 1 to 3, the low-side driver being configured to drive the low-side transistor as the power transistor.

12. An electronic device comprising: Motor; as well as The motor driving device according to claim 11, wherein the motor driving device is configured to drive the motor.

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