PWM wave blocking circuit and PWM wave driving circuit

Abstract

According to the PWM wave blocking circuit and the PWM wave driving circuit provided by the invention, the timing unit and the clearing unit are arranged, the characteristic that the clearing unit can perform timing value zero clearing only when the micro-control module is not in a breakpoint state is utilized, and the micro-control module is set to turn over the level of an enable control signal when the timing unit performs timing to a timing period, so that the PWM wave is blocked. Therefore, when the circuit is not in the breakpoint state, the clearing unit can clear the timing value, so that the timing value cannot overflow in the state, the level of the control signal is enabled to be kept, and the level conversion module keeps working; and in the breakpoint state, the clearing unit cannot clear the timing value, and the timing value overflows, so that the enable control signal can be overturned, and finally the level conversion module stops working and interrupts the conversion and output of the PWM wave sending signal, thereby ensuring the controllability of the external transmission of the PWM wave sending signal, and ensuring the transmission safety.

Description

Technical Field

[0001] The present application relates to the technical field of PWM wave generation control, and in particular to a PWM wave blocking circuit and a PWM wave driving circuit. Background Art

[0002] MCU is often used for PWM wave control in inverters and controllable rectifier power supplies. During the development and debugging stage, simulation debugging of the MCU code is usually required, which requires setting breakpoints for debugging under simulation conditions. When the code is executed to the breakpoint, the PWM wave module of the MCU is still transmitting, and the MCU code is stuck at the breakpoint, so it will not control the PWM module. Therefore, in this case, the uncontrolled PWM wave may cause abnormal wave transmission, which may cause danger.

[0003] The hardware usually provides a hardware overcurrent detection protection circuit. When an overcurrent fault occurs in the inverter, the level conversion chip is turned off, the PWM output is blocked, and the power inverter is turned off. At the same time, the overcurrent information is input into the MCU. After the MCU receives the overcurrent signal, it also stops PWM ripple. This solution requires an actual external fault to provide protection. In the pure software detection protection solution, there is a risk of not being able to provide timely protection if the ripple is uncontrollable during the debugging stage. Summary of the invention

[0004] The present application provides a PWM wave blocking circuit and a PWM wave driving circuit. When the MCU reaches a breakpoint in DEBUG debugging mode, the PWM wave can be automatically blocked to reduce the risk of development and debugging.

[0005] A PWM wave blocking circuit, comprising:

[0006] Microcontroller module, used for outputting enable control signal and PWM wave signal;

[0007] A level conversion module, connected to the microcontroller module, for performing level conversion on the PWM wave signal according to the enable control signal and outputting the level conversion;

[0008] The microcontroller module comprises:

[0009] A timing unit, used for performing periodic timing and obtaining a timing value;

[0010] a clearing unit connected to the timing unit, and configured to clear the timing value if the timing value reaches a duration threshold when the microcontroller module is not in a breakpoint state;

[0011] The microcontrol module is also used to flip the level of the enable control signal if the timing value reaches the timing cycle of the timing unit, so that the level conversion module stops the level conversion and output of the PWM wave signal; wherein the duration threshold is less than the timing cycle.

[0012] In one embodiment, the PWM wave blocking circuit further includes:

[0013] The latch module is connected to the microcontroller module and the level conversion module respectively, and is used to latch and output the enable control signal after the level is flipped.

[0014] In one embodiment, the latch module includes a D flip-flop; the power supply terminal of the D flip-flop is used to receive the power supply voltage; the clear terminal of the D flip-flop is connected to the microcontroller module, and the output terminal of the D flip-flop is connected to the level conversion module.

[0015] In one embodiment, the latch module also includes a resistor R1 and a capacitor C1; the first end of the resistor R1, the first end of the capacitor C1 and the power supply end of the D trigger are connected in common, and the second end of the resistor R1 is connected to the preset end of the D trigger for receiving a reset signal; the second end of the capacitor C1 is connected to the ground end; when the D trigger is powered on, the reset signal is set to maintain a low level for a preset period of time and then be pulled up to a high level.

[0016] In one embodiment, the reset signal is output by the microcontroller module.

[0017] In one of the embodiments, the duration threshold is equal to a carrier period of a carrier signal, and the timing period is equal to 1.5 times of the duration threshold.

[0018] In one embodiment, the PWM wave blocking circuit further includes:

[0019] The inversion module is connected to the clearing end of the microcontrol module and the D flip-flop respectively, and is used for inverting the enable control signal output by the microcontrol module and then outputting it to the D flip-flop.

[0020] In one embodiment, the inverting module includes a resistor R2, a resistor R3, a capacitor C2, a capacitor C3 and an inverter; the first end of the resistor R2 is used to receive a first power supply voltage, the second end of the resistor R2 is respectively connected to the first end of the resistor R3 and the microcontrol module, and the second end of the resistor R3 is respectively connected to the first end of the capacitor C2 and the input end of the inverter; the first end of the capacitor C3 is connected to the ground, and the second end of the capacitor C3 is commonly connected to the power supply end of the inverter for jointly receiving the first power supply voltage; the second end of the capacitor C2 is commonly connected to the common end of the inverter and to the ground.

[0021] In one embodiment, the level conversion module includes: multiple input resistors, capacitor C4, capacitor C5, resistor R4 and a level converter; the first end of each input resistor is connected to the ground end, and the second end of each input resistor is connected to each input end of the level converter in a one-to-one correspondence; the first end of the capacitor C4, the first end of the capacitor C5 and the power supply end of the level converter are connected in common to receive a second power supply voltage; the enable end of the level converter and the first end of the resistor R4 are respectively connected to the output end of the D trigger, and the second end of the resistor R4 is connected to the ground end; the second end of the capacitor C4 and the second end of the capacitor C5 are respectively connected to the ground end.

[0022] A PWM wave driving circuit includes the above-mentioned PWM wave blocking circuit, and further includes:

[0023] The power driving circuit is connected to the level conversion module and is used to generate a motor driving signal according to the PWM wave signal after level conversion.

[0024] By setting the timing unit and the clearing unit, and utilizing the characteristic that the clearing unit can clear the timing value only when the microcontroller module is not in the breakpoint state, the microcontroller module is set to flip the level of the enabling control signal when the timing unit reaches the timing cycle, so that when it is not in the breakpoint state, since the clearing unit can clear the timing value, the timing value will not overflow in this state, the level of the enabling control signal is maintained, and the level conversion module keeps working; while in the breakpoint state, since the clearing unit cannot clear the timing value, the timing value will eventually overflow, and the enabling control signal can be flipped, and finally the level conversion module stops working, interrupting the conversion and output of the PWM wave signal, thereby ensuring the controllable external transmission of the PWM wave and ensuring the transmission safety. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A structural block diagram of a PWM wave blocking circuit according to an embodiment of the present application;

[0026] Figure 2This is a structural block diagram of a PWM wave blocking circuit according to another embodiment of the present application;

[0027] Figure 3 A circuit structure diagram of a latch module according to an embodiment of the present application;

[0028] Figure 4 This is a structural block diagram of a PWM wave blocking circuit according to another embodiment of the present application;

[0029] Figure 5 This is a circuit structure diagram of an inverting module according to an embodiment of the present application;

[0030] Figure 6 A circuit structure diagram of a level conversion module according to an embodiment of the present application;

[0031] Figure 7 This is a structural block diagram of a PWM wave blocking circuit according to another embodiment of the present application. DETAILED DESCRIPTION

[0032] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0033] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0034] It should be noted that all directional indications in the embodiments of the present application (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly. The connection can be a direct connection or an indirect connection.

[0035] In addition, in this application, descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0036] The embodiment of the present invention provides a PWM wave blocking circuit, such as Figure 1 As shown, the PWM wave blocking circuit includes a microcontroller module 110 and a level conversion module 120. The microcontroller module 110 is used to output an enable control signal and a PWM wave signal. The level conversion module 120 is connected to the microcontroller module 110 and is used to perform level conversion on the PWM wave signal according to the enable control signal and output it. The microcontroller module 110 includes a timing unit 111 and a clearing unit 112. The timing unit 111 is used to perform period timing to obtain a timing value. The clearing unit 112 is connected to the timing unit 111 and is used to clear the timing value if the timing value reaches a duration threshold when the microcontroller module 110 is not in a breakpoint state. The microcontroller module 110 is also used to flip the level of the enable control signal if the timing value reaches the timing cycle of the timing unit 111, so that the level conversion module 120 stops the level conversion and output of the PWM wave signal. The duration threshold is less than the timing cycle.

[0037] It can be understood that the enable control signal output by the microcontroller module 110 is used to control the enable state of the level conversion module 120, and the level of the enable control signal can be high or low to enable or stop the level conversion module 120. Initially, the enable control signal output by the microcontroller module 110 is a target level, and the target level can put the level conversion module 120 in an operating state, so that the level conversion module 120 can convert the PWM wave signal output by the microcontroller module 110 into a specific voltage range to meet the external drive requirements.

[0038] The breakpoint state may be a state of abnormal operation, for example, a state in which the microcontroller module 110 needs to be debugged during the development and debugging phase. The microcontroller module 110 may be a microcontroller unit MCU, and the PWM wave signal may be output by a PWM wave module in the microcontroller unit MCU. The timing unit 111 may be a counter, and the timing value is represented by the count value of the counter.

[0039] The timing unit 111 in the microcontroller can perform periodic timing all the time. When a timing cycle is completed, the timing value will overflow, and the timing unit 111 will start timing again. At the same time, the microcontroller will flip the level of the enable signal and then output it. When the microcontroller module 110 is not in a breakpoint state, the clearing unit 112 will clear the timing value when the timing value reaches the duration threshold, and the duration threshold is less than the timing cycle. Therefore, when the microcontroller module 110 is not in a breakpoint state, the timing value will be cleared before reaching the timing cycle. At this time, the microcontroller 110 will not flip the level of the enable control signal. When the microcontroller module 110 is in a breakpoint state, since the clearing unit 112 does not perform a clearing action, the timing value will reach the timing cycle and overflow. At this time, the microcontroller 110 will flip the level of the enable control signal, thereby controlling the level conversion module 120 to stop working, that is, stop the level conversion and output of the PWM wave signal.

[0040] In this way, by setting the timing unit 111 and the clearing unit 112, and utilizing the characteristic that the clearing unit 112 can clear the timing value only when the microcontroller module 110 is not in the breakpoint state, the microcontroller module 110 is set to flip the level of the enabling control signal when the timing unit 111 reaches the timing cycle, so that when it is not in the breakpoint state, since the clearing unit 112 can clear the timing value, the timing value will not overflow in this state, the level of the enabling control signal is maintained, and the level conversion module 120 keeps working; while in the breakpoint state, since the clearing unit 112 cannot clear the timing value, the timing value will eventually overflow, and then the enabling control signal can be flipped, and finally the level conversion module 120 stops working, interrupting the conversion and output of the PWM wave signal, thereby ensuring the controllable external transmission of the PWM wave and ensuring the transmission safety.

[0041] In one embodiment, the PWM wave blocking circuit further includes a latch module 130, such as Figure 2 As shown, the latch module 130 is connected to the micro-control module 110 and the level conversion module 120 respectively, and is used to latch and output the enable control signal after the level is flipped.

[0042] It can be understood that the latch module 130 can latch the enable control signal, that is, once the microcontroller module 110 enters the breakpoint state, the latch module 130 can latch and output the enable control signal after the level is flipped, thereby instructing the level conversion module 120 to stop working. Even if the level of the enable control signal output by the microcontroller module 110 is restored to the initial value, the level of the enable control signal output by the latch module 130 is still the flipped level, so that the level conversion module 120 continues to maintain the shutdown state. In this way, latching the enable signal through the latch module 130 can prevent the loss or change of the enable control signal, ensure the effective control of the PWM wave signal output, and ensure the safety of signal transmission.

[0043] In one embodiment, Figure 3 As shown, the latch module 130 includes a D flip-flop U1; a power supply terminal VCC of the D flip-flop U1 is used to receive a power supply voltage VDD; a clear terminal of the D flip-flop U1 Connected to the microcontroller module 110, the output terminal of the D flip-flop U1 Connected to the level conversion module 120 .

[0044] When the D flip-flop U1 is powered on, it can drive the level conversion module 120 to convert the level and output it according to the enable control signal output by the microcontroller module 110. The clear terminal of the D flip-flop U1 is low level effective. The received enable control signal (indicated by Vin in the figure) can be at a high level, so that the D flip-flop U1 maintains the output and the level conversion module 120 is in a working state; and after entering the breakpoint state, the clear terminal of the D flip-flop U1 is The received enable control signal Vin jumps to a low level, and the signal output by the D flip-flop U1 (indicated by DEB in the figure) also flips, thereby controlling the level conversion module 120 to stop the output of the PWM wave. Further, when the clear terminal of the D flip-flop U1 is When the received enable control signal Vin jumps to high level again, the clear terminal The D flip-flop U1 maintains output, and the level conversion module 120 is still in shutdown state, so as to achieve the latching and output of the enable control signal Vin after the level flip. Among them, the power supply terminal VCC of the D flip-flop U1 can be connected to the power supply to receive the power supply voltage VDD.

[0045] In one embodiment, continue to refer to Figure 3 As shown, the latch module 130 also includes a resistor R1 and a capacitor C1; the first end of the resistor R1, the first end of the capacitor C1 and the power supply end of the D trigger U1 are connected in common, and the second end of the resistor R1 and the preset end of the D trigger U1 are connected in common. The second end of the capacitor C1 is connected to the ground; when the D flip-flop U1 is powered on, the reset signal SD2 is set to maintain a low level for a preset time and then be pulled up to a high level.

[0046] Among them, the preset terminal of D flip-flop U1 It is effective at low level. It can be understood that resistor R1 is used to realize the preset terminal The capacitor C1 can be connected to the power supply to filter the power supply. When the D flip-flop U1 is powered on, the reset signal SD2 is first at a low level, and the clear terminal of the D flip-flop U1 is The received enable control signal Vin is at a high level, thereby ensuring that the level of the output of the D flip-flop U1 is at a low level, thereby ensuring that the level conversion module 120 is in a working state when the D flip-flop U1 is powered on, and after a preset time, the reset signal SD2 is pulled up to a high level, the reset fails, and the output of the D flip-flop U1 is cleared. The received enable control signal Vin determines that when entering the breakpoint

[0047] ————state, that is, when the enable control signal Vin received by the clear terminal CLR jumps to a low level, the D flip-flop U1 latches and outputs the received enable control signal Vin.

[0048] In some other embodiments, the preset time length may be a minimum time to ensure that the D flip-flop U1 achieves a stable output according to the reset signal.

[0049] In one embodiment, the reset signal SD2 may be output by the micro control module 110 .

[0050] It is understandable that the reset signal SD2 can be generated by presetting the micro-control module 110 , wherein the preset duration can also be set by the micro-control module 110 .

[0051] In one embodiment, the duration threshold is equal to the carrier period of the carrier signal, and the timing period is equal to 1.5 times the duration threshold.

[0052] It can be understood that the microcontroller module schedules and executes the code according to the execution frequency of the PWM cycle. For example, when the carrier frequency is 8kHz, that is, the carrier cycle is 125us, the microcontroller module executes code calculation and counter clearing every 125us, and calculates the PWM duty cycle of the next beat in each calculation. Since calculation and code execution require time, in order to avoid the overflow of the timing value before it has time to be cleared under normal working conditions, it is necessary to set the timing cycle to be greater than the duration threshold. However, if the timing cycle is set too large, the PWM wave cannot be blocked in time. Therefore, setting the timing cycle to 1.5 times the duration threshold can not only ensure that the timing value is cleared in time and avoid the PWM wave from being blocked incorrectly, but also ensure the timeliness of the PWM wave blocking. At the same time, the action time of a PWM duty cycle is within a carrier cycle. The timing cycle is set to 1.5 times the duration threshold, that is, 1.5 times the carrier cycle, which can also avoid the action time of the same PWM duty cycle being delayed to the next cycle.

[0053] In one embodiment, the PWM wave blocking circuit further includes an inverting module 140, such as Figure 4 As shown, the inverting module 140 is connected to the clear terminal of the microcontroller module 110 and the D flip-flop U1 respectively. The connection is used to invert the enable control signal (indicated by OEBUG_O in the figure) output by the micro-control module 110 and then output it to the D flip-flop U1.

[0054] It can be understood that after the microcontroller module 110 outputs the enable control signal OEBUG_O, in order to make the level of the enable control signal OEBUG_O adapt to the clear terminal of the D flip-flop U1, In order to effectively control the level conversion module 120 , the inversion module 140 may be set to perform level flipping to meet control requirements.

[0055] In one embodiment, Figure 5 As shown, the inverting module 140 includes a resistor R2, a resistor R3, a capacitor C2, a capacitor C3 and an inverter U2; the first end of the resistor R2 is used to receive a first power supply voltage Vc, the second end of the resistor R2 is respectively connected to the first end of the resistor R3 and the micro-control module 110, and the second end of the resistor R3 is respectively connected to the first end of the capacitor C2 and the input end of the inverter U2; the first end of the capacitor C3 is connected to the ground, and the second end of the capacitor C3 is commonly connected to the power supply end of the inverter U2, for jointly receiving the first power supply voltage Vc; the second end of the capacitor C2 is commonly connected to the common end of the inverter U2 and to the ground.

[0056] Among them, OEBUG_O is the enable control signal output by the microcontroller module 110; the first power supply voltage Vc can be provided by the power supply, the capacitor C3 is a power decoupling capacitor, which is connected to the power supply to filter the power supply, the resistor R2 is used to realize the pull-up of the enable control signal, and the resistor R3 and the capacitor C2 can be used to realize signal filtering to enhance the anti-interference ability of the circuit.

[0057] In one embodiment, Figure 6 As shown, the level conversion module 120 includes multiple input resistors (represented by Ri in the figure), capacitors C4, capacitors C5, resistors R4 and a level converter U3; the first end of each input resistor is connected to the ground, and the second end of each input resistor is connected to each input end of the level converter U3 in a one-to-one correspondence; the first end of the capacitor C4, the first end of the capacitor C5 and the power supply end VCC of the level converter U3 are commonly connected to receive the second power supply voltage vcc; the enable end of the level converter U3 and the first end of the resistor R4 are respectively connected to the output end of the D trigger U1, and the second end of the resistor R4 is connected to the ground; the second end of the capacitor C4 and the second end of the capacitor C5 are respectively connected to the ground.

[0058] It can be understood that the level converter U3 can realize the level conversion of multiple PWM signals, and the resistance values ​​of each input resistor can be set to be the same or different according to the requirements; the enable terminal of the level converter U3 may include two (in the figure, and Resistor R4 is used to realize the pull-down of the enable control signal of the enable terminal of the level converter U3.

[0059] An embodiment of the present invention further provides a PWM wave blocking circuit, comprising a microcontroller module 110, a level conversion module 120, a latch module 130 and an inverting module 140, wherein the microcontroller module 110 further comprises a timing unit 111 and a clearing unit 112. The specific circuit structure and working process of each module can be referred to the above embodiment and will not be described in detail here.

[0060] The embodiment of the present invention further provides a PWM wave driving circuit, including the PWM wave blocking circuit of any of the above embodiments, and also including a power driving circuit 150, referring to Figure 7 As shown, the power driving circuit 150 is connected to the level conversion module 120 and is used to generate a motor driving signal according to the PWM wave signal after level conversion.

[0061] It can be understood that the PWM wave driving circuit equipped with a PWM wave blocking circuit has the ability to block the PWM wave output in time during the motor driving process when the MCU enters the breakpoint state for development and debugging, thereby stopping the motor driving and ensuring work safety.

[0062] The above description is only a preferred embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A PWM wave blocking circuit, characterized in that: include: Microcontroller module, used for outputting enable control signal and PWM wave signal; A level conversion module, connected to the microcontroller module, for performing level conversion on the PWM wave signal according to the enable control signal and outputting the level conversion; The microcontroller module comprises: A timing unit, used for performing periodic timing and obtaining a timing value; a clearing unit connected to the timing unit, and configured to clear the timing value if the timing value reaches a duration threshold when the microcontroller module is not in a breakpoint state; The microcontrol module is also used to flip the level of the enable control signal if the timing value reaches the timing cycle of the timing unit, so that the level conversion module stops the level conversion and output of the PWM wave signal; wherein the duration threshold is less than the timing cycle.

2. The PWM wave blocking circuit according to claim 1, characterized in that: The PWM wave blocking circuit also includes: The latch module is connected to the microcontroller module and the level conversion module respectively, and is used to latch and output the enable control signal after the level is flipped.

3. The PWM wave blocking circuit according to claim 2, characterized in that: The latch module includes a D flip-flop; a power supply end of the D flip-flop is used to receive a power supply voltage; a clear end of the D flip-flop is connected to the microcontroller module, and an output end of the D flip-flop is connected to the level conversion module.

4. The PWM wave blocking circuit according to claim 3, characterized in that: The latch module also includes a resistor R1 and a capacitor C1; the first end of the resistor R1, the first end of the capacitor C1 and the power supply end of the D trigger are connected in common, and the second end of the resistor R1 is connected to the preset end of the D trigger for receiving a reset signal; the second end of the capacitor C1 is connected to the ground end; when the D trigger is powered on, the reset signal is set to maintain a low level for a preset period of time and then be pulled up to a high level.

5. The PWM wave blocking circuit according to claim 4, characterized in that: The reset signal is output by the microcontroller module.

6. The PWM wave blocking circuit according to claim 1, characterized in that: The duration threshold is equal to the carrier period of the carrier signal, and the timing period is equal to 1.5 times of the duration threshold.

7. The PWM wave blocking circuit according to claim 3, characterized in that: The PWM wave blocking circuit also includes: The inversion module is connected to the clearing end of the microcontrol module and the D flip-flop respectively, and is used for inverting the enable control signal output by the microcontrol module and then outputting it to the D flip-flop.

8. The PWM wave blocking circuit according to claim 7, characterized in that: The inverting module includes a resistor R2, a resistor R3, a capacitor C2, a capacitor C3 and an inverter; the first end of the resistor R2 is used to receive a first power supply voltage, the second end of the resistor R2 is respectively connected to the first end of the resistor R3 and the micro-control module, and the second end of the resistor R3 is respectively connected to the first end of the capacitor C2 and the input end of the inverter; the first end of the capacitor C3 is connected to the ground end, and the second end of the capacitor C3 is commonly connected to the power supply end of the inverter for jointly receiving the first power supply voltage; the second end of the capacitor C2 is commonly connected to the common end of the inverter and is connected to the ground end.

9. The PWM wave blocking circuit according to claim 3, characterized in that: The level conversion module includes: multiple input resistors, capacitors C4, capacitors C5, resistors R4 and a level converter; the first end of each input resistor is connected to the ground end, and the second end of each input resistor is connected to each input end of the level converter in a one-to-one correspondence; the first end of the capacitor C4, the first end of the capacitor C5 and the power supply end of the level converter are commonly connected to receive a second power supply voltage; the enable end of the level converter and the first end of the resistor R4 are respectively connected to the output end of the D trigger, and the second end of the resistor R4 is connected to the ground end; the second end of the capacitor C4 and the second end of the capacitor C5 are respectively connected to the ground end.

10. A PWM wave driving circuit, characterized in that: The PWM wave blocking circuit according to any one of claims 1 to 9 further comprises: The power driving circuit is connected to the level conversion module and is used to generate a motor driving signal according to the PWM wave signal after level conversion.

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