Level shift circuit and GaN power switch device driving circuit
By connecting the low-voltage NMOS tubes in series with each other in the level shift circuit, the problems of large parasitic capacitance and slow signal transmission speed in the existing level shift circuit are solved, and high transmission speed and strong immunity are achieved.
Patent Information
- Application Number
- CN202411761699.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-03
- Publication Date
- 2025-03-25
AI Technical Summary
The existing level shift circuit has a large parasitic capacitance, which slows down the signal transmission speed and reduces the immunity of floating power rails dV/dt.
A level shift circuit is designed to realize signal transmission from low-side to high-side by connecting low-voltage NMOS tubes in series, and reduce parasitic capacitance to ground while replacing high-voltage N-type transverse diffusion metal oxide semiconductor (LDMOS).
It realizes high transmission speed, improves the immunity of floating power rail dV/dt, and reduces the single-cycle net charge loss of floating power rail.
Smart Images
Figure CN119696570A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of integrated circuits, and in particular to a level shift circuit and a GaN power switch device driving circuit. Background Art
[0002] The level shift circuit is a circuit module that converts low-voltage domain signals into high-voltage domain signals. It is mainly used to ensure the normal operation of power devices and their drive circuits. However, the parasitic capacitance of the commonly used level shift circuits is large, which can easily slow down the signal transmission speed and reduce the anti-interference ability to the floating power rail dV / dt. Summary of the invention
[0003] In order to at least overcome the above-mentioned deficiencies in the prior art, the purpose of the present application is to provide a level shift circuit and a GaN power switch device driving circuit.
[0004] In a first aspect, an embodiment of the present application provides a level shift circuit, the level shift circuit comprising: a pulse generation module, a first signal transmission module, a second signal transmission module, a first signal conversion module, a second signal conversion module and a signal latch module;
[0005] The pulse generating module comprises a signal input terminal, a first pulse output terminal and a second pulse output terminal; the first pulse output terminal is connected to the first signal transmission module, the second pulse output terminal is connected to the second signal transmission module, the first pulse output terminal is used to output a first pulse signal to the first signal transmission module when a first change edge of the signal inputted from the signal input terminal is detected, and the second pulse output terminal is used to output a second pulse signal to the second signal transmission module when a second change edge of the signal inputted from the signal input terminal is detected; the first change edge and the second change edge are respectively one of a rising edge and a falling edge;
[0006] The first signal transmission module includes at least two first switch devices connected in series; the second signal transmission module includes at least two second switch devices connected in series; the first switch device and the second switch device include low-voltage NMOS tubes;
[0007] The first signal transmission module is connected to the first signal conversion module, and the second signal transmission module is connected to the second signal conversion module;
[0008] The first signal transmission module and the first signal conversion module are used to convert the first pulse signal from a low voltage domain to a high voltage domain, and the second signal transmission module and the second signal conversion module are used to convert the second pulse signal from a low voltage domain to a high voltage domain;
[0009] The first signal conversion module and the second signal conversion module are respectively connected to the signal latch module, and the signal latch module is used to output corresponding square wave signals according to the converted first pulse signal and the second pulse signal.
[0010] In a possible implementation, the level shift circuit further includes a clamp protection module; the clamp protection module includes a plurality of diode series units, and the plurality of diode series units are respectively connected to the first switch device or the second switch device;
[0011] The diode series connection unit includes at least two diodes connected in series.
[0012] In a possible implementation, the first signal transmission module includes a first low-voltage NMOS transistor and a second low-voltage NMOS transistor connected in series, and the second signal transmission module includes a third low-voltage NMOS transistor and a fourth low-voltage NMOS transistor connected in series;
[0013] The clamping protection module includes a first diode series unit, a second diode series unit, a third diode series unit and a fourth diode series unit;
[0014] The input end of the first diode series unit is connected to the drain of the first low-voltage NMOS tube, and the output end of the first diode series unit is connected to the source of the first low-voltage NMOS tube; the input end of the second diode series unit is connected to the drain of the second low-voltage NMOS tube, and the output end of the second diode series unit is connected to the source of the second low-voltage NMOS tube; the input end of the third diode series unit is connected to the drain of the third low-voltage NMOS tube, and the output end of the third diode series unit is connected to the source of the third low-voltage NMOS tube; the input end of the fourth diode series unit is connected to the drain of the fourth low-voltage NMOS tube, and the output end of the fourth diode series unit is connected to the source of the fourth low-voltage NMOS tube.
[0015] In a possible implementation, the source of the first low-voltage NMOS tube and the source of the third low-voltage NMOS tube are grounded; the gate of the first low-voltage NMOS tube is connected to the first pulse output end, and the gate of the third low-voltage NMOS tube is connected to the second pulse output end; the drain of the first low-voltage NMOS tube is connected to the source of the second low-voltage NMOS tube, the drain of the third low-voltage NMOS tube is connected to the source of the fourth low-voltage NMOS tube, the gate of the second low-voltage NMOS tube and the gate of the fourth low-voltage NMOS tube are connected to a low-voltage power rail, the drain of the second low-voltage NMOS tube is connected to the first signal conversion module, and the drain of the fourth low-voltage NMOS tube is connected to the second signal conversion module.
[0016] In a possible implementation, an operating voltage of the first low-voltage NMOS transistor, the second low-voltage NMOS transistor, the third low-voltage NMOS transistor, and the fourth low-voltage NMOS transistor includes 5V.
[0017] In a possible implementation, the first signal conversion module includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube and a second NMOS tube; the second signal conversion module includes a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a third NMOS tube and a fourth NMOS tube;
[0018] The gate of the first PMOS tube, the gate of the second PMOS tube, and the gate of the third PMOS tube are connected to the output end of the first signal transmission module, the gate of the fourth PMOS tube, the gate of the fifth PMOS tube, and the gate of the sixth PMOS tube are connected to the output end of the second signal transmission module, the source of the first PMOS tube, the source of the second PMOS tube, the source of the third PMOS tube, the source of the fourth PMOS tube, the source of the fifth PMOS tube, and the source of the sixth PMOS tube are connected to a floating power supply, the gate of the first PMOS tube is connected to the drain of the first PMOS tube, the gate of the fourth PMOS tube is connected to the drain of the fourth PMOS tube, the source of the first NMOS tube, The source of the second NMOS tube, the source of the third NMOS tube and the source of the fourth NMOS tube are connected to the floating ground, the gate of the first NMOS tube and the gate of the second NMOS tube are connected to the drain of the second PMOS tube, the gate of the third NMOS tube and the gate of the fourth NMOS tube are connected to the drain of the fifth PMOS tube, the drain of the third PMOS tube and the drain of the fourth NMOS tube are connected to the output end of the level shift circuit, the drain of the sixth PMOS tube and the drain of the second NMOS tube are connected to the reverse output end of the level shift circuit, the gate of the first NMOS tube is connected to the drain of the first NMOS tube, and the gate of the third NMOS tube is connected to the drain of the third NMOS tube.
[0019] In a possible implementation, the pulse generating module includes a first pulse generating unit and a second pulse generating unit;
[0020] The first pulse generating unit comprises a first inverter, a second inverter, a third inverter and a first NOR gate; the input end of the level shift circuit is connected to the first input end of the first NOR gate via the first inverter, the second inverter and the third inverter in sequence, the input end of the level shift circuit is connected to the second input end of the first NOR gate, and the output end of the first NOR gate is connected to the first pulse output end of the pulse generating module;
[0021] The second pulse generating unit includes a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter and a second NOR gate; the input end of the level shift circuit is connected to the first input end of the second NOR gate via the fourth inverter, the fifth inverter, the sixth inverter and the seventh inverter in sequence, the input end of the level shift circuit is connected to the second input end of the second NOR gate via the fourth inverter, and the output end of the second NOR gate is connected to the second pulse output end of the pulse generating module.
[0022] In a possible implementation, the signal latch module includes an eighth inverter and a ninth inverter;
[0023] The input end of the eighth inverter and the output end of the ninth inverter are connected to the inverting output end of the level shift circuit, and the output end of the eighth inverter and the input end of the ninth inverter are connected to the output end of the level shift circuit.
[0024] In a possible implementation, the level shift circuit has a floating power rail forward dV / dt resistance capability greater than 15 V / ns.
[0025] In a second aspect, an embodiment of the present application further provides a GaN power switch device driving circuit, wherein the GaN power switch device driving circuit includes the level shift circuit described in the first aspect above.
[0026] Based on any of the above aspects, the level shift circuit and GaN power switch device driving circuit provided in the embodiments of the present application can realize signal transmission from the low side to the high side by connecting low-voltage NMOS tubes in series. While replacing the high-voltage N-type laterally diffused metal oxide semiconductor (Laterally Diffused Metal Oxide Semiconductor, LDMOS), the parasitic capacitance to the ground can be reduced, and the transmission speed is high. The anti-interference capability to the floating power rail dV / dt can be improved, and the net charge loss of the floating power rail in a single cycle can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.
[0028] Figure 1 It is a structural schematic diagram of a level shift circuit in the prior art;
[0029] Figure 2 One of the structural schematic diagrams of the level shift circuit provided in this embodiment;
[0030] Figure 3 A second structural schematic diagram of the level shift circuit provided in this embodiment;
[0031] Figure 4 A cross-sectional schematic diagram of a diode provided in this embodiment;
[0032] Figure 5 A schematic diagram of the structure of the first signal conversion module and the second signal conversion module provided in this embodiment;
[0033] Figure 6 A schematic diagram of the structure of the pulse generating module provided in this embodiment;
[0034] Figure 7 A schematic diagram of the structure of the signal latch module provided in this embodiment;
[0035] Figure 8 A schematic diagram of a simulation of the output rising edge delay characteristics of the level shift circuit provided in this embodiment;
[0036] Fig. 9 A schematic diagram of a simulation of the output falling edge delay characteristics of the level shift circuit provided in this embodiment;
[0037] Fig.10 A schematic diagram of simulation of the floating power rail dV / dt interference immunity capability of the level shift circuit provided in this embodiment;
[0038] Fig.11 This is a schematic diagram of the structure of the GaN power switch device driving circuit provided in this embodiment.
[0039] Icon: 100-pulse generating module; 110-first pulse generating unit; 120-second pulse generating unit; 210-first signal transmission module; 220-second signal transmission module; 310-first signal conversion module; 320-second signal conversion module; 400-signal latch module; 500-clamping protection module; 510-first diode series unit; 520-second diode series unit; 530-third diode series unit; 540-fourth diode series unit. DETAILED DESCRIPTION
[0040] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.
[0041] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0042] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.
[0043] In the description of this application, it should be noted that the terms "upper", "lower", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the application is usually placed when in use, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.
[0044] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.
[0045] The inventor has found that Figure 1 , Figure 1An example of a high-voltage active coupling type level shift circuit in the prior art is provided. During the signal transmission process, the low-side portion of the high-voltage active coupling type level shift circuit can generate a short pulse through the pulse generation module 100' and turn on the high-voltage N-type laterally diffused metal oxide semiconductor (Laterally Diffused Metal Oxide Semiconductor, LDMOS). The high-side portion of the high-voltage active coupling type level shift circuit can act on the signal latch module 400' through a two-stage current mirror to achieve signal transmission and update. After the signal transmission is completed, the high-voltage N-type laterally diffused metal oxide semiconductor (Laterally Diffused Metal Oxide Semiconductor, LDMOS) is turned off, and the signal latch module 400' latches the updated signal until the next signal transmission state comes.
[0046] Due to the presence of the drain drift region, the area of MND1 and MND2 is usually larger than that of the low-voltage NMOS tube, which introduces larger drain and gate parasitic capacitances, resulting in larger parasitic capacitances C to ground at nodes A', B', C' and D'. PA '、C PB '、C PC ' and C PD ', which results in slower signaling and reduced immunity to floating supply rail dV / dt.
[0047] In view of this, this embodiment provides a solution that can solve the above-mentioned problem, and the solution provided by this embodiment is described in detail below.
[0048] Please refer to Figure 2 , Figure 2 The level shift circuit provided in this embodiment may include a pulse generating module 100, a first signal transmission module 210, a second signal transmission module 220, a first signal conversion module 310, a second signal conversion module 320 and a signal latch module 400.
[0049] The pulse generating module 100 may include a signal input terminal, a first pulse output terminal, and a second pulse output terminal. The first pulse output terminal may be connected to the first signal transmission module 210, the second pulse output terminal may be connected to the second signal transmission module 220, the signal input terminal may be used to input a pulse width modulation (PWM) signal, the first pulse output terminal may be used to output a first pulse signal to the first signal transmission module 210 when a first change edge of the signal inputted from the signal input terminal is detected, and the second pulse output terminal may be used to output a second pulse signal to the second signal transmission module 220 when a second change edge of the signal inputted from the signal input terminal is detected. The first change edge and the second change edge may be one of a rising edge and a falling edge, respectively.
[0050] In this embodiment, during the signal transmission process, when the pulse width modulation (PWM) signal inputted from the signal input terminal changes from a high level to a low level, i.e., when a falling edge comes, the first pulse output terminal can output the first pulse signal; when the pulse width modulation (PWM) signal inputted from the signal input terminal changes from a low level to a high level, i.e., when a rising edge comes, the second pulse output terminal can output the second pulse signal. Both the first pulse signal and the second pulse signal are short pulse signals.
[0051] The first signal transmission module 210 may include at least two first switch devices connected in series; the second signal transmission module 220 may include at least two second switch devices connected in series. Both the first switch device and the second switch device may be low-voltage NMOS tubes.
[0052] In this embodiment, the first signal transmission module 210 may include at least two identical low-voltage NMOS transistors, and at least two low-voltage NMOS transistors are connected in series. The second signal transmission module 220 may also include at least two identical low-voltage NMOS transistors, and at least two low-voltage NMOS transistors are connected in series. Specifically, the number of low-voltage NMOS transistors in the first signal transmission module 210 is the same as the number of low-voltage NMOS transistors in the second signal transmission module 220.
[0053] The first signal transmission module 210 may be connected to the first signal conversion module 310, and the second signal transmission module 220 may be connected to the second signal conversion module 320. The first signal transmission module 210 and the first signal conversion module 310 may be used to convert the first pulse signal from a low voltage domain to a high voltage domain, and the second signal transmission module 220 and the second signal conversion module 320 may be used to convert the second pulse signal from a low voltage domain to a high voltage domain.
[0054] The first signal conversion module 310 and the second signal conversion module 320 may be connected to the signal latch module 400 respectively, and the signal latch module 400 may be used to output corresponding square wave signals according to the converted first pulse signal and the second pulse signal.
[0055] In this embodiment, when the pulse width modulation (PWM) signal input by the signal input end changes from a high level to a low level, that is, when a falling edge comes, the first pulse output end can output the first pulse signal to the first signal transmission module 210, and the first signal transmission module 210 can transmit the first pulse signal to the first signal conversion module 310. The first signal conversion module 310 can convert the first pulse signal from a low voltage domain to a high voltage domain, and input the first pulse signal in the high voltage domain to the signal latch module 400. The signal latch module 400 can latch the output signal as a high level. When the pulse width modulation (PWM) signal inputted by the signal input terminal changes from a low level to a high level, that is, when a rising edge comes, the second pulse output terminal can output the second pulse signal to the second signal transmission module 220, and the second signal transmission module 220 can transmit the second pulse signal to the second signal conversion module 320, and the second signal conversion module 320 can convert the second pulse signal from a low voltage domain to a high voltage domain, and input the second pulse signal of the high voltage domain to the signal latch module 400, and the signal latch module 400 can latch the output signal as a low level.
[0056] In the above structure, by connecting low-voltage NMOS tubes in series, signal transmission from the low side to the high side can be achieved. While replacing the high-voltage N-type laterally diffused metal oxide semiconductor (LDMOS), the parasitic capacitance to the ground can be reduced, and the transmission speed is high. The anti-interference ability to the floating power rail dV / dt can be improved, and the single-cycle net charge loss of the floating power rail can be reduced.
[0057] In addition, the level shift circuit provided in this embodiment can be applied to a driving circuit with a maximum voltage of 10V.
[0058] In one possible implementation, see Figure 3 The level shift circuit may further include a clamp protection module 500. The clamp protection module 500 may include a plurality of diode series units, and the plurality of diode series units may be connected to the first switch device or the second switch device respectively. The diode series unit may include at least two diodes connected in series.
[0059] In this embodiment, each of the first switching devices and each of the second switching devices can be connected to a diode series unit, the input end of the diode series unit is connected to the drain of the first switching device or the second switching device, and the output end of the diode series unit is connected to the source of the first switching device or the second switching device. The diode series unit can be used to prevent the drain-source voltage of the first switching device and the second switching device from exceeding the rated value.
[0060] The diode series unit may be formed by at least two diodes connected in series. The series connection of diodes refers to electrically connecting the cathode of one diode to the anode of another diode. The cathode of the diodes connected in series may be electrically connected to the drain of the first switching device or the second switching device, and the anode of the diodes connected in series may be electrically connected to the source of the first switching device or the second switching device. For example, each of the diode series units may include two diodes connected in series, wherein the cathode of the first diode may be connected to the anode of the second diode, the anode of the first diode may be electrically connected to the source of the first switching device or the second switching device, and the cathode of the second diode may be electrically connected to the drain of the first switching device or the second switching device.
[0061] It should be noted that the number of diodes connected in series in the diode series unit can be determined according to the rated values of the drain-source voltages of the first switch device and the second switch device. By reasonably setting the number of diodes connected in series in the diode series unit, it can be ensured that the clamping voltage of the diode series unit is lower than the rated values of the drain-source voltages of the first switch device and the second switch device. When the rated values of the drain-source voltages of the first switch device and the second switch device are large, the level shift circuit may also not include the clamping protection module 500.
[0062] Please refer to Figure 4 , Figure 4The cross-sectional schematic diagram of the diode provided in the example embodiment shows that the anode area of the diode in the diode series unit is smaller than the drain area of the NLDMOS. Therefore, compared with the drain-to-ground parasitic capacitance of the high-voltage N-type laterally diffused metal oxide semiconductor (LDMOS) in the prior art, the parasitic capacitance between the anode and cathode of the diode in the diode series unit, as well as the parasitic capacitance between the anode and cathode and the ground are smaller.
[0063] In one possible implementation, please refer again to Figure 3 The first signal transmission module 210 may include a first low-voltage NMOS transistor MN1 and a second low-voltage NMOS transistor MN2 connected in series, and the second signal transmission module 220 may include a third low-voltage NMOS transistor MN3 and a fourth low-voltage NMOS transistor MN4 connected in series.
[0064] The clamp protection module 500 may include a first diode series unit 510 , a second diode series unit 520 , a third diode series unit 530 and a fourth diode series unit 540 .
[0065] The input end of the first diode series unit 510 can be connected to the drain of the first low-voltage NMOS transistor MN1, and the output end of the first diode series unit 510 can be connected to the source of the first low-voltage NMOS transistor MN1. The input end of the second diode series unit 520 can be connected to the drain of the second low-voltage NMOS transistor MN2, and the output end of the second diode series unit 520 can be connected to the source of the second low-voltage NMOS transistor MN2. The input end of the third diode series unit 530 can be connected to the drain of the third low-voltage NMOS transistor MN3, and the output end of the third diode series unit 530 can be connected to the source of the third low-voltage NMOS transistor MN3. The input end of the fourth diode series unit 540 can be connected to the drain of the fourth low-voltage NMOS transistor MN4, and the output end of the fourth diode series unit 540 can be connected to the source of the fourth low-voltage NMOS transistor MN4.
[0066] In this embodiment, when the first signal transmission module 210 and the second signal transmission module 220 each include only two low-voltage NMOS tubes connected in series, and the clamping protection module 500 includes four diode series units, a node E is included between the first low-voltage NMOS tube MN1 and the second low-voltage NMOS tube MN2 connected in series, and the voltage of the node E does not exceed the clamping voltage of the first diode series unit 510, and a node F is included between the third low-voltage NMOS tube MN3 and the fourth low-voltage NMOS tube MN4 connected in series, and the voltage of the node F does not exceed the clamping voltage of the third diode series unit 530.
[0067] The clamping voltage of the first diode series unit 510 is less than the rated value of the drain-source voltage of the first low-voltage NMOS tube MN1, the clamping voltage of the second diode series unit 520 is less than the rated value of the drain-source voltage of the second low-voltage NMOS tube MN2, the clamping voltage of the third diode series unit 530 is less than the rated value of the drain-source voltage of the third low-voltage NMOS tube MN3, and the clamping voltage of the fourth diode series unit 540 is less than the rated value of the drain-source voltage of the fourth low-voltage NMOS tube MN4. In this way, it can be ensured that the drain-source voltages of the first low-voltage NMOS tube MN1, the second low-voltage NMOS tube MN2, the third low-voltage NMOS tube MN3 and the fourth low-voltage NMOS tube MN4 are not over-voltaged under all working conditions. In addition, when there is no short pulse effect and the high-side floating power rail remains constant, the first diode series unit 510 and the third diode series unit 530 are not conducting; when there is no short pulse effect and the high-side floating ground is constant at 5V, the second diode series unit 520 and the fourth diode series unit 540 are not conducting, thus ensuring zero static power consumption of the circuit.
[0068] In one possible implementation, please refer again to Figure 3 , the source of the first low-voltage NMOS tube MN1 and the source of the third low-voltage NMOS tube MN3 are grounded. The gate of the first low-voltage NMOS tube MN1 can be connected to the first pulse output terminal, and the gate of the third low-voltage NMOS tube MN3 can be connected to the second pulse output terminal. The drain of the first low-voltage NMOS tube MN1 can be connected to the source of the second low-voltage NMOS tube MN2, and the drain of the third low-voltage NMOS tube MN3 can be connected to the source of the fourth low-voltage NMOS tube MN4. The gate of the second low-voltage NMOS tube MN2 and the gate of the fourth low-voltage NMOS tube MN4 can be connected to the low-voltage power rail respectively, the drain of the second low-voltage NMOS tube MN2 can be connected to the first signal conversion module 310, and the drain of the fourth low-voltage NMOS tube MN4 can be connected to the second signal conversion module 320.
[0069] In this embodiment, when the maximum floating power supply voltage is 2V DD When the low-voltage NMOS transistors in the first signal transmission module 210 and the second signal transmission module 220 are not over-voltage in all working states, and the low-voltage NMOS transistors can be used for voltage resistance by connecting them in series. The voltage of the low-voltage power rail can be 5V.
[0070] In addition, the drain and body areas of the low-voltage NMOS tubes in the first signal transmission module 210 and the second signal transmission module 220 are smaller than the drain area of the NLDMOS. Therefore, compared with the drain-to-ground parasitic capacitance of the high-voltage N-type laterally diffused metal oxide semiconductor (Laterally Diffused Metal Oxide Semiconductor, LDMOS) in the prior art, the drain-source parasitic capacitance of the low-voltage NMOS tubes in the first signal transmission module 210 and the second signal transmission module 220, as well as the drain-source parasitic capacitance and the drain-source parasitic capacitance to ground are smaller. Compared with the gate-to-ground parasitic capacitance of the high-voltage N-type laterally diffused metal oxide semiconductor (Laterally Diffused Metal Oxide Semiconductor, LDMOS) in the prior art, the gate-to-ground parasitic capacitance of the low-voltage NMOS tubes in the first signal transmission module 210 and the second signal transmission module 220 is also smaller. That is, the parasitic capacitance C to ground of nodes A, B, C, and D is smaller than that of nodes A, B, C, and D. PA , C PB , C PC and C PD Also smaller.
[0071] In a possible implementation manner, the operating voltage of the first low-voltage NMOS transistor MN1, the second low-voltage NMOS transistor MN2, the third low-voltage NMOS transistor MN3, and the fourth low-voltage NMOS transistor MN4 may be 5V.
[0072] In this embodiment, the first signal transmission module 210 and the second signal transmission module 220 can both be composed of 5V NMOS tubes. Since the low-voltage NMOS tubes in the first signal transmission module 210 and the second signal transmission module 220 are exactly the same, the diode series units corresponding to each NMOS tube are exactly the same, that is, the number of diodes connected in series in each diode series unit is the same.
[0073] In one possible implementation, see Figure 5The first signal conversion module 310 may include a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NMOS transistor MN5, and a second NMOS transistor MN6. The second signal conversion module 320 may include a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a third NMOS transistor MN7, and a fourth NMOS transistor MN8.
[0074] The gate of the first PMOS tube MP1, the gate of the second PMOS tube MP2, and the gate of the third PMOS tube MP3 can be connected to the output end of the first signal transmission module 210, the gate of the fourth PMOS tube MP4, the gate of the fifth PMOS tube MP5, and the gate of the sixth PMOS tube MP6 can be connected to the output end of the second signal transmission module 220, the source of the first PMOS tube MP1, the source of the second PMOS tube MP2, the source of the third PMOS tube MP3, the source of the fourth PMOS tube MP4, the source of the fifth PMOS tube MP5, and the source of the sixth PMOS tube MP6 can be connected to a floating power supply, and the gate of the first PMOS tube MP1 can be connected to the output end of the first PMOS tube MP4. The gate of the fourth PMOS tube MP4 can be connected to the drain of the fourth PMOS tube MP4, the source of the first NMOS tube MN5, the source of the second NMOS tube MN6, the source of the third NMOS tube MN7 and the source of the fourth NMOS tube MN8 can be connected to the floating ground, the gate of the first NMOS tube MN5 and the gate of the second NMOS tube MN6 can be connected to the drain of the second PMOS tube MP2, the gate of the third NMOS tube MN7 and the gate of the fourth NMOS tube MN8 can be connected to the drain of the fifth PMOS tube MP5, the drain of the third PMOS tube MP3 and the drain of the fourth NMOS tube MN8 can be connected to the output terminal V O_LS The drain of the sixth PMOS tube MP6 and the drain of the second NMOS tube MN6 can be connected to the reverse output end of the level shift circuit, the gate of the first NMOS tube MN5 can be connected to the drain of the first NMOS tube MN5, and the gate of the third NMOS tube MN7 can be connected to the drain of the third NMOS tube MN7.
[0075] In this embodiment, when the pulse width modulation (PWM) signal inputted from the signal input terminal changes from a high level to a low level, that is, when a falling edge comes, the first pulse output terminal can output the first pulse signal, so that the first low-voltage NMOS tube MN1 and the second low-voltage NMOS tube MN2 are turned on, and after the first low-voltage NMOS tube MN1 and the second low-voltage NMOS tube MN2 are turned on, the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the first NMOS tube MN5 and the second NMOS tube MN6 are all turned on, and the current flowing through the third PMOS tube MP3 turns the output terminal V O_LS The potential of the level shift circuit is pulled up, and the current flowing through the second NMOS tube MN6 increases the inverting output terminal V O_LS- The potential of the level shift circuit is pulled low, and the output terminal V O_LS When the first pulse signal disappears, the output terminal V O_LS Still output high level.
[0076] When the pulse width modulation (PWM) signal inputted from the signal input terminal changes from a low level to a high level, that is, when a rising edge comes, the second pulse output terminal can output the second pulse signal to turn on the third low-voltage NMOS tube MN3 and the fourth low-voltage NMOS tube MN4. After the third low-voltage NMOS tube MN3 and the fourth low-voltage NMOS tube MN4 are turned on, the fourth PMOS tube MP4, the fifth PMOS tube MP5, the sixth PMOS tube MP6, the third NMOS tube MN7 and the fourth NMOS tube MN8 are all turned on. The current flowing through the sixth PMOS tube MP6 turns the inverting output terminal V O_LS- The potential of the output terminal V O_LS The potential of the level shift circuit is pulled low, and the output terminal V O_LS When the first pulse signal disappears, the output terminal V O_LS Still outputs low level.
[0077] In addition, the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the fourth PMOS tube MP4, the fifth PMOS tube MP5 and the sixth PMOS tube MP6 can all be 5V PMOS tubes, and the first NMOS tube MN5, the second NMOS tube MN6, the third NMOS tube MN7 and the fourth NMOS tube MN8 can all be 5V NMOS tubes.
[0078] In one possible implementation, see Figure 6 , the pulse generating module 100 may include a first pulse generating unit 110 and a second pulse generating unit 120 .
[0079] The first pulse generating unit 110 may include a first inverter Inv1, a second inverter Inv2, a third inverter Inv3 and a first NOR gate Nor1. The input end of the level shift circuit may be connected to the first input end of the first NOR gate Nor1 via the first inverter Inv1, the second inverter Inv2 and the third inverter Inv3 in sequence, the input end of the level shift circuit may be connected to the second input end of the first NOR gate Nor1, and the output end of the first NOR gate Nor1 may be connected to the first pulse output end of the pulse generating module 100.
[0080] The second pulse generating unit 120 may include a fourth inverter Inv4, a fifth inverter Inv5, a sixth inverter Inv6, a seventh inverter Inv7 and a second NOR gate Nor2. The input end of the level shift circuit may be connected to the first input end of the second NOR gate Nor2 via the fourth inverter Inv4, the fifth inverter Inv5, the sixth inverter Inv6 and the seventh inverter Inv7 in sequence, the input end of the level shift circuit may be connected to the second input end of the second NOR gate Nor2 via the fourth inverter Inv4, and the output end of the second NOR gate Nor2 may be connected to the second pulse output end of the pulse generating module 100.
[0081] In this embodiment, the first pulse generating unit 110 can convert the pulse width modulation (PWM) signal inputted at the signal input terminal into the first pulse signal when the pulse width modulation (PWM) signal jumps from a high level to a low level, and controls the opening and closing of the first low-voltage NMOS tube MN1 and the second low-voltage NMOS tube MN2. The second pulse generating unit 120 can convert the pulse width modulation (PWM) signal inputted at the signal input terminal into the second pulse signal when the pulse width modulation (PWM) signal jumps from a low level to a high level, and controls the opening and closing of the third low-voltage NMOS tube MN3 and the fourth low-voltage NMOS tube MN4.
[0082] In one possible implementation, see Figure 7 , the signal latch module 400 may include an eighth inverter Inv8 and a ninth inverter Inv9.
[0083] The input end of the eighth inverter Inv8 and the output end of the ninth inverter Inv9 can be connected to the inverting output end V O_LS- The output end of the eighth inverter Inv8 and the input end of the ninth inverter Inv9 can be connected to the output end V O_LS connect.
[0084] In a possible implementation, the level shift circuit has a floating power rail forward dV / dt resistance capability greater than 15 V / ns.
[0085] Please refer to Figure 8 , Figure 8 The schematic diagram of the output rising edge delay characteristics simulation of the level shift circuit provided by this embodiment and the high voltage active coupling type level shift circuit in the prior art is illustrated. When the load capacitance is about 140fF, V OUTH1 =V OUTH2 = 0V, the rising edge transmission delay of the level shift circuit provided by this embodiment is only 370ps, which is 98ps shorter than the rising edge transmission delay of the high voltage active coupling type level shift circuit in the prior art. PA The floating power rail net charge loss in a single cycle is smaller. When the floating power rail bootstrap capacitance is equal, the level shift circuit outputs a rising stage. For the floating power rail voltage, the level shift circuit provided by this embodiment is 1V higher than the high-voltage active coupling type level shift circuit in the prior art.
[0086] Please refer to Fig. 9 , Fig. 9 The schematic diagram of the output falling edge delay characteristics simulation of the level shift circuit provided by this embodiment and the high voltage active coupling type level shift circuit in the prior art is illustrated. When the load capacitance is about 140fF, V OUTH1 =V OUTH2 =5V, the falling edge transmission delay of the level shift circuit provided in this embodiment is only 327ps. On the signal transmission path, the difference between the delay of the signal reaching node D and the delay of the signal reaching node d is 21ps, and the difference between the delay of the signal reaching node B and the delay of the signal reaching node b is 39ps. O_LS When the voltage drop range is larger and the drop time is longer, the falling edge transmission delay of the level shift circuit provided in this embodiment can still be 21.5ps shorter than the falling edge transmission delay of the high-voltage active coupling level shift circuit in the prior art. PB The floating power rail net charge loss in a single cycle is smaller. When the floating power rail bootstrap capacitance is equal, in the output falling stage of the level shift circuit, for the floating power rail voltage, the level shift circuit provided by this embodiment is 1.3V higher than the high-voltage active coupling type level shift circuit in the prior art.
[0087] Please refer to Fig.10 , Fig.10 The schematic diagram of the simulation of the floating power rail dV / dt immunity of the level shift circuit provided by this embodiment and the high-voltage active coupling type level shift circuit in the prior art is illustrated. During the rising process of the floating power rail, the floating power rail forward dV / dt immunity of the level shift circuit provided by this embodiment is greater than 15V / ns, while the floating power rail forward dV / dt immunity of the high-voltage active coupling type level shift circuit in the prior art is less than 11V / ns.
[0088] An embodiment of the present application further provides a GaN power switch device driving circuit, and the GaN power switch device driving circuit may include the level shift circuit provided in the present application.
[0089] Please refer to Fig.11 The GaN power switch device driving circuit may include a driving output stage high-side pull-up NMOS tube MN UP , drive the output stage low side pull-down NMOS tube MN DOWN, high-side buffer, low-side buffer, level shift circuit, bootstrap switch, bootstrap control circuit and bootstrap capacitor C. The GaN power switch device driving circuit adopts dual NMOS tube as output stage, which can save the area of driving stage and output parasitic capacitance, and is conducive to further improving the driving transmission speed and the switching speed of power GaN tube. Among them, the level shift circuit can be used to convert the signal input terminal V IN The input drive control signal is converted to V OUTH ~V BOOT voltage domain, and after passing through the high-side buffer, controls the high-side pull-up NMOS tube MN of the driving output stage UP switch.
[0090] In summary, the present embodiment provides a level shift circuit and a GaN power switch device driving circuit. By connecting low-voltage NMOS tubes in series, signal transmission from the low side to the high side can be achieved. While replacing the high-voltage N-type laterally diffused metal oxide semiconductor (LDMOS), the parasitic capacitance to the ground can be reduced, and the transmission speed is high. The anti-interference capability to the floating power rail dV / dt can be improved, and the single-cycle net charge loss of the floating power rail can be reduced.
[0091] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0092] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A level shift circuit, characterized in that: include: A pulse generating module, a first signal transmitting module, a second signal transmitting module, a first signal converting module, a second signal converting module and a signal latching module; The pulse generating module comprises a signal input terminal, a first pulse output terminal and a second pulse output terminal; the first pulse output terminal is connected to the first signal transmission module, the second pulse output terminal is connected to the second signal transmission module, the first pulse output terminal is used to output a first pulse signal to the first signal transmission module when a first change edge of the signal inputted from the signal input terminal is detected, and the second pulse output terminal is used to output a second pulse signal to the second signal transmission module when a second change edge of the signal inputted from the signal input terminal is detected; the first change edge and the second change edge are respectively one of a rising edge and a falling edge; The first signal transmission module includes at least two first switch devices connected in series; the second signal transmission module includes at least two second switch devices connected in series; the first switch device and the second switch device include low-voltage NMOS tubes; The first signal transmission module is connected to the first signal conversion module, and the second signal transmission module is connected to the second signal conversion module; The first signal transmission module and the first signal conversion module are used to convert the first pulse signal from a low voltage domain to a high voltage domain, and the second signal transmission module and the second signal conversion module are used to convert the second pulse signal from a low voltage domain to a high voltage domain; The first signal conversion module and the second signal conversion module are respectively connected to the signal latch module, and the signal latch module is used to output corresponding square wave signals according to the converted first pulse signal and the second pulse signal.
2. The level shift circuit according to claim 1, characterized in that: The level shift circuit further includes a clamp protection module; the clamp protection module includes a plurality of diode series units, and the plurality of diode series units are respectively connected to the first switch device or the second switch device; The diode series connection unit includes at least two diodes connected in series.
3. The level shift circuit according to claim 2, characterized in that: The first signal transmission module includes a first low-voltage NMOS transistor and a second low-voltage NMOS transistor connected in series, and the second signal transmission module includes a third low-voltage NMOS transistor and a fourth low-voltage NMOS transistor connected in series; The clamp protection module includes a first diode series unit, a second diode series unit, a third diode series unit and a fourth diode series unit; The input end of the first diode series unit is connected to the drain of the first low-voltage NMOS tube, and the output end of the first diode series unit is connected to the source of the first low-voltage NMOS tube; the input end of the second diode series unit is connected to the drain of the second low-voltage NMOS tube, and the output end of the second diode series unit is connected to the source of the second low-voltage NMOS tube; the input end of the third diode series unit is connected to the drain of the third low-voltage NMOS tube, and the output end of the third diode series unit is connected to the source of the third low-voltage NMOS tube; the input end of the fourth diode series unit is connected to the drain of the fourth low-voltage NMOS tube, and the output end of the fourth diode series unit is connected to the source of the fourth low-voltage NMOS tube.
4. The level shift circuit according to claim 3, characterized in that: The source of the first low-voltage NMOS tube and the source of the third low-voltage NMOS tube are grounded; the gate of the first low-voltage NMOS tube is connected to the first pulse output end, and the gate of the third low-voltage NMOS tube is connected to the second pulse output end; the drain of the first low-voltage NMOS tube is connected to the source of the second low-voltage NMOS tube, the drain of the third low-voltage NMOS tube is connected to the source of the fourth low-voltage NMOS tube, the gate of the second low-voltage NMOS tube and the gate of the fourth low-voltage NMOS tube are connected to a low-voltage power rail, the drain of the second low-voltage NMOS tube is connected to the first signal conversion module, and the drain of the fourth low-voltage NMOS tube is connected to the second signal conversion module.
5. The level shift circuit according to claim 3, characterized in that: The operating voltage of the first low-voltage NMOS transistor, the second low-voltage NMOS transistor, the third low-voltage NMOS transistor and the fourth low-voltage NMOS transistor includes 5V.
6. The level shift circuit according to claim 1, characterized in that: The first signal conversion module includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube and a second NMOS tube; the second signal conversion module includes a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a third NMOS tube and a fourth NMOS tube; The gate of the first PMOS tube, the gate of the second PMOS tube, and the gate of the third PMOS tube are connected to the output end of the first signal transmission module, the gate of the fourth PMOS tube, the gate of the fifth PMOS tube, and the gate of the sixth PMOS tube are connected to the output end of the second signal transmission module, the source of the first PMOS tube, the source of the second PMOS tube, the source of the third PMOS tube, the source of the fourth PMOS tube, the source of the fifth PMOS tube, and the source of the sixth PMOS tube are connected to a floating power supply, the gate of the first PMOS tube is connected to the drain of the first PMOS tube, the gate of the fourth PMOS tube is connected to the drain of the fourth PMOS tube, the source of the first NMOS tube, The source of the second NMOS tube, the source of the third NMOS tube and the source of the fourth NMOS tube are connected to the floating ground, the gate of the first NMOS tube and the gate of the second NMOS tube are connected to the drain of the second PMOS tube, the gate of the third NMOS tube and the gate of the fourth NMOS tube are connected to the drain of the fifth PMOS tube, the drain of the third PMOS tube and the drain of the fourth NMOS tube are connected to the output end of the level shift circuit, the drain of the sixth PMOS tube and the drain of the second NMOS tube are connected to the reverse output end of the level shift circuit, the gate of the first NMOS tube is connected to the drain of the first NMOS tube, and the gate of the third NMOS tube is connected to the drain of the third NMOS tube.
7. The level shift circuit according to claim 1, characterized in that: The pulse generating module comprises a first pulse generating unit and a second pulse generating unit; The first pulse generating unit comprises a first inverter, a second inverter, a third inverter and a first NOR gate; the input end of the level shift circuit is connected to the first input end of the first NOR gate via the first inverter, the second inverter and the third inverter in sequence, the input end of the level shift circuit is connected to the second input end of the first NOR gate, and the output end of the first NOR gate is connected to the first pulse output end of the pulse generating module; The second pulse generating unit includes a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter and a second NOR gate; the input end of the level shift circuit is connected to the first input end of the second NOR gate via the fourth inverter, the fifth inverter, the sixth inverter and the seventh inverter in sequence, the input end of the level shift circuit is connected to the second input end of the second NOR gate via the fourth inverter, and the output end of the second NOR gate is connected to the second pulse output end of the pulse generating module.
8. The level shift circuit according to claim 1, characterized in that: The signal latch module includes an eighth inverter and a ninth inverter; The input end of the eighth inverter and the output end of the ninth inverter are connected to the inverting output end of the level shift circuit, and the output end of the eighth inverter and the input end of the ninth inverter are connected to the output end of the level shift circuit.
9. The level shift circuit according to claim 1, characterized in that: The level shift circuit has a floating power rail forward dV / dt resistance capability greater than 15V / ns.
10. A GaN power switch device driving circuit, characterized in that: A level shift circuit comprising any one of claims 1 to 9.