Transceiver physical layer interface

Abstract

The invention relates to a transceiver physical layer interface. Example embodiments include a transmission line transceiver comprising: first and second ends; a control module; the amplifier module is connected between the control module and the first end and the second end; a switchable terminal resistance circuit connected between the first and second ends, the switchable terminal resistance circuit comprising a terminal resistor connected in series with a switch controllable by the control module; a pair of resistors connected in series, the pair of resistors connected in series being connected between the first and second ends; and a capacitor connected between a node connecting the pair of series-connected resistors and a common node, where the control module is configured to open the switch during transmission of a signal via a transmission line capacitively connected to the first and second ends to disconnect the terminal resistors.

Description

Technical Field

[0001] The present disclosure relates to a transceiver physical layer interface. Background Art

[0002] In a communication system including a pair of transceivers communicating signals along a transmission line, a termination resistor at each transceiver is used to reduce reflections along the transmission line.

[0003] Figure 1 1 shows an example of a communication system including a pair of transceivers connected by a transmission line. The system 100 includes a first transceiver 101 and a second transceiver 102 connected by a transmission line 103, which in this example includes a twisted pair. Each transceiver 101, 102 is a physical interface of a transformer physical layer (TPL). The transmission line 103 is isolated from the transceivers 101, 102 by isolation capacitors 104a, 104b, 105a, 105b at either end of the transmission line 103. In the example shown, the first transceiver 101 is in a transmission mode and the second transceiver 102 is in a reception mode. Each transceiver 101, 102 includes a pair of ends 106a, 106b, 107a, 107b connected to the transmission line 103 via corresponding capacitors 104a, 104b, 105a, 105b. Termination resistors Rterm 108, 109 are connected between terminals of each transceiver 101, 102. Each transceiver 101, 102 includes two receiver amplifiers RX 110a, 110b, 112a, 112b and one transmitter amplifier TX 111, 113 connected between terminals 106a, 106b, 1071, 107b and a control module 114, 115.

[0004] Figure 2 Schematically showing the differential voltage between the terminals TXP, TXN as a function of time at the transmitter during the transmission of a logic level 1 followed by a logic level 0. For a logic level 1, the transmitter applies a positive differential voltage during a first phase in a first time period 201, then applies a negative differential voltage during a second phase in a second time period 202, and then subsequently applies a zero differential voltage during a third phase in a third time period. The duration of the first time period 201 and the second time period 202 are approximately the same, while the duration of the third time period 203 is approximately twice the duration of each of the first and second time periods. For a logic level 0, the transmitter first applies a negative differential voltage during the first phase, then applies a positive differential voltage during the second phase, and applies a zero differential voltage during the third phase. Similar to the case of a logic level 1, for a logic level 0, the third phase is approximately twice the length of each of the first and second phases.

[0005] To mitigate line attenuation, the differential voltage applied to the transmission line is made as high as possible. The power consumption of the transmitter depends mainly on the applied differential voltage and the bus load, which represents the equivalent resistance seen across the output connections TXP, TXN which will include the termination resistor Rterm on the receiver side.

[0006] During the first and second phases, if the terminal resistor is connected on the transmitter side, the transmitter power consumption will increase. In order to reduce this, the terminal resistor can be disconnected during the first and second phases to save the power consumption of the transmitter. An example of a switchable terminal resistor that reduces the loss when transmitting a signal along a transmission line is disclosed in WO 88 / 03731A1, wherein the terminal resistor is switched into the transceiver circuit within a set time length sufficient for the leading edge of the data bit to be received through the transmission line after the transmission / reception signal is enabled.

[0007] For line transmission systems that need to operate at high voltages in the presence of EMI, such as in automotive applications, the design of switchable termination resistors may be more complicated due to the limited maximum acceptable gate voltage of the MOSFET, high EMI, and high common-mode voltage.

[0008] Figure 3 , an alternative communication system 300 is shown in which a switchable termination resistor is provided between the terminals 106a, 106b, 107a, 107b of each transceiver 101, 102 by connecting a termination resistor Rterm 303, 304 in series with switches 301, 302, each switch 301, 302 being controllable by a respective one of the controllers 114, 115. The other components of the system 300 are otherwise similar to Figure 1 The switches 301, 302 allow each transceiver to disconnect the terminal resistors Rterm 303, 304 on the transmission side during the 1st and 2nd phases (see Figure 2 ), resulting in half the power consumption for the same differential voltage due to the change in load after disconnecting the resistor on the transmission side. This solution optimizes power consumption, but has the disadvantage of inducing high common mode voltages when disturbed by receptor current injection (BCI). Although the solution described is suitable for transformer coupled transmission lines, the switch termination resistor combined with capacitive coupled transmission lines is not an ideal solution. Summary of the invention

[0009] According to a first aspect, a transmission line transceiver is provided, the transmission line transceiver comprising:

[0010] first and second ends;

[0011] Control module;

[0012] an amplifier module connected between the control module and the first and second terminals;

[0013] a switchable terminal resistance circuit connected between the first and second terminals, the switchable terminal resistance circuit comprising a terminal resistance connected in series with a switch controllable by the control module;

[0014] a pair of series connected resistors connected between the first and second terminals;

[0015] a capacitor connected between a node connecting the pair of series-connected resistors and a common node,

[0016] The control module is configured to operate the switch to disconnect the terminal resistor during transmission of a signal via a transmission line capacitively connected to the first and second ends.

[0017] According to a second aspect, there is provided a communication system, the communication system comprising:

[0018] first and second transceivers, each of the first and second transceivers being according to the first aspect; and

[0019] A transmission line is connected to the first and second ends of each of the first and second transceivers via an isolation capacitor.

[0020] Each of the resistors connected in series may have an equal resistance value.

[0021] A resistance value of each of the series-connected resistors may match a characteristic impedance of the transmission line.

[0022] The characteristic impedance of the transmission line may be approximately 120Ω + / - 15%.

[0023] The resistance value of each of the series-connected resistors may be greater than the resistance value of the terminal resistor of each of the first and second transceivers. This allows reducing the power consumption effect of the series-connected resistors that maintain the cross-terminal connection.

[0024] In some examples, the resistance value of each of the series-connected resistors may be between about 150Ω and about 350Ω.

[0025] The capacitance value of the capacitor may be between about 10 nF and about 200 nF.

[0026] The control module may be configured to transmit data bits on the transmission line by:

[0027] providing first and second pulses to the amplifier module to drive respective positive and negative differential voltage levels across the first and second terminals during respective first and second time periods while maintaining the switch open; and

[0028] The switch is maintained closed during a subsequent third time period.

[0029] According to a third aspect, there is provided a method of operating a transceiver according to the first aspect, the method comprising transmitting a data bit on a transmission line by:

[0030] the control module providing first and second pulses to the amplifier module to drive respective positive and negative differential voltage levels across the first and second terminals during respective first and second time periods; and

[0031] The control module maintains the switch closed during a subsequent third time period.

[0032] Each of the resistors connected in series may have an equal resistance value.

[0033] A resistance value of each of the series-connected resistors may match a characteristic impedance of the transmission line.

[0034] The characteristic impedance of the transmission line may be approximately 120Ω + / - 15%.

[0035] A resistance value of each of the serially connected resistors may be greater than a resistance value of the terminal resistor.

[0036] The resistance value of each of the series-connected resistors may be between about 150Ω and about 350Ω. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Embodiments will be described by way of example only with reference to the accompanying drawings, in which:

[0038] Figure 1 is a schematic diagram of a communication system including a pair of transceivers connected to a capacitively coupled transmission line;

[0039] Figure 2 a schematic diagram showing a differential voltage on a transmission line varying with time;

[0040] Figure 3 is a schematic diagram of an alternative communication system including a pair of transceivers connected to a capacitive transmission line;

[0041] Figure 4 is a schematic diagram of another communication system including a pair of transceivers connected to a capacitively coupled transmission line, wherein a shunt filter is connected to each transceiver;

[0042] Figure 5 is a schematic diagram of a switchable termination resistor circuit and associated drive circuit for a transmission line communication system;

[0043] Figure 6 It is a curve showing the common mode voltage of two different capacitively coupled transmission line communication systems changing with frequency;

[0044] Figure 7 is a schematic diagram of the experimental setup for testing bulk current injection interference on a transmission line;

[0045] Figure 8 is a curve showing the BCI open-loop level of the communication system with and without the splitter filter as a function of frequency;

[0046] Fig. 9 It is a curve showing the BCI open-loop level of the communication system with switched terminal resistance changing with frequency;

[0047] Fig.10 is another plot of BCI open loop level versus frequency for a communication system with switched termination resistors and shunt filters.

[0048] It should be noted that the drawings are diagrammatic and not drawn to scale. For clarity and convenience in the drawings, the relative sizes and proportions of the various parts of these drawings have been shown in an enlarged or reduced manner. The same reference numerals are used overall to refer to corresponding or similar features in modified and different embodiments. DETAILED DESCRIPTION

[0049] Figure 4 Schematic diagram of an example communication system 400 is shown, the example communication system 400 comprising a first transceiver 401 and a second transceiver 402 connected by a transmission line 403, the transmission line 403 comprising a twisted pair of wires in this example. Figure 1 As in the communication system of FIG. 4 , the transmission line 403 is isolated from the transceivers 401, 402 by isolation capacitors 404a, 404b, 405a, 405b at either end of the transmission line 403. In the example shown, the first transceiver 401 is in a transmission mode and the second transceiver 402 is in a reception mode. Each transceiver 401, 402 includes a pair of ends 406a, 406b, 407a, 407b connected to the transmission line 403 via respective capacitors 404a, 404b, 405a, 405b. Internal termination resistors Rinternal 408, 409 are connected in series with switches 410, 411 between the ends 406a, 406b, 407a, 407b of each transceiver 401, 402. Each transceiver 401 , 402 comprises two receiver amplifiers RX 412 a , 412 b , 413 a , 413 b and one transmitter amplifier TX 414 , 415 connected between terminals 406 a , 406 b , 407 a , 407 b and a control module 416 , 417 .

[0050] A pair of series connected resistors Rsplit 418a, 418b, 419a, 419b are connected between the terminals 406a, 406b, 407a, 407b of each transceiver 401, 402. Capacitors Csplit 420, 421 are connected between nodes 423, 424 connecting the pair of series connected resistors 418a, 418b, 419a, 419b and a common node 422. The series connected resistors 419a, 419b and the switchable termination resistor 409 provide a combined receiver load resistance Rload_RX for the transceiver operating as a receiver, which in this example is the second transceiver 402.

[0051] The resistors 418a, 418b, 419a, 419b and the capacitors 420, 421 connected in series are Figure 4 401, 402. This is largely due to the fact that the values ​​of capacitors 420, 421 typically need to be between about 10 and 200 nF, which would result in a larger IC area if the capacitors were located inside the transceiver. However, the switchable termination resistor circuit can be located inside the transceiver 401, 402 because no large capacitance value is required. Therefore, in general terms, the switchable termination resistor circuit can be located inside the transceiver, and the series-connected resistor and capacitor are located outside the transceiver.

[0052] The terminal resistance Rinternal may be matched to the characteristic impedance of the transmission line 403 to avoid reflection effects and rebound during communication. The characteristic impedance of an example cable for the transmission line 403 may be about 120Ω.

[0053] The shunt resistor Rsplit Figure 4 Indicated as being connected to the outside of each transceiver 401. The value of Rsplit can be selected so that it does not cause misadjustment of the terminal resistance, which would cause the value of Rsplit to be higher than the internal terminal resistance Rinternal. Typically, the value of Rsplit can be in the range of 150-350Ω, where the terminal resistance is as indicated above.

[0054] In a specific example, if the internal termination resistance value is set to 170Ω, in order to use the lowest possible Rsplit while generating the same differential voltage, the total receiver load resistance Rload_RX should be approximately 130Ω, resulting in a value of Rsplit of approximately 300Ω.

[0055] With Rsplit = 250Ω and Rinternal = 170Ω, the receiver load resistance is Rload_RX = 127Ω. The equivalent resistive load of the driver is 102Ω, which is the impedance seen by the driver during phases 1 and 2 when the internal termination resistor 409 is turned off.

[0056] With Rsplit=200Ω and Rinternal=170Ω, the receiver load resistance Rload_RX=119Ω, and the equivalent resistive load is 92Ω.

[0057] With Rsplit=150Ω and Rinternal=170Ω, the receiver load resistance Rload_RX=109Ω, and the equivalent resistive load is 80Ω.

[0058] Figure 5 Schematic diagram of an example switchable terminal resistor circuit 501 with an associated driver circuit 502 is shown. The switchable terminal resistor circuit 501 is connected to a transceiver (e.g. Figure 4 The switchable terminal resistance circuit 501 includes a first resistor R1 and a second resistor R2 connected to the corresponding first terminal TXP and the second terminal TXN. The first NMOS terminal resistance switch Mnsw1 and the second NMOS terminal resistance switch Mnsw2 are connected in series between the first resistor R1 and the second resistor R2. The source connections of the terminal resistance switches Mnsw1 and Mnsw2 are connected together, and the drain connections of the terminal resistance switches Mnsw1 and Mnsw2 are connected to the corresponding first resistor R1 and the second resistor R2. By applying a gate voltage to the gates of the terminal resistance switches Mnsw1 and Mnsw2, the first terminal resistance switch Mnsw1 and the second terminal resistance switch Mnsw2 are turned on, and the first resistor R1 is connected to the second resistor R2 via the first terminal resistance switch Mnsw1 and the second terminal resistance switch Mnsw2, thereby connecting the terminal resistance between the first terminal TXP and the second terminal TXN. The total terminal resistance includes the first resistor R1 and the second resistor R2 connected in series, and the source-drain resistance (which can be several ohms) of the first terminal resistance switch Mnsw1 and the second terminal resistance switch Mnsw2. Turning off the first terminal resistance switch Mnsw1 and the second terminal resistance switch Mnsw2 disconnects the terminal resistance from the first terminal TXP and the second terminal TXN, thereby keeping the connection between the terminals TXP and TXN open.

[0059] The gate connection of the first terminal resistance switch Mnsw1 and the second terminal resistance switch Mnsw2 is connected to the input node 504, and the input node 504 is connected to the output of the driving circuit 502 for driving the switchable terminal resistance circuit 501. The source connection of the first terminal resistance switch Mnsw1 and the second terminal resistance switch Mnsw2 is connected together at the midpoint node 503 of the switchable terminal resistance circuit 501. The Zener diode Dz1 is connected between the input node 304 and the midpoint node 503, and the cathode of the Zener diode Dz1 is connected to the input node 504. The Zener diode Dz1 maintains the gate-source voltage across the first terminal resistance switch Mnsw1 and the second terminal resistance switch Mnsw2 within a set voltage range defined by the breakdown voltage of the Zener diode. The Zener diode Dz1 thereby allows the switchable terminal resistance circuit 501 to operate in the presence of electromagnetic interference, which may cause a high voltage to be induced across the first terminal TXP and the second terminal TXN. The Zener diode may clamp the gate-source voltage across the terminal resistance switches Mnsw1 , Mnsw2 to 5V, for example, when the switchable terminal resistance circuit 501 is enabled.

[0060] During normal operation in the absence of electromagnetic interference, the common mode voltage on the transmission lines connected to the first and second connections TXP and TXN may for example be about 2.5 V. To operate the switches Mnsw1 , Mnsw2 , the voltage at the input node 504 will need to be above about 5.5 V but below the breakdown voltage of the Zener diode Dz1 .

[0061] The driving circuit 502 provides a gate voltage G_Nsw to an input node 504 that operates the first and second terminal resistance switches Mnsw1 and Mnsw2. The driving circuit 502 is connected between a supply voltage line 505 that provides a supply voltage VPRE_TPL (eg, 7V) and a ground voltage line 506 at a ground voltage AGND (eg, 0V).

[0062] The driver circuit 502 operates as a level shifter, allowing the low voltage input signal Rterm_en, Rterm_enb to drive the higher voltage output signal G_Nsw, and allowing the output voltage to float with the voltage level at the midpoint node 503 of the switchable terminal resistance circuit 501. To allow the output voltage to float, the driver circuit 302 includes a first diode D1 and a second diode D2 connected to the input node 504, the cathode of the first diode D1 is connected to the input node 304, and the anode of the second diode D2 is connected to the input node 504. The diodes D1, D2 prevent current from flowing back from the switchable terminal resistance circuit 501 to the driver circuit 502 in the presence of high levels of electromagnetic interference.

[0063] The first NMOS switch Mn1, the second NMOS switch Mn2, and the third NMOS switch Mn3 of the driving circuit 502 have a source connection connected to the ground voltage line 505, and a gate connection connected to receive the termination resistance enable signal Rterm_en or its inverted signal Rterm_enb. The gate connections of the first NMOS switch Mn1 and the third NMOS switch Mn3 receive Rterm_enb, while the second NMOS switch Mn2 receives Rterm_en.

[0064] The driver circuit 502 further comprises first, second, third, fourth, fifth and sixth PMOS switches Mp1-Mp6. The gate connection of the first PMOS switch Mp1 is connected to the drain connection of the second PMOS switch Mp2. The gate connection of the second PMOS switch Mp2 is connected to the drain connection of the first PMOS switch Mp1. The source connections of the first, second and third PMOS switches are connected to the supply voltage line 504. The gate connection of the third PMOS switch Mp3 is connected to the drain connection of the second PMOS switch Mp2.

[0065] The source connection of the fourth PMOS switch Mp4 is connected to the drain connection of the first PMOS switch Mp1, and the drain connection of the fourth PMOS switch Mp4 is connected to the drain connection of the first NMOS switch Mn1. The gate connection of the fourth PMOS switch Mp4 is connected to the gate connection of the fifth PMOS switch Mp5. The source connection of the fifth PMOS switch Mp5 is connected to the drain connection of the second PMOS switch Mp2. The drain connection of the fifth PMOS switch Mp5 is connected to the drain connection of the second NMOS switch Mn2.

[0066] The gate connections of the fifth PMOS switch Mp5 and the sixth PMOS switch Mp6 are connected together. The source connection of the sixth PMOS switch Mp6 is connected to the drain connection of the third PMOS switch Mp3. The drain connection of the sixth PMOS switch Mp6 is connected to the anode connection of the first diode D1.

[0067] The drain connection of the third NMOS switch Mn3 is connected to the cathode connection of the second diode D2.

[0068] To turn on the termination resistor, an enable signal Rterm_en is provided to the second NMOS switch Mn2, and its inverted signal is provided to the first NMOS switch Mn1 and the third NMOS switch Mn3. Then, the voltage applied at the input node 304 is the supply voltage VPRE_TPL minus a diode voltage, that is, the voltage across the first diode D1. The supply voltage VPRE_TPL needs to be sufficient to pull the gates of the termination switches Mnsw1 and Mnsw2, but lower than the supply voltage required to drive the current through the Zener diode Dz1.

[0069] To disconnect the terminal resistor, the third NMOS switch Mn3 is turned on by Rterm_enb, which pulls the drain of the NMOS switch Mn3 and the gate voltage at the input node 304 down to approximately one diode voltage to ground, thereby disconnecting the terminal resistor switches Mnsw1 and Mnsw2.

[0070] In the simulation, the Figure 4 The difference in common-mode voltage between a communication system with a shunt resistor arrangement and a system with only switchable internal termination resistors. The results of this simulation are Figure 6 . A first curve 601 shows the common mode voltage that varies with frequency for a first communication system having only switchable internal terminal resistances. A second curve 602 shows the common mode voltage of a second communication system with a shunt resistor arrangement added. The first communication system produces a peak common mode voltage of about 42V at about 7MHz, while the second communication system has a significantly lower peak common mode voltage of about 20V at about the same frequency. In these simulation results, a value of 200Ω is selected for Rsplit and a value of 100nF is selected for Csplit. In particular, in the interval of about 100kHz to about 10MHz, a larger effect of the shunt resistor arrangement can be seen.

[0071] use Figure 7 The experimental setup shown in the BCI measurement tests the arrangement on silicon, wherein each of nodes 1-6 represents a pair of transceivers as described herein, the nodes being controlled by a master TPL. Each of the nodes comprises two transceivers, for example, node 1 has a transceiver connected to the master TPL and a second transceiver linked to node 2. For another example, node 3 has a first transceiver connected to node 2, and the second transceiver of node 3 is connected to node 4 via a cable. The BCI open-loop level is measured on the transmission line connecting each node. In the experimental setup, the BCI is injected only on the cable, for example, on the cable between node 3 and node 4 at the location where the BCI probe is located. In an alternative setup, the BCI may be injected on the cable between node 1 and the master TPL, which in Figure 7 Not depicted.

[0072] The results of the experimental arrangement are Figure 8 It is shown in Figure 8Curves are shown showing the BCI open loop level (in mA) as a function of frequency (in MHz) compared to the limits defined by the VW TL81000 standard 801. The first curve 802 shows the results of using a switched termination resistor alone, which does not pass the standard due to a drop below the required level between about 5-7MHz. The second curve 803 shows the results of using a switched termination resistor in combination with a shunt resistor arrangement, where the values ​​of Rsplit and Csplit are 200Ω and 100nF, respectively, which passes the standard over the entire frequency range. In addition, at low frequencies, the injected level increases from about 100 / 150mA to about 200mA, resulting in higher immunity to noise below 2MHz. Further optimization by selecting the values ​​of the shunt resistor and capacitor can produce even better performance.

[0073] Fig. 9 shows that compared with TL81000 standard 902 and the more stringent ISO 11452-4 Class 4 standard 903, only internal switchable termination resistors (i.e., similar to Figure 3 901 shows a curve of BCI open loop level versus frequency for a communication system with an arrangement in FIG. This shows that while meeting the TL81000 standard, the BCI level fails the more stringent standard 903 in the range between about 1 and 6 MHz due to the high common mode in this frequency range.

[0074] Fig.10 Again compared to ISO 11452-4 Class 4 standard 1002, a shunt resistor arrangement is added (i.e., similar to Figure 4 Figure 1001 shows the BCI open loop level versus frequency for a communication system with a shunt resistor arrangement). This shows that with proper optimization of the components, the shunt resistor arrangement solution allows the system to pass 200mA BCI levels over the entire frequency range. This applies to both setups tested on the distributed system. The same setup was tested on a centralized board with similar results.

[0075] In summary, the shunt resistor arrangement described herein allows for a significant improvement in EMC robustness during BCI testing compared to an arrangement with internal switchable termination resistors alone, where for example power consumption during transmission is increased by only about 20%. The solution exhibits about 40% lower power consumption than conventional arrangements with only external termination resistors.

[0076] The transmission system described herein may be particularly applicable in battery management systems such as vehicle battery systems, where isolated electrical connectivity is required, current consumption is a critical parameter, and electromagnetic interference may be high. The transmission system described herein may also be applicable in other applications where isolated transmission with low current consumption may be required, especially in the presence of high electromagnetic interference.

[0077] Other changes and modifications will be apparent to the skilled person upon reading this disclosure. Such changes and modifications may involve equivalent other features that are already known to us in the field of transmission line transceivers and may be used as a substitute or supplement to the features already described herein.

[0078] Although the attached claims are directed to specific feature combinations, it should be understood that the scope of the disclosure of the present invention also includes any novel feature or any novel feature combination or any generalized form thereof disclosed explicitly or implicitly herein, regardless of whether it relates to the same invention as currently claimed in any claim or whether it alleviates the same technical problem as any or all of the technical problems alleviated by the present invention.

[0079] Features described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features described in the context of a single embodiment for the sake of brevity may also be provided separately or in any suitable subcombination. Applicants hereby caution that new claims may be formulated based on such features and / or combinations of such features during the prosecution of this application or any further application derived therefrom.

[0080] For the sake of completeness, it is also stipulated that the term "comprising" does not exclude other elements or steps, the term "a" does not exclude a plurality, a single processor or other unit may realize the functions of several components recited in the claims, and the reference signs in the claims should not be construed as limiting the scope of the claims.

Claims

1. A transmission line transceiver (401), characterized in that: include: first and second ends (406a, 406b); Control module (416); an amplifier module (414) connected between the control module (416) and the first and second terminals (406a, 406b); a switchable terminal resistance circuit (408, 410) connected between the first and second ends (406a, 406b), the switchable terminal resistance circuit (408, 410) comprising a terminal resistance (408) connected in series with a switch (410) controllable by the control module (416); a pair of series-connected resistors (418a, 418b) connected between the first and second terminals (406a, 406b); a capacitor (420) connected between a node (423) connecting the pair of series-connected resistors (418a, 418b) and a common node (422), The control module (416) is configured to operate the switch (410) to disconnect the terminal resistor (408) during signal transmission via the transmission line (403) connected to the first and second ends (406a, 406b) in a capacitive manner.

2. A communication system (400), characterized in that: include: a first and a second transceiver (401, 402), each of the first and second transceivers (401, 402) according to claim 1; as well as A transmission line (403) connected to the first and second ends (407a, 407b, 406a, 406b) of each of the first and second transceivers (401, 402) via isolation capacitors (405a, 405b, 404a, 404b).

3. The communication system (400) according to claim 2, characterized in that Each of the series-connected resistors (419a, 419b, 418a, 418b) has an equal resistance value.

4. The communication system (400) according to claim 2, characterized in that The resistance value of each of the series-connected resistors (419a, 419b, 418a, 418b) matches the characteristic impedance of the transmission line (403).

5. The communication system (400) according to claim 3, characterized in that The characteristic impedance of the transmission line (403) is about 120Ω+ / -15%.

6. The communication system (400) according to claim 3 or claim 4, characterized in that: The resistance value of each of the serially connected resistors (419a, 419b, 418a, 418b) is greater than the resistance value of the terminal resistor (409, 408) of each of the first and second transceivers (401, 402).

7. The transmission line transceiver (402) or the communication system (400) according to any of the preceding claims, characterized in that The resistance value of each of the series-connected resistors (419a, 419b, 418a, 418b) is between about 150Ω and about 350Ω.

8. The transmission line transceiver (402) or the communication system (400) according to any one of the preceding claims, characterized in that The capacitance value of the capacitor (420, 421) is between about 10nF and about 200nF.

9. The transmission line transceiver (402) or the communication system (400) according to any one of the preceding claims, characterized in that The control module (416) is configured to transmit data bits on the transmission line (403) by: providing first and second pulses to the amplifier module (414) to drive respective positive and negative differential voltage levels across the first and second terminals (406a, 406b) during respective first and second time periods (201, 202) while maintaining the switch (410) open; as well as The switch (410) is maintained closed during a subsequent third time period (203).

10. A method of operating the transceiver according to claim 1, characterized in that: The method comprises transmitting data bits on the transmission line (403) by: The control module (416) provides first and second pulses to the amplifier module (414) to drive respective positive and negative differential voltage levels across the first and second terminals (406a, 406b) during respective first and second time periods (201, 202); as well as The control module (416) maintains the switch (410) closed during a subsequent third time period (203).

Images