A Time Latching Method Based on Functional Cards

Abstract

The present invention discloses a time latching method based on a functional card, which includes: a time latch receives a trigger signal and latches the current time point; the current time point includes coarse time timing information and fine time timing information; when the time latch is triggered, a fine time calculation unit multiplies the counting value of a counter unit by a second period to obtain time difference information as the fine time timing information. In the present invention, on the basis of the basic protocol time accuracy in the protocol transmission process, the local clock of the functional card is used for fine time calculation. Each functional card clock internally sets an independent counter and innovatively uses a counter reset command design. The use of nanosecond-level refresh counting can greatly reduce errors and further improve the time accuracy latched by the time latch when an event occurs, and is particularly suitable for technical fields with high requirements for time accuracy.

Description

Technical Field

[0001] The present invention relates to the field of signal acquisition, and particularly to a time latching method based on a function card. Background Art

[0002] Function cards, usually also known as industrial control cards or data acquisition / output cards, play an important role in the fields of industrial automation and process control. One of their main functions is to be applied to event timestamps and event synchronization, ensuring that multiple acquisition devices can accurately record the time when an event occurs and achieve high-precision synchronization. For example: Digital signals refer to signals with two states (such as on / off, high / low, 1 / 0). In industrial automation, digital signals are often used to represent the status of devices or control instructions. Through function cards, precise timing and synchronization of digital events can be achieved. When a digital signal changes, the function card will record the timestamp of this event and synchronize with other acquisition devices to ensure that all devices can accurately record the time of the same event. Analog signals refer to continuously changing physical quantities, such as voltage, current, temperature, pressure, etc. These signals are common in industrial processes and usually need to be accurately measured and recorded; function cards can collect analog signals and process them to obtain accurate timestamps. Similarly, they can also be synchronized with other acquisition devices to ensure that the timestamps of all relevant events are consistent.

[0003] Function card time latching refers to locking and storing the time information on a function card (such as a data acquisition card) through specific technical means in a data acquisition system. This can ensure that during the data acquisition process, the time information will not change due to changes in the system clock or external interference, thus guaranteeing the accuracy and consistency of the data. However, the time latching methods of function cards in the prior art have the following problems: Function cards in the prior art generally only synchronize the current timestamp information (second level) and time synchronization codes (pulses). At this time, the synchronization accuracy mainly depends on the accuracy corresponding to the protocol of the time synchronization code itself. For example, when using IRIG-G(DC), the synchronization accuracy can be maintained at the microsecond level. However, in some technical fields, the synchronization accuracy requirement is in the nanosecond level, and the solutions in the prior art cannot be achieved. Summary of the Invention

[0004] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a time latching method based on a function card.

[0005] The purpose of the present invention is achieved through the following technical solutions:

[0006] In the first aspect of the present invention, a time latching method based on a function card is provided, including:

[0007] The time latch receives a trigger signal and latches the current time point; the current time point includes coarse time timing information and fine time timing information; the coarse time timing information is obtained by extracting the time stamp of the coarse time refreshed every first period, and the first period corresponds to the IRIG-G(DC) protocol; the fine time timing information is obtained by extracting the fine time counted every second period, and the second period corresponds to the local clock frequency.

[0008] The fine time timing information is specifically the time difference information generated by the local clock within each first period. The local clock includes a counter unit and a fine time calculation unit. The maximum counting number of the counter unit is the first period divided by the second period. The counter unit performs an increment operation every second period until it reaches the maximum counting number and then resets to zero.

[0009] When the time latch is triggered, the fine time calculation unit multiplies the counting value of the counter unit by the second period to obtain the time difference information as the fine time timing information.

[0010] Further, the coarse time timing information is the coarse time timing information of the main controller card.

[0011] Further, for the coarse time based on the coarse time timing information of the main controller card, it is overwritten and updated every third period. The overwrite update method includes:

[0012] The time information generator sends the generated time information pulse to the bus signal distributor every third period, and the bus signal distributor sends the time information pulse to the IRIG-G(DC) decoder.

[0013] The IRIG-G(DC) decoder processes the received time information pulse to obtain the overwrite update time timing information. The overwrite update time timing information includes extracting the code element of the time information pulse using the code element extraction module, extracting the timing information and pulse of the time information pulse using the timing information pulse extraction module.

[0014] Use the overwrite update time timing information to overwrite and update the coarse time.

[0015] Further, the time information pulse generated by the time information generator is a relative time information pulse. The time information generator includes an IRIG-G(DC) encoder, and the IRIG-G(DC) encoder includes a code element generator, a time extraction pre-carry processing module, and a time synchronizer.

[0016] The time information generator generates a relative time information pulse, including:

[0017] The soft-core CPU sends the initial time information to the IRIG-G(DC) encoder through the AVALON bus, and the IRIG-G(DC) encoder starts timing on the initial time information to obtain relative time information;

[0018] The symbol generator of the IRIG-G(DC) encoder converts the relative time information into symbols, and then the time extraction pre-carry processing module and the time synchronizer convert the symbols into relative time information pulses, and send the relative time information pulses to the bus signal distributor.

[0019] Further, the time information pulses generated by the time information generator are real time information pulses, and the time information generator includes a second CAT5e network interface and a third MLVDS transceiver;

[0020] The time information generator generates real time information pulses, including:

[0021] The second CAT5e network interface receives the real time information pulses sent by the external high-precision time service module and forwards them to the bus signal distributor through the third MLVDS transceiver.

[0022] Further, the IRIG-G(DC) decoder forms the time stamps of the coarse time refreshed every first cycle as synchronization pulses of the coarse time timing information of the functional sub-card, and sends them to the backplane timing bus through the first MLVDS transceiver.

[0023] Further, the time information generator sends the generated time information pulses to the bus signal distributor every third cycle, and the bus signal distributor sends the time information pulses as cross-chassis coarse time synchronization information to the outside through the second MLVDS transceiver and the first CAT5e network interface.

[0024] Further, the coarse time timing information is the coarse time timing information of the functional sub-card;

[0025] The coarse time timing information of the functional sub-card is received by the fourth MLVDS transceiver through the backplane timing bus every first cycle, sent to the IRIG-G(DC) decoder for decoding and obtained.

[0026] Further, the coarse time timing information is cross-chassis coarse time timing information; the coarse time on which the cross-chassis coarse time timing information is based is covered and updated every third cycle, and the covering and updating method includes:

[0027] Receive the time information pulse sent externally as the cross-box coarse time synchronization information every third cycle through the third CAT5e network port, and send it to the IRIG-G(DC) decoder through the fifth MLVDS transceiver and the bus signal distributor. The IRIG-G(DC) decoder decodes to obtain the cross-box coverage update time synchronization information, which includes the symbol of the time information pulse extracted by the symbol extraction module, the timing information and pulse of the time information pulse extracted by the timing information pulse extraction module;

[0028] Use the cross-box coverage update time synchronization information to overwrite and update the coarse time.

[0029] Further, the functional card includes an automatic event trigger, an IRIG-G(DC) decoder, and a soft-core CPU; the automatic event trigger includes a signal preprocessing module, a multi-channel data source module, a data filter module, a threshold discrimination module, and an event pulse generator; the IRIG-G(DC) decoder includes a DMA data transfer module, a time latch, a time information register group, and an event FIFO module;

[0030] The functional card event trigger time record includes:

[0031] The signal preprocessing module of the automatic event trigger receives an external trigger signal for digital processing, and sequentially sends it to the data filter module and the threshold discrimination module through the multi-channel data source module for filtering and threshold screening. The screened data source directly triggers the event pulse generator to form a first code including the trigger channel and the trigger event;

[0032] The DMA data transfer module of the IRIG-G(DC) decoder receives the first code through the AVALON bus and simultaneously triggers the time latch. The time latch puts the decoded current time point into the time information register group. The DMA data transfer module re-encodes the current time point and the first code taken out from the time information register group to form a second code including the trigger channel, the trigger time, and the trigger event; the second code is put into the event FIFO module for storage;

[0033] The functional card event trigger time reading includes:

[0034] The soft-core CPU reads the current time point data from the time information register group of the IRIG-G(DC) decoder through the AVALON bus to obtain the time information of the current trigger event; and / or:

[0035] The soft-core CPU reads the second code from the event FIFO module of the IRIG-G(DC) decoder through the AVALON bus to obtain the time information of the historical event trigger.

[0036] The beneficial effects of the present invention are as follows:

[0037] In an exemplary embodiment of the present invention, on the basis of the basic protocol time accuracy (the accuracy of the coarse time, in microseconds) in the protocol transmission process, the local clock of the function card is used for fine time calculation. Each function card clock internally sets an independent counter and innovatively uses the counter reset command design. By using nanosecond-level refresh counting, the error can be greatly reduced, and the time accuracy of the time latch when an event occurs can be further improved (i.e., up to the nanosecond level), which is particularly suitable for technical fields with high requirements for time accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a flowchart of a time latching method based on function cards provided by an exemplary embodiment of the present invention;

[0039] Figure 2 It is a schematic diagram of the coverage update method of the coarse time based on the coarse time timing information of the main controller card provided by an exemplary embodiment of the present invention;

[0040] Figure 3 It is a schematic diagram of the time information pulse provided by an exemplary embodiment of the present invention;

[0041] Figure 4 It is a schematic diagram of the relative time information pulse generated by the time information generator provided by an exemplary embodiment of the present invention;

[0042] Figure 5 It is a schematic diagram of the real time information pulse generated by the time information generator provided by an exemplary embodiment of the present invention;

[0043] Figure 6 It is a schematic diagram of the synchronous pulse transmission as the coarse time timing information of the function sub-card provided by an exemplary embodiment of the present invention;

[0044] Figure 7 It is a schematic diagram of the time information pulse transmission as the cross-chassis coarse time synchronization information provided by an exemplary embodiment of the present invention;

[0045] Figure 8 It is a schematic diagram of the acquisition of the coarse time timing information of the function sub-card provided by an exemplary embodiment of the present invention;

[0046] Figure 9 It is the coverage update method of the coarse time based on the cross-chassis coarse time timing information provided by an exemplary embodiment of the present invention;

[0047] Figure 10 It is a schematic diagram of the structure of the function card provided by an exemplary embodiment of the present invention;

[0048] Figure 11Event trigger flowchart provided by an exemplary embodiment of the present invention;

[0049] Figure 12 Main controller card of the functional card structure provided by an exemplary embodiment of the present invention Figure 10 Schematic diagram of the architecture for latching relative time

[0050] Figure 13 Main controller card of the functional card structure provided by an exemplary embodiment of the present invention Figure 10 Schematic diagram of the architecture for latching real time

[0051] Figure 14 Functional sub - card of the functional card structure provided by an exemplary embodiment of the present invention Figure 10 Schematic diagram of the architecture for latching time

[0052] Figure 15 Schematic diagram of the architecture for latching relative time within one chassis for the main controller card and the functional sub - card provided by an exemplary embodiment of the present invention

[0053] Figure 16 Schematic diagram of the architecture for latching real time within one chassis for the main controller card and the functional sub - card provided by an exemplary embodiment of the present invention

[0054] Figure 17 Schematic diagram of the architecture for latching relative time for multiple chassis provided by an exemplary embodiment of the present invention

[0055] Figure 18 Schematic diagram of the architecture for latching real time for multiple chassis provided by an exemplary embodiment of the present invention. Detailed implementation manners

[0056] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0057] In the description of the present invention, it should be noted that the directions or position relationships indicated by terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are the directions or position relationships based on the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention. In addition, terms such as "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0058] In the description of the present invention, it should be noted that unless otherwise clearly specified and defined, the terms "installation", "connection", and "coupling" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0059] In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0060] See Figure 1 , Figure 1 which shows a flowchart of a time latching method based on a functional card provided by an exemplary embodiment of the present invention, including:

[0061] A time latch receives a trigger signal and latches the current time point; the current time point includes coarse time timing information and fine time timing information; the coarse time timing information is obtained by extracting the time stamp of the coarse time refreshed every first period, and the first period corresponds to the IRIG-G(DC) protocol; the fine time timing information is obtained by extracting the fine time counted every second period, and the second period corresponds to the local clock frequency;

[0062] Specifically, the fine time timing information is the time difference information generated by the local clock within each first period. The local clock includes a counter unit and a fine time calculation unit. The maximum counting number of the counter unit is the first period divided by the second period. The counter unit performs an increment operation every second period until it reaches the maximum counting number and then performs a reset operation;

[0063] When the time latch is triggered, the fine time calculation unit multiplies the counting value of the counter unit by the second period to obtain the time difference information as the fine time timing information.

[0064] Specifically, aiming at the problem of low time synchronization accuracy of the functional card in the prior art, in this exemplary embodiment, when the time latch receives a trigger signal (i.e., a trigger signal generated by an external event that requires time latching), the current time point is latched using both the coarse time timing information and the fine time timing information. Specifically:

[0065] For the coarse time timing information, it refers to obtaining the timestamp of the coarse time refreshed based on the first cycle (preferably 0.1ms, i.e. 100us) corresponding to the IRIG-G (DC) protocol, wherein the coarse time (the coarse time refresh module storage can be set separately) is refreshed every first cycle (the specific refresh method is detailed in the subsequent exemplary embodiments); when the time latch latches the current time point, the timestamp of the coarse time is obtained to obtain the coarse time timing information at the current time point; at this time, the event synchronization time of the functional card can be accurate to microseconds, for example: XXyears:XXdays:XXhours:XXminutes:XXseconds+100us.

[0066] The fine time timing information refers to the fine time obtained by counting the second cycle corresponding to the local clock frequency of the functional card (for example, when the local clock frequency is 100Mhz, the clock cycle of the local clock, that is, the second cycle is 10ns). The time difference information and counting related contents are explained by taking the first cycle of 0.1ms (when matching the second cycle unit, the corresponding is 100000ns) and the second cycle of 10ns as an example (other first cycles and second cycles are analogous): The maximum number of counts of the counter unit is the first cycle divided by the second cycle, that is, 100000ns / 10ns=10000 (times), that is, 10000 counts can be performed in each first cycle (coarse time), and the counter unit performs an increment operation every 10ns. Until the count reaches 10000; when the time latch latches the current time point, the count value of the counter unit is obtained, for example, the count value is 351, then the fine time calculation unit calculates the time difference information of 351*10ns=3510ns (that is, the count value of the above-mentioned counter unit multiplied by the second cycle) generated by the local clock operation of the functional card within a first cycle (0.1ms) after the current coarse time, and uses this information as the fine time timing information; at this time, the synchronization time of the functional card (based on the microsecond level of the coarse time timing information) can be accurate to the nanosecond level, for example: XXyears:XXdays:XXhours:XXminutes:XXseconds+100us+3510ns.

[0067] To summarize, in this exemplary embodiment, on top of the basic protocol time accuracy (coarse time accuracy, microsecond level) based on the protocol transmission process, the local clock of the functional card is used to perform fine time calculations, an independent counter is set inside the clock of each functional card and an innovative counter reset command design is used. The use of nanosecond refresh counts can greatly reduce errors and further improve the time accuracy of the time latch when an event occurs (i.e., to the nanosecond level), which is particularly suitable for technical fields that require very high time accuracy.

[0068] It should be noted that: According to actual requirements, the function card can be divided into a main controller card and a functional sub-card. The main controller card provides coarse time (including relative time and real time, which will be elaborated later), and the functional sub-card needs to obtain the coarse time from the main controller card. Whether it is the main controller or the functional sub-card, they can both be applied to the time latching method based on the function card mentioned in this exemplary embodiment. There can be only one main controller card, or there can be one main controller card and at least one functional sub-card connected to the main controller card. The following exemplary embodiments will preferably expand and explain more implementation methods of the time latching method mentioned in this exemplary embodiment around the main controller card and the functional sub-card:

[0069] More preferably, in an exemplary embodiment, the coarse time timing information is the coarse time timing information of the main controller card. For this exemplary embodiment, it can be used for the main controller card.

[0070] More preferably, in an exemplary embodiment, the coarse time based on the coarse time timing information of the main controller card is covered and updated every third cycle, as Figure 2 shown, the covering and updating method includes:

[0071] The time information generator sends the generated time information pulses to the bus signal distributor every third cycle, and the bus signal distributor sends the time information pulses to the IRIG-G(DC) decoder;

[0072] The IRIG-G(DC) decoder processes the received time information pulses to obtain the covering and updating time timing information, and the covering and updating time timing information includes extracting the code elements of the time information pulses by using the code element extraction module, extracting the timing information and pulses of the time information pulses by using the timing information pulse extraction module;

[0073] Use the covering and updating time timing information to cover and update the coarse time.

[0074] Specifically, in this exemplary embodiment, for the coarse time timing information of the main controller card (that is, the main controller card corresponding to generating its own coarse time), in order to make the coarse time more accurate (reduce the error of internal time calculation), the time information pulses generated by the time information generator every third cycle (for example, 0.01s, corresponding to 10ms) will be used for covering and updating, where the time information pulses generated by the time information generator are accurate time information.

[0075] Specifically: The time information generator sends the generated time information pulses to the bus signal distributor every third cycle. The bus signal distributor sends the time information pulses to the IRIG-G(DC) decoder. The IRIG-G(DC) decoder processes the received time information pulses to obtain the time service information for covering and updating the time, and finally uses the time service information for covering and updating the coarse time. Among them, the time service information for covering and updating includes extracting the code elements of the time information pulses by the code element extraction module, extracting the time service information and pulses of the time information pulses by the time service information pulse extraction module.

[0076] In a specific exemplary embodiment, the time information pulses are as Figure 3 shown. Specifically: Each frame of pulses includes 100 bits of data, which are respectively assigned as the year, day, hour, minute, second, 0.1 second, and 0.01 second for time service information. Each bit of data is represented in the form of 0 code element, 1 code element, or P code element. The 0 code element and 1 code element respectively represent 0 and 1 in binary, while the P code element indicates the cut-off of the corresponding digit. Among them, the 1st - 10th bits represent seconds, the 11th - 20th bits represent minutes, the 21st - 30th bits represent hours, the 31st - 45th bits represent days, the 46th - 50th bits represent 0.1 seconds, the 51st - 60th bits represent 0.01 seconds, the 61st - 70th bits represent years, and the 71st - 100th bits represent control functions. And Figure 2 the time information pulses in represent: 24 years, 304 days, 11 hours, 15 minutes, 30.26 seconds. Figure 2 "TIME FRAME" in represents that the third cycle is 0.01 second, and "INDEX COUNT" represents that the first cycle is 0.1 ms.

[0077] More preferably, in an exemplary embodiment, the time information pulses generated by the time information generator are relative time information pulses, as Figure 4 shown. The time information generator includes an IRIG-G(DC) encoder, and the IRIG-G(DC) encoder includes a code element generator, a time extraction pre-carry processing module, and a time synchronizer;

[0078] The time information generator generates relative time information pulses, including:

[0079] The soft-core CPU sends the initial time information to the IRIG-G(DC) encoder through the AVALON bus, and the IRIG-G(DC) encoder starts timing on the initial time information to obtain relative time information;

[0080] The symbol generator of the IRIG-G(DC) encoder converts the relative time information into symbols, and then the time extraction pre-carry processing module and the time synchronizer convert the symbols into relative time information pulses, and send the relative time information pulses to the bus signal distributor.

[0081] Specifically, in this exemplary embodiment, the time information pulse generated by the time information generator of the main controller card is a relative time information pulse. That is to say, when there is no need to synchronize with the external real time, the relative time is for the entire system. At this time, the time of this main controller card and the time sent by this main controller card to the function sub-card are both relative times. The specific generation process of the relative time is as follows:

[0082] The soft-core CPU sends the initial time information to the IRIG-G(DC) encoder through the AVALON bus, and the IRIG-G(DC) encoder will start timing on the basis of the initial time to obtain the relative time information by itself, and then the soft-core CPU is no longer needed to participate. However, during the process, the soft-core CPU can obtain the current time of the IRIG-G(DC) encoder and correct it (the correction operation itself may introduce errors, so the correction operation should be a slow operation, such as correcting once an hour or a day, or even not correcting, because the error accumulation will not affect the accuracy of the relative time).

[0083] After the initial time information enters the IRIG-G(DC) encoder, the symbol generator converts the initial time information into symbols, and then the time extraction pre-carry processing module and the time synchronizer convert the symbols into relative time information pulses, and then transmit the relative time information to the bus signal distributor. So far, the relative time information pulses are generated. Subsequently, the bus signal distributor transmits the relative time information pulses to the IRIG-G(DC) decoder for decoding to obtain the covered update time timing information (to realize the acquisition of the relative time within the board), or transmits them to the second MLVDS transceiver and the first CAT5e network port to externally emit pulses (to realize the coarse time synchronization of other chassis, such as the subsequent cross-chassis exemplary embodiment).

[0084] More preferably, in an exemplary embodiment, the time information pulse generated by the time information generator is a real time information pulse, as Figure 5 shown, the time information generator includes a second CAT5e network port and a third MLVDS transceiver;

[0085] The time information generator generates real time information pulses, including:

[0086] The second CAT5e network port receives the real time information pulse sent by the external high-precision timing module, and forwards it to the bus signal distributor through the third MLVDS transceiver.

[0087] Specifically, in this exemplary embodiment, the time information pulse generated by the time information generator of the main controller card is a real time information pulse, that is, if synchronization with external real time is required, an external high-precision timing module (which can be a GPS / 5G / PTP high-precision timing module) needs to be connected, and the high-precision timing module sends the real time information pulse to the main controller card, specifically, the second CAT5e network port of the main controller card receives the external real time information pulse and transmits it to the third MLVDS transceiver, and the third MLVDS transceiver transmits the real time information pulse to the bus signal distributor, and the real time information pulse is generated. Subsequently, the bus signal distributor sends the real time information pulse to the IRIG-G (DC) decoder for decoding to obtain the coverage update time timing information (realizing the acquisition of the real time in the board), or transmits it to the second MLVDS transceiver and the first CAT5e network port to transmit pulses externally (realizing the coarse time synchronization of other chassis, such as the subsequent cross-chassis exemplary embodiment).

[0088] It should be noted that the latching process for latching real time and relative time is the same, which mainly depends on whether the main controller card uses an external high-precision timing module.

[0089] More preferably, in an exemplary embodiment, Figure 6 As shown, the IRIG-G (DC) decoder forms the timestamp of the coarse time refreshed in each first cycle as the synchronization pulse of the coarse time timing information of the functional daughter card, and sends it to the backplane timing bus through the first MLVDS transceiver.

[0090] Specifically, this exemplary embodiment is applicable to a main controller card that needs to send coarse time timing information to a functional sub-card. The main controller card sends the synchronization pulse of the coarse time timing information of the functional sub-card to the backplane timing bus through the first MLVDS transceiver every first cycle, wherein the coarse time timing information of the functional sub-card corresponds to the coarse time timing information of the main controller card; the functional sub-card connected to the backplane timing bus can obtain the coarse time timing information of the functional sub-card every first cycle.

[0091] In addition, the backplane timing bus in the chassis uses MLVDS technology, and its phase accuracy is much higher than the TTL level. The error generated during signal transmission is negligible compared to the nanosecond error of the above-mentioned clock synchronization delay.

[0092] More preferably, in an exemplary embodiment, Figure 7As shown, the time information generator sends the generated time information pulses to the bus signal distributor every third cycle. The bus signal distributor sends the time information pulses as cross-chassis coarse time synchronization information to the outside through the second MLVDS transceiver and the first CAT5e network port.

[0093] Specifically, this exemplary embodiment is applicable to application scenarios that require multiple sets of chassis. Each set of chassis includes a main controller card and preferably an externally connected functional sub-card. Regardless of the number of chassis in the entire system, only one chassis serves as the time generator to provide timing information for the entire system. The limitation of this exemplary embodiment corresponds to the main controller card of the chassis serving as the time generator. The bus signal distributor sends the time information pulses as cross-chassis coarse time synchronization information to other chassis outside through the second MLVDS transceiver and the first CAT5e network port. The third CAT5e network port of the main controller card in other chassis receives the time information pulses every third cycle and sends them to the IRIG-G(DC) decoder through the fifth MLVDS transceiver to obtain cross-chassis coverage update time timing information. The coverage method of this coverage update time timing information is the same as the in-chassis coverage time; subsequent cross-chassis coarse time calculation refers to this coverage update time timing information.

[0094] In addition, this exemplary embodiment also provides high stability and long-distance timing capabilities: The timing bus uses MLVDS differential pairs for transmission, and standard CAT5e interfaces and cables are used for timing between chassis, which can improve the reliability of long-distance timing and further reduce errors. By reducing the pulse rise and fall times, the path becomes steeper and the slope is larger, reducing the errors caused by the edges. Especially in the case of a very long transmission path, the reduced errors are quite significant.

[0095] More preferably, in an exemplary embodiment, the coarse time timing information is the coarse time timing information of the functional sub-card;

[0096] As Figure 8 shown, the coarse time timing information of the functional sub-card is obtained by the fourth MLVDS transceiver receiving the synchronization pulse through the backplane timing bus every first cycle and sending it to the IRIG-G(DC) decoder for decoding.

[0097] Specifically, in this exemplary embodiment, this exemplary embodiment is applicable to the limitation of the functional sub-card. The functional sub-card itself does not have a time generation device. Therefore, the fourth MLVDS transceiver connected to the backplane timing bus receives the synchronization pulse sent by the main controller card and sends the synchronization pulse to the IRIG-G(DC) decoder for decoding to complete the coarse time synchronization of the functional sub-card.

[0098] Preferably, in an exemplary embodiment, the coarse time timing information is cross-chassis coarse time timing information; the coarse time on which the cross-chassis coarse time timing information is based is updated every third cycle, and the update method includes:

[0099] As Figure 9 shown, the time information pulses sent externally as cross-chassis coarse time synchronization information are received every third cycle through the third CAT5e network port, and are sent to the IRIG-G(DC) decoder through the fifth MLVDS transceiver and the bus signal distributor. The IRIG-G(DC) decoder decodes to obtain cross-chassis coverage update time synchronization information, which includes extracting the code elements of the time information pulses using the code element extraction module, and extracting the timing information and pulses of the time information pulses using the timing information pulse extraction module;

[0100] The coarse time is updated by covering and updating using the cross-chassis coverage update time synchronization information.

[0101] Specifically, in this exemplary embodiment, it is applicable to application scenarios that require multiple groups of chassis. Each group of chassis includes a main controller card and preferably external functional sub-cards. Regardless of the number of chassis in the entire system, only one chassis serves as the time generator to provide timing information for the entire system. And the limitation of this exemplary embodiment corresponds to the main controller card in other chassis that receives the cross-chassis coarse time timing information sent by the chassis serving as the time generator. The third CAT5e network port of this main controller card receives the time information pulses every third cycle, and sends them to the IRIG-G(DC) decoder through the fifth MLVDS transceiver for decoding to obtain the coverage update time timing information, thereby completing the coarse time coverage update of its own chassis.

[0102] Preferably, in an exemplary embodiment, as Figure 10 shown, the functional card includes an automatic event trigger, an IRIG-G(DC) decoder, and a soft-core CPU; the automatic event trigger includes a signal preprocessing module, a multi-channel data source module, a data filter module, a threshold discrimination module, and an event pulse generator; the IRIG-G(DC) decoder includes a DMA data transfer module, a time latch, a time information register group, and an event FIFO module (in addition, in Figure 10 , the code element extraction module and the timing information pulse extraction module in the foregoing exemplary embodiment are also shown. At the same time, the coarse time refresh module and the fine time refresh module respectively correspond to the extraction of the coarse time timing information and the fine time timing information in the foregoing exemplary embodiment);

[0103] The recording of the functional card event trigger time includes:

[0104] The signal preprocessing module of the automatic event trigger receives an external trigger signal for digital quantity processing, and sequentially sends it to the data filter module and the threshold discrimination module through the multi-channel data source module for filtering and threshold screening. The screened data source directly triggers the event pulse generator to form a first code including the trigger channel and the trigger event;

[0105] The DMA data transfer module of the IRIG-G(DC) decoder receives the first code through the AVALON bus and simultaneously triggers the time latch. The time latch puts the decoded current time point into the time information register group. The DMA data transfer module re-encodes the current time point and the first code taken out from the time information register group to form a second code including the trigger channel, the trigger time, and the trigger event; The second code is put into the event FIFO module for storage;

[0106] The function card event trigger time reading includes:

[0107] The soft-core CPU reads the current time point data from the time information register group of the IRIG-G(DC) decoder through the AVALON bus to obtain the time information of the current trigger event; and / or:

[0108] The soft-core CPU reads the second code from the event FIFO module of the IRIG-G(DC) decoder through the AVALON bus to obtain the time information of the historical event trigger.

[0109] Specifically, in this exemplary embodiment, an event trigger mechanism applicable to both the main controller card and the function sub-card is disclosed, such as Figure 11 shown:

[0110] S1: The external trigger signal (switching quantity, analog quantity, level signal or pulse, not limited) is transmitted to the signal preprocessing module of the automatic event trigger through the function card input terminal (converting the analog quantity into a digital quantity);

[0111] S2: After preprocessing, it is connected to the multi-channel data source module of the automatic event trigger. The multi-channel data source module is divided into multiple data source channels (the number of channels is limited by the internal resources of the system itself). In one exemplary embodiment (such as Figure 10 shown), 32 data source channels are set, namely CH1 data source, CH2 data source, CH3 data source..........CH32 data source;

[0112] S3: Transfer the data sources of different channels to the data filter module, and perform technical filtering according to the filtering rules set in the data filter module, with adjustable filtering length. Specifically, when the input data is a digital quantity, the filtering rule is "debounce" filtering. For example, when the input data is continuously collected as N 1s, the latter stage of the filter will output 1. The same applies when the input data is 0, and the value of N can be set here. When the input data is an analog quantity, the filtering rule is "moving average filtering". For example, perform 5-point sliding filtering on the input data to eliminate peak jitter and prevent misoperation of threshold judgment.

[0113] S4: Transmit the data sources screened by the data filter to the threshold discrimination module. The threshold parameters of the threshold discrimination module are set by the soft-core CPU (transmitted through the AVALON bus), and the determined value or upper and lower limits of the set threshold parameters are used to screen the data sources that meet the parameter settings.

[0114] S5: The data sources screened by the threshold discrimination module directly trigger the event pulse generator. The event pulse generator encodes different data sources to form the first encoding. The encoding rule of the first encoding is: 1: Trigger event; 2: Trigger event; 3: Trigger event........32: Trigger event (different serial numbers represent different channel names, and the trigger event refers to the rule by which it is triggered, such as rising edge or falling edge).

[0115] The above steps (S1~S5) are all executed in sequence by the automatic event trigger.

[0116] S6: The event pulse generator sends the first encoding to the DMA data transfer module of the IRIG-G(DC) decoder through the AVALON bus. The DMA data transfer module triggers the time latch at the same moment when it receives the encoding. The time latch performs the Figure 1 latching steps as shown and puts the decoded current time point into the time information register group.

[0117] S7: The DMA data transfer module combines the current time point saved in the time information register group and the first encoding sent by the event pulse generator into a group of data for re-encoding to form the second encoding containing the trigger channel, trigger time, and trigger event. The setting rule of the second encoding is: trigger channel (serial number): trigger time (time): trigger event (trigger rule), such as 1: time: rising edge; 2: time: falling edge..........(where the serial number represents the channel name, which is represented bit by bit in binary conversion mode; time represents the latched instantaneous time corresponding to the channel name, that is, the current time point; the trigger rule represents the rule by which it is triggered, such as rising edge or falling edge).

[0118] S8: Put the second encoding into the event FIFO module for storage.

[0119] The above steps (S6~S8) are all executed in sequence by the IRIG-G(DC) decoder. By analogy with the corresponding time points of subsequent data sources, the specific time points when different data sources enter the input end of the functional card can be obtained.

[0120] S9: The soft-core CPU reads the current time point data from the time information register group of the IRIG-G(DC) decoder through the AVALON bus to obtain the time information of the current trigger event;

[0121] S10: The soft-core CPU reads the second encoding from the event FIFO module of the IRIG-G(DC) decoder through the AVALON bus to obtain the time information of the historical event trigger.

[0122] The above steps (S9 and S10) are selectively executed by the soft-core CPU according to actual requirements.

[0123] It should be noted that:

[0124] (1) The reason for finally storing the data group, i.e., the second encoding, in the event FIFO module is that the time information register group can only store the latest time data information, and subsequent new time data information will overwrite the previous time data information. Therefore, only by storing the data group obtained in step S6 in the event FIFO module can the preservation and reading of the historical time information in step S10 be realized; on the other hand, if only the time information of the current trigger event needs to be obtained, the soft-core CPU can directly read the latest data from the time information register group through the AVALON bus (as described in step S9).

[0125] (2) As a coprocessor, the DMA data transfer module can operate independently across the soft-core CPU when the time point information of the historical trigger event needs to be read, reducing the burden on the soft-core CPU.

[0126] The specific benefits achieved by the DMA data transfer module in this exemplary embodiment include: ① Greatly improving time accuracy: If the soft-core CPU is used for latching instead of using the DMA, a random error (ranging from a few microseconds to a few milliseconds) will be introduced, which will have a great impact on the system synchronization accuracy and cannot be eliminated; while using the DMA will only introduce a fixed error at the nanosecond level, which is relatively easy to be eliminated in later applications. ② Independently handling the work of the soft-core CPU on its behalf, enabling it to handle other matters, accelerating the system operation efficiency and thus improving the overall system performance. ③ The event FIFO module can cache the latched historical instantaneous time information for the soft-core CPU to read at any time.

[0127] In addition, Figures 12 - 18 The schematic diagrams of the functional card architecture and chassis architecture obtained by combining the above exemplary embodiments are shown. Specifically:

[0128] Figure 12 shows the architecture diagram of the main controller card for latching relative time based on the Figure 10 function card structure. The related process of the main controller card for latching relative time includes: the soft-core CPU sends the initial time information to the IRIG-G(DC) encoder through the AVALON bus, and the IRIG-G(DC) encoder starts timing on its own based on the initial time; after the initial time information enters the IRIG-G(DC) encoder, as Figure 4 shown, the symbol generator inside the IRIG-G(DC) encoder converts the initial time information into symbols, and then the time extraction pre-carry processing module and the time synchronizer convert the symbols into relative time information pulses. Every third cycle (0.01 s), the relative time information pulses are transmitted to the bus signal distributor, and the bus signal distributor transmits the pulse signals to the IRIG-G(DC) decoder for decoding or transmits them to the second MLVDS transceiver and the first CAT5e network port for external pulse emission. When transmitted to the IRIG-G(DC) decoder, the IRIG-G(DC) decoder extracts the symbols and the timing information pulses from the relative time information pulses to obtain the updated coarse time, and then refreshes the extracted timestamp information every first cycle (0.1 ms) through the timing time (coarse time) (and sends it as the synchronization pulse of the coarse time timing information of the functional sub-card to the backplane timing bus through the first MLVDS transceiver and then to the functional sub-card. If there is a functional sub-card, as Figure 6 shown), the timing time (fine time) refreshes the time difference information generated by its own clock every second cycle (10 ns). Coarse time + fine time = current time point (absolute time point of the current moment), and the time point immediately latched after the time latch is triggered is this time point.

[0129] Figure 13 shows the architecture diagram of the main controller card for latching real time based on the Figure 10 function card structure. The related process of the main controller card for latching real time includes: the high-precision timing module sends real time information pulses to the main controller card. The second CAT5e network port of the main controller card receives external pulses and transmits them to the bus signal distributor through the third MLVDS transceiver. The bus signal distributor sends the real time information pulses to the IRIG-G(DC) decoder or emits them externally through the second MLVDS transceiver. The remaining time latching content is the same as the Figure 12 related process described above and will not be elaborated here.

[0130] Figure 14 shows the architecture diagram based on Figure 10Schematic diagram of the architecture of the latching time of the functional daughter card in the functional card structure. The related processes of the functional daughter card for latching time include: receiving the synchronization pulse sent by the main controller card through the fourth MLVDS transceiver connected to the backplane timing bus, and sending the synchronization pulse to the IRIG-G(DC) decoder for decoding to complete the coarse time synchronization of the functional daughter card (corresponding to Figure 8 ). The latching content for the remaining time is the same as the related processes described in Figure 12 , and will not be elaborated here.

[0131] Figure 15 and Figure 16 show the schematic diagram of the architecture for latching relative time and real time in a chassis including the main controller card and the functional daughter card, where Figure 15 the related logic is the same as that of Figure 12 superimposed with Figure 14 . The related logic of Figure 16 is the same as that of Figure 13 superimposed with Figure 14 , and will not be elaborated here.

[0132] Figure 17 and Figure 18 show the schematic diagram of the architecture for latching relative time and real time in multiple chassis. The functional daughter card is not shown in the figure. If needed, it can be superimposed according to the related content of Figure 15 and Figure 16 . Among them, the time information generator (the relative time is generated by the IRIG-G(DC) encoder and the real time is sent by the external high-precision timing module) sends the generated time information pulse to the bus signal distributor every third cycle. The bus signal distributor sends the time information pulse as the cross-chassis coarse time synchronization information to the main controller card of the cross-chassis device through the second MLVDS transceiver and the first CAT5e network port. The main controller card of the cross-chassis device receives the time information pulse sent externally as the cross-chassis coarse time synchronization information through the third CAT5e network port every third cycle, and sends it to the IRIG-G(DC) decoder through the fifth MLVDS transceiver and the bus signal distributor. The IRIG-G(DC) decoder decodes to obtain the cross-chassis coverage update time synchronization information ( Figure 9 ). The latching content for the remaining time is the same as the related processes described in Figure 12 , and will not be elaborated here.

[0133] Obviously, the above embodiments are merely examples given for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, based on the above description, other different forms of changes or variations can be made. It is not necessary and impossible to enumerate all the implementation manners here. And the obvious changes or variations derived therefrom are still within the protection scope of the present invention.

Claims

1. A time latching method based on a functional card, characterized in that: Including: A time latch receives a trigger signal and latches the current time point; the current time point includes coarse time timing information and fine time timing information; The coarse time timing information is obtained by extracting the time stamp of the coarse time refreshed every first period, and the first period corresponds to the IRIG-G(DC) protocol; the fine time timing information is obtained by extracting the fine time counted every second period, and the second period corresponds to the local clock frequency; The fine time timing information is specifically the time difference information generated by the local clock within each first period. The local clock includes a counter unit and a fine time calculation unit. The maximum counting number of the counter unit is the first period divided by the second period. The counter unit performs an increment operation every second period until it reaches the maximum counting number and then performs a reset operation; When the time latch is triggered, the fine time calculation unit multiplies the counting value of the counter unit by the second period to obtain the time difference information as the fine time timing information.

2. The time latching method based on a functional card according to claim 1, characterized in that: The coarse time timing information is the coarse time timing information of the main controller card.

3. A time latching method based on a functional card according to claim 2, characterized in that: For the coarse time based on the coarse time timing information of the main controller card, it is covered and updated every third period. The covering and updating method includes: The time information generator sends the generated time information pulse to the bus signal distributor every third period, and the bus signal distributor sends the time information pulse to the IRIG-G(DC) decoder; The IRIG-G(DC) decoder processes the received time information pulse to obtain the covered and updated time timing information. The covered and updated time timing information includes extracting the code element of the time information pulse by the code element extraction module, extracting the timing information and pulse of the time information pulse by the timing information pulse extraction module; Using the covered and updated time timing information to cover and update the coarse time.

4. A time latching method based on a functional card according to claim 3, characterized in that: The time information pulse generated by the time information generator is a relative time information pulse. The time information generator includes an IRIG-G(DC) encoder, and the IRIG-G(DC) encoder includes a code element generator, a time extraction pre-carry processing module and a time synchronizer; The time information generator generates a relative time information pulse, including: The soft-core CPU sends the initial time information to the IRIG-G(DC) encoder through the AVALON bus, and the IRIG-G(DC) encoder starts timing on the initial time information to obtain the relative time information; The code element generator of the IRIG-G(DC) encoder converts the relative time information into code elements, and then the time extraction pre-carry processing module and the time synchronizer convert the code elements into relative time information pulses and send the relative time information pulses to the bus signal distributor.

5. A time latching method based on a functional card according to claim 3, characterized in that: The time information pulse generated by the time information generator is a real time information pulse. The time information generator includes a second CAT5e network port and a third MLVDS transceiver; The time information generator generates a real time information pulse, including: The second CAT5e network port receives the real time information pulse sent by the external high-precision timing module and forwards it to the bus signal distributor through the third MLVDS transceiver.

6. A time latching method based on a functional card as claimed in any one of claims 2 to 5, characterized in that: The IRIG-G(DC) decoder forms the time stamp of the coarse time refreshed every first cycle as a synchronization pulse of the coarse time timing information of the functional sub-card, and sends it to the backplane timing bus through the first MLVDS transceiver.

7. A time latching method based on a function card according to any one of claims 3 to 5, characterized in that: The time information generator sends the generated time information pulse to the bus signal distributor every third cycle. The bus signal distributor sends the time information pulse to the outside through the second MLVDS transceiver and the first CAT5e network port as the cross-chassis coarse time synchronization information.

8. A time latching method based on a functional card according to claim 1, characterized in that: The coarse time timing information is the coarse time timing information of the functional sub-card; The coarse time timing information of the functional sub-card is obtained by the fourth MLVDS transceiver receiving the synchronization pulse through the backplane timing bus every first cycle and sending it to the IRIG-G(DC) decoder for decoding.

9. A time latching method based on a functional card according to claim 1, characterized in that: The coarse time timing information is the cross-chassis coarse time timing information; the coarse time on which the cross-chassis coarse time timing information is based is covered and updated every third cycle, and the covering and updating method includes: Receiving the time information pulse sent from the outside as the cross-chassis coarse time synchronization information through the third CAT5e network port every third cycle, and sending it to the IRIG-G(DC) decoder through the fifth MLVDS transceiver and the bus signal distributor. The IRIG-G(DC) decoder decodes to obtain the cross-chassis covering and updating time synchronization information. The cross-chassis covering and updating time synchronization information includes extracting the code elements of the time information pulse by using the code element extraction module, and extracting the timing information and pulse of the time information pulse by using the timing information pulse extraction module; Covering and updating the coarse time by using the cross-chassis covering and updating time synchronization information.

10. A time latching method based on a functional card according to claim 1, characterized in that: The functional card includes an automatic event trigger, an IRIG-G(DC) decoder, and a soft-core CPU; the automatic event trigger includes a signal preprocessing module, a multi-channel data source module, a data filter module, a threshold discrimination module, and an event pulse generator; the IRIG-G(DC) decoder includes a DMA data transfer module, a time latch, a time information register group, and an event FIFO module; The recording of the event trigger time of the functional card includes: The signal preprocessing module of the automatic event trigger receives the external trigger signal for digital processing, and sequentially sends it to the data filter module and the threshold discrimination module through the multi-channel data source module for filtering and threshold screening. The data source after screening directly triggers the event pulse generator to form the first encoding including the trigger channel and the trigger event; The DMA data transfer module of the IRIG-G(DC) decoder receives the first encoding through the AVALON bus and triggers the time latch at the same time. The time latch puts the decoded current time point into the time information register group. The DMA data transfer module re-encodes the current time point and the first encoding taken out from the time information register group to form the second encoding including the trigger channel, the trigger time, and the trigger event; and puts the second encoding into the event FIFO module for storage; The reading of the event trigger time of the functional card includes: The soft-core CPU reads the current time point data from the time information register group of the IRIG-G(DC) decoder through the AVALON bus to obtain the time information of the current trigger event; and / or: The soft-core CPU reads the second encoding from the event FIFO module of the IRIG-G(DC) decoder through the AVALON bus to obtain the time information of the historical event trigger.

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