Heterogeneous multi-core system, communication method and computer readable storage medium

Abstract

The invention is suitable for the technical field of computers, and provides a heterogeneous multi-core system, a communication method and a computer readable storage medium, the system comprises a server and a heterogeneous multi-core SOC, and the heterogeneous multi-core SOC comprises a plurality of cores; a virtual network is arranged between the server and the plurality of kernels; a client side of a first application program is arranged on the server, a server side of the first application program is arranged on the first kernel, the client side of the first application program communicates with the server side of the first application program through a virtual network, and the first kernel is any one of a plurality of kernels; the first application program comprises a network tool or a chip management tool. A virtual network is arranged between a server and a plurality of kernels, and a client and a server for network tool or chip management work are respectively arranged on the server and the kernels, so that the management of the kernels is realized, the server and the kernels do not need to be connected through a network port, and the hardware interface connection between the server and an SOC chip is reduced.

Description

Technical Field

[0001] The present application belongs to the field of computer technology, and in particular, relates to a heterogeneous multi-core system, a communication method, and a computer-readable storage medium. Background Art

[0002] With the development of computer science, people's demand for processing power is growing. Heterogeneous multi-core SOC (System On a Chip) architecture came into being. Heterogeneous multi-core SOC is composed of multiple types of cores, and different types of cores have different CPU architectures, such as ARM (Advanced RISC Machine), RISC-V (Reduced Instruction Set Computing-Five), NPU (Neural Processing Unit), etc. In heterogeneous multi-core SOC, different types of cores can work in parallel, and dynamically allocate workloads to the most suitable cores according to the characteristics and requirements of the task to optimize the performance and energy efficiency of the system. Based on the above characteristics, heterogeneous multi-core SOC has been widely used in artificial intelligence (AI), scientific computing, games, image processing and other fields.

[0003] In the development and application of heterogeneous multi-core SOC, each core on the SOC needs to be connected to the server through an external network port and a serial port, so that users can manage each core through the server. When the number of cores included in the heterogeneous multi-core SOC is large, a large number of interfaces need to be connected between the SOC and the server. This will increase the hardware cost of the heterogeneous multi-core SOC, and the operation is also more cumbersome. Therefore, how to manage each core in the heterogeneous multi-core SOC without adding additional hardware has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] The embodiments of the present application provide a heterogeneous multi-core system, a communication method and a computer-readable storage medium, which can solve the technical problem of the large number of interfaces between heterogeneous multi-core SOCs and servers in the prior art.

[0005] In a first aspect, an embodiment of the present application provides a heterogeneous multi-core system, including: a server and a heterogeneous multi-core SOC, the heterogeneous multi-core SOC including multiple cores;

[0006] A virtual network is set up between the server and multiple cores;

[0007] A client of a first application is arranged on a server, and a server of the first application is arranged on a first core. The client of the first application communicates with the server of the first application through a virtual network. The first core is any one of a plurality of cores, and the first application includes a network tool or a chip management tool.

[0008] In a second aspect, an embodiment of the present application provides a communication method, which is applied to the system of the first aspect, and the method includes:

[0009] The server obtains request information generated by the client of the first application;

[0010] The server sends request information to the first kernel through the virtual network;

[0011] The first kernel obtains response data generated by the server of the first application in response to the request information;

[0012] The first kernel sends response data to the server through the virtual network.

[0013] In a third aspect, an embodiment of the present application provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor comprises a processor and various cores on a server in the system described in the first aspect above.

[0014] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the steps performed by the server or any one of the cores in the method described in the second aspect above.

[0015] In a fifth aspect, an embodiment of the present application provides a computer program product, which, when executed on an electronic device, enables the terminal device to execute the steps of the server or any one of the kernels in the method described in the second aspect above.

[0016] As can be seen from the above, in the embodiment of the present application, since the server and the multiple cores are connected via a virtual network, and the management tool application is installed between the server and the core, the user can manage the core through the server. In a heterogeneous multi-core system, there is no need to connect each core to the server via a physical interface, so the management of multiple cores can be achieved on the basis of reducing the hardware interface on the heterogeneous multi-core SOC. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 It is a schematic diagram of the structure of a heterogeneous multi-core system provided by an embodiment of the present application;

[0019] Figure 2 This is a schematic diagram of a virtual network connection between a server and each core in a heterogeneous multi-core system provided by an embodiment of the present application;

[0020] Figure 3 It is a schematic diagram of the principle of data exchange between two cores through an inter-core communication module in a heterogeneous multi-core system provided by an embodiment of the present application;

[0021] Figure 4 is a schematic diagram of the software architecture of a heterogeneous multi-core system provided in another embodiment of the present application;

[0022] Figure 5 is an interaction diagram of a communication method provided by an embodiment of the present application;

[0023] Figure 6 It is a schematic diagram of the structure of an electronic device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0024] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0025] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0026] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0027] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0028] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0029] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0030] In traditional heterogeneous multi-core systems, each core on the heterogeneous multi-core SOC is connected to the server through an external network port and a serial port, so that users can manage each core through the server, such as accessing the core, sending files to the core, maintaining the core, or debugging the multi-core. It is costly to increase the hardware interface to ensure the adjustability and maintainability of the heterogeneous multi-core system, and the operation is cumbersome because more interfaces need to be connected. Furthermore, in order to meet the connection of multiple interfaces, it is necessary to reserve enough interfaces on the heterogeneous multi-core SOC and the server, which will affect the productization of the heterogeneous multi-core SOC.

[0031] In order to solve the above technical problems, an embodiment of the present application provides a heterogeneous multi-core system, which includes a server and a heterogeneous multi-core SOC, the heterogeneous multi-core SOC includes multiple cores, and the server and the multiple cores are connected to each other through a virtual network; a client of a first application is set on the server, and a server of the first application is set on the first core, the client of the first application communicates with the server of the first application through a virtual network, the first core is any one of the multiple cores, and the first application includes a network tool or a chip management tool. By setting up a virtual network between the server and the multiple cores, and installing an application of the management tool between the server and the core, the user can manage the core through the server. In a heterogeneous multi-core system, there is no need to connect each core to the server through a physical interface, so the management of multiple cores can be achieved on the basis of reducing the hardware interface on the heterogeneous multi-core SOC.

[0032] The heterogeneous multi-core system in the embodiment of the present application is exemplarily described below with reference to the accompanying drawings.

[0033] Figure 1 Schematic diagram of the structure of a heterogeneous multi-core system in an embodiment of the present application. Figure 1 As shown, in this embodiment, the heterogeneous multi-core system includes: a server, SOC0, and SOC1, wherein SOC0 and SOC1 are two heterogeneous multi-core SOCs, and SOC0 and SOC1 include 4 cores respectively. A virtual network is formed between the server and the multiple cores, thereby realizing the network connection between the server and the multiple cores; the client of the application is set on the server, and the server of the application is set on the core, wherein the application can be a network tool or a chip management tool. The user can manage the core through the client on the server, for example, the client can access the core, remotely log in, or share file transfers, etc.

[0034] like Figure 1 As shown, in an embodiment of the present application, the server may include: a chip management tool and a network tool module, a virtual network card module and an inter-core communication module, and each core includes: a network tool module, a virtual network card module and an inter-core communication module.

[0035] In the server: the chip management tool / network tool module is used to provide users with related services of the chip management tool and the network tool. For example, the chip management tool and the network tool module may include the client of the corresponding tool, and the client cooperates with the server provided on the kernel (i.e., the network tool module on the kernel) to provide services to users. The virtual network card module is used to realize the virtual network connection between the server and the kernel. For example, the virtual network card module may include a virtual network device driver. The connection between the virtual network device driver and the virtual network driver device provided on the kernel is the virtual network connection between the server and the kernel. The inter-core communication module is used to realize point-to-point communication between the server and the kernel. For example, the inter-core communication module in the server has the same structure and function as the inter-core communication module in the kernel. The shared memory area and the MailBox module are used to complete the data sending and receiving between the server and the kernel. The specific data sending and receiving process is the same as Figure 3 The process shown is similar and will not be described again here.

[0036] In each kernel: the network tool module is used to cooperate with the chip management tool / network tool module in the server to provide the corresponding tool service to the user. For example, the network tool module may include the server end of the corresponding tool. The virtual network card module is used to implement a virtual network connection between the kernel and the server (or between kernels). For example, the virtual network card module may include a virtual network device driver. The connection between the virtual network device driver and the virtual network driver device set on the kernel is the virtual network connection between the server and the kernel. The connection between the virtual network device driver and the virtual network driver device set on other kernels is the virtual network connection between the kernel and other kernels. The inter-core communication module is used to implement point-to-point communication between the kernel and the server, and / or to implement point-to-point communication between the kernel and other kernels. The data sending and receiving process of the inter-core communication module is the same as that of the server. Figure 3 The process shown is similar and will not be described again here.

[0037] Understandably, Figure 1 In the illustrated embodiment, the heterogeneous multi-core system includes two heterogeneous multi-core SOCs. This example should not be understood as a limitation on the number of heterogeneous multi-core SOCs. Those skilled in the art can increase or decrease the number of heterogeneous multi-core SOCs as needed, that is, in a heterogeneous multi-core system, the number of heterogeneous multi-core SOCs can be more or less, and this application does not impose any limitation on this.

[0038] The following is an exemplary description of the application programs set on the server and the kernel in the embodiments of the present application using common network tools.

[0039] For example, the application can be an SSH remote login tool, and the user can log in to each kernel through the SSH client on the server. The user can execute commands, view system status, configure the kernel, and so on in the SSH client. For example, the application can also be an SCP tool, and the user can use the SCP client to transfer files between the server and each kernel, making it easier for the user to share files and data between the server and the kernel. For another example, the application can also be an FTP tool, and the user can use the FTP client to perform more flexible file transfer and sharing between the server and the kernel.

[0040] It is understandable that by setting up a virtual network between the server and the core, common network tools can be deployed on the server and multiple cores, thereby reducing the manpower and time costs of developing tools. And because the use of common network tools is more user-friendly, the training process before using new R&D tools can be avoided, and users can use them directly, improving work efficiency.

[0041] In some embodiments, Figure 1 As shown, a virtual network card (i.e., a virtual network device driver) can be installed on the server and each core respectively, and the virtual network includes: a connection between the virtual network card on the server and the virtual network card (i.e., a virtual network device driver) on each core. That is, by setting a virtual network card (i.e., a virtual network device driver) on the server and the core, a network connection between the server and the core can be achieved.

[0042] In some other embodiments, the virtual network may also include a connection between virtual network cards (ie, virtual network device drivers) between cores, that is, a virtual network also exists between different cores.

[0043] To facilitate understanding, the process of building a virtual network is exemplarily described below.

[0044] It is understandable that before building a virtual network, it is necessary to allocate shared memory in advance, allocate a first memory for each core to share with the server, and map the first memory corresponding to each core to the memory space of the server through PCIe to obtain a shared memory area corresponding to each core (the shared memory area is the shared memory area between each core and the server). It is understandable that for any two cores that need to be connected to a virtual network, a shared memory will be allocated. After completing the allocation of shared memory, the virtual network is constructed. The construction of the virtual network mainly includes the following steps:

[0045] (1) Load the virtual network device driver on the server and each core respectively. The name of the virtual network device driver in the embodiment of the present application is vnet.ko, that is, insmod vnet.ko.

[0046] (2) Use the common network configuration command ifconfig to configure the IP address of the vnet for the server and each core. For example: ifconfig vnet 192.168.10.100.

[0047] (3) After completing the loading of the virtual network device driver and the configuration of the IP address, the virtual network device driver on the server will monitor the status of the virtual network device drivers on other cores (each core will also monitor the status of the virtual network device drivers on the server or other cores): the status of the core that is already online is marked as online. After monitoring that a core is already online, the inter-core communication module is initialized to determine the shared memory between the core and the core.

[0048] (4) The virtual network device driver on the server or each core will periodically check the status of the virtual network device drivers on other devices (cores or servers): connect to the configured virtual network device driver, and disconnect the core that has uninstalled the virtual network device driver. Regular checks can ensure the validity of the connection between each virtual network driver device, thereby ensuring the reliability of the virtual network.

[0049] Exemplarily, the virtual network connection established between the server and each core is as follows: Figure 2 As shown in the figure, the IP address of the server is 192.168.10.100; the IP addresses of the four cores CoreA, CoreB, CoreC and CoreD on SOC0 are 192.168.10.101, 192.168.10.102, 192.168.10.103 and 192.168.10.104 respectively; the addresses of the four cores CoreA, CoreB, CoreC and CoreD on SOC1 are 192.168.10.111, 192.168.10.112, 192.168.10.113 and 192.168.10.114 respectively.

[0050] It is understandable that for Linux systems, a virtual network is formed by loading a virtual network device driver on the kernel or server; for RTOS (Real Time Operating System), a lightweight network protocol stack such as lwip can be used to form a virtual network.

[0051] In the embodiment of the present application, the server and SOC0, as well as the server and SOC1, are connected via PCIe, that is, the board equipped with SOC0 and the board equipped with SOC1 are connected to the server via PCIe interfaces, respectively.

[0052] In some embodiments, SOC0 and SOC1 can be set on the same board, and the board is connected to the server through a PCIe interface. That is, when a heterogeneous multi-core system includes multiple heterogeneous multi-core SOCs, the multiple heterogeneous multi-core SOCs can be set on one board or multiple boards, where each board can be set with one or more heterogeneous multi-core SOCs, and this application does not specifically limit the number of boards.

[0053] In some other embodiments, two servers may be set in the heterogeneous multi-core system. Assume that the two servers are the first server and the second server, respectively. The heterogeneous multi-core SOC is connected to the first server via PCIe, and a virtual network is set between the first server and the heterogeneous multi-core SOC; the first server and the second server are connected via the network. The user can manage the cores in the heterogeneous multi-core SOC connected to the first server through the interaction between the second server and the first server.

[0054] It is understandable that the second server is connected to the first server via a network, and the second server may be a local server or a remote server, which is not limited in this embodiment of the present application.

[0055] It should be understood that the first server may be Figure 1 , Figure 2 , Figure 4 and Figure 5 Servers in a heterogeneous multi-core system as shown in .

[0056] After explaining the construction of the virtual network above, the inter-core communication module is exemplarily explained below.

[0057] It can be understood that the inter-core communication module is mainly used to complete point-to-point communication between two cores (or between a server and a core). Generally speaking, the inter-core communication module completes data sending and receiving between two cores (or between a server and a core) through a shared memory area and a MailBox module.

[0058] The following takes the inter-core communication module between two cores as an example to illustrate the structure and data interaction method of the inter-core communication module.

[0059] Figure 3 A schematic diagram of the principle of data exchange between two cores through an inter-core communication module in a heterogeneous multi-core system provided in an embodiment of the present application. Figure 3As shown, two shared memory areas are allocated between the two cores CoreA and CoreB as channels for data transmission, and the two shared memories are respectively a first shared memory area 310 and a second shared memory area 320, wherein: the first shared memory area 310 is a shared memory from CoreA to CoreB, that is, a shared memory used when CoreA sends data to CoreB; the second shared memory area 320 is a shared memory from CoreB to CoreA, that is, a shared memory used when CoreB sends data to CoreA.

[0060] like Figure 3 As shown, the head of each shared memory area allocates an area to store the read pointer (312, 322) and the write pointer (311, 321). The cores CoreA and CoreB synchronize the location of the data area through the read and write pointers. After each read and write operation, the read and write pointers are updated according to the read and write content. After the kernel of the data sending end writes the data to the shared memory area, it sends an interrupt to the kernel of the other end through the MailBox module to notify the other end to read.

[0061] like Figure 3 As shown, a user program 331 is running on the core CoreA, and the user program 331 communicates with the peer through the inter-core communication module. The inter-core communication module of the core CoreA includes: a first data sending submodule 332, a first data receiving submodule 333, and a first storage management and connection management module 334.

[0062] A user program 341 runs on the core CoreB, and the user program 341 communicates with the peer through the inter-core communication module. The inter-core communication module of the core CoreB includes: a second data sending submodule 342, a second data receiving submodule 343, and a second storage management and connection management module 344.

[0063] The first storage management and connection management module 334 and the second storage management and connection management module 344 are used to implement storage management of the corresponding kernel and connection management between kernels.

[0064] When the user program 331 instructs the kernel CoreA to send data to the kernel CoreB, the first data sending submodule 332 writes the data into the first shared memory area 310 and updates the position of the write pointer 311; after updating the write pointer 311, the first data sending submodule 332 sends an interrupt to the kernel CoreB through the MailBox module; after receiving the interrupt, the second data receiving submodule 343 uses the callback function to query the write pointer 311 and the read pointer 312, and determines whether the write pointer 311 and the read pointer 312 are equal. If they are not equal, it means that there is data to be received. The second data receiving submodule 343 reads the read pointer 312 and reads data from the starting position of the read pointer 312. After reading the data, the read pointer 312 is updated.

[0065] When the user program 341 instructs the kernel CoreB to send data to CoreA, the second data sending submodule 342 writes the data into the second shared memory area 320 and updates the position of the write pointer 321; after updating the write pointer 321, the second data sending submodule 342 sends an interrupt to the kernel CoreA through the MailBox module; after receiving the interrupt, the first data receiving submodule 333 uses the callback function to query the write pointer 321 and the read pointer 322, and determines whether the write pointer 321 and the read pointer 322 are equal. If they are not equal, it means that there is data to be received. The first data receiving submodule 333 reads the read pointer 322 and reads data from the starting position of the read pointer 322. After reading the data, the read pointer 322 is updated.

[0066] It is understandable that before using the inter-core communication module for data exchange, the inter-core communication module needs to be initialized and connected. Taking two cores as an example, the initialization and connection process includes:

[0067] (1) First, two shared memory areas are allocated to keep the information of the two cores about the shared memory areas synchronized. It can be understood that each shared memory area includes a management memory area and a data area, wherein the management memory area stores the base address, length, read pointer and write pointer of the data area.

[0068] (2) Determine whether the peer is online based on the status of the peer's kernel. If the peer's kernel is online and can communicate, try to connect to the peer's kernel. It should be understood that all kernels (including servers) will agree on a shared area to synchronize the online information of each kernel (including servers). When the kernel is online, the corresponding bit is set.

[0069] The above describes the process of data interaction between two cores through the inter-core communication module. It can be understood that the process of data interaction between the server and the core through the inter-core communication module is similar to the above process and will not be repeated here.

[0070] It should be understood that multiple cores on the same heterogeneous multi-core SOC can share memory through an external DDR (double rate synchronous dynamic random access memory). However, the memory used by the server and the core is different, and memory cannot be shared directly. Therefore, the server and the core can share memory through PCIe memory mapping. For example, a memory area shared with the server can be determined in the memory of each core, and the memory area is mapped to the server's memory space to become a mapped memory area. This mapped memory area is the shared memory area between the server and the core. Figure 1 As shown, each core in SOC0 and SOC1 has a memory area mapped to the memory area of ​​the server through PCIe memory mapping, thereby realizing shared memory between the server and the core.

[0071] For ease of understanding, the software architecture of the heterogeneous multi-core system in this application is exemplarily described below with reference to the accompanying drawings. Figure 4 A schematic diagram of the software architecture of a heterogeneous multi-core system provided in another embodiment of the present application.

[0072] like Figure 4 As shown, the heterogeneous multi-core system in this implementation includes a server and a heterogeneous multi-core SOC, wherein the heterogeneous multi-core SOC includes two cores: core CoreA and core CoreB, and the heterogeneous multi-core SOC is connected to the server through a PICe interface.

[0073] like Figure 4 As shown, the network architecture of the heterogeneous multi-core system in the embodiment of the present application is similar to the layered structure of the network protocol stack. The network architecture of the heterogeneous multi-core system in the embodiment of the present application is exemplarily described below.

[0074] like Figure 4 As shown, the network architecture includes: a shared memory and interrupt layer 410, an inter-core communication layer 420, a virtual network card driver layer 430, a TCP / IP protocol stack layer 440, and a network tool / chip management client layer 450, wherein:

[0075] Shared memory and interrupt layer 410, in the embodiment of the present application, data is ultimately transmitted via shared memory and MailBox interrupts.

[0076] The inter-core communication layer 420 is used to complete the transmission and reception of data frames, mainly to ensure that data is transmitted between cores or between a core and a server in the form of meaningful data frames.

[0077] Virtual network card driver layer 430, in the embodiment of the present application, this layer user identifies different kernels or servers, thereby ensuring that data is transmitted from one kernel (or server) to the destination kernel (or server). In this layer, IP addresses are used to identify different kernels or servers on the network, that is, each kernel and server in a heterogeneous multi-core system has a unique IP address. This layer provides an interface to the upper TCP / IP protocol stack layer 440, and completes the transmission and reception of data frames together with the lower inter-core communication layer 420.

[0078] The TCP / IP protocol stack layer 440 is a TCP / IP protocol stack in the embodiment of the present application. This layer is used to implement end-to-end reliable data transmission. This layer uses port numbers to identify different tools and is responsible for correctly transmitting data to the target port.

[0079] The network tool / chip management client layer 450 includes various tool clients for implementing different application functions, such as file transfer and sharing (FTP or SCP), remote login (SSH), etc. In this layer, data is transmitted and received through protocols at various levels.

[0080] It can be understood that the virtual network card driver layer 430 in the embodiment of the present application mainly includes: a network initialization module, an open network module, a data sending module and a data receiving module, wherein: the network initialization module is mainly used to register network devices (i.e., kernels or servers), set MAC addresses, etc., and initialize the inter-core communication module of the kernel (or server); the open network module is used to configure the network IP address for the kernel (or server), and when other kernels (or servers) that can be connected are detected, try to connect to other kernels (or servers); the data sending module sends network data packets through the data sending submodule in the inter-core communication layer; the data receiving module is used to analyze the network data packets through the callback function after receiving the interrupt, and send the valid data packets to the upper TCP / IP protocol stack layer 440 for parsing and processing.

[0081] It is understandable that the description of the network architecture in the embodiments of the present application is exemplary, and those skilled in the art may make appropriate adjustments and plans to the network architecture as needed, and the present application does not impose any specific limitations on this.

[0082] After introducing the network architecture of the heterogeneous multi-core system in the embodiment of the present application, in order to make the heterogeneous multi-core system in the present application easier to understand, the communication method based on the heterogeneous multi-core system in the embodiment of the present application is exemplarily described below.

[0083] Figure 5 An interaction diagram showing the communication method provided by the present application is shown in FIG. Figure 5 , the method comprising:

[0084] Step S501: The server obtains request information generated by the client of the first application.

[0085] In an embodiment, the client of the first application is installed on the server. When the user needs to use the first application to manage the first kernel, the user operates on the client of the first application, the first application client generates corresponding request information, and the server obtains the request information from the client of the first application.

[0086] For example, the client of the first application may be a remote login client, and the request information may be a request to log in to the first kernel.

[0087] Of course, the first application client may also be any other possible client, and this application does not impose any limitation on this.

[0088] Step S502: The server sends request information to the first kernel through the virtual network.

[0089] In the embodiment, after obtaining the request information, the server sends the request information to the first kernel through the virtual network.

[0090] Exemplarily, after obtaining the request information, the server determines that the destination device of the request information is the first kernel according to the request information (for example, according to the IP address in the request information).

[0091] Exemplarily, the server sends request information to the first kernel through the virtual network, specifically including: the server writes the request information into the first shared memory area (i.e., the shared memory area of ​​the server and the first kernel), after the server completes writing the request information, it sends an interrupt to the first kernel through the MailBox module; after receiving the interrupt, the first kernel reads the request information from the first shared memory area. The specific process can refer to the data interaction process of the inter-core communication module in the previous text, which will not be repeated here.

[0092] Step S503: The first kernel obtains the response data generated by the server of the first application in response to the request information 。

[0093] In the embodiment, the request information is finally sent to the first application server on the first kernel. The first application server generates response data in response to the request information. The first kernel obtains the response data from the server of the first application.

[0094] For example, assuming that the request information is a request to remotely log in to the first kernel, the response data is usually a response to the login result. If the login is successful, the response data may include a welcome message or a command line prompt after the login. If the login fails, the response data will include a corresponding error message.

[0095] Step S504: the first kernel sends response data to the server through the virtual network.

[0096] In an embodiment, after obtaining the response data, the first kernel determines that the destination device of the response data is the server based on the response data (i.e., based on the IP address of the server included in the corresponding data), and sends the response data to the server through the virtual network.

[0097] In the embodiment of the present application, after receiving the response data, the server displays the response data to the user, for example, it may display the response of the first kernel to the login result to the user.

[0098] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0099] Figure 6 This is a schematic diagram of the structure of an electronic device provided by an embodiment of the present application. Figure 6 As shown, the electronic device 6 of this embodiment includes: a processor 60, a memory 61, and a computer program 62 stored in the memory 61 and executable on the at least one processor 60, wherein the processor 60 includes the processor and each core of the server in any of the above-mentioned system embodiments.

[0100] The electronic device 6 may be a computing device such as a desktop computer, a notebook, a PDA, or a cloud server. The electronic device may include, but is not limited to, a processor 60 and a memory 61. Those skilled in the art will appreciate that Figure 6 It is only an example of the electronic device 6 and does not constitute a limitation on the electronic device 6. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, it may also include input and output devices, network access devices, etc.

[0101] The processor 60 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0102] In some embodiments, the memory 61 may be an internal storage unit of the electronic device 6, such as a hard disk or memory of the electronic device 6. In other embodiments, the memory 61 may also be an external storage device of the electronic device 6, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped on the electronic device 6. Further, the memory 61 may also include both an internal storage unit of the electronic device 6 and an external storage device. The memory 61 is used to store an operating system, an application program, a boot loader (BootLoader), data, and other programs, such as the program code of the computer program, etc. The memory 61 may also be used to temporarily store data that has been output or is to be output.

[0103] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps performed by the server or any one of the cores in the above-mentioned various method embodiments are implemented.

[0104] An embodiment of the present application provides a computer program product. When the computer program product runs on an electronic device, the electronic device implements the steps executed by the server or any one of the cores in the above-mentioned various method embodiments.

[0105] The present application also provides a chip, which includes: a processing unit and a communication unit, wherein the processing unit may be, for example, a processor, and the communication unit may be, for example, an input / output interface, a pin or a circuit, etc. The processing unit may execute computer instructions to enable a computer device to execute the steps executed by a server or any one of the cores in any of the method embodiments provided in the present application.

[0106] Optionally, the computer instructions are stored in a storage unit.

[0107] Optionally, the storage unit is a storage unit in the chip, such as a register, a cache, etc. The storage unit can also be a storage unit located outside the chip in the terminal, such as a ROM or other types of static storage devices that can store static information and instructions, random RAM, etc. Among them, the processor mentioned in any of the above can be a CPU, a microprocessor, an ASIC, or one or more integrated circuits for controlling the execution of the program of the above method. The processing unit and the storage unit can be decoupled and respectively set on different physical devices, and connected by wired or wireless means to realize the respective functions of the processing unit and the storage unit, so as to support the system chip to realize the various functions in the above embodiments. Alternatively, the processing unit and the memory can also be coupled on the same device.

[0108] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0109] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0110] In the embodiments provided in the present application, it should be understood that the disclosed devices / equipment and methods can be implemented in other ways. For example, the device / equipment embodiments described above are merely schematic, for example, the division of the modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0111] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0112] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0113] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the steps of the above-mentioned various method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium can at least include: any entity or device that can carry the computer program code to the electronic archive generation device / terminal device, recording medium, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electric carrier signal, telecommunication signal and software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disk. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electric carrier signals and telecommunication signals.

[0114] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A heterogeneous multi-core system, characterized in that: include: A server and a heterogeneous multi-core SOC, wherein the heterogeneous multi-core SOC includes multiple cores; A virtual network is provided between the server and the plurality of cores; A client of a first application is arranged on the server, and a server of the first application is arranged on the first core. The client of the first application communicates with the server of the first application through the virtual network. The first core is any one of the multiple cores. The first application includes a network tool or a chip management tool.

2. The system according to claim 1, characterized in that The network tool includes: at least one of an SCP tool, an FTP tool and an SSH tool.

3. The system according to claim 1, characterized in that A virtual network device driver is installed on the server and the first core respectively, and the virtual network includes a connection between the virtual network device driver on the server and the virtual network device driver on the first core.

4. The system according to claim 1, characterized in that The server and the first kernel perform data exchange via a first shared memory area and a MailBox module, wherein the first shared memory area is used to store exchange data between the server and the first kernel.

5. The system according to claim 4, characterized in that The heterogeneous multi-core SOC is connected to the server via PCIe, and the first shared memory area includes: a mapped memory obtained by mapping part of the memory of the first core to the memory space of the server via PCIe.

6. The system according to any one of claims 1 to 5, characterized in that: The first kernel and the second kernel are respectively installed with virtual network device drivers, and the virtual network includes: a connection between the virtual network device driver on the first kernel and the virtual network device driver on the second kernel, and the second kernel is any kernel among the multiple kernels except the first kernel.

7. The system according to claim 6, characterized in that The first kernel and the second kernel perform data exchange via a second shared memory area and a MailBox module, wherein the second shared memory area is used to store exchange data between the first kernel and the second kernel.

8. A communication method, characterized in that: Applied to the system according to any one of claims 1 to 7, the method comprises: The server obtains request information generated by a client of the first application program; The server sends the request information to the first kernel through the virtual network; The first kernel obtains response data generated by the server of the first application in response to the request information; The first kernel sends the response data to the server through the virtual network.

9. The method according to claim 8, characterized in that The server sends the request information to the first kernel through the virtual network, including: The server writes the request information into the first shared memory area, and sends an interrupt to the first kernel through the MailBox module, so that the first kernel receives the interrupt and reads the request information from the first shared memory area.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps performed by the server or any one of the cores in the method according to claim 8 or 9 are implemented.

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