Device debugging method, device, device, device system and medium

Abstract

The present invention discloses a device debugging method, apparatus, equipment, device system and medium, which relates to the field of communication technology, including: when the target device is powered on, obtaining the network card information of the target device, and identifying the target network card that supports the shared network port from the network cards of the target device based on the network card information; if the target network card is identified for the first time, controlling the preset control device in the target device to switch to the target interface channel to establish a communication link between the management controller and the target network card; the target interface channel is the information transmission channel of the network controller sideband interface; the data transceiver signal appearing in the target interface channel is connected to the preset control device, so that the preset control device performs spectrum analysis on the data transceiver signal, and debugs the clock phase offset that meets the preset functional requirements based on the spectrum analysis results. By debugging the clock phase offset that meets the preset requirements through this solution, the clock signal and the data signal timing are accurately matched.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a device debugging method, apparatus, device, device system and medium. Background Art

[0002] The Network Controller Sideband Interface (NCSI) protocol is primarily used to support out-of-band management of servers. It defines a sideband interface that enables efficient communication between a server's management controller (such as a baseboard management controller) and a network controller (network interface card). This communication mechanism is independent of the server's main operating system, allowing network devices to be managed and monitored even when the operating system is unavailable. Therefore, NCSI is crucial for server management and monitoring. However, in related technologies, communication between servers and network interface cards using NCSI requires an external clock input, and a phase offset between the clock and data signals is required to ensure data sampling between the communicating chips. This external clock input requires circuit design to determine the link lengths from the CLK buffer to the master and slave chips, calculate the phase offset according to the NCSI protocol, and then burn it offline into the EEPROM (Electrically Erasable Programmable Read-Only Memory).

[0003] It can be seen that how to achieve precise timing matching between clock signals and data signals is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of the embodiments of the present invention is to provide a device debugging method, apparatus, device, device system and medium, which can solve the problem of inaccurate timing matching between clock signals and data signals.

[0005] In a first aspect, the present invention discloses a device debugging method, which is applied to a management controller, comprising:

[0006] When the target device is powered on, the network card information of the target device is obtained, and based on the network card information, a target network card that supports a shared network port is identified from each network card of the target device;

[0007] If the target network card is identified for the first time, the preset control device in the target device is controlled to switch to the target interface channel to establish a communication link between the management controller and the target network card; the target interface channel is an information transmission channel of the network controller sideband interface;

[0008] The data transceiver signal appearing in the target interface channel is connected to a preset control device so that the preset control device performs spectrum analysis on the data transceiver signal and debugs a clock phase offset that meets the preset functional requirements based on the spectrum analysis result.

[0009] Optionally, after the target device is powered on, obtain the target device's network card information, including:

[0010] When the target device is powered on, the presence information of each expansion card on the target device identified and reported by the preset control component is obtained;

[0011] The network card information of the target device is read from the expansion card through a preset communication bus according to the in-position information.

[0012] Optionally, identifying a target network card that supports a shared network port from each network card of the target device based on the network card information includes:

[0013] Parse and determine whether there is a support flag for supporting shared network ports in the network card information;

[0014] If it exists, the corresponding network card is determined to be the target network card that supports the shared network port.

[0015] Optionally, after determining that the corresponding network card is a target network card that supports a shared network port, the method further includes:

[0016] Match the unique identity of the target network card with the unique identity of each historical network card;

[0017] If the matching result is that the unique identification identifier of the historical network card is consistent with the unique identification identifier of the target network card, it is determined that the identification result of the target network card is not the first identification result.

[0018] Optionally, after determining that the identification result of the target network card is not the first identification result, the method further includes:

[0019] Reading a target clock phase offset corresponding to the unique identification of the target network card from a preset memory;

[0020] Sending the target clock phase offset to a preset control device so that the preset control device sets the state of the initial communication link between the target network card and the management controller to a ready state using a communication strategy constructed based on the target clock phase offset;

[0021] Performing a stability verification process on the initial communication link to obtain corresponding verification results;

[0022] Adjusting a clock phase offset of an initial communication link based on the verification result;

[0023] Alternatively, the initial communication link is determined as the target communication link based on the verification result.

[0024] Optionally, the communication strategy constructed based on the target clock phase offset is used to set the state of the initial communication link between the target network card and the management controller to a ready state, including:

[0025] By presetting the clock management circuit of the control device and adjusting the phase offset of the clock signal between the target network card and the management controller according to the target clock phase offset, a corresponding communication strategy is obtained, and the state of the initial communication link between the target network card and the management controller is set to a ready state.

[0026] Optionally, a stability verification process for the initial communication link is performed to obtain corresponding verification results, including:

[0027] determining whether the number of data packets sent and the number of data packets received via the initial communication link within a preset time range are the same;

[0028] If they are not the same, a readjustment instruction is sent to the preset control device so that the preset control device can re-adjust the new clock phase offset according to the readjustment instruction and the communication timing requirements of the communication link protocol;

[0029] Jump execution to the step of sending the target clock phase offset to the preset control device until the stability verification is passed, and output the current clock phase offset as the clock phase offset that meets the preset functional requirements.

[0030] Optionally, the data transceiver signal appearing in the target interface channel is connected to a preset control device so that the preset control device performs spectrum analysis on the data transceiver signal and debugs a clock phase offset that meets preset functional requirements based on the spectrum analysis result, including:

[0031] Added a spectrum analysis component for spectrum analysis in the preset control device;

[0032] Connecting the data transmission signal and the data reception signal transmitted through the target interface channel to the spectrum analysis component, so that the spectrum analysis component can determine the data transmission time point and the data reception time point respectively from the data transmission signal and the data reception signal;

[0033] The spectrum analyzer calculates the data transmission delay based on the data transmission time and data reception time, and then uses the data transmission delay and the internal reference clock of the target device to determine the clock phase offset.

[0034] By using a preset control device and directly increasing and / or decreasing the phase offset of the clock signal between the target network card and the management controller according to the clock phase offset, a clock phase offset that meets the preset functional requirements is obtained, and the clock phase offset that meets the preset functional requirements is reported to the management controller through a preset communication bus.

[0035] In a second aspect, the present invention discloses a device debugging apparatus, which is applied to a management controller and includes:

[0036] An information acquisition module is used to obtain the network card information of the target device after the target device is powered on, and identify the target network card that supports the shared network port from the network cards of the target device based on the network card information;

[0037] a channel switching module, configured to control a preset control device in the target device to switch to a target interface channel if the target network card is identified for the first time, so as to establish a communication link between the management controller and the target network card; the target interface channel is an information transmission channel of the network controller sideband interface;

[0038] The offset adjustment module is used to connect the data transceiver signal appearing in the target interface channel to the preset control device so that the preset control device can perform spectrum analysis on the data transceiver signal and debug the clock phase offset that meets the preset functional requirements based on the spectrum analysis results.

[0039] In a third aspect, the present invention discloses an electronic device, comprising:

[0040] Memory for storing computer programs;

[0041] The processor is used to execute the computer program to implement the steps of the device debugging method disclosed above.

[0042] In a fourth aspect, the present invention discloses a device system, including a management controller, a network card, a preset control device, and a channel switching device; the channel switching device is used to switch the preset control device to an information transmission channel of a network controller sideband interface;

[0043] Furthermore, the management controller implements the steps of the device debugging method disclosed above by executing the computer program.

[0044] In a fifth aspect, the present invention discloses a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the device debugging method disclosed above are implemented.

[0045] It can be seen that the present invention discloses a device debugging method, which is applied to a management controller, including: when the target device is powered on, obtaining the network card information of the target device, and identifying the target network card that supports the shared network port from the network cards of the target device based on the network card information; if the target network card is identified for the first time, controlling the preset control device in the target device to switch to the target interface channel to establish a communication link between the management controller and the target network card; the target interface channel is the information transmission channel of the network controller sideband interface; connecting the data transceiver signal appearing in the target interface channel to the preset control device, so that the preset control device performs spectrum analysis on the data transceiver signal, and debugging the clock phase offset that meets the preset functional requirements based on the spectrum analysis result.

[0046] It can be seen from the above technical solution that by quickly determining whether the network card is being identified for the first time, different operation procedures are adopted. For the first time identification, it is automatically switched to the appropriate target interface channel instead of adopting a fixed single link management method; after identifying the target network card that is inserted for the first time, the management controller controls the preset control device in the target device to switch to the corresponding target interface channel, establishes a communication link between the target network card and the management controller, and connects the data transmission and reception signal generated by the communication link to the preset control device for spectrum analysis, thereby obtaining the adjusted clock signal offset, thereby meeting the communication timing requirements between the management controller and the target network card, achieving precise matching of clock signals and data signals, ensuring that data can be accurately sampled at the appropriate clock edge, and reducing communication errors caused by timing mismatch; moreover, the preset control device can analyze the adjusted clock signal offset and report it to the management controller. The management controller can record this offset information and directly call the corresponding clock signal offset when the same network card is identified subsequently, avoiding repeated complex debugging processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0048] Figure 1 A flow chart of a device debugging method provided by an embodiment of the present invention;

[0049] Figure 2 A flow chart of a specific device debugging method provided by an embodiment of the present invention;

[0050] Figure 3 A circuit design diagram of a CPLD replacing a CLK Buffer provided by an embodiment of the present invention;

[0051] Figure 4 A schematic diagram of the structure of a device debugging apparatus provided in an embodiment of the present invention;

[0052] Figure 5 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention;

[0053] Figure 6 A schematic diagram of the structure of a device system provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0054] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0055] The terms "including" and "having," as used in the present description and accompanying drawings, and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements and may include steps or elements that are not listed.

[0056] In order to enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0057] The NCSI protocol is primarily used to support out-of-band management of servers. It defines a sideband interface that enables efficient communication between a server's management controller (such as a baseboard management controller) and a network controller (NIC). This communication mechanism is independent of the server's main operating system, allowing network devices to be managed and monitored even when the operating system is unavailable. Therefore, NCSI is crucial for server management and monitoring during operation. However, in related technologies, communication between servers and NICs using NCSI requires an external clock input, and a phase offset between the clock and data signals is required to ensure data sampling between the communicating chips. This external clock input requires careful design during board routing, determining the link length from the CLK buffer to the master and slave chips, calculating the phase offset according to the NCSI protocol, and then burning it offline into EEPROM.

[0058] To this end, the present invention provides a device debugging solution that can achieve precise timing matching of clock signals and data signals.

[0059] Reference Figure 1As shown, the present invention provides a device debugging method, which is applied to a management controller, comprising:

[0060] Step S11: After the target device is powered on, the network card information of the target device is obtained, and based on the network card information, a target network card that supports a shared network port is identified from among the network cards of the target device.

[0061] In this embodiment, after the target device is powered on, the presence information of each expansion card on the target device identified and reported by the preset control device is obtained; it can be understood that the target device is a server, the management controller is specifically a baseboard management controller BMC (Board Management Controller), and the preset control device is a CPLD (Complex Programmable Logic Device). Therefore, after the server is powered on, the BMC issues instructions to control the CPLD, and the CPLD further identifies and reports the presence information of each expansion card on the server, that is, the CPLD identifies the #PRSNT signal of each expansion card to determine whether these expansion cards have been correctly installed in the slot of the server, that is, whether they are "in place", where the expansion cards may include but are not limited to: OCP (Open Compute Project) standard cards and PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) standard cards.

[0062] In this embodiment, the target device's network card information is read from the expansion card based on the presence information and via a preset communication bus. It is understood that after the CPLD determines the presence of OCP and PCIE standard cards, it sends this presence information to the BMC. This allows the BMC to know which expansion cards are installed in the server and to further configure and manage them, such as loading the corresponding drivers or allocating system resources. The BMC then reads the network card information from the expansion card via the preset I2C (Inter-Integrated Circuit) communication bus and the expansion card's presence information. Specifically, the BMC sends specific query commands to each standard card in place, and these commands follow a specific communication protocol. For example, for industry-standard OCP and PCIE standard cards, they both have specified device identification registers or information storage areas. The query commands sent by the BMC can read the information in these areas to determine the card's type, function, and other details, namely the network card information.

[0063] In this embodiment, the network card information is parsed and determined to determine whether a support flag indicating shared network port support is present. If present, the corresponding network card is determined to be the target network card supporting shared network port support. It is understood that after the BMC reads the network card information, it parses the information to determine whether it contains network card functionality. This involves interpreting the device function code or specific configuration registers. Specifically, the network card information format returned by the expansion card is typically organized according to a certain standard or a format customized by the expansion card manufacturer. Within the network card information, specific bits or fields are used to identify whether the device supports the shared port function. For example, there may be a specific byte in which the combination of certain bits (such as bits 3-5) indicates shared port support. If the binary value of these bits is "010," it indicates shared port support, while "000" indicates support. The BMC determines whether the expansion card supports shared port support by identifying these specific bit combinations.

[0064] To accurately determine whether a NIC is the target, the BMC also consults the device's technical documentation and relevant industry protocol standards. Different NIC manufacturers use different identification methods, but generally, their technical documentation explains how to use the returned device information to determine whether various features are supported. For example, for expansion cards that comply with a specific industry standard (such as a specific version of the PCIE NIC standard), the documentation will clearly define the location and format of the shared port support identifier. By referring to these documents and standards, the BMC accurately determines whether the NIC supports shared ports from the information returned by the device, and thus determines the target NIC.

[0065] In this embodiment, after determining that the corresponding network card is the target network card, the unique identity identifier of the target network card is matched with the unique identity identifiers of each historical network card; if the matching result is a matching result in which the unique identity identifier of the historical network card is consistent with the unique identity identifier of the target network card, then the identification result of the target network card is determined to be a non-first identification result. It can be understood that there is an area inside the BMC to store historical network card information. When the network card is identified as supporting the shared port function through the I2C bus, the BMC will compare the unique identity identifier of the network card (such as device ID, MAC address, specific hardware version number, etc.) with the stored historical network card information. By comparing this information one by one, it can be determined whether the network card has been identified before. For example, if the device ID of the newly identified network card is exactly the same as the device ID of a certain network card that has been recorded, then it can be preliminarily determined that this network card is not being identified for the first time.

[0066] In this embodiment, if it is not the first time that the network card is identified, the target clock phase offset corresponding to the unique identity of the target network card is read from the preset memory; the target clock phase offset is sent to the preset control device so that the preset control device uses the communication strategy constructed based on the target clock phase offset to set the state of the initial communication link between the target network card and the management controller to the ready state; it can be understood that after calling the corresponding CLK phase offset strategy, that is, the target clock phase offset, from the preset memory, the BMC will send this offset to the CPLD. After receiving the offset, the CPLD constructs a corresponding communication strategy to set the state of the initial communication link between the target network card and the management controller to the ready state. Among them, the specific process of constructing the communication strategy is as follows:

[0067] By presetting the control device's clock management circuit and adjusting the phase offset of the clock signal between the target network card and the management controller based on the target clock phase offset, a corresponding communication strategy is established, and the initial communication link between the target network card and the management controller is set to the ready state. It can be understood that the CPLD utilizes its internal clock management circuitry (such as a clock buffer or phase-locked loop) to adjust the clock phase offset between the master and slave chips (BMC and target network card) to establish the communication strategy. In this way, the clock synchronization of the communication link is set to the valid state of the historical record, providing suitable clock conditions for subsequent data transmission.

[0068] In this embodiment, a stability verification process is performed on the initial communication link to obtain a corresponding verification result; the clock phase offset of the initial communication link is adjusted based on the verification result; or, based on the verification result, the initial communication link is determined to be the target communication link. Specifically, a determination is made as to whether the number of data packets sent and received via the initial communication link within a preset time range is the same; if not, a readjustment instruction is sent to a preset control device so that the preset control device re-debugs a new clock phase offset according to the readjustment instruction and in accordance with the communication timing requirements of the communication link protocol; and the process jumps to executing the step of sending the target clock phase offset to the preset control device until the stability verification is passed and the current clock phase offset is output as the clock phase offset that meets the preset functional requirements. It is understandable that the stability verification of the initial communication link in the ready state is carried out. The stability verification is the network packet loss detection and functional stress detection to evaluate whether the communication link can work stably and efficiently when the CLK offset recorded before the application is applied. Specifically, when the shared network port is connected, the specific data format message is included in the data packet. When the shared port is detected to be connected, the packet loss mechanism detection is continuously performed. It is set that no packet loss for 1 hour is considered to have passed the network function stress test. If a packet loss problem is detected during the stress test, the BMC sends an instruction to the CPLD to make a secondary adjustment within the NCSI protocol timing range, and then perform the stress test again until the network function stress test passes and is considered to be normal. The CLK offset at this time is written into the preset memory, avoiding the need for multiple complex network function tests as in related technologies.

[0069] Step S12: If the target network card is identified for the first time, control the preset control device in the target device to switch to the target interface channel to establish a communication link between the management controller and the target network card; the target interface channel is the information transmission channel of the network controller sideband interface.

[0070] In this embodiment, the unique identifier of the target network card is matched with the unique identifiers of each historical network card. If the match result shows that the unique identifier of the historical network card is not consistent with the unique identifier of the target network card, the identification result of the target network card is determined to be the first identification result. Then, the BMC issues an instruction to the CPLD to switch the NCSI path, so that the BMC and the target network card establish a communication link, and the shared port path is connected. The NCSI path is the target interface channel.

[0071] Step S13: connecting the data transceiver signal appearing in the target interface channel to a preset control device so that the preset control device performs spectrum analysis on the data transceiver signal and debugs a clock phase offset that meets preset functional requirements based on the spectrum analysis result.

[0072] In this embodiment, a spectrum analysis component for spectrum analysis is added to the preset control device. Data transmission signals and data reception signals transmitted through the target interface channel are connected to the spectrum analysis component, allowing the spectrum analysis component to determine the data transmission time point and data reception time point, respectively, from the data transmission signal and data reception signal. The spectrum analysis component calculates the data transmission delay based on the data transmission time point and the data reception time point, and then determines the clock phase offset using the data transmission delay and the internal reference clock of the target device. The preset control device directly increases and / or decreases the phase offset of the clock signal between the target network card and the management controller based on the clock phase offset to obtain a clock phase offset that meets the preset functional requirements, and the clock phase offset that meets the preset functional requirements is reported to the management controller via a preset communication bus. It is understood that the CPLD directly uses the TX_EN (Transmit Enable, data transmission signal) and RX_CRSDV (Receive Carrier Sense and Data Valid, data reception signal) connected to the target interface channel, and the signal spectrum analysis component added to the CPLD determines the data transmission time point and data reception time point, respectively, from the data transmission signal and the data reception signal. The difference between the two time points reflects the delay in the data transmission process.

[0073] It's important to note that since data transmission relies on clock signals for synchronization, comparing this delay with the expected clock signal transmission time can be used to determine the clock signal phase offset. For example, in ideal NCSI communication, data should be sampled on a specific clock edge based on the clock signal and protocol-specified data transmission timing (e.g., setup time ≥ 4ns for data rise before clock rise, and hold time ≤ 2ns for clock rise before data fall, with a clock cycle of 20ns). However, if the actual data transmission time determined by TX_EN and RX_CRSDV does not meet this ideal, the time difference from the ideal is the clock signal offset relative to the normal timing. This indicates the degree of clock signal asynchrony between the master and slave chips, providing a key quantitative basis for subsequent CPLD clock phase adjustments.

[0074] Furthermore, the data transmission delay and the server's internal reference clock can be used to quantify the clock phase offset. First, the internal reference clock provides a precise time base for data transmission delay. Because the internal reference clock has a stable period and frequency, by comparing the data transmission delay with the internal reference clock period, the delay in data transmission relative to the clock period can be determined.

[0075] For example, assume the internal reference clock period is T and the data transmission delay is Δt. If Δt is greater than a fraction of the clock period T (for example, within the setup time range specified by the NCSI protocol, where the data rise time precedes the clock rise time), then this excess time is a manifestation of clock offset. In this way, the data transmission delay is converted into a quantified value of the clock offset relative to the internal reference clock, providing a specific numerical basis for subsequent adjustment of the clock signal phase.

[0076] In addition to quantifying the clock phase offset, the direction and magnitude of the clock signal phase adjustment can also be determined. If data transmission delay causes data to arrive at the receiver earlier than the ideal clock edge (as required by the NCSI protocol), this indicates a relative lag in the clock signal. The CPLD internally increases the clock phase offset, performing a positive phase adjustment. The adjustment magnitude is determined by comparing the data transmission delay with the internal reference clock period. Conversely, if data transmission delay causes data to arrive at the receiver later than the ideal clock edge, the clock signal is relatively advanced, requiring a reduction in the clock phase offset, performing a negative phase adjustment. This analysis, based on data transmission delay and the internal reference clock, accurately guides the CPLD in phase-adjusting the clock signals between the master and slave chips to meet the timing requirements of the NCSI protocol. This allows the CPLD to adjust the appropriate CLK phase offset, which is then applied directly to CLK0 / CLK1 / CLK2.

[0077] Furthermore, for clock phase offset calculation, in addition to the aforementioned spectrum analysis component, different operating conditions can be taken into account. Machine learning or artificial intelligence-based algorithms can be used to predict and adjust the CLK phase offset. By training on large amounts of clock data, these algorithms may be able to more accurately predict the optimal CLK phase offset under different operating conditions, thereby improving system stability and performance. Specifically, a large amount of clock data can be collected from existing systems. This data should include CLK signal parameters under different operating conditions, such as clock frequency, phase, operating temperature, and load conditions. This data will serve as training data to help the algorithm learn the relationship between CLK phase offset and various operating conditions. Sensors and data acquisition devices can be used to obtain these parameters to ensure data accuracy and integrity. For example, a high-precision frequency meter can be used to measure clock frequency, and a temperature sensor can be used to measure operating temperature. Feature extraction is then performed on the collected data. Relevant features for CLK phase offset calculation may include: the rate of change of clock frequency, which reflects the fluctuation of clock frequency over different time periods; and the correlation between temperature and clock frequency, which extracts this correlation as a feature due to the influence of temperature on clock frequency. The relationship between load variation and clock phase: Different loads may cause clock phase shifts, and load variations are used as features. The data is then normalized to ensure that data with different features are on the same scale and mapped to the range of 0 to 1 to facilitate subsequent algorithm processing. Considering the interactive effects of multiple factors (such as temperature, load, and frequency variations) on clock phase offset, deep learning networks can learn more complex mapping relationships. A neural network model (such as a multilayer perceptron or deep learning network) is selected as the initial model. The preprocessed data is divided into a training set and a validation set. The training set is used to train the model, and the validation set is used to evaluate model performance. The selected model is trained on the training set, and the model parameters are adjusted by minimizing a loss function (such as mean squared error (MSE). The backpropagation algorithm is used to update the network weights and biases. During training, the model performance on the validation set is continuously monitored to prevent overfitting. If the model error on the validation set begins to increase, it may indicate overfitting and requires measures such as adding regularization terms or adjusting model complexity. Once the model performance reaches a satisfactory level, it is deployed in the actual system. During system operation, real-time clock data is collected as input to the model, which then outputs a predicted CLK phase offset. The system adjusts the CLK phase offset based on the model's predictions, achieving precise clock control and improving system stability and performance.

[0078] In this embodiment, after the clock phase offset that meets the preset functional requirements is reported to the BMC via I2C, the BMC will send this offset to the CPLD. After receiving the offset, the CPLD constructs a corresponding communication strategy to set the state of the initial communication link between the target network card and the management controller to the ready state, and then jumps to the aforementioned publicly disclosed stability verification process.

[0079] Reference Figure 2 As shown, the present invention discloses a specific device debugging method process, the specific steps are as follows:

[0080] 1. When the server is powered on, the CPLD recognizes that the OCP and PCIE card #PRSNT are in place and reports this information to the BMC.

[0081] 2. The BMC obtains network card information through the I2C bus, identifies which network card supports the shared port function, and determines whether this is the first time the network card is used:

[0082] ① If it is not the first recognition, the corresponding CLK phase offset strategy is directly called from the EEPROM and sent to the CPLD;

[0083] ②If it is the first time recognition, proceed to step 3.

[0084] 3. The BMC instructs the CPLD to switch the NCSI path, so that the BMC main control chip and the network card slave device establish a link, and the shared port path is connected.

[0085] 4. CPLD performs logic according to the instructions issued by BMC:

[0086] ① If there is only the instruction for first-time identification of the network card, the CPLD directly uses the TX_EN and RX_CRSDV of the master and slave chips to debug the appropriate CLK phase offset through the signal spectrum analysis module and the timing requirements of the clock and data in the NCSI protocol, and directly acts on CLK0 / CLK1 / CLK2 internally;

[0087] ② If it is identified that the BMC issues a re-debugging instruction due to packet loss, a new CLK phase offset is re-debugged according to the disable logic issued by the BMC.

[0088] 5. The CPLD reports the CLK phase offset to the BMC, which then writes it into the EEPROM to record the binding relationship between the network card and the BMC.

[0089] 6. The BMC then checks the packet loss mechanism and, through network function stress testing at a specific time, determines whether the current CLK phase offset meets functional requirements.

[0090] 7. If the requirements are not met, a re-debugging instruction is issued and the process returns to step 4-② to continue.

[0091] If the requirements are met, confirm that the binding relationship in step 5 is valid and the logic ends.

[0092] In this way, by replacing the CLK buffer with a CPLD and expanding the ISO Switch (Isolation Switch) design by more than one point, the CPLD has a built-in signal spectrum analysis module and logic, and the BMC designs the logic of the network card chip identification and memory mechanism, network packet loss detection, and functional pressure mechanism. This can effectively improve the R&D investment caused by manual calculation, return board testing, and repeated adjustments after the shared port link design, and save single board costs.

[0093] like Figure 3 Taking a dual-shared port server design as an example, the CLK buffer, EEPROM, and 50M crystal oscillator were removed and replaced with a CPLD and a 25M crystal oscillator input. A signal spectrum analysis module was added to the CPLD. Referring to the NCSI testing methodology and principles (actual signal data transmission is through NCSI_Data, with TX_EN and RX_CRSDV serving as the transmitter and receiver signals indicating when data is being sent and received, respectively), the NCSI data transmission signals, TX_EN and RX_CRSDV, were connected to the CPLD without affecting the existing communication link. These signals served as inputs for signal spectrum analysis and phase offset adjustment. The CPLD, using the spectrum analysis module, determined the CLK offset between the master and slave chips, directly increasing or decreasing the phase offset internally to achieve adjustment. The adjusted offset was then reported to the BMC via the I2C bus.

[0094] The BMC incorporates two mechanisms into its logic. The first is the network card chip identification and memory mechanism. When the server is powered on for the first time with a network card, after the BMC identifies the specific chip of the network card through the I2C link, the CLK clock offset adjusted by the CPLD is written into the EEPROM as a fixed pairing relationship. The next time such a network card is identified, the corresponding offset strategy can be directly called. The second is the shared port packet loss mechanism detection; a specific data format message is included in the data packet. When the BMC detects that the shared port is connected, it continuously performs the packet loss mechanism detection. If there is no packet loss for 1 hour, it is considered that the network function stress test has passed. If a packet loss problem is detected during the stress test, the BMC sends a command to the CPLD to make a second adjustment within the NCSI protocol timing range, and then perform the stress test again; until the network function stress test passes, it is considered to be functioning normally, and the CLK clock offset at this time is written into the EEPROM.

[0095] It can be seen that the present invention discloses a device debugging method, which is applied to a management controller, including: when the target device is powered on, obtaining the network card information of the target device, and identifying the target network card that supports the shared network port from the network cards of the target device based on the network card information; if the target network card is identified for the first time, controlling the preset control device in the target device to switch to the target interface channel to establish a communication link between the management controller and the target network card; the target interface channel is the information transmission channel of the network controller sideband interface; connecting the data transceiver signal appearing in the target interface channel to the preset control device, so that the preset control device performs spectrum analysis on the data transceiver signal, and debugging the clock phase offset that meets the preset functional requirements based on the spectrum analysis result.

[0096] It can be seen from the above technical solution that by quickly determining whether the network card is being identified for the first time, different operation procedures are adopted. For the first time identification, it is automatically switched to the appropriate target interface channel instead of adopting a fixed single link management method; after identifying the target network card that is inserted for the first time, the management controller controls the preset control device in the target device to switch to the corresponding target interface channel, establishes a communication link between the target network card and the management controller, and connects the data transmission and reception signal generated by the communication link to the preset control device for spectrum analysis, thereby obtaining the adjusted clock signal offset, thereby meeting the communication timing requirements between the management controller and the target network card, achieving precise matching of clock signals and data signals, ensuring that data can be accurately sampled at the appropriate clock edge, and reducing communication errors caused by timing mismatch; moreover, the preset control device can analyze the adjusted clock signal offset and report it to the management controller. The management controller can record this offset information and directly call the corresponding clock signal offset when the same network card is identified subsequently, avoiding repeated complex debugging processes.

[0097] Reference Figure 4 As shown, the present invention also discloses a device debugging apparatus, which is applied to a management controller and includes:

[0098] The information acquisition module 11 is used to obtain the network card information of the target device after the target device is powered on, and identify the target network card that supports the shared network port from the network cards of the target device based on the network card information;

[0099] The channel switching module 12 is configured to control a preset control device in the target device to switch to a target interface channel if the target network card is identified for the first time, so as to establish a communication link between the management controller and the target network card; the target interface channel is an information transmission channel of the network controller sideband interface;

[0100] The offset adjustment module 13 is used to connect the data transceiver signal appearing in the target interface channel to the preset control device so that the preset control device can perform spectrum analysis on the data transceiver signal and debug the clock phase offset that meets the preset functional requirements based on the spectrum analysis results.

[0101] It can be seen that by quickly determining whether the network card is being identified for the first time, different operation procedures are adopted. For the first time identification, it is automatically switched to the appropriate target interface channel instead of adopting a fixed single link management method; after identifying the target network card that is inserted for the first time, the management controller controls the preset control device in the target device to switch to the corresponding target interface channel, establishes a communication link between the target network card and the management controller, and connects the data transmission and reception signal generated by the communication link to the preset control device for spectrum analysis, thereby obtaining the adjusted clock signal offset, thereby meeting the communication timing requirements between the management controller and the target network card, achieving precise matching of clock signals and data signals, ensuring that data can be accurately sampled at the appropriate clock edge, and reducing communication errors caused by timing mismatch; moreover, the preset control device can analyze the adjusted clock signal offset and report it to the management controller. The management controller can record the offset information and directly call the corresponding clock signal offset when the same network card is identified subsequently, avoiding repeated complex debugging processes.

[0102] Furthermore, the embodiment of the present application also discloses an electronic device, Figure 5 is a structural diagram of an electronic device according to an exemplary embodiment. Figure 5 The content herein should not be construed as limiting the scope of use of this application. The electronic device may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps of the device debugging method disclosed in any of the aforementioned embodiments. Furthermore, the electronic device in this embodiment may specifically be an electronic computer.

[0103] In this embodiment, the power supply 23 is used to provide operating voltage for various hardware devices on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and external devices. The communication protocol it follows is any communication protocol that can be applied to the technical solution of this application and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world. Its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0104] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or CD, etc. The resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0105] The operating system 221 is used to manage and control the hardware devices on the electronic device, as well as the computer program 222, which can be Windows Server, NetWare, Unix, Linux, etc. In addition to including a computer program capable of implementing the device debugging method performed by the electronic device disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program capable of implementing other specific tasks.

[0106] Reference Figure 6 As shown, the present invention also provides a device system, including a management controller, a network card, a preset control device and a channel switching device; the channel switching device is used to switch the preset control device to the information transmission channel of the network controller sideband interface; and the management controller implements the steps of the device debugging method disclosed above by executing a computer program. Specifically, a new ISO Switch chip, that is, a channel switching device, and CPLD controls the OCP_RISER_EN used to switch the path, which can expand the NCSI link from one to multiple, and enable the BMC to establish interaction with multiple links by itself. The in-place signals of the OCP network card and the PCIE standard card are connected to the CPLD through GPIO (General-Purpose Input / Output Ports) and reported to the BMC. The BMC can automatically identify the logic and switch the corresponding shared port link by itself.

[0107] Furthermore, this application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the device debugging method disclosed above is implemented. For the specific steps of this method, please refer to the corresponding content disclosed in the above embodiments and will not be repeated here.

[0108] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. Reference can be made to the descriptions of the identical or similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the methods.

[0109] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0110] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0111] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0112] The above is a detailed introduction to the technical solution provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, according to the ideas of the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A device debugging method, characterized in that: Applicable to management controllers, including: When the target device is powered on, network card information of the target device is obtained, and a target network card that supports a shared network port is identified from each network card of the target device based on the network card information; If the target network card is identified for the first time, controlling a preset control device in the target device to switch to a target interface channel to establish a communication link between the management controller and the target network card; the target interface channel is an information transmission channel of a network controller sideband interface; Connecting the data transceiver signal appearing in the target interface channel to the preset control device, so that the preset control device performs spectrum analysis on the data transceiver signal and debugs a clock phase offset that meets preset functional requirements based on the spectrum analysis result; Connecting the data transceiver signal appearing in the target interface channel to the preset control device so that the preset control device performs spectrum analysis on the data transceiver signal and debugs a clock phase offset that meets preset functional requirements based on the spectrum analysis result, including: Adding a spectrum analysis component for spectrum analysis to the preset control device; Connecting the data transmission signal and the data reception signal transmitted through the target interface channel to the spectrum analysis component, so that the spectrum analysis component can determine the data transmission time point and the data reception time point from the data transmission signal and the data reception signal respectively; calculating a data transmission delay based on the data sending time point and the data receiving time point by the spectrum analysis component, and then determining a clock phase offset by using the data transmission delay and an internal reference clock of the target device; The phase offset of the clock signal between the target network card and the management controller is directly increased and / or decreased through the preset control device and according to the clock phase offset to obtain a clock phase offset that meets the preset functional requirements, and the clock phase offset that meets the preset functional requirements is reported to the management controller through a preset communication bus.

2. The device debugging method according to claim 1, characterized in that: When the target device is powered on, obtaining the network card information of the target device includes: When the target device is powered on, obtaining the presence information of each expansion card on the target device identified and reported by the preset control component; The network card information of the target device is read from the expansion card through a preset communication bus according to the presence information.

3. The device debugging method according to claim 1, characterized in that: The identifying a target network card that supports a shared network port from each network card of the target device based on the network card information includes: Parse and determine whether there is a support identifier for supporting shared network ports in the network card information; If it exists, the corresponding network card is determined to be the target network card that supports the shared network port.

4. The device debugging method according to claim 3, characterized in that: After determining that the corresponding network card is a target network card that supports a shared network port, the method further includes: Matching the unique identity identifier of the target network card with the unique identity identifiers of each historical network card; If the matching result is a matching result in which the unique identification identifier of the historical network card is consistent with the unique identification identifier of the target network card, it is determined that the identification result of the target network card is not the first identification result.

5. The device debugging method according to claim 4, characterized in that: After determining that the identification result of the target network card is not the first identification result, the method further includes: Reading a target clock phase offset corresponding to the unique identification of the target network card from a preset memory; Sending the target clock phase offset to a preset control device so that the preset control device sets the state of the initial communication link between the target network card and the management controller to a ready state using a communication strategy constructed based on the target clock phase offset; Performing a stability verification process on the initial communication link to obtain a corresponding verification result; Adjusting a clock phase offset of the initial communication link based on the verification result; Alternatively, the initial communication link is determined to be a target communication link based on the verification result.

6. The device debugging method according to claim 5, characterized in that: The communication strategy constructed based on the target clock phase offset sets the state of the initial communication link between the target network card and the management controller to a ready state, including: The phase offset of the clock signal between the target network card and the management controller is adjusted according to the target clock phase offset through the clock management circuit of the preset control device to obtain a corresponding communication strategy, and the state of the initial communication link between the target network card and the management controller is set to a ready state.

7. The device debugging method according to claim 5, characterized in that: The performing of the stability verification process of the initial communication link to obtain a corresponding verification result includes: Determining whether the number of data packets sent and the number of data packets received through the initial communication link within a preset time range are the same; If they are not the same, a readjustment instruction is sent to the preset control device, so that the preset control device re-adjusts a new clock phase offset according to the readjustment instruction and the communication timing requirements of the communication link protocol; Jump to the step of sending the target clock phase offset to the preset control device until the stability verification is passed, and output the current clock phase offset as the clock phase offset that meets the preset functional requirements.

8. A device debugging apparatus, characterized in that: Applicable to management controllers, including: An information acquisition module is used to acquire network card information of the target device after the target device is powered on, and identify a target network card that supports a shared network port from each network card of the target device based on the network card information; a channel switching module, configured to control a preset control device in the target device to switch to a target interface channel to establish a communication link between the management controller and the target network card if the target network card is identified for the first time; the target interface channel is an information transmission channel of a network controller sideband interface; an offset adjustment module, configured to connect the data transceiver signal appearing in the target interface channel to the preset control device, so that the preset control device performs spectrum analysis on the data transceiver signal and debugs a clock phase offset that meets preset functional requirements based on the spectrum analysis result; The offset adjustment module is specifically used to add a spectrum analysis component for spectrum analysis in the preset control device; connect the data sending signal and the data receiving signal transmitted through the target interface channel to the spectrum analysis component, so that the spectrum analysis component can respectively determine the data sending time point and the data receiving time point from the data sending signal and the data receiving signal; calculate the data transmission delay through the spectrum analysis component and based on the data sending time point and the data receiving time point, and then determine the clock phase offset using the data transmission delay and the internal reference clock of the target device; directly increase and / or decrease the phase offset of the clock signal between the target network card and the management controller through the preset control device and based on the clock phase offset to obtain a clock phase offset that meets the preset functional requirements, and report the clock phase offset that meets the preset functional requirements to the management controller through a preset communication bus.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of the device debugging method according to any one of claims 1 to 7.

10. A device system, characterized in that: It includes a management controller, a network card, a preset control device and a channel switching device; the channel switching device is used to switch the preset control device to the information transmission channel of the network controller sideband interface; Furthermore, the management controller implements the steps of the device debugging method according to any one of claims 1 to 7 by executing a computer program.

11. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the device debugging method according to any one of claims 1 to 7.

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