Metal oxide semiconductor capacitor structure

Abstract

The invention provides a metal oxide semiconductor (MOS) capacitor structure. The metal oxide semiconductor (MOS) capacitor structure comprises a counter-doped region in a channel region under a gate. A semiconductor region is arranged between the deep ion trap and the counter-doped region, and the doping concentration of the semiconductor region is lower than that of the deep ion trap. Two times of P-type trap ion implantation in the active region of the component in the past can be omitted, so that the manufacturing process cost is relatively low, the doping dosage of the counter-doping region can be reduced, and the TDDB (Time Dependent Dielectric Breakdown) problem of the component is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an improved metal oxide semiconductor (MOS) capacitor structure. Background Art

[0002] MOS capacitors are composed of a semiconductor substrate, an insulating film, and a gate. Conventional MOS capacitor manufacturing processes typically require the use of a dedicated MOS capacitor hard shield, two P-type well ion implantations, and one counter-dope ion implantation, resulting in high manufacturing costs and poor time-dependent dielectric breakdown (TDDB). Summary of the Invention

[0003] The main purpose of the present invention is to provide an improved MOS capacitor structure to solve the deficiencies or shortcomings of the prior art.

[0004] On one hand, the present invention provides a metal oxide semiconductor (MOS) capacitor structure, comprising: a substrate having a first conductivity type; a first trench isolation structure arranged in the substrate and surrounding an active region of the substrate; a source region arranged in the active region; a drain region arranged in the active region and separated from the source region, wherein the source region and the drain region have a second conductivity type; a channel region arranged between the source region and the drain region; an anti-doping region arranged in the channel region, wherein the anti-doping region has the second conductivity type; a deep ion well arranged in the substrate below the channel region, wherein the deep ion well has the second conductivity type; a first semiconductor region arranged between the deep ion well and the anti-doping region and located directly below the anti-doping region; a gate arranged above the channel region; and a gate dielectric layer arranged between the gate and the channel region, wherein the doping concentration of the first semiconductor region is lower than the doping concentration of the deep ion well.

[0005] According to an embodiment of the present invention, the first semiconductor region has dopants of the first conductivity type and dopants of the second conductivity type.

[0006] According to an embodiment of the present invention, the MOS capacitor structure further includes: a spacer disposed on a sidewall of the gate.

[0007] According to an embodiment of the present invention, the MOS capacitor structure further includes: a lightly doped drain (LDD) region disposed in the substrate directly below the spacer, wherein the LDD region has the second conductivity type.

[0008] According to an embodiment of the present invention, the counter-doping region overlaps with the LDD region.

[0009] According to an embodiment of the present invention, the counter-doping region overlaps with the LDD region, the source region, and the drain region.

[0010] According to an embodiment of the present invention, the MOS capacitor structure further includes: a second trench isolation structure, arranged in the substrate and surrounding the first trench isolation structure; and a first pick-up doping region, arranged in the substrate between the first trench isolation structure and the second trench isolation structure, wherein the first pick-up doping region has the first conductivity type.

[0011] According to an embodiment of the present invention, the MOS capacitor structure further includes: a third trench isolation structure, arranged in the substrate and surrounding the second trench isolation structure; a second pick-up doping region, arranged in the substrate between the second trench isolation structure and the third trench isolation structure, wherein the second pick-up doping region has the second conductivity type; and an ion trap, arranged in the substrate between the second pick-up doping region and the deep ion trap, wherein the ion trap has the second conductivity type.

[0012] According to an embodiment of the present invention, a second semiconductor region is provided between the deep ion well and the source region, and between the deep ion well and the drain region.

[0013] According to an embodiment of the present invention, the first conductivity type is P type, and the second conductivity type is N type.

[0014] Another aspect of the present invention provides a metal oxide semiconductor (MOS) capacitor structure, comprising: a substrate having a first conductivity type; a first trench isolation structure disposed in the substrate and surrounding an active region of the substrate; a source region disposed in the active region; a drain region disposed in the active region and spaced apart from the source region, wherein the source region and the drain region have a second conductivity type; a channel region disposed between the source region and the drain region; an anti-doping region disposed in the channel region, wherein the anti-doping region has the second conductivity type; and a deep ion well disposed in the substrate directly below the channel region. The invention relates to a substrate comprising a first semiconductor region disposed between the deep ion well and the anti-doped region, wherein the deep ion well has a second conductivity type; a second semiconductor region disposed between the source region and the deep ion well and between the drain region and the deep ion well in the substrate, wherein the second semiconductor region surrounds the first semiconductor region, wherein the doping concentration of the second semiconductor region is higher than the doping concentration of the first semiconductor region; a gate disposed above the channel region; and a gate dielectric layer disposed between the gate and the channel region, wherein the doping concentration of the first semiconductor region is lower than the doping concentration of the deep ion well.

[0015] According to an embodiment of the present invention, the first semiconductor region has dopants of the first conductivity type and dopants of the second conductivity type.

[0016] According to an embodiment of the present invention, the MOS capacitor structure further includes: a spacer disposed on a sidewall of the gate.

[0017] According to an embodiment of the present invention, the MOS capacitor structure further includes: a lightly doped drain (LDD) region disposed in the substrate directly below the spacer, wherein the LDD region has the second conductivity type.

[0018] According to an embodiment of the present invention, the counter-doping region overlaps with the LDD region.

[0019] According to an embodiment of the present invention, the counter-doping region overlaps with the LDD region, the source region, and the drain region.

[0020] According to an embodiment of the present invention, the MOS capacitor structure further includes: a second trench isolation structure, arranged in the substrate and surrounding the first trench isolation structure; and a first pick-up doping region, arranged in the substrate between the first trench isolation structure and the second trench isolation structure, wherein the first pick-up doping region has the first conductivity type, and wherein the second semiconductor region is arranged between the first pick-up doping region and the deep ion well.

[0021] According to an embodiment of the present invention, the MOS capacitor structure further includes: a third trench isolation structure, arranged in the substrate and surrounding the second trench isolation structure; a second pick-up doping region, arranged in the substrate between the second trench isolation structure and the third trench isolation structure, wherein the second pick-up doping region has the second conductivity type; and an ion trap, arranged in the substrate between the second pick-up doping region and the deep ion trap, wherein the ion trap has the second conductivity type.

[0022] According to an embodiment of the present invention, the second semiconductor region is adjacent to the ion trap.

[0023] According to an embodiment of the present invention, the first conductivity type is P type, and the second conductivity type is N type. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a schematic cross-sectional view of a metal oxide semiconductor capacitor structure according to an embodiment of the present invention;

[0025] Figure 2 FIG1 is a schematic cross-sectional view of a metal oxide semiconductor capacitor structure according to another embodiment of the present invention.

[0026] Explanation of symbols

[0027] 1. 2MOS capacitor structure

[0028] 100 base

[0029] 101 Deep Ion Trap

[0030] 102 first semiconductor region

[0031] 102a second semiconductor region

[0032] 103 Anti-doping region

[0033] 104 Ion Trap

[0034] 106 Ion Trap

[0035] 210 Gate

[0036] 202 gate dielectric layer

[0037] AA active area

[0038] CH channel area

[0039] DR drain region

[0040] DRD Lightly Doped Drain

[0041] PD1 first pickup doping region

[0042] PD2 second pickup doping region

[0043] SR source region

[0044] SRD Lightly Doped Drain

[0045] ST1 first trench isolation structure

[0046] ST2 second trench isolation structure

[0047] ST3 third trench isolation structure

[0048] SP spacer DETAILED DESCRIPTION

[0049] Hereinafter, the details will be described with reference to the accompanying drawings, which also constitute a part of the detailed description of the specification and are illustrated in a manner that describes specific examples of the embodiments that can be implemented. The following embodiments are described in sufficient detail to enable a person skilled in the art to implement them.

[0050] Of course, other embodiments may be implemented, and any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be considered limiting, and the embodiments contained therein are to be defined by the appended claims.

[0051] In the semiconductor structure shown, two different conductivity types are present: P-type, in which the majority of charge carriers are positively charged holes, which typically migrate along the valence band of the semiconductor in the presence of an electric field; and N-type, in which the majority of charge carriers are negatively charged electrons, which typically migrate along the conduction band in the presence of an electric field. Dopants can be introduced into an intrinsic semiconductor to produce a conductivity type. Heavily, moderately, and lightly doped P-type materials are designated P, N, and N, respectively. + , P and P - , while heavily, moderately and lightly doped N-type materials are designated as N + , N and N - .

[0052] See also Figure 1 , which is a cross-sectional schematic diagram of a metal oxide semiconductor (MOS) capacitor structure according to an embodiment of the present invention. Figure 1 As shown, the MOS capacitor structure 1 includes a substrate 100 having a first conductivity type, for example, a silicon substrate. A first trench isolation structure ST1 is provided in the substrate 100, surrounding the active area AA of the substrate 100. A source region SR and a drain region DR are provided in the active area AA, wherein the drain region DR is spaced apart from the source region SR. The source region SR and the drain region DR have a second conductivity type. According to an embodiment of the present invention, the first conductivity type may be a P type, and the second conductivity type may be an N type. According to an embodiment of the present invention, for example, the substrate 100 may be a P type silicon substrate, and the source region SR and the drain region DR may be an N + Doped region. During operation, it provides a low voltage V S Provides a low voltage V to the source region SR D A drain region DR is provided.

[0053] According to an embodiment of the present invention, a channel region CH is formed between the source region SR and the drain region DR. According to an embodiment of the present invention, at least an anti-doping region 103 is provided in the channel region CH, wherein the anti-doping region 103 has a second conductivity type, for example, N + According to an embodiment of the present invention, a deep ion well 101 is disposed in the substrate 100 below the channel region CH, wherein the deep ion well 101 has a second conductivity type, for example, N-type.

[0054] According to an embodiment of the present invention, a first semiconductor region 102 is disposed between the deep ion well 101 and the anti-doping region 103 and directly below the anti-doping region 103. According to an embodiment of the present invention, the doping concentration of the first semiconductor region 102 is lower than the doping concentration of the deep ion well 101. According to an embodiment of the present invention, the first semiconductor region 102 may have dopants of the first conductivity type and dopants of the second conductivity type.

[0055] According to an embodiment of the present invention, a gate 210 is provided above the channel region CH, such as a polysilicon gate or a metal gate. According to an embodiment of the present invention, a gate dielectric layer 202 is provided between the gate 210 and the channel region CH, such as a silicon dioxide layer, but not limited thereto. During operation, a high voltage V is provided. G Provided to the gate 210.

[0056] According to an embodiment of the present invention, the MOS capacitor structure 1 further includes a spacer SP disposed on a sidewall of the gate 210. According to an embodiment of the present invention, the MOS capacitor structure 1 further includes a lightly doped drain (LDD) region SRD and a lightly doped drain region DRD disposed in the substrate 100 directly below the spacer SP, wherein the lightly doped drain region SRD and the lightly doped drain region DRD have the second conductivity type.

[0057] According to an embodiment of the present invention, the counter-doping region 103 overlaps the lightly doped drain region SRD and the lightly doped drain region DRD. According to an embodiment of the present invention, the counter-doping region 103 overlaps the lightly doped drain region SRD and the lightly doped drain region DRD, the source region SR and the drain region DR.

[0058] According to an embodiment of the present invention, the MOS capacitor structure 1 further includes a second trench isolation structure ST2 disposed in the substrate 100 and surrounding the first trench isolation structure ST1, and a first pickup doping region PD1 disposed in the substrate 100 between the first trench isolation structure ST1 and the second trench isolation structure ST2. According to an embodiment of the present invention, the first pickup doping region PD1 has a first conductivity type, for example, P + Type. During operation, the voltage V B Give the first pickup doping region PD1, for example, V B =0V.

[0059] According to an embodiment of the present invention, the MOS capacitor structure 1 further includes a third trench isolation structure ST3 disposed in the substrate 100 and surrounding the second trench isolation structure ST2. According to an embodiment of the present invention, the MOS capacitor structure 1 further includes a second pickup doping region PD2 disposed in the substrate 100 between the second trench isolation structure ST2 and the third trench isolation structure ST3. According to an embodiment of the present invention, the second pickup doping region PD2 has a second conductivity type, for example, N + During operation, the voltage V is provided via the second pickup doping region PD2. DNW Given the deep ion trap 101, for example, V DNW =V CC .

[0060] According to an embodiment of the present invention, the MOS capacitor structure 1 further includes an ion well 106, which is arranged in the substrate 100 between the second pickup doping region PD2 and the deep ion well 101, wherein the ion well 106 has a second conductivity type, for example, N-type. According to an embodiment of the present invention, the ion well 106 is an input-output N-type well. According to an embodiment of the present invention, a second semiconductor region 102a is further provided between the deep ion well 101 and the source region SR and between the deep ion well 101 and the drain region DR. According to an embodiment of the present invention, the doping concentration of the second semiconductor region 102a is also lower than the doping concentration of the deep ion well 101. According to an embodiment of the present invention, the junction between the anti-doped region 103 and the first semiconductor region 102 is shallower than the junction between the source region SR and the second semiconductor region 102a. According to an embodiment of the present invention, the junction between the anti-doped region 103 and the first semiconductor region 102 is shallower than the junction between the drain region DR and the second semiconductor region 102a.

[0061] According to an embodiment of the present invention, MOS capacitor structure 1 further includes an ion well 104 disposed in substrate 100 between second trench isolation structure ST2 and deep ion well 101. Ion well 104 has a first conductivity type, for example, P-type. According to an embodiment of the present invention, ion well 104 is an input / output P-type well. According to an embodiment of the present invention, ion well 104 does not extend directly below first pickup doping region PD1.

[0062] See also Figure 2 , which is a cross-sectional schematic diagram of a MOS capacitor structure according to another embodiment of the present invention. Figure 2 As shown, the MOS capacitor structure 2 also includes a substrate 100 having a first conductivity type, for example, a silicon substrate. A first trench isolation structure ST1 is provided in the substrate 100, surrounding the active area AA of the substrate 100. A source region SR and a drain region DR are provided in the active area AA, wherein the drain region DR is spaced apart from the source region SR. The source region SR and the drain region DR have a second conductivity type. According to an embodiment of the present invention, the first conductivity type may be P-type, and the second conductivity type may be N-type. According to an embodiment of the present invention, for example, the substrate 100 may be a P-type silicon substrate, and the source region SR and the drain region DR may be N-type. + Doped region. During operation, it provides a low voltage V S Provides a low voltage V to the source region SR D A drain region DR is provided.

[0063] According to an embodiment of the present invention, a channel region CH is provided between the source region SR and the drain region DR. According to an embodiment of the present invention, at least an anti-doping region 103 is provided in the channel region CH, wherein the anti-doping region 103 has a second conductivity type, for example, N +According to an embodiment of the present invention, a deep ion well 101 is provided in the substrate 100 below the channel region CH, wherein the deep ion well 101 has a second conductivity type, for example, N type. During operation, a voltage V is provided. DNW Given the deep ion trap 101, for example, V DNW =V CC .

[0064] According to an embodiment of the present invention, a first semiconductor region 102 is disposed between the deep ion well 101 and the anti-doping region 103 and directly below the anti-doping region 103. According to an embodiment of the present invention, the doping concentration of the first semiconductor region 102 is lower than the doping concentration of the deep ion well 101. According to an embodiment of the present invention, the first semiconductor region 102 may have dopants of the first conductivity type and dopants of the second conductivity type.

[0065] According to an embodiment of the present invention, a gate 210 is provided above the channel region CH, such as a polysilicon gate or a metal gate. According to an embodiment of the present invention, a gate dielectric layer 202 is provided between the gate 210 and the channel region CH, such as a silicon dioxide layer, but not limited thereto. During operation, a high voltage V is provided. G Provided to the gate 210.

[0066] According to an embodiment of the present invention, the MOS capacitor structure 1 further includes a spacer SP disposed on a sidewall of the gate 210. According to an embodiment of the present invention, the MOS capacitor structure 1 further includes a lightly doped drain region SRD and a lightly doped drain region DRD disposed in the substrate 100 directly below the spacer SP, wherein the lightly doped drain region SRD and the lightly doped drain region DRD have the second conductivity type.

[0067] According to an embodiment of the present invention, the counter-doping region 103 overlaps the lightly doped drain region SRD and the lightly doped drain region DRD. According to an embodiment of the present invention, the counter-doping region 103 overlaps the lightly doped drain region SRD and the lightly doped drain region DRD, the source region SR and the drain region DR.

[0068] According to an embodiment of the present invention, the MOS capacitor structure 1 further includes a second trench isolation structure ST2 disposed in the substrate 100 and surrounding the first trench isolation structure ST1, and a first pickup doping region PD1 disposed in the substrate 100 between the first trench isolation structure ST1 and the second trench isolation structure ST2. According to an embodiment of the present invention, the first pickup doping region PD1 has a first conductivity type, for example, P + type.

[0069] According to an embodiment of the present invention, the MOS capacitor structure 1 further includes a third trench isolation structure ST3 disposed in the substrate 100 and surrounding the second trench isolation structure ST2. According to an embodiment of the present invention, the MOS capacitor structure 1 further includes a second pickup doping region PD2 disposed in the substrate 100 between the second trench isolation structure ST2 and the third trench isolation structure ST3. According to an embodiment of the present invention, the second pickup doping region PD2 has a second conductivity type, for example, N + type.

[0070] According to an embodiment of the present invention, the MOS capacitor structure 1 further includes an ion well 106, which is arranged in the substrate 100 between the second pickup doping region PD2 and the deep ion well 101, wherein the ion well 106 has a second conductivity type, for example, N-type. According to an embodiment of the present invention, the ion well 106 is an input-output N-type well. According to an embodiment of the present invention, a second semiconductor region 102a is further provided between the deep ion well 101 and the source region SR and between the deep ion well 101 and the drain region DR. The second semiconductor region 120a surrounds the first semiconductor region 120. The second semiconductor region 120a is also provided between the first pickup doping region PD1 and the deep ion well 101. According to an embodiment of the present invention, the doping concentration of the second semiconductor region 102a is greater than the doping concentration of the first semiconductor region 102.

[0071] According to an embodiment of the present invention, the MOS capacitor structure 1 further includes an ion well 104, which is arranged in the substrate 100 between the second trench isolation structure ST2 and the deep ion well 101, wherein the ion well 104 has a first conductivity type, for example, a P type. According to an embodiment of the present invention, the ion well 104 is an input-output P-type well. For example, the second semiconductor region 102a can have a first conductivity type, for example, a P type, and its doping concentration is equal to the ion well 104, but is not limited thereto. According to an embodiment of the present invention, the second semiconductor region 102a can be regarded as an extension of the ion well 104. The second semiconductor region 102a can prevent leakage current from occurring between the deep ion well 101 and the source region SR or between the deep ion well 101 and the drain region DR during operation.

[0072] The advantage of the present invention is that the two P-type well ion implantations in the active region AA are omitted, so the manufacturing process cost is lower and the doping dose of the anti-doped region 103 can be reduced, thereby improving the time-dependent dielectric breakdown (TDDB) problem of the device.

[0073] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A metal oxide semiconductor capacitor structure, comprising: A substrate having a first conductivity type; A first trench isolation structure is disposed in the substrate and surrounds an active region of the substrate; A source region is disposed in the active region; a drain region disposed in the active region and spaced apart from the source region, wherein the source region and the drain region have a second conductivity type; A channel region, disposed between the source region and the drain region; An anti-doping region is disposed in the channel region, wherein the anti-doping region has the second conductivity type; A deep ion trap is disposed in the substrate below the channel region, wherein the deep ion trap has a second conductivity type; A first semiconductor region is disposed between the deep ion well and the anti-doping region and is located directly below the anti-doping region; A gate is disposed above the channel region; as well as The gate dielectric layer is disposed between the gate and the channel region, wherein the doping concentration of the first semiconductor region is lower than the doping concentration of the deep ion well.

2. The metal oxide semiconductor capacitor structure according to claim 1, wherein: The first semiconductor region has a first conductivity type dopant and a second conductivity type dopant.

3. The metal oxide semiconductor capacitor structure according to claim 1, wherein: Also includes: The spacer is arranged on the side wall of the gate.

4. The metal oxide semiconductor capacitor structure as claimed in claim 3, wherein: Also includes: The lightly doped drain region is disposed in the substrate directly below the spacer, wherein the lightly doped drain region has the second conductivity type.

5. The metal oxide semiconductor capacitor structure as claimed in claim 4, wherein: The counter-doped region overlaps with the lightly doped drain region.

6. The metal oxide semiconductor capacitor structure according to claim 4, wherein: The counter-doped region overlaps with the lightly doped drain region, the source region and the drain region.

7. The metal oxide semiconductor capacitor structure according to claim 1, wherein: Also includes: A second trench isolation structure is disposed in the substrate and surrounds the first trench isolation structure; as well as The first pickup doping region is disposed in the substrate between the first trench isolation structure and the second trench isolation structure, wherein the first pickup doping region has the first conductivity type.

8. The metal oxide semiconductor capacitor structure according to claim 7, wherein: Also includes: A third trench isolation structure is disposed in the substrate and surrounds the second trench isolation structure; a second pickup doping region disposed in the substrate between the second trench isolation structure and the third trench isolation structure, wherein the second pickup doping region has the second conductivity type; and An ion trap is disposed in the substrate between the second pickup doping region and the deep ion trap, wherein the ion trap has the second conductivity type.

9. The metal oxide semiconductor capacitor structure according to claim 1, wherein: A second semiconductor region is arranged between the deep ion well and the source region and between the deep ion well and the drain region.

10. The metal oxide semiconductor capacitor structure according to claim 1, wherein: The first conductivity type is P type, and the second conductivity type is N type.

11. A metal oxide semiconductor capacitor structure, comprising: A substrate having a first conductivity type; A first trench isolation structure is disposed in the substrate and surrounds an active region of the substrate; A source region is disposed in the active region; A drain region is disposed in the active region and is spaced apart from the source region, wherein: The source region and the drain region have a second conductivity type; A channel region, disposed between the source region and the drain region; An anti-doping region is disposed in the channel region, wherein the anti-doping region has the second conductivity type; A deep ion trap is disposed in the substrate directly below the channel region, wherein the deep ion trap has a second conductivity type; A first semiconductor region is located between the deep ion well and the anti-doping region; A second semiconductor region is disposed in the substrate between the source region and the deep ion well and between the drain region and the deep ion well, wherein the second semiconductor region surrounds the first semiconductor region, wherein the doping concentration of the second semiconductor region is higher than the doping concentration of the first semiconductor region; A gate is disposed above the channel region; and The gate dielectric layer is disposed between the gate and the channel region, wherein the doping concentration of the first semiconductor region is lower than the doping concentration of the deep ion well.

12. The metal oxide semiconductor capacitor structure according to claim 11, wherein: The first semiconductor region has dopants of the first conductivity type and dopants of the second conductivity type.

13. The metal oxide semiconductor capacitor structure according to claim 11, wherein: Also includes: The spacer is arranged on the side wall of the gate.

14. The metal oxide semiconductor capacitor structure according to claim 13, wherein: Also includes: The lightly doped drain region is disposed in the substrate directly below the spacer, wherein the lightly doped drain region has the second conductivity type.

15. The metal oxide semiconductor capacitor structure according to claim 14, wherein: The counter-doped region overlaps with the lightly doped drain region.

16. The metal oxide semiconductor capacitor structure according to claim 14, wherein: The counter-doped region overlaps with the lightly doped drain region, the source region and the drain region.

17. The metal oxide semiconductor capacitor structure according to claim 11, wherein: Also includes: A second trench isolation structure is disposed in the substrate and surrounds the first trench isolation structure; as well as A first pickup doping region is disposed in the substrate between the first trench isolation structure and the second trench isolation structure, wherein the first pickup doping region has the first conductivity type, and wherein the second semiconductor region is disposed between the first pickup doping region and the deep ion well.

18. The metal oxide semiconductor capacitor structure according to claim 17, wherein: Also includes: A third trench isolation structure is disposed in the substrate and surrounds the second trench isolation structure; a second pickup doping region disposed in the substrate between the second trench isolation structure and the third trench isolation structure, wherein the second pickup doping region has the second conductivity type; and An ion trap is disposed in the substrate between the second pickup doping region and the deep ion trap, wherein the ion trap has the second conductivity type.

19. The metal oxide semiconductor capacitor structure according to claim 18, wherein: The second semiconductor region is adjacent to the ion trap.

20. The metal oxide semiconductor capacitor structure according to claim 11, wherein: The first conductivity type is P type, and the second conductivity type is N type.

Images