Semiconductor device and forming method thereof

Abstract

The invention discloses a semiconductor device and a forming method thereof. The structure comprises a substrate; the heterojunction bipolar transistor device is connected to the surface of the substrate, the heterojunction bipolar transistor device comprises an emitter layer, a base layer, a plurality of collector layers and a first isolation structure located in the emitter layer and the base layer, the emitter layer is provided with a first side and a second side which are opposite to each other, and the collector layers are arranged on the first side and the second side. The base layer, the collector layer and the substrate are located on the first side, the base layer is located between the collector layer and the emitter layer, stray capacitance CBE and stray capacitance CBC can be reduced, meanwhile, a substrate material with high heat dissipation performance can be selected, and the heat dissipation capacity of the heterojunction bipolar transistor device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a method for forming the same. Background Art

[0002] The RF front-end chips of wireless communication devices include power amplifiers, antenna switches, RF filters, multiplexers, and low-noise amplifiers, etc. Among them, power amplifiers include bipolar junction transistor (BJT) power amplifiers, heterojunction bipolar transistor (HBT) power amplifiers, pseudomorphic high electron mobility transistor (PHEMT) power amplifiers, etc.

[0003] With the development of wireless communication technology, more and more frequency bands are used, and more frequency bands mean more complex circuit design. However, the parasitic capacitance inside the device is a factor that limits the operating frequency and bandwidth of the device.

[0004] Therefore, the existing heterojunction bipolar transistor technology needs to be further improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor device and a method for forming the same, so as to improve the performance of the formed heterojunction bipolar transistor device.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a heterojunction bipolar transistor device, including: a substrate; a heterojunction bipolar transistor device, bonded to the surface of the substrate, the heterojunction bipolar transistor device including an emitter layer, a base layer, a plurality of collector layers, and a first isolation structure located within the emitter layer and the base layer, the emitter layer having a first side and a second side opposite to each other, the base layer, the collector layer and the substrate are located on the first side, and the base layer is located between the collector layer and the emitter layer.

[0007] Optionally, the material of the substrate includes silicon or silicon carbide.

[0008] Optionally, it also includes: a plurality of functional devices located on the surface of the substrate, wherein the plurality of functional devices are located between adjacent heterojunction bipolar transistor devices; and the functional devices include silicon-based devices.

[0009] Optionally, the heterojunction bipolar transistor device also includes: a base contact layer, the base contact layer and the plurality of collector layers are located on the same side of the base layer and are separate from each other; the base layer includes a plurality of collector regions, a plurality of electrical contact regions and a plurality of first isolation regions, the plurality of collector regions are arranged along a first direction, the collector layer is located in the collector region, the base contact layer is located in the electrical contact region, and the first isolation structure is located in the first isolation region.

[0010] Optionally, the plurality of collector regions are further arranged along a second direction, and the first direction and the second direction are perpendicular to each other.

[0011] Optionally, the electrical contact region is located between the collector regions adjacent to each other in the second direction, and the first isolation region is located between the collector regions adjacent to each other in the first direction.

[0012] Optionally, the electrical contact regions located in the first direction are interconnected and extend along the first direction.

[0013] Optionally, the first isolation regions located in the second direction are connected to each other and extend along the second direction.

[0014] Optionally, the base contact layer includes a plurality of first contact strips, wherein the first contact strips are located on the surface of the electrical contact region and extend along the first direction, and the first contact strips are located between the collector layers adjacent to each other in the second direction.

[0015] Optionally, the base contact layer further includes: a plurality of second contact strips connected to the plurality of first contact strips, the second contact strips are located on the surface of the first isolation region and extend along the second direction, and the second contact strips are located between two adjacent collector layers in the first direction.

[0016] Optionally, the heterojunction bipolar transistor device further includes: a base conductive structure and a collector conductive structure, the base conductive structure is electrically connected to the base contact layer, the collector conductive structure is electrically connected to the collector layer, and the base conductive structure and the collector conductive structure are located on the first side.

[0017] Optionally, it further includes: a first conductive plug penetrating the substrate, the first conductive plug being electrically connected to the base conductive structure; and a second conductive plug penetrating the substrate, the second conductive plug being electrically connected to the collector conductive structure.

[0018] Optionally, it further includes: an emitter conductive structure, the emitter conductive structure is electrically connected to the emitter layer; and a third conductive plug penetrating the substrate, the third conductive plug is electrically connected to the emitter conductive structure.

[0019] Optionally, it further includes: a second passivation layer located on a second side of the emitter layer; and an emitter lead-out structure located in the second passivation layer, wherein the emitter lead-out structure is electrically connected to the emitter layer.

[0020] Optionally, the heterojunction bipolar transistor device also includes: a second barrier layer located between the base layer and the plurality of collector layers, the material of the second barrier layer being different from the material of the base layer, and the conductivity type of the second barrier layer being different from the conductivity type of the base layer; the base contact layer being embedded in the second barrier layer and in contact with the base layer.

[0021] Correspondingly, the technical solution of the present invention also provides a method for forming a heterojunction bipolar transistor device, comprising: providing a substrate, the substrate comprising a first surface and a second surface relative to each other; forming a plurality of heterojunction bipolar transistor devices on the first surface of the substrate, the substrate and the plurality of heterojunction bipolar transistor devices constituting an initial device structure, each of the heterojunction bipolar transistor devices comprising an emitter layer, a base layer, a plurality of collector layers, and a first isolation structure located within the emitter layer and the base layer, the emitter layer having a first side and a second side relative to each other, the base layer and the collector layer being located on the first side, the base layer being located between the collector layer and the emitter layer, and the substrate being located on the second side; providing a base, the material of the base being different from that of the substrate; with the first side of the emitter layer facing the base, and using a bonding process to bond the initial device structure and the base to each other; after the bonding process, removing the substrate.

[0022] Optionally, the initial device structure includes a plurality of first regions and a plurality of second regions, the second regions are located between adjacent first regions, and the heterojunction bipolar transistor device is located within the first regions; the method further includes: after removing the substrate, etching a portion of the initial device structure located in the second regions to expose a portion of the substrate surface; forming a plurality of functional devices on the exposed substrate surface; the functional devices include silicon-based devices.

[0023] Optionally, the method for forming the heterojunction bipolar transistor device includes: forming an emitter material layer on the first surface of the substrate; forming a base material layer on the emitter material layer; forming a collector material layer on the base material layer; etching the collector material layer to form a plurality of collector layers; etching the base material layer until the emitter material layer is exposed to form the base layer; and injecting ions into the emitter material layer and the base layer between two adjacent collector layers through an ion implantation process to form the first isolation structure in the emitter material layer and the base layer, and forming the emitter layer with the portion of the emitter material layer where no ions are implanted.

[0024] Optionally, the method for forming the heterojunction bipolar transistor device further includes: using the ion implantation process to implant ions into the emitter material layer, and simultaneously forming a second isolation structure in the emitter material layer while forming the first isolation structure, wherein the second isolation structure surrounds the emitter layer.

[0025] Optionally, the process parameters of the ion implantation process include: the ions include one or more of boron ions, helium ions and hydrogen ions, and the implantation dose range is 1×10 13 ion / cm 2 Up to 1×10 14 ion / cm 2 .

[0026] Optionally, the method for forming the heterojunction bipolar transistor device also includes: forming a base contact layer on the base layer; the base layer includes a plurality of collector regions, a plurality of electrical contact regions and a plurality of first isolation regions, the plurality of collector regions are arranged along a first direction, the collector layer is located in the collector region, the base contact layer is located in the electrical contact region, and the first isolation structure is located in the first isolation region.

[0027] Optionally, the plurality of collector regions are further arranged along a second direction, and the first direction and the second direction are perpendicular to each other.

[0028] Optionally, the electrical contact region is located between the collector regions adjacent to each other in the second direction, and the first isolation region is located between the collector regions adjacent to each other in the first direction.

[0029] Optionally, the method for forming the base contact layer further includes: forming a plurality of first contact strips on the surface of the electrical contact region, wherein the first contact strips extend along the first direction and are located between two adjacent collector layers in the second direction.

[0030] Optionally, the first contact strip crosses the first isolation region.

[0031] Optionally, the method for forming the base contact layer further includes: forming a plurality of second contact strips connected to the plurality of first contact strips on the surface of the first isolation region, the second contact strips extending along the second direction, and the second contact strips being located between two adjacent collector layers in the first direction.

[0032] Optionally, the method for forming the heterojunction bipolar transistor device includes: forming a base conductive structure and a collector conductive structure, the base conductive structure and the base contact layer are electrically connected, the collector conductive structure and the collector layer are electrically connected, and the base conductive structure and the collector conductive structure are located on the first side.

[0033] Optionally, the method further includes: forming a first conductive plug penetrating the substrate, the first conductive plug being electrically connected to the base conductive structure; and forming a second conductive plug penetrating the substrate, the second conductive plug being electrically connected to the collector conductive structure.

[0034] Optionally, the method further includes: forming an emitter conductive structure, wherein the emitter conductive structure is electrically connected to the emitter layer; and forming a third conductive plug penetrating the substrate, wherein the third conductive plug is electrically connected to the emitter conductive structure.

[0035] Optionally, the method further includes: forming a second passivation layer on a second side of the emitter layer; and forming an emitter lead-out structure in the second passivation layer to electrically connect the emitter lead-out structure to the emitter layer.

[0036] Optionally, after forming the plurality of heterojunction bipolar transistor devices and before the bonding process, the method further includes: forming a first dielectric layer on the plurality of heterojunction bipolar transistor devices; and bonding the first dielectric layer and the substrate to each other.

[0037] Optionally, before forming a number of heterojunction bipolar transistor devices, a first barrier layer is also formed on the first surface, and the material of the first barrier layer is different from the material of the emitter layer; after removing the substrate, the first barrier layer is also removed; the material of the first barrier layer includes indium gallium phosphide.

[0038] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0039] In the semiconductor device provided by the technical solution of the present invention, in each heterojunction bipolar transistor device, the emitter layer is placed at the bottom layer to carry the base layer and the collector layer, so the area of ​​the emitter layer is the largest. Under the requirement of a fixed emitter layer area, the area of ​​the PN junction formed between the collector layer and the base layer is small, thereby reducing the parasitic capacitance (i.e., junction capacitance) C between the collector layer and the base layer. BC At the same time, by providing a first isolation structure in the emitter layer and the base layer, the PN junction area formed between the emitter layer and the base layer can be reduced, thereby reducing the parasitic capacitance C between the emitter layer and the base layer. BE , which is beneficial to improving the cutoff frequency and RF gain of the device. In addition, the heterojunction bipolar transistor device is bonded to the surface of a substrate (such as a silicon substrate), and a substrate material with higher heat dissipation performance can be selected to improve the heat dissipation capacity of the heterojunction bipolar transistor device.

[0040] Furthermore, several functional devices located on the surface of the substrate, and several of the functional devices located between adjacent heterojunction bipolar transistor devices, can be integrated with devices such as low-noise amplifiers, switches, and filters based on the substrate, which can improve the integration of RF devices and reduce the size of RF devices.

[0041] Furthermore, a plurality of collector regions are arranged along the first direction, and a plurality of the collector regions are also arranged along the second direction, the first direction and the second direction are perpendicular to each other, and under the requirement of a fixed emitter layer area, the total area of ​​the collector layer is reduced, and the parasitic capacitance (i.e., junction capacitance) C between the collector layer and the base layer is further reduced. BC .

[0042] Furthermore, the first isolation regions located in the second direction are interconnected and extend along the second direction. By increasing the size of the first isolation region along the second direction, the area of ​​the first isolation region is increased, and the area of ​​the PN junction formed between the emitter layer and the base layer is further reduced, so as to further reduce the parasitic capacitance C between the emitter layer and the base layer. BE , improving the cutoff frequency and RF gain of the device.

[0043] Furthermore, several of the second contact strips in the base contact layer are arranged between the collector layers adjacent to each other in the first direction, so as to disperse the base current, reduce the heat concentration effect caused by the current concentration, and improve the heat dissipation capacity. Moreover, the arrangement of several of the second contact strips and several of the first contact strips makes the distribution of the base contact layer more uniform, which is beneficial to reduce stress and prevent device deformation.

[0044] In the method for forming a semiconductor device provided by the technical solution of the present invention, a heterojunction bipolar transistor device is formed on a substrate. In each heterojunction bipolar transistor device, the emitter layer is placed at the bottom layer to carry the base layer and the collector layer, so the area of ​​the emitter layer is the largest. Under the requirement of a fixed emitter layer area, the area of ​​the PN junction formed between the collector layer and the base layer is small, thereby reducing the parasitic capacitance (i.e., junction capacitance) C between the collector layer and the base layer. BC At the same time, by providing a first isolation structure in the emitter layer and the base layer, the PN junction area formed between the emitter layer and the base layer can be reduced, thereby reducing the parasitic capacitance C between the emitter layer and the base layer. BE , which is beneficial to improving the cutoff frequency and radio frequency gain of the device. In addition, the heterojunction bipolar transistor device is bonded to the surface of a substrate (such as a silicon substrate), and the material of the substrate is different from the material of the substrate. A substrate material with higher heat dissipation performance can be selected to improve the heat dissipation capacity of the heterojunction bipolar transistor device.

[0045] Furthermore, a number of functional devices are formed on the exposed surface of the substrate, and integration with devices such as low-noise amplifiers, switches, and filters can be achieved based on the substrate, thereby improving the integration of radio frequency devices and reducing the size of radio frequency devices.

[0046] Furthermore, a plurality of collector regions are arranged along the first direction, and a plurality of the collector regions are also arranged along the second direction, the first direction and the second direction are perpendicular to each other, and under the requirement of a fixed emitter layer area, the total area of ​​the collector layer is reduced, and the parasitic capacitance (i.e., junction capacitance) C between the collector layer and the base layer is further reduced. BC .

[0047] Furthermore, the first contact strip crosses the first isolation region, and by increasing the size of the first isolation region along the second direction, thereby increasing the area of ​​the first isolation region, further reducing the area of ​​the PN junction formed between the emitter layer and the base layer, so as to further reduce the parasitic capacitance C between the emitter layer and the base layer. BE , improving the cutoff frequency and RF gain of the device.

[0048] Furthermore, several of the second contact strips in the base contact layer are arranged between the collector layers adjacent to each other in the first direction, so as to disperse the base current, reduce the heat concentration effect caused by the current concentration, and improve the heat dissipation capacity. Moreover, the arrangement of several of the second contact strips and several of the first contact strips makes the distribution of the base contact layer more uniform, which is beneficial to reduce stress and prevent device deformation. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figures 1 to 3 It is a schematic diagram of the structure of a heterojunction bipolar transistor device;

[0050] Figures 4 to 48 It is a structural schematic diagram of each step of a method for forming a semiconductor device according to an embodiment of the present invention;

[0051] Figures 49 to 51 It is a structural schematic diagram of each step of a method for forming a semiconductor device according to another embodiment of the present invention. DETAILED DESCRIPTION

[0052] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0053] As described in the background art, the performance of heterojunction bipolar transistor devices formed by the existing technology needs to be improved. Now, a heterojunction bipolar transistor device is described and analyzed.

[0054] Figures 1 to 3 It is a structural schematic diagram of a heterojunction bipolar transistor device.

[0055] Please refer to Figures 1 to 3 , Figure 1 for Figure 2 and Figure 3 The schematic diagram of the top view of the passivation layer is omitted. Figure 2 for Figure 1 Schematic diagram of the cross-sectional structure along the DD1 direction, Figure 3 for Figure 1 The cross-sectional structural schematic diagram along the EE1 direction in the figure, the heterojunction bipolar transistor device comprises: a substrate 100; a first collector portion 101, an isolation layer 102 and a prism structure on the first collector portion 101 located on the substrate 100, the prism structure comprising a second collector portion 103 and a base layer 104 located on the second collector portion 103, the collector layer comprising the first collector portion 101 and the second collector portion 103, the isolation layer 102 is located on the side wall of the first collector portion 101 and surrounds the first collector portion 101; a plurality of emitter layers 105 and a base contact layer located on the base layer 104, the plurality of emitter layers 105 are arranged parallel to the first direction X and along the second direction Y, the first The direction X is perpendicular to the second direction Y, the base contact layer includes a base bus line 106 parallel to the second direction Y and a plurality of base portions 107 parallel to the first direction X, each of the base portions 107 is located between adjacent emitter layers 105 and is electrically connected to the base bus line 106; an emitter contact layer 108 located on each of the emitter layers 105; a passivation layer 109 located on the surfaces of the emitter layer 105, the emitter contact layer 108 and the base layer 104, the passivation layer 109 having an opening (not shown in the figure), the opening exposing a portion of the surface of the base layer 104, and the base contact layer is also located in the opening; and a collector contact layer 110 located on the first collector portion 101.

[0056] In the above heterojunction bipolar transistor device, a parasitic capacitance (ie, junction capacitance) C exists at the contact surface (ie, PN interface) between the collector layer and the base layer 104. BC The prism structure formed by the second collector portion 103 of the collector layer and the base layer 104 is at the bottom layer, which is used to carry the emitter layer 105 and the base contact layer. Therefore, the area of ​​the upper surface of the prism structure is larger than the area of ​​the emitter layer 105. The area of ​​the emitter layer 105 determines the output power of the device. Under the requirement of a fixed emitter layer area, the above structure makes the contact surface between the collector layer and the base layer 104 larger, thereby making the parasitic capacitance C BC Large, affecting the device's RF performance (such as power gain).

[0057] In order to solve the above problems, the present invention provides a heterojunction bipolar transistor device and a method for forming the same. A heterojunction bipolar transistor device is formed on a substrate. In each heterojunction bipolar transistor device, the emitter layer is placed at the bottom layer to carry the base layer and the collector layer. Therefore, the emitter layer has the largest area. Under the requirement of a fixed emitter layer area, the PN junction area formed between the collector layer and the base layer is small, thereby reducing the parasitic capacitance (i.e., junction capacitance) C between the collector layer and the base layer. BC At the same time, by providing a first isolation structure in the emitter layer and the base layer, the PN junction area formed between the emitter layer and the base layer can be reduced, thereby reducing the parasitic capacitance C between the emitter layer and the base layer. BE , which is beneficial to improving the cutoff frequency and radio frequency gain of the device. In addition, the heterojunction bipolar transistor device is bonded to the surface of a substrate (such as a silicon substrate), and the material of the substrate is different from the material of the substrate. A substrate material with higher heat dissipation performance can be selected to improve the heat dissipation capacity of the heterojunction bipolar transistor device.

[0058] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0059] Figures 4 to 48 It is a structural schematic diagram of each step of a method for forming a semiconductor device according to an embodiment of the present invention.

[0060] Please refer to Figure 4 , providing a substrate 20, wherein the substrate 20 includes a first surface 20a and a second surface 20b opposite to each other.

[0061] The material of the substrate 20 includes gallium arsenide or indium phosphide. In this embodiment, the material of the substrate 20 is gallium arsenide.

[0062] In this embodiment, a first barrier layer 22 is further formed on the first surface 20a, and the material of the first barrier layer 20a is different from the material of the emitter layer to be formed subsequently. In another embodiment, the first barrier layer may not be formed.

[0063] In this embodiment, the material of the first barrier layer 22 includes indium gallium phosphide. Here, selecting indium gallium phosphide as the first barrier layer 22 can reduce the defect problem introduced by lattice adaptation between the first barrier layer 22 and the device layer.

[0064] In this embodiment, the thickness of the first barrier layer 22 is in a range of 200 nm to 2000 nm.

[0065] Please refer to Figure 5, a plurality of heterojunction bipolar transistor devices 21 are formed on the first surface 20a of the substrate 20, the substrate 20 and the plurality of heterojunction bipolar transistor devices 21 constitute an initial device structure Q1, each of the heterojunction bipolar transistor devices 21 includes an emitter layer, a base layer, a plurality of collector layers, and a first isolation structure located within the emitter layer and the base layer, the emitter layer having a first side and a second side opposite to each other, the base layer and the collector layer are located on the first side, the base layer is located between the collector layer and the emitter layer, and the substrate is located on the second side.

[0066] Specifically, a plurality of heterojunction bipolar transistor devices 21 are formed on the surface of the first barrier layer 22 .

[0067] In this embodiment, the initial device structure Q1 includes a plurality of first regions i and a plurality of second regions ii, wherein the second regions ii are located between adjacent first regions i, and the heterojunction bipolar transistor device 21 is located within the first regions i.

[0068] In this embodiment, the heterojunction bipolar transistor device 21 also includes: a collector contact layer located on the surface of each collector layer; a base contact layer located on a portion of the surface of the base layer, and the base contact layer and several of the collector layers are separate from each other; an emitter contact layer located on a portion of the surface of the emitter layer, and the emitter contact layer and the base layer are separate from each other.

[0069] In this embodiment, the heterojunction bipolar transistor device 21 also includes: a base conductive structure and a collector conductive structure, the base conductive structure is electrically connected to the base contact layer, the collector conductive structure is electrically connected to the collector contact layer, and the emitter conductive structure, the base conductive structure and the collector conductive structure are located on the first side.

[0070] In this embodiment, the heterojunction bipolar transistor device 21 also includes: an emitter conductive structure, which is electrically connected to the emitter contact layer; the emitter conductive structure includes an emitter conductive portion and an emitter conductive bus connected to the emitter conductive portion, the emitter conductive portion extends along the second direction, and the emitter conductive bus extends along the first direction; the emitter conductive bus and the base conductive structure are respectively located on both sides of the emitter layer.

[0071] In another embodiment, the heterojunction bipolar transistor device may include only the base conductive structure and the collector conductive structure, but not the emitter conductive structure.

[0072] Here, it should be noted that for the convenience of description, Figure 5The specific structure of the heterojunction bipolar transistor device 21 is not shown in the figure, and the specific structure and formation method of the heterojunction bipolar transistor device 21 will be described in detail later.

[0073] Please refer to Figure 6 , providing a substrate 30 , wherein the material of the substrate 30 is different from the material of the substrate 20 .

[0074] In this embodiment, the material of the substrate 30 includes silicon.

[0075] In other embodiments, the substrate may also be made of silicon carbide, silicon germanium, a multi-component semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). The multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0076] Please refer to Figure 7 , the first side of the emission layer is directed toward the substrate 30 , and a bonding process is used to bond the initial device structure Q1 and the substrate 30 to each other.

[0077] In this embodiment, after forming the plurality of heterojunction bipolar transistor devices 21 and before the bonding process, a first dielectric layer 31 is formed on the plurality of heterojunction bipolar transistor devices 21 ; and the first dielectric layer 31 and the substrate 30 are bonded to each other.

[0078] In this embodiment, the method for forming the first dielectric layer 31 includes: forming a first dielectric material layer (not shown) on a plurality of the heterojunction bipolar transistor devices; and planarizing the first dielectric material layer to form the first dielectric layer 31 .

[0079] In this embodiment, the material of the first dielectric material layer is silicon oxide. The purpose of forming the first dielectric layer 31 is to improve the firmness of the mutual bonding between the substrate structure and the base 30 .

[0080] Please refer to Figure 8 After the bonding process, the substrate 20 is removed.

[0081] In this embodiment, the method for removing the substrate 20 includes: thinning the initial device structure Q1 until a plurality of the heterojunction bipolar transistor devices 21 are exposed.

[0082] Specifically, the emitter layer of the heterojunction bipolar transistor device 21 is exposed.

[0083] In this embodiment, the thinning process includes a mechanochemical grinding process.

[0084] In this embodiment, the thinning process further includes a first etching process after the mechanical chemical grinding process, and the first etching process includes one of a dry etching process and a wet etching process or a combination of both.

[0085] The first barrier layer 22 acts as an etching stop during the thinning process, which is beneficial to protecting the heterojunction bipolar transistor device 21.

[0086] In this embodiment, after removing the substrate 20 , the first barrier layer 22 is also removed.

[0087] Please refer to Fig. 9 After removing the substrate 20, a portion of the initial device structure Q1 located in the second region ii is further etched to expose a portion of the surface of the base 30.

[0088] In this embodiment, after removing the substrate 20 and before etching the portion of the initial device structure Q1 located in the second region ii, a first passivation layer (not shown in the figure) is formed on the surface of the first region i of the initial device structure Q1. The first passivation layer is used to protect the plurality of heterojunction bipolar transistor devices 21.

[0089] Specifically, after removing the first barrier layer 22 , the first passivation layer is formed.

[0090] In this embodiment, the method of etching the portion of the initial device structure Q1 located in the second region ii includes one of a dry etching process and a wet etching process or a combination of both.

[0091] Please refer to Fig.10 , a plurality of functional devices 23 are formed on the exposed surface of the substrate 30 .

[0092] At this point, the substrate 20 and the base 30 formed with the heterojunction bipolar transistor device are bonded to each other through a bonding process. The material of the base 30 is different from that of the substrate 20. A base 30 material with higher heat dissipation performance can be selected to improve the heat dissipation capacity of the heterojunction bipolar transistor device.

[0093] Furthermore, a number of functional devices 23 are formed on the exposed surface of the substrate 30, and integration with devices such as low-noise amplifiers, switches, and filters can be achieved based on the substrate 30, thereby improving the integration of RF devices and reducing the size of RF devices.

[0094] In this embodiment, the functional device 23 includes a silicon-based device structure.

[0095] Specifically, the silicon-based device structure may be an active device or a passive device.

[0096] It should be noted that Fig.10 Schematic diagram of a capacitor as the functional device 23 is given in FIG. , which is only used for illustration, and the structure of the functional device 23 is not limited thereto.

[0097] Please continue to refer to Fig.10 A second passivation layer 24 is also formed on the second side of the emitter layer.

[0098] Specifically, a second passivation layer 24 is formed on the surfaces of the plurality of functional devices 23 and the plurality of heterojunction bipolar transistor devices 21 .

[0099] In this embodiment, after forming the second passivation layer 24, a first conductive plug (not shown in the figure) penetrating the substrate 30 is also formed, and the first conductive plug is electrically connected to the base conductive structure; a second conductive plug (not shown in the figure) penetrating the substrate 30 is formed, and the second conductive plug is electrically connected to the collector conductive structure; a third conductive plug (not shown in the figure) penetrating the substrate 30 is formed, and the third conductive plug is electrically connected to the emitter conductive structure. The first conductive plug, the second conductive plug and the third conductive plug are used for electrical connection between the heterojunction bipolar transistor device 21 and the outside world.

[0100] In another embodiment, only the first conductive plug and the second conductive plug may be formed, without forming the third conductive plug, and an emitter lead-out structure may be formed in the second passivation layer to electrically connect the emitter lead-out structure to the emitter layer. The first conductive plug, the second conductive plug and the emitter lead-out structure are used to electrically connect the heterojunction bipolar transistor device 21 to the outside world. Specifically, a groove is formed in the second passivation layer, and the emitter layer exposed by the groove has the emitter lead-out structure formed in the groove.

[0101] Next, the specific structure and formation method of the heterojunction bipolar transistor device 21 will be described in detail.

[0102] It should be noted here that the subsequent Figures 11 to 48 It is used to illustrate the structure and formation method of heterojunction bipolar transistor devices. At the same time, for simplicity, Figures 11 to 48 The substrate 20 is omitted.

[0103] Please Figure 4 Based on this, continue to refer to Figure 11 to Figure 12 , Fig.11 for Fig.12 A top view of the structure. Fig.12 yes Fig.11In the cross-sectional structural diagram along the MM1 direction, an emitter material layer 201 is formed on the first surface 20a of the substrate 20; a base material layer 202 is formed on the emitter material layer 201; and a collector material layer 203 is formed on the base material layer 202.

[0104] The emitter material layer 201 is used to form an emitter layer, the base material layer 202 is used to form a base layer, and the collector material layer 203 is used to form a collector layer.

[0105] In this embodiment, the substrate 20 includes a plurality of first regions i, including an active region AA and a second isolation region I, and the second isolation region I surrounds the active region AA. The active region AA is used to define the position of the emitter layer, and the second isolation region I is used to define the position of the second isolation structure.

[0106] In this embodiment, the active area AA includes a base mesa region bp; the base mesa region bp includes a base lead-out region bc, a gap region g and a collector mesa region cp arranged along the second direction Y, and the base lead-out region bc and the collector mesa region cp are located on both sides of the gap region g. The base mesa region bp is used to define the position of the base layer, the collector mesa region cp is used to define the positions of several collector layers, and the base lead-out region bc is used to define the position of the base terminal.

[0107] In this embodiment, the active area AA further includes two emission lead-out areas ec, the two emission lead-out areas ec and the base surface area cp are arranged along the first direction X, and the two emission lead-out areas ec are respectively located on both sides of the base surface area cp. The emission lead-out area ec is used to define the position of the first emitter conductive portion.

[0108] In this embodiment, the material of the emitter material layer 201 includes one or more of gallium arsenide, indium gallium arsenide and indium gallium phosphide; the material of the base material layer 202 includes gallium arsenide; and the material of the collector material layer 203 includes gallium arsenide.

[0109] In this embodiment, the thickness of the emitter material layer 201 is in the range of 0.2µm to 2µm; the thickness of the base material layer 202 is in the range of 40nm to 80nm; and the thickness of the collector material layer 203 is in the range of 1µm to 2µm.

[0110] In this embodiment, an NPN type heterojunction bipolar transistor is formed, that is, the conductivity type of the collector layer and the emitter layer is N type, and the conductivity type of the base layer is P type.

[0111] In another embodiment, it can also be used to form a PNP type heterojunction bipolar transistor.

[0112] In this embodiment, the conductive ion doping concentration in the emitter material layer 201 is in the range of 1.0×10 17 atom / cm 3 Up to 2.0×10 19 atom / cm 3 The conductive ion doping concentration in the base material layer 202 is in the range of 1.0×10 19 atom / cm 3 Up to 5.5×10 19 atom / cm 3 The conductive ion doping concentration in the collector material layer 203 is in the range of 1×10 15 atom / cm 3 Up to 5.0×10 18 atom / cm 3 .

[0113] In this embodiment, a second barrier material layer (not shown in the figure) is further formed on the surface of the base material layer 202, and the collector material layer 203 is formed on the surface of the second barrier material layer. The material of the second barrier material layer is different from that of the base material layer 202, and the conductivity type of the second barrier material layer is different from that of the base material layer 202. The second barrier material layer is used to protect the base layer to reduce the influence of surface defects on the performance of the base layer, and in the etching process of forming the collector, it also serves as an etching stop layer to protect the base layer.

[0114] In another embodiment, the second barrier material layer may not be formed.

[0115] In this embodiment, the material of the second barrier material layer includes indium gallium phosphide; the thickness of the second barrier material layer ranges from 30 nm to 50 nm; the conductive ion doping concentration in the second barrier material layer ranges from 2.0×10 17 atom / cm 3 Up to 5.0×10 17 atom / cm 3 .

[0116] Please refer to Figures 13 to 16 , Fig.13 for Figures 14 to 16 A top view of the structure. Fig.14 yes Fig.13 Schematic diagram of the cross-sectional structure along the MM1 direction, Fig.15 yes Fig.13 Schematic diagram of the cross-sectional structure along the NN1 direction, Fig.16 yes Fig.13 In the schematic cross-sectional structure diagram along the FF1 direction, the collector material layer 203 is etched to form a plurality of collector layers 205.

[0117] In this embodiment, a plurality of collector layers 205 are arranged along the first direction X.

[0118] In this embodiment, before etching the collector material layer 203 , a plurality of collector contact layers 204 are formed on a portion of the surface of the collector material layer 203 .

[0119] In this embodiment, the method for etching the collector material layer 203 further includes: etching the collector material layer 203 using the plurality of collector contact layers 204 as masks.

[0120] Here, due to the second barrier material layer on the surface of the base material layer 202, in the process of etching the collector material layer 203, a process with different etching selectivities for the base material layer 202 and the second barrier material layer can be selected, so that the second barrier material layer can act as an etching stop layer, thereby reducing the etching damage to the base material layer 202, and helping to improve the performance of the formed base layer.

[0121] In this embodiment, a plurality of collector layers 205 are formed on the collector surface region cp.

[0122] In this embodiment, a plurality of the collector contact layers 204 are also arranged along the second direction Y.

[0123] In this embodiment, the plurality of collector layers 205 are also arranged along the second direction Y, and the first direction X and the second direction Y are perpendicular to each other. Here, by arranging the plurality of collector layers 205 along the second direction Y, the total area of ​​the collector layer is further reduced under the requirement of a fixed emitter layer area, and the parasitic capacitance (i.e., junction capacitance) C between the collector layer and the base layer is further reduced. BC A base contact layer may be provided on the surface of the base layer between adjacent collector layers 205 in the second direction Y (see the subsequent description of the first contact strip).

[0124] It should be noted that Fig.13 Only a number of collector layers arranged in a 3×2 array are shown. The number and arrangement of the collector layers are not limited thereto and can be adjusted according to actual needs. For example, the arrangement of the collector layers can also be a 2×3 array.

[0125] In another embodiment, a plurality of the collector layers are arranged along the first direction and extend along the second direction, but are not arranged along the second direction. For example, the plurality of collector layers are arranged in a 3×1 array.

[0126] In yet another embodiment, a plurality of the collector layers are arranged along a first direction and extend along the first direction, but are not arranged along the second direction.

[0127] In this embodiment, the material of the collector contact layer 204 includes metal, and the metal includes one or more of gold germanium, nickel and gold.

[0128] In this embodiment, the formation process of the collector contact layer 204 includes an evaporation process.

[0129] In this embodiment, the method for forming the collector contact layer 204 also includes: forming a first mask layer (not shown in the figure) on the surface of the collector material layer 203, the first mask layer having a first mask groove (not shown in the figure), the first mask groove exposing a portion of the collector material layer 203; forming the collector contact layer 204 in the first mask groove; and removing the first mask layer.

[0130] In this embodiment, the material of the first mask layer includes photoresist.

[0131] The process of etching the collector material layer 203 includes one of a dry etching process and a wet etching process or a combination of the two. In this embodiment, the process of etching the collector material layer 203 is a dry etching process.

[0132] Please refer to Figures 17 to 20 , Fig.17 for Figures 18 to 20 A top view of the structure. Fig.18 yes Fig.17 Schematic diagram of the cross-sectional structure along the MM1 direction, Fig.19 yes Fig.17 Schematic diagram of the cross-sectional structure along the NN1 direction, Fig. 20 yes Fig.17 The cross-sectional structure schematic diagram along the FF1 direction, etching the base material layer 202 (such as Fig.14 As shown), until the emitter material layer 201 is exposed, the base layer 206 is formed.

[0133] In this embodiment, the base layer 206 is formed on the base mesa region bp.

[0134] The base layer 206 includes a plurality of collector regions (not shown in the figure), a plurality of electrical contact regions S1 and a plurality of first isolation regions S2; the collector region is used to define the position of the collector layer, and the collector layer is located on the collector region; the electrical contact region S1 is used to define the position where the base contact layer is in electrical contact with the base layer; the first isolation region S2 is used to define the position of the first isolation structure.

[0135] In this embodiment, a plurality of collector regions are arranged along the first direction X and the second direction Y. Under the requirement of a fixed emitter layer area, the total area of ​​the collector layer 205 is reduced, and the parasitic capacitance (ie, junction capacitance) C between the collector layer and the base layer is further reduced. BC。

[0136] In this embodiment, the electrical contact region S1 is located between the collector regions adjacent to each other in the second direction Y, and the first isolation region S2 is located between the collector regions adjacent to each other in the first direction X.

[0137] In another embodiment, a plurality of collector regions are arranged along the first direction and extend along the second direction but are not arranged along the second direction, and the electrical contact region is located at one side of the collector region in the second direction.

[0138] In this embodiment, the electrical contact regions S1 located in the first direction X are interconnected and extend along the first direction X.

[0139] In this embodiment, the method for forming the base layer 206 further includes: forming a second mask layer (not shown in the figure) on the base platform area bp; and etching the base material layer 202 using the second mask layer as a mask to form the base layer 206.

[0140] In this embodiment, the second barrier material layer is further etched to form a second barrier layer. Specifically, before etching the base material layer 202, the second barrier material layer is etched using the second mask layer as a mask to form a second barrier layer.

[0141] In this embodiment, the material of the second mask layer includes photoresist.

[0142] Please refer to Figure 21 to Figure 24 , Fig.21 for Figure 22 to Figure 24 A top view of the structure. Fig. 22 yes Fig.21 Schematic diagram of the cross-sectional structure along the MM1 direction, Fig.23 yes Fig.21 Schematic diagram of the cross-sectional structure along the NN1 direction, Fig.24 yes Fig.21 , ions are injected into the base layer 206 located in the first isolation region S2 and the emitter material layer 201 located below the first isolation region S2 through an ion implantation process, that is, into the emitter material layer 201 (such as Fig.17As shown in the figure, ions are implanted into the emitter material layer 201 and the base layer 206 to form the first isolation structure 207 in the emitter material layer 201 and the base layer 206, and the emitter layer 208 is formed by the portion of the emitter material layer 201 where ions are not implanted.

[0143] Specifically, the emitter layer 208 is formed by using the emitter material layer 201 on the active area AA.

[0144] In this embodiment, the ion implantation process is also used to implant ions into the emitter material layer 201 , and while forming the first isolation structure 207 , a second isolation structure 209 is formed in the emitter material layer 201 . The second isolation structure 209 surrounds the emitter layer 208 .

[0145] Specifically, the ions are implanted into the emitter material layer 201 on the second isolation region I to form a second isolation structure 209 with the emitter material layer 201 on the second isolation region I.

[0146] In this embodiment, a plurality of first isolation regions S2 are located between the collector regions adjacent to each other in the first direction X and are arranged at intervals along the second direction Y; the first isolation structure 207 is formed between two collector layers 205 adjacent to each other in the first direction X, and the first isolation structures 207 are arranged at intervals along the second direction Y (e.g. Fig.21 as shown).

[0147] In another embodiment, the first isolation region is adjacent to the electrical contact region.

[0148] In another embodiment, the first isolation region is located between the collector regions adjacent to each other in the first direction, and the first isolation regions located in the second direction are interconnected and extend along the second direction; the first isolation structure is formed between two collector layers adjacent to each other in the first direction, and the first isolation structure extends along the second direction. By increasing the size of the first isolation region (first isolation structure) along the second direction, thereby increasing the area of ​​the first isolation region (first isolation structure), further reducing the area of ​​the PN junction formed between the emitter layer and the base layer, and further reducing the parasitic capacitance C between the emitter layer and the base layer. BE , improving the cutoff frequency and RF gain of the device.

[0149] In this embodiment, the process parameters of the ion implantation process include: the ions include one or more of boron ions, helium ions and hydrogen ions, and the implantation dose range is 1×10 13 ion / cm 2 Up to 1×10 14 ion / cm 2 .

[0150] Subsequently, a base contact layer is formed on the base layer 206 ; and an emitter contact layer is formed on the exposed surface of the emitter layer 208 .

[0151] In this embodiment, after forming the base contact layer, the emitter contact layer is formed. For details, please refer to Figures 25 to 32 .

[0152] Please refer to Figure 25 to Figure 28 , Fig.25 for Figure 26 to Figure 28 The schematic diagram of the top view of the first protective layer is omitted. Fig.26 yes Fig.25 Schematic diagram of the cross-sectional structure along the MM1 direction, Fig. 27 yes Fig.25 Schematic diagram of the cross-sectional structure along the NN1 direction, Fig.28 yes Fig.25 In the schematic diagram of the cross-sectional structure along the FF1 direction, a first protective layer 210 is formed on the emitter layer 208, the base layer 206 and the collector contact layer 204, and the first protective layer 210 has a first groove (not shown in the figure), and the first groove exposes a portion of the second barrier layer (not shown in the figure); the base contact layer is formed in the first groove.

[0153] In this embodiment, the method for forming the first protective layer 210 includes: forming a first protective material layer on the emitter layer 208, the base layer 206 and the collector contact layer 204; forming a patterned first photoresist layer (not shown in the figure) on the surface of the first protective material layer; and etching the first protective material layer using the first photoresist layer as a mask.

[0154] The material of the first protective layer 210 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbon nitride. In this embodiment, the material of the first protective layer 210 is silicon nitride.

[0155] In this embodiment, the process for forming the base contact layer includes an evaporation process.

[0156] The base contact layer includes a multi-layer metal structure, which includes: a first metal layer, a second metal layer, a third metal layer and a fourth metal layer stacked in sequence in a direction perpendicular to the surface of the substrate 20 .

[0157] In this embodiment, the material of the first metal layer includes platinum, the material of the second metal layer includes titanium, the material of the third metal layer includes platinum, and the material of the fourth metal layer includes copper or gold.

[0158] The base contact layer includes a plurality of first contact strips 302 . The first contact strips 302 extend along the first direction X. The first contact strips 302 are located between the collector layers 205 adjacent to each other in the second direction Y.

[0159] The method for forming the base contact layer includes: forming a first contact strip 302 on the surface of the electrical contact region S1 , wherein the first contact strip 302 extends along the first direction X, and the first contact strip 302 connects the electrical contact regions adjacent to each other in the first direction X.

[0160] In another embodiment, the first isolation regions located in the second direction Y are connected to each other and extend along the second direction Y, and the first contact strip crosses the first isolation regions.

[0161] In this embodiment, the method for forming the base contact layer further includes: forming a plurality of second contact strips 301 connected to the plurality of first contact strips 302 on the surface of the first isolation region S2, the second contact strips 301 extending along the second direction Y, and the second contact strips 301 being located between two adjacent collector layers 205 in the first direction X.

[0162] Here, relative to only setting a plurality of first contact strips 302, a plurality of second contact strips 301 in the base contact layer are set between the collector layers 205 adjacent to each other in the first direction X, so as to disperse the base current, reduce the heat concentration effect caused by the current concentration, and improve the heat dissipation capacity. Moreover, the setting of the plurality of second contact strips 301 and the plurality of first contact strips 302 makes the distribution of the base contact layer more uniform, which is beneficial to reducing stress and preventing device deformation.

[0163] In this embodiment, the method for forming the base contact layer further includes: forming a base terminal 300 on one side of the collector layer 205 in the second direction Y, and connecting the second contact strips 301 to the base terminal 300. Specifically, the base terminal 300 is formed on the base lead-out region bc.

[0164] In another embodiment, the base terminal may not be formed. By omitting the base terminal, the base layer does not need to provide a placement position for the base terminal, which can effectively reduce the area of ​​the base layer, further reduce the area of ​​the PN junction formed between the base layer and the emitter layer, and further reduce the parasitic capacitance C between the emitter layer and the base layer. BE , thereby improving the RF gain and cutoff frequency of the device structure and improving the performance of the device structure. Since the base layer removes the portion that is provided for the base terminal and cannot contribute to current, the utilization efficiency of the device structure can be effectively improved.

[0165] In another embodiment, the electrical contact regions located in the first direction X are interconnected and extend along the first direction X, and the method for forming the base contact layer includes: forming a plurality of first contact strips and a base terminal, omitting the second contact strip, the first contact strip being located between the adjacent collector layers in the second direction Y and extending along the first direction X; the base terminal being located on one side of the plurality of collector layers in the first direction X.

[0166] In another embodiment, the base contact layer comprises only the first contact strip.

[0167] In this embodiment, the method for forming the base contact layer further includes: performing annealing treatment on the base contact layer so that the base contact layer is embedded in the second barrier layer, and the material of the base contact layer is diffused into the base layer 206 so that the base contact layer is in contact with the base layer 206. The annealing treatment is used to reduce the ohmic contact resistance between the base contact layer and the base layer 206.

[0168] After forming the first isolation structure 207 , the base contact layer is formed.

[0169] In this embodiment, the first isolation structure 207 is formed between two adjacent collector layers 205 in the first direction X; and the second contact strip 301 is located on the first isolation structure 207 .

[0170] In another embodiment, the electrical contact region is formed between two adjacent collector layers in the first direction, the isolation region is formed between two adjacent collector layers in the second direction, and the first isolation structure is formed between two adjacent collector layers in the second direction; the first contact strip is located on the surface of the first isolation structure.

[0171] Please refer to Figure 29 to Figure 32 , Fig.29 for Figure 30 to Figure 32 The schematic diagram of the top view of the first protective layer and the second protective layer is omitted. Fig.30 yes Fig.29 Schematic diagram of the cross-sectional structure along the MM1 direction, Fig.31 yes Fig.29 Schematic diagram of the cross-sectional structure along the NN1 direction, Fig.32 yes Fig.29 In the schematic diagram of the cross-sectional structure along the FF1 direction, a second protective layer 211 is formed on the surface of the first protective layer 210 and the base contact layer; a second groove (not shown in the figure) is formed in the first protective layer 210 and the second protective layer 211, and the second groove exposes part of the emitter layer 208; and the emitter contact layer 303 is formed in the second groove.

[0172] At this point, the emitter layer 208 is placed at the bottom layer to support the base layer 206 and the collector layer 205, so the area of ​​the emitter layer 208 is the largest. Under the requirement of a fixed emitter layer 208 area, the area of ​​the PN junction formed between the collector layer 205 and the base layer 206 is small, thereby reducing the parasitic capacitance (i.e., junction capacitance) C between the collector layer 205 and the base layer 206. BC At the same time, by providing a first isolation structure in the emitter layer 208 and the base layer 206, the PN junction area formed between the emitter layer 208 and the base layer 206 can be reduced, thereby reducing the parasitic capacitance C between the emitter layer and the base layer. BE , which is beneficial to improve the cutoff frequency and RF gain of the device.

[0173] In this embodiment, the method for forming the second protective layer 211 includes: forming a second protective material layer on the surface of the first protective layer 210 and the base contact layer; forming a patterned second photoresist layer (not shown in the figure) on the surface of the second protective material layer; and etching the second protective material layer using the second photoresist layer as a mask.

[0174] The material of the second protective layer 211 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbon nitride. In this embodiment, the material of the second protective layer 211 is silicon nitride.

[0175] The emitter contact layer 303 includes a stack of multiple metal layers, and the materials of two adjacent metal layers are different from each other; the material of the metal layer includes titanium or platinum. In this embodiment, the emitter contact layer 303 includes a stack of a titanium metal layer, a platinum metal layer, a titanium metal layer, a platinum metal layer and a titanium metal layer.

[0176] In this embodiment, the emitter contact layer 303 is formed on the two emitter extraction regions ec.

[0177] Subsequently, a base conductive structure and a collector conductive structure are formed, the base conductive structure and the base contact layer are electrically connected, the collector conductive structure and the collector contact layer are electrically connected, and the emitter conductive structure, the base conductive structure and the collector conductive structure are located on the first side.

[0178] In this embodiment, an emitter conductive structure is also formed, and the emitter conductive structure is electrically connected to the emitter contact layer.

[0179] In another embodiment, the emitter conductive structure may not be formed.

[0180] The materials of the base conductive structure, the collector conductive structure and the emitter conductive structure include one or more combinations of copper, aluminum, titanium, gold, platinum, tungsten, cobalt, nickel and tantalum. In this embodiment, the metal includes copper.

[0181] In this embodiment, the formation method of the base conductive structure, the collector conductive structure and the emitter conductive structure can be referred to in Figures 33 to 48 .

[0182] Please refer to Figure 33 to Figure 36 , Fig.33 for Figure 34 to Figure 36 The schematic diagram of the top view of the first protective layer, the second protective layer and the third protective layer is omitted. Fig.34 yes Fig.33 Schematic diagram of the cross-sectional structure along the MM1 direction, Fig.35 yes Fig.33 Schematic diagram of the cross-sectional structure along the NN1 direction, Fig.36 yes Fig.33 In the schematic diagram of the cross-sectional structure along the FF1 direction, a third protective layer 212 is formed on the second protective layer 211; a first opening 213 is formed in the third protective layer 212, the first opening 213 is located on the emitter lead-out region ec, and exposes the emitter contact layer 303; a second opening 214 is formed in the second protective layer 211 and the third protective layer 212, the second opening 214 exposes the base contact layer; a plurality of third openings 215 are formed in the first protective layer 210, the second protective layer 211 and the third protective layer 212, the third openings 215 expose the collector contact layer 204.

[0183] Specifically, the second opening 214 exposes the base terminal 300 .

[0184] In this embodiment, the method for forming the third protective layer 212 includes: forming a third protective material layer on the surface of the second protective layer 211 and the emitter contact layer; forming a patterned third photoresist layer (not shown in the figure) on the surface of the third protective material layer; and etching the third protective material layer using the third photoresist layer as a mask.

[0185] The material of the third protective layer 212 includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbon nitride. In this embodiment, the material of the third protective layer 212 is silicon nitride.

[0186] Please refer to Figures 37 to 40 , Fig.37 for Figures 38 to 40The schematic diagram of the top view of the first protective layer, the second protective layer and the third protective layer is omitted. Fig.38 yes Fig.37 Schematic diagram of the cross-sectional structure along the MM1 direction, Fig.39 yes Fig.37 Schematic diagram of the cross-sectional structure along the NN1 direction, Fig.40 yes Fig.37 Schematic diagram of the cross-sectional structure along the FF1 direction, the emitter conductive portion 304a is formed in the first opening 213, and the emitter conductive bus 304b is formed on the surface of the third protective layer 212, the emitter conductive structure includes the emitter conductive portion 304a and the emitter conductive bus 304b, the emitter conductive portion 304a is connected to the emitter conductive bus 304b, the emitter conductive portion 304a extends along the second direction Y, the emitter conductive bus 304b extends along the first direction X, a first base conductive layer 305a is formed in the second opening 214, and the base conductive structure includes the first base conductive layer 305a.

[0187] In this embodiment, the formation process of the emitter conductive structure and the first base conductive layer 305 a includes a lift-off process.

[0188] The emitter conductive structure is used to draw out the current in the emitter layer 208 .

[0189] In this embodiment, the emitter conductive bus 304 b and the base conductive structure are respectively located on two sides of the emitter layer 208 .

[0190] Please refer to Figure 41 to Figure 43 , Fig.41 The viewing direction is the same as Fig.38 , Fig.42 The viewing direction is the same as Fig.39 , Fig.43 The viewing direction is the same as Fig.40 A packaging material layer 216 is formed on the surface of the first base conductive layer 305a, the emitter conductive structure and the third protective layer 212, and the packaging material layer 216 exposes the surface of the first base conductive layer 305a and exposes a plurality of the third openings 215.

[0191] The material of the packaging material layer 216 includes a polymer material. In this embodiment, the material of the packaging material layer 216 is polyimide.

[0192] Please refer to Figures 44 to 47 , Fig.44 for Figure 45 to Figure 47 The schematic diagram of the top view of the structure of the first protective layer, the second protective layer, the third protective layer and the packaging material layer is omitted. Fig.45 yes Fig.44 Schematic diagram of the cross-sectional structure along the MM1 direction, Fig.46 yes Fig.44 Schematic diagram of the cross-sectional structure along the NN1 direction, Fig.47 yes Fig.44 Schematic diagram of the cross-sectional structure along the FF1 direction, a second base conductive layer 305b is formed on the exposed surface of the first base conductive layer 305a, the base conductive structure also includes the second base conductive layer 305b, a collector conductive portion 306a is formed on the surface of the packaging material layer 216 in the plurality of the third openings 215 and between the adjacent third openings 215, a collector conductive bus 306b is formed on the surface of part of the packaging material layer 216, the collector conductive structure includes the plurality of the collector conductive portions 306a and the collector conductive bus 306b, the plurality of the collector conductive portions 306a are arranged along the first direction X and extend along the second direction Y, the collector conductive bus 306b extends along the first direction X and is connected to the plurality of the collector conductive portions 306a.

[0193] In this embodiment, the second base conductive layer 305 b also extends to a portion of the surface of the packaging material layer 216 .

[0194] In this embodiment, the formation process of the second base conductive layer 305 b and the collector conductive structure includes a lift-off process.

[0195] In this embodiment, the base conductive structure includes a first base conductive layer 305 a and a second base conductive layer 305 b located on the surface of the first base conductive layer 305 a .

[0196] In this embodiment, the collector conductive bus 306 b and the base conductive structure are located on two opposite sides of the emitter layer 208 in the second direction Y, respectively.

[0197] In another embodiment, the base contact layer includes a plurality of first contact strips and a plurality of second contact strips, the base terminal is omitted, the base conductive structure is located on the surface of the plurality of second contact strips, and the base conductive structure is located between two adjacent collector layers in the first direction.

[0198] In another embodiment, the base contact layer includes only a plurality of first contact strips, a plurality of collector conductive portions extend along the first direction and are arranged along the second direction, the collector conductive bus extends along the second direction, the base conductive structure is located on the surfaces of the plurality of first contact strips, and the base conductive structure is located between two adjacent collector layers in the second direction.

[0199] In another embodiment, the base contact layer includes a plurality of first contact strips and a base terminal, the second contact strip is omitted, a plurality of collector conductive portions extend along the first direction and are arranged along the second direction, the collector conductive bus extends along the second direction, the base terminal is located on one side of the plurality of collector layers in the first direction X, the base conductive structure is located on the surface of the base terminal, and the base conductive structure and the collector conductive bus are respectively located on opposite sides of the emitter layer in the first direction X.

[0200] In this embodiment, the collector conductive bus 306b has a first projection on the surface of the substrate 20, and the emitter conductive bus 304b has a second projection on the surface of the substrate 20, and the first projection and the second projection do not overlap each other.

[0201] In this embodiment, please Fig.45 Based on this, continue to refer to Fig.48 After forming the second base conductive layer 305 b and the collector conductive structure, a fourth protective layer 307 is formed on the surfaces of the second base conductive layer 305 b , the collector conductive structure and the packaging material layer 216 .

[0202] The material of the fourth protective layer 307 includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbon nitride. In this embodiment, the material of the fourth protective layer 307 is silicon nitride.

[0203] Accordingly, the embodiment of the present invention also provides a heterojunction bipolar transistor device formed by the above method, please continue to refer to Fig.10 , Figures 44 to 48 The heterojunction bipolar transistor device includes: a substrate 30; a heterojunction bipolar transistor device, bonded to the surface of the substrate 30, the heterojunction bipolar transistor device 21 includes an emitter layer 208, a base layer 206, a plurality of collector layers 205, and a first isolation structure 207 located in the emitter layer 208 and the base layer 206, the emitter layer 208 has a first side (not shown in the figure) and a second side (not shown in the figure) opposite to each other, the base layer 206, the collector layer 205 and the substrate 30 are located on the first side, and the base layer 206 is located between the collector layer 205 and the emitter layer 208.

[0204] At this point, in each heterojunction bipolar transistor device, the emitter layer 208 is placed at the bottom layer to carry the base layer 206 and the collector layer 205, so the area of ​​the emitter layer 208 is the largest. Under the requirement of a fixed emitter layer 208 area, the area of ​​the PN junction formed between the collector layer 205 and the base layer 206 is small, thereby reducing the parasitic capacitance (i.e., junction capacitance) C between the collector layer 205 and the base layer 206. BC At the same time, by providing a first isolation structure in the emitter layer 208 and the base layer 206, the PN junction area formed between the emitter layer 208 and the base layer 206 can be reduced, thereby reducing the parasitic capacitance C between the emitter layer 208 and the base layer 206. BE , which is beneficial to improving the cutoff frequency and RF gain of the device. In addition, the heterojunction bipolar transistor device is bonded to the surface of a substrate (such as a silicon substrate), and a substrate material with higher heat dissipation performance can be selected to improve the heat dissipation capacity of the heterojunction bipolar transistor device.

[0205] In this embodiment, the material of the substrate 30 includes silicon or silicon carbide.

[0206] In this embodiment, the heterojunction bipolar transistor device 21 further includes: a plurality of functional devices 23 located on the surface of the substrate 30 , wherein the plurality of functional devices 23 are located between adjacent heterojunction bipolar transistor devices; and the functional devices 23 include silicon-based devices.

[0207] Here, the substrate 30 can be used to integrate with low-noise amplifiers, switches, filters and other devices, thereby improving the integration of radio frequency devices and reducing the size of radio frequency devices.

[0208] In this embodiment, the heterojunction bipolar transistor device 21 further includes: a second isolation structure 209 located on the side wall of the emitter layer 208 .

[0209] In this embodiment, the heterojunction bipolar transistor device 21 further includes: a base contact layer, and the base contact layer and the plurality of collector layers 205 are located on the same side of the base layer 206 and are separate from each other.

[0210] In this embodiment, the base layer 206 includes a plurality of collector regions (not shown in the figure), a plurality of electrical contact regions S1 (such as Fig.17 As shown) and a plurality of first isolation regions S2 (as Fig.17 As shown), several collector regions are arranged along a first direction X, the collector layer 205 is located in the collector region, the base contact layer is located in the electrical contact region S1, and the first isolation structure 207 is located in the first isolation region S2.

[0211] In this embodiment, the heterojunction bipolar transistor device 21 further includes: a collector contact layer 204 located on the surface of each collector layer 205 .

[0212] In another embodiment, the heterojunction bipolar transistor device may not include the collector contact layer.

[0213] In this embodiment, the heterojunction bipolar transistor device 21 further includes: an emitter contact layer 303 located on a partial surface of the emitter layer 208 , and the emitter contact layer 303 and the base layer 206 are separate from each other.

[0214] In another embodiment, the heterojunction bipolar transistor device may not include the emitter contact layer 303 .

[0215] In this embodiment, a plurality of collector layers 205 are arranged along a first direction X and extend along a second direction Y. The first direction X and the second direction Y are perpendicular to each other.

[0216] In this embodiment, the base contact layer includes a plurality of first contact strips 302, which are located on the surface of the electrical contact region S1 and extend along the first direction X. The first contact strips 302 connect the adjacent electrical contact regions S1 in the first direction X, and the first contact strips 302 are located between the adjacent collector layers 205 in the second direction Y.

[0217] In this embodiment, a plurality of the collector regions are further arranged along the second direction Y.

[0218] Specifically, the plurality of collector layers 205 are arranged along the second direction Y. Under the requirement of a fixed emitter layer area, the total area of ​​the collector layer 205 is reduced, and the parasitic capacitance (ie, junction capacitance) C between the collector layer and the base layer is further reduced. BC。

[0219] In another embodiment, a plurality of the collector layers are arranged along the first direction and extend along the second direction, but are not arranged along the second direction.

[0220] In this embodiment, the electrical contact region S1 is located between the collector regions adjacent to each other in the second direction Y, and the first isolation region S2 is located between the collector regions adjacent to each other in the first direction X.

[0221] In this embodiment, the electrical contact regions S1 located in the first direction X are interconnected and extend along the first direction X.

[0222] In another embodiment, the first isolation regions located in the second direction are connected to each other and extend along the second direction.

[0223] In this embodiment, the base contact layer also includes: a plurality of second contact strips 301 connected to the plurality of first contact strips 302, the second contact strips 301 are located on the surface of the first isolation region S2 and extend along the second direction Y, and the second contact strips 301 are located between two adjacent collector layers 205 in the first direction X.

[0224] Here, several of the second contact strips 301 in the base contact layer are arranged between the collector layers 205 adjacent to each other in the first direction X, so as to disperse the base current, reduce the heat concentration effect caused by the current concentration, and improve the heat dissipation capacity. Moreover, the arrangement of several of the second contact strips 301 and several of the first contact strips 302 makes the distribution of the base contact layer more uniform, which is beneficial to reduce stress and prevent device deformation.

[0225] In this embodiment, the heterojunction bipolar transistor device 21 also includes: a second barrier layer (not shown in the figure) located on the surface of the base layer 206, a plurality of collector layers 205 located on part of the surface of the second barrier layer, the material of the second barrier layer is different from the material of the base layer 206, and the conductivity type of the second barrier layer is different from the conductivity type of the base layer 206; the base contact layer is embedded in the second barrier layer and in contact with the base layer 206.

[0226] In this embodiment, the heterojunction bipolar transistor device 21 further includes: a second passivation layer 24 located on the second side of the emitter layer 208 .

[0227] In this embodiment, the heterojunction bipolar transistor device 21 further includes: a base conductive structure and a collector conductive structure, the base conductive structure is electrically connected to the base contact layer, the collector conductive structure is electrically connected to the collector layer, and the base conductive structure and the collector conductive structure are located on the first side. Specifically, the collector conductive structure is electrically connected to the collector contact layer.

[0228] In this embodiment, the base conductive structure includes: a first base conductive layer 305 a located on the base contact layer and a second base conductive layer 305 b located on the first base conductive layer 305 a .

[0229] Specifically, the first base conductive layer 305 a is located on the base terminal 300 .

[0230] In this embodiment, the collector conductive structure includes: a plurality of collector conductive parts 306a and a collector conductive bus 306b, the plurality of collector conductive parts 306a are connected to the plurality of collector contact layers 204, the plurality of collector conductive parts 306a are arranged along the first direction X and extend along the second direction Y, and the collector conductive bus 306b extends along the first direction X and is connected to the plurality of collector conductive parts 306a.

[0231] In this embodiment, the collector conductive bus 306 b and the base conductive structure are respectively located on two sides of the emitter layer 208 .

[0232] In this embodiment, the heterojunction bipolar transistor device 21 further includes: an emitter conductive structure, and the emitter conductive structure is electrically connected to the emitter layer 208. Specifically, the emitter conductive structure is electrically connected to the emitter contact layer 303.

[0233] In this embodiment, the emitter conductive structure includes: an emitter conductive portion 304a and an emitter conductive bus 304b connected to the emitter conductive portion 304a, the emitter conductive portion 304a extends along the second direction Y, and the emitter conductive bus 304b extends along the first direction X; the emitter conductive bus 304b and the base conductive structure are respectively located on both sides of the emitter layer 208, and the emitter conductive portion 304a is located on the surface of the emitter contact layer 303.

[0234] In this embodiment, the material of the base conductive structure, the collector conductive structure and the emitter conductive structure comprises metal, and the metal comprises a combination of one or more of copper, aluminum, titanium, gold, platinum, tungsten, cobalt, nickel and tantalum. In this embodiment, the metal comprises copper.

[0235] In this embodiment, the heterojunction bipolar transistor device 21 further includes: a first conductive plug (not shown in the figure) penetrating the substrate 30, the first conductive plug being electrically connected to the base conductive structure; and a second conductive plug (not shown in the figure) penetrating the substrate 30, the second conductive plug being electrically connected to the collector conductive structure.

[0236] In this embodiment, the heterojunction bipolar transistor device 21 further includes: a third conductive plug (not shown in the figure) penetrating the substrate 30, and the third conductive plug is electrically connected to the emitter conductive structure. The first conductive plug, the second conductive plug and the third conductive plug are used for electrical connection between the heterojunction bipolar transistor device 21 and the outside world.

[0237] In another embodiment, only the first conductive plug and the second conductive plug may be included without the third conductive plug, and the heterojunction bipolar transistor device further includes: an emitter lead-out structure located in the second passivation layer, the emitter lead-out structure being electrically connected to the emitter layer. The first conductive plug, the second conductive plug and the emitter lead-out structure are used for electrical connection between the heterojunction bipolar transistor device 21 and the outside world.

[0238] Figures 49 to 51 It is a structural schematic diagram of each step of a method for forming a semiconductor device according to another embodiment of the present invention.

[0239] This embodiment is based on the previous embodiment ( Fig.16 ) continues to describe the method for forming a semiconductor device, and the rest is the same as the previous embodiment. Fig.17 The main difference between the first isolation region and the electrical contact region is that the distribution of the first isolation region and the electrical contact region is different. The following will be described in detail with reference to the accompanying drawings.

[0240] Please refer to Fig.49 , Fig.49 The collector contact layer 204 is omitted, and the base material layer 202 (such as Fig.13 As shown), until the emitter material layer 201 is exposed, a base layer 406 is formed, the base layer 406 includes a plurality of collector regions (not shown in the figure), a plurality of electrical contact regions n1 and a plurality of first isolation regions n2, the plurality of collector regions are arranged along a first direction X, and the collector layer 205 is formed on the collector regions.

[0241] In this embodiment, the electrical contact region n1 is located between the adjacent collector regions in the second direction Y and is arranged along the first direction X; a plurality of first isolation regions n2 are located between the adjacent collector regions in the first direction X, and the first isolation regions n2 located in the second direction Y are interconnected and extend along the second direction Y.

[0242] In another embodiment, the electrical contact region is located between the adjacent collector regions in the second direction, and the electrical contact regions located in the first direction are interconnected and extend along the first direction; the first isolation region is located between the adjacent collector regions in the first direction and is arranged along the second direction.

[0243] In this embodiment, the first isolation region n2 is adjacent to the electrical contact region n1.

[0244] Please refer to Fig.50, through an ion implantation process, ions are implanted into the base layer 406 located in the first isolation region n2 and the emitter material layer 201 located below the first isolation region n2, that is, ions are implanted into the emitter material layer 201 and the base layer 406 between two adjacent collector layers 205 in the first direction X to form a first isolation structure 407 in the emitter material layer 201 and the base layer 406, and an emitter layer 408 is formed with the emitter material layer 201 into which ions are not implanted.

[0245] In this embodiment, the ions are further implanted into the emitter material layer 201 on the second isolation region I to form a second isolation structure 409 with the emitter material layer 201 on the second isolation region I.

[0246] Please refer to Fig.51 The base contact layer is formed on the surface of the electrical contact region n1, and the base contact layer includes a first contact strip 602, which extends along the first direction X. The first contact strip 602 connects the adjacent electrical contact regions n1 in the first direction X, and the first contact strip 602 is located between the adjacent collector layers 205 in the second direction Y.

[0247] In this embodiment, the first contact strip 602 crosses the first isolation region n2.

[0248] Here, relative to the previous embodiment, by increasing the size of the first isolation region n2 along the second direction Y, thereby increasing the area of ​​the first isolation region n2 (first isolation structure), the area of ​​the PN junction formed between the emitter layer 408 and the base layer 406 is further reduced, so as to further reduce the parasitic capacitance C between the emitter layer 408 and the base layer 406. BE , improving the cutoff frequency and RF gain of the device.

[0249] In this embodiment, the method for forming the base contact layer also includes: forming a plurality of second contact strips 601 connected to the first contact strips 602, wherein the second contact strips 601 are located in the first isolation region n2 and extend along the second direction Y, and the second contact strips 601 are located between two adjacent collector layers 205 in the first direction X.

[0250] In this embodiment, the method for forming the base contact layer further includes: forming a base terminal 600 on one side of a plurality of the collector layers 205 in the second direction Y, and a plurality of the second contact strips 601 are connected to the base terminal 600 .

[0251] Specifically, a base terminal 600 is formed on the base lead-out region bc.

[0252] Subsequently, the method for forming the semiconductor device may refer to the method in the previous embodiment. Figures 33 to 48 And related narratives will not be repeated here.

[0253] Accordingly, the embodiment of the present invention further provides a semiconductor device formed by the above method, please continue to refer to Fig.51 , I will not go into details here.

[0254] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; A heterojunction bipolar transistor device is bonded to the surface of the substrate, the heterojunction bipolar transistor device includes an emitter layer, a base layer, a plurality of collector layers, and a first isolation structure located within the emitter layer and the base layer, the emitter layer having a first side and a second side opposite to each other, the base layer, the collector layer and the substrate are located on the first side, and the base layer is located between the collector layer and the emitter layer.

2. The semiconductor device according to claim 1, wherein The material of the substrate includes silicon or silicon carbide.

3. The semiconductor device according to claim 1, wherein Also includes: A plurality of functional devices are located on the surface of the substrate, and the plurality of functional devices are located between adjacent heterojunction bipolar transistor devices; the functional devices include silicon-based devices.

4. The semiconductor device according to claim 1, wherein The heterojunction bipolar transistor device also includes: a base contact layer, the base contact layer and the plurality of collector layers are located on the same side of the base layer and are separate from each other; the base layer includes a plurality of collector regions, a plurality of electrical contact regions and a plurality of first isolation regions, the plurality of collector regions are arranged along a first direction, the collector layer is located in the collector region, the base contact layer is located in the electrical contact region, and the first isolation structure is located in the first isolation region.

5. The semiconductor device according to claim 4, wherein: The plurality of collector regions are also arranged along a second direction, and the first direction and the second direction are perpendicular to each other.

6. The semiconductor device according to claim 5, characterized in that The electrical contact region is located between the collector regions adjacent to each other in the second direction, and the first isolation region is located between the collector regions adjacent to each other in the first direction.

7. The semiconductor device according to claim 6, wherein: The electrical contact regions located in the first direction are connected to each other and extend along the first direction.

8. The semiconductor device according to claim 6, wherein: The first isolation regions located in the second direction are connected to each other and extend along the second direction.

9. The semiconductor device according to claim 6, wherein: The base contact layer includes a plurality of first contact strips, wherein the first contact strips are located on the surface of the electrical contact region and extend along the first direction, and the first contact strips are located between the collector layers adjacent to each other in the second direction.

10. The semiconductor device according to claim 9, wherein: The base contact layer further includes: a plurality of second contact strips connected to the plurality of first contact strips, the second contact strips are located on the surface of the first isolation region and extend along the second direction, and the second contact strips are located between two adjacent collector layers in the first direction.

11. The semiconductor device according to claim 4, wherein The heterojunction bipolar transistor device further includes: a base conductive structure and a collector conductive structure, the base conductive structure is electrically connected to the base contact layer, the collector conductive structure is electrically connected to the collector layer, and the base conductive structure and the collector conductive structure are located on the first side.

12. The semiconductor device according to claim 11, wherein Also includes: A first conductive plug penetrating the substrate, the first conductive plug being electrically connected to the base conductive structure; A second conductive plug passes through the substrate, and the second conductive plug is electrically connected to the collector conductive structure.

13. The semiconductor device according to claim 11, wherein Also includes: An emitter conductive structure, wherein the emitter conductive structure is electrically connected to the emitter layer; A third conductive plug passes through the substrate, and the third conductive plug is electrically connected to the emitter conductive structure.

14. The semiconductor device according to claim 11, wherein: Also includes: a second passivation layer located on a second side of the emitter layer; An emitter lead-out structure is located in the second passivation layer, and the emitter lead-out structure is electrically connected to the emitter layer.

15. The semiconductor device according to claim 4, wherein: The heterojunction bipolar transistor device also includes: a second barrier layer located between the base layer and a plurality of collector layers, the material of the second barrier layer being different from the material of the base layer, and the conductivity type of the second barrier layer being different from the conductivity type of the base layer; the base contact layer being embedded in the second barrier layer and in contact with the base layer.

16. A method for forming a semiconductor device, characterized in that: include: providing a substrate, the substrate comprising a first side and a second side opposite to each other; Forming a plurality of heterojunction bipolar transistor devices on the first surface of the substrate, the substrate and the plurality of heterojunction bipolar transistor devices constitute an initial device structure, each of the heterojunction bipolar transistor devices comprises an emitter layer, a base layer, a plurality of collector layers, and a first isolation structure located in the emitter layer and the base layer, the emitter layer has a first side and a second side opposite to each other, the base layer and the collector layer are located on the first side, the base layer is located between the collector layer and the emitter layer, and the substrate is located on the second side; providing a substrate, wherein the material of the substrate is different from the material of the backing; With the first side of the emission layer facing the substrate, the initial device structure and the substrate are bonded to each other using a bonding process; After the bonding process, the substrate is removed.

17. The method for forming a semiconductor device according to claim 16, wherein: The initial device structure includes a plurality of first regions and a plurality of second regions, wherein the second regions are located between adjacent first regions, and the heterojunction bipolar transistor device is located within the first regions; the method further includes: after removing the substrate, etching a portion of the initial device structure located in the second regions to expose a portion of the substrate surface; forming a plurality of functional devices on the exposed substrate surface; the functional devices include silicon-based devices.

18. The method for forming a semiconductor device according to claim 16, wherein: The method for forming the heterojunction bipolar transistor device includes: forming an emitter material layer on the first surface of the substrate; forming a base material layer on the emitter material layer; forming a collector material layer on the base material layer; etching the collector material layer to form a plurality of collector layers; etching the base material layer until the emitter material layer is exposed to form the base layer; and injecting ions into the emitter material layer and the base layer through an ion implantation process to form the first isolation structure in the emitter material layer and the base layer, and forming the emitter layer with the portion of the emitter material layer into which ions are not implanted.

19. The method for forming a semiconductor device according to claim 18, wherein: The method for forming the heterojunction bipolar transistor device further includes: using the ion implantation process to implant ions into the emitter material layer, and simultaneously forming a second isolation structure in the emitter material layer while forming the first isolation structure, wherein the second isolation structure surrounds the emitter layer.

20. The method for forming a semiconductor device according to claim 18 or 19, characterized in that: The process parameters of the ion implantation process include: the ions include one or more of boron ions, helium ions and hydrogen ions, and the implantation dose range is 1×10 13 ion / cm 2 Up to 1×10 14 ion / cm 2 .

21. The method for forming a semiconductor device according to claim 18, wherein: The method for forming the heterojunction bipolar transistor device also includes: forming a base contact layer on the base layer; the base layer includes a plurality of collector regions, a plurality of electrical contact regions and a plurality of first isolation regions, the plurality of collector regions are arranged along a first direction, the collector layer is located in the collector region, the base contact layer is located in the electrical contact region, and the first isolation structure is located in the first isolation region.

22. The method for forming a semiconductor device according to claim 21, wherein: The plurality of collector regions are also arranged along a second direction, and the first direction and the second direction are perpendicular to each other.

23. The method for forming a semiconductor device according to claim 22, wherein: The electrical contact region is located between the collector regions adjacent to each other in the second direction, and the first isolation region is located between the collector regions adjacent to each other in the first direction.

24. The method for forming a semiconductor device according to claim 23, wherein: The method for forming the base contact layer comprises: forming a plurality of first contact strips on the surface of the electrical contact region, wherein the first contact strips extend along the first direction and are located between the collector layers adjacent to each other in the second direction.

25. The method for forming a semiconductor device according to claim 24, wherein: The first contact strip crosses the first isolation region.

26. The method for forming a semiconductor device according to claim 24, wherein: The method for forming the base contact layer also includes: forming a plurality of second contact strips connected to the plurality of first contact strips on the surface of the first isolation region, the second contact strips extending along the second direction, and the second contact strips being located between two adjacent collector layers in the first direction.

27. The method for forming a semiconductor device according to claim 21, wherein: The method for forming the heterojunction bipolar transistor device includes: forming a base conductive structure and a collector conductive structure, wherein the base conductive structure is electrically connected to the base contact layer, the collector conductive structure is electrically connected to the collector layer, and the base conductive structure and the collector conductive structure are located on the first side.

28. The method for forming a semiconductor device according to claim 27, wherein: Also includes: forming a first conductive plug penetrating the substrate, wherein the first conductive plug is electrically connected to the base conductive structure; A second conductive plug is formed penetrating the substrate, wherein the second conductive plug is electrically connected to the collector conductive structure.

29. The method for forming a semiconductor device according to claim 27, wherein: Also includes: An emitter conductive structure is formed, and the emitter conductive structure is electrically connected to the emitter layer; and a third conductive plug is formed penetrating the substrate, and the third conductive plug is electrically connected to the emitter conductive structure.

30. The method for forming a semiconductor device according to claim 27, wherein: Also includes: A second passivation layer is formed on a second side of the emitter layer; and an emitter lead-out structure is formed in the second passivation layer so that the emitter lead-out structure is electrically connected to the emitter layer.

31. The method for forming a semiconductor device according to claim 16, wherein: After forming the plurality of heterojunction bipolar transistor devices and before the bonding process, the method further includes: forming a first dielectric layer on the plurality of heterojunction bipolar transistor devices; and bonding the first dielectric layer and the substrate to each other.

32. The method for forming a semiconductor device according to claim 16, wherein: Before forming a number of heterojunction bipolar transistor devices, a first barrier layer is formed on the first surface, the material of the first barrier layer is different from the material of the emitter layer; after removing the substrate, the first barrier layer is also removed; the material of the first barrier layer includes indium gallium phosphide.

Images