Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a method for manufacturing the semiconductor device, which can reduce variation of breakdown tolerance under the condition of large current flow and improve reliability. A semiconductor device in which a transistor is formed on a semiconductor substrate having a first main surface and a second main surface, wherein a transistor region of the semiconductor substrate has: an n-type first semiconductor layer; a p-type second semiconductor layer provided closer to the first main surface side than the first semiconductor layer; an n-type third semiconductor layer provided closer to the first main surface side than the second semiconductor layer; a trench gate penetrating the third semiconductor layer and the second semiconductor layer from the first main surface in the thickness direction and reaching the inside of the first semiconductor layer; and an interlayer insulating film provided on the trench gate, the interlayer insulating film having at least one narrow portion in which the length in the width direction intersecting the extending direction of the trench gate in plan view is locally narrowed.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and in particular to a semiconductor device having a trench gate. Background Art

[0002] In Patent Document 1, as an example of a switching device having a trench gate, Figure 1 , discloses an insulated gate bipolar transistor (IGBT) in which an emitter layer connected to an emitter electrode is formed in a stripe shape in a direction intersecting with the extending direction of a trench gate.

[0003] An interlayer insulating film is formed on the upper portion of the trench gate, and a plurality of contact regions are formed between adjacent trench gates along the extending direction of the trench gate.

[0004] The length, ie, the width, of the interlayer insulating film in the left-right direction is formed to be larger in the portion where the emitter layer is provided than in the portion where the emitter layer is not provided. The interlayer insulating film has a plan view shape in which projections and depressions are repeatedly formed left and right along the trench gate.

[0005] Patent Document 1: Japanese Patent Application Publication No. 2008-91491

[0006] As described above, conventional techniques employ a structure in which the width of the interlayer insulating film at the portion where the emitter layer is provided is increased to narrow the contact portion between the emitter electrode and the emitter layer, thereby suppressing the current even when a large current flows, such as when a short circuit occurs, to improve reliability.

[0007] In such a conventional semiconductor device, since the contact portion between the emitter electrode and the emitter layer is narrowed, the current path when the IGBT is on is also narrowed, which causes a problem that the loss of the transistor increases due to the increase in on-resistance. Summary of the invention

[0008] The present disclosure is completed to solve the above-mentioned problems, and its purpose is to provide a semiconductor device with improved reliability by not narrowing the current path when the IGBT is turned on, reducing the deviation of the gate insulation breakdown resistance, the reverse bias safe operating area (RBSOA) and the breakdown resistance under conditions such as the flow of large current such as short-circuit testing.

[0009] The semiconductor device disclosed herein is a semiconductor device in which a transistor is formed on a semiconductor substrate having a first main surface and a second main surface, wherein the semiconductor substrate has a transistor region in which the transistor is formed, and the transistor region has: a first main electrode electrically connected to the first main surface; a second main electrode electrically connected to the second main surface; a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type disposed at a position closer to the first main surface than the first semiconductor layer; and a third semiconductor layer of a first conductivity type disposed at a position closer to the first main surface than the first semiconductor layer. 2 semiconductor layers are located near the first main surface and are electrically connected to the first main electrode; a trench gate penetrates the third semiconductor layer and the second semiconductor layer from the first main surface in the thickness direction and reaches the first semiconductor layer; and an interlayer insulating film is arranged on the trench gate, the interlayer insulating film has at least one narrow width portion whose length in the width direction intersecting the extension direction of the trench gate when viewed from above is locally narrowed, and the length in the width direction of the narrow width portion is longer than the length in the width direction of the trench gate.

[0010] According to the semiconductor device involved in the present disclosure, it is possible to provide a semiconductor device with improved reliability by reducing the variation in breakdown withstand capacity under conditions such as large current flowing without narrowing the current path when the transistor is turned on due to the interlayer insulating film having at least one narrow width portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a top view showing a semiconductor device as an RC-IGBT.

[0012] Figure 2 It is a top view showing a semiconductor device as an RC-IGBT.

[0013] Figure 3 This is a partial top view of the IGBT region in the RC-IGBT.

[0014] Figure 4 This is a partial cross-sectional view of the IGBT region in the RC-IGBT.

[0015] Figure 5 This is a partial cross-sectional view of the IGBT region in the RC-IGBT.

[0016] Figure 6 This is a partial top view of the diode region in the RC-IGBT.

[0017] Figure 7 This is a partial cross-sectional view of the diode region in the RC-IGBT.

[0018] Figure 8 This is a partial cross-sectional view of the diode region in the RC-IGBT.

[0019] Fig. 9 This is a cross-sectional view of the boundary portion between the IGBT region and the diode region of the RC-IGBT.

[0020] Fig.10 This is a cross-sectional view of the boundary portion between the IGBT region and the terminal region of the RC-IGBT.

[0021] Fig.11 This is a cross-sectional view of the boundary portion between the IGBT region and the terminal region of the RC-IGBT.

[0022] Fig.12 This is a cross-sectional view for explaining a method for manufacturing the RC-IGBT.

[0023] Fig.13 This is a cross-sectional view for explaining a method for manufacturing the RC-IGBT.

[0024] Fig.14 This is a cross-sectional view for explaining a method for manufacturing the RC-IGBT.

[0025] Fig.15 This is a cross-sectional view for explaining a method for manufacturing the RC-IGBT.

[0026] Fig.16 This is a cross-sectional view for explaining a method for manufacturing the RC-IGBT.

[0027] Fig.17 This is a cross-sectional view for explaining a method for manufacturing the RC-IGBT.

[0028] Fig.18 This is a cross-sectional view for explaining a method for manufacturing the RC-IGBT.

[0029] Fig.19 This is a cross-sectional view for explaining a method for manufacturing the RC-IGBT.

[0030] Fig. 20 This is a cross-sectional view for explaining a method for manufacturing the RC-IGBT.

[0031] Fig.21 This is a cross-sectional view for explaining a method for manufacturing the RC-IGBT.

[0032] Fig. 22 This is a cross-sectional view for explaining a method for manufacturing the RC-IGBT.

[0033] Fig.23 It is a partial plan view showing the structure of the RC-IGBT according to the first embodiment.

[0034] Fig.24It is an overall plan view showing the structure of the RC-IGBT according to the second embodiment.

[0035] Fig.25 It is a cross-sectional view showing the structure of the RC-IGBT according to the second embodiment.

[0036] Fig.26 It is a cross-sectional view showing the structure of the RC-IGBT according to the second embodiment.

[0037] Fig. 27 It is a diagram showing the structure of the RC-IGBT according to the second embodiment.

[0038] Fig.28 It is a cross-sectional view showing a manufacturing process of the RC-IGBT according to the second embodiment.

[0039] Fig.29 It is a cross-sectional view showing a manufacturing process of the RC-IGBT according to the second embodiment.

[0040] Fig.30 It is a cross-sectional view showing a manufacturing process of the RC-IGBT according to the second embodiment.

[0041] Fig.31 It is a cross-sectional view showing a manufacturing process of the RC-IGBT according to the second embodiment.

[0042] Fig.32 It is a cross-sectional view showing a manufacturing process of the RC-IGBT according to the second embodiment.

[0043] Fig.33 It is a cross-sectional view showing a manufacturing process of the RC-IGBT according to the second embodiment.

[0044] Fig.34 It is a cross-sectional view showing a manufacturing process of the RC-IGBT according to the second embodiment.

[0045] Fig.35 It is a cross-sectional view showing a manufacturing process of the RC-IGBT according to the second embodiment.

[0046] Fig.36 It is a partial plan view showing the structure of the RC-IGBT according to the third embodiment.

[0047] Fig.37 This is an enlarged view of a narrow width portion of the RC-IGBT according to the third embodiment.

[0048] Fig.38 It is a cross-sectional view of a narrow width portion of the RC-IGBT according to the third embodiment.

[0049] Fig.39 It is a partial plan view showing the structure of the RC-IGBT according to the fourth embodiment.

[0050] Fig.40 This is a flowchart for explaining the method for manufacturing the RC-IGBT according to the fifth embodiment.

[0051] Fig.41 A diagram for explaining a method for manufacturing the RC-IGBT according to the fifth embodiment.

[0052] Fig.42 A diagram for explaining a method for manufacturing the RC-IGBT according to the fifth embodiment.

[0053] Fig.43 A diagram for explaining a method for manufacturing the RC-IGBT according to the fifth embodiment.

[0054] Fig.44 A diagram for explaining a method for manufacturing the RC-IGBT according to the fifth embodiment.

[0055] Fig.45 A diagram for explaining a method for manufacturing the RC-IGBT according to the fifth embodiment.

[0056] Fig.46 This is a flowchart for explaining another method for manufacturing the RC-IGBT according to the fifth embodiment.

[0057] Fig.47 The figure shows an exposure pattern when the resist material is a positive type.

[0058] Fig.48 The diagram shows a pattern of a resist mask obtained by exposing a positive resist material.

[0059] Fig.49 It is a cross-sectional view showing another method of manufacturing the step portion.

[0060] Fig.50 It is a cross-sectional view showing another method of manufacturing the step portion.

[0061] Fig.51 It is a cross-sectional view showing another method of manufacturing the step portion.

[0062] Description of Reference Numerals

[0063] 1…n — drift layer; 4…interlayer insulating film; 6…emitter electrode; 7…collector electrode; 10…IGBT region; 11…active trench gate; 13…n + Type source layer; 14…p +type contact layer; 15…p-type base layer; 20…diode region; 30…terminal region; 35…narrow width portion; 37…step difference portion; 40a, 40b…cross-direction interlayer insulating film. DETAILED DESCRIPTION

[0064] <First>

[0065] In the following description, n-type and p-type refer to the conductivity type of the semiconductor. In the present disclosure, the first conductivity type is described as n-type and the second conductivity type is described as p-type. However, the first conductivity type may be described as p-type and the second conductivity type as n-type. — The impurity concentration of the n-type is lower than that of the n-type. + The n-type indicates that the impurity concentration is higher than that of the n-type. — The impurity concentration of the p-type is lower than that of the p-type. + The MOSFET type indicates that the impurity concentration is higher than that of the p-type.

[0066] In addition, the drawings are schematically shown, and the mutual relationship between the size and position of the images shown in different drawings is not necessarily accurately described, and can be appropriately changed. In addition, in the following description, the same components are marked with the same reference numerals for illustration, and their names and functions are also the same. Therefore, there is a case where the detailed description about them is omitted.

[0067] In addition, in the following description, there are cases where terms such as "up", "down", "side", "front" and "back" are used to indicate specific positions and directions, but these terms are used to facilitate understanding of the contents of the implementation method and have nothing to do with the directions during actual implementation.

[0068] Hereinafter, before describing the embodiment, a reverse conducting IGBT (RC-IGBT: Reverse Conducting IGBT) provided on a semiconductor substrate shared by an IGBT and a freewheeling diode (FWD: Free Wheeling Diode) will be described.

[0069] Figure 1 1 is a top view showing a semiconductor device as an RC-IGBT. Figure 2 It is a top view showing a semiconductor device of an RC-IGBT as another structure. Figure 1 The semiconductor device 100 shown in the figure has the IGBT region 10 and the diode region 20 arranged in a stripe shape, and can be simply referred to as a “stripe type”. Figure 2The semiconductor device 101 shown has a plurality of diode regions 20 arranged in the vertical and horizontal directions and an IGBT region 10 arranged around the diode region 20 , and can be simply referred to as an “island type”.

[0070] (1) Stripe-type overall plane structure

[0071] exist Figure 1 In the embodiment, the semiconductor device 100 includes an IGBT region 10 and a diode region 20 in one semiconductor device. The IGBT region 10 and the diode region 20 extend from one end of the semiconductor device 100 to the other end, and are alternately arranged in stripes in a direction orthogonal to the extending direction of the IGBT region 10 and the diode region 20. Figure 1 In the figure, three IGBT regions 10 and two diode regions are shown, and all diode regions 20 are shown as a structure sandwiched by the IGBT regions 10. However, the number of IGBT regions 10 and diode regions 20 is not limited to this. The number of IGBT regions 10 can be more than three or less than three, and the number of diode regions 20 can be more than two or less than two. In addition, Figure 1 The IGBT region 10 and the diode region 20 may be replaced in the structure, or all the IGBT regions 10 may be sandwiched by the diode regions 20. In addition, the IGBT region 10 and the diode region 20 may be provided adjacent to each other one by one.

[0072] like Figure 1 As shown, a pad region 40 is provided adjacent to the IGBT region 10 on the lower side of the paper. The pad region 40 is a region where a control pad 410 for controlling the semiconductor device 100 is provided. The IGBT region 10 and the diode region 20 are collectively referred to as a cell region. A termination region 30 is provided around the region where the cell region and the pad region 40 are combined in order to maintain the withstand voltage of the semiconductor device 100. In the termination region 30, a known withstand voltage maintenance structure can be appropriately selected and provided. For example, the withstand voltage maintenance structure can be configured such that an FLR (Field Limiting Ring) that surrounds the cell region with a p-type termination well layer of a p-type semiconductor and a VLD (Variation of Lateral Doping) that surrounds the cell region with a p-type well layer having a concentration gradient are provided on the first main surface side, which is the front side of the semiconductor device 100. The number of annular p-type termination well layers used for the FLR and the concentration distribution used for the VLD can be appropriately selected according to the withstand voltage design of the semiconductor device 100. Alternatively, a p-type termination well layer may be provided over almost the entire pad region 40 , or an IGBT cell and a diode cell may be provided in the pad region 40 .

[0073] The control pad 410 may be, for example, a current sensing pad 410a, a Kelvin emitter pad 410b, a gate pad 410c, and temperature sensing diode pads 410d and 410e. The current sensing pad 410a is a control pad for detecting a current flowing to the cell region of the semiconductor device 100, and is electrically connected to an IGBT cell or a diode cell that is part of the cell region so that when a current flows to the cell region of the semiconductor device 100, a current of a fraction to tens of thousands of the current flowing to the entire cell region flows.

[0074] The Kelvin emitter pad 410b and the gate pad 410c are control pads to which a gate drive voltage is applied for on / off control of the semiconductor device 100. The Kelvin emitter pad 410b is electrically connected to the p-type base layer of the IGBT unit, and the gate pad 410c is electrically connected to the gate trench electrode of the IGBT unit. The Kelvin emitter pad 410b and the p-type base layer can be connected via the p + The temperature sensing diode pads 410d and 410e are control pads electrically connected to the anode and cathode of the temperature sensing diode provided in the semiconductor device 100. The temperature of the semiconductor device 100 is measured by measuring the voltage between the anode and cathode of the temperature sensing diode (not shown) provided in the cell region.

[0075] (2) Island-type overall plane structure

[0076] exist Figure 2 In the embodiment, the semiconductor device 101 includes an IGBT region 10 and a diode region 20 in one semiconductor device. A plurality of diode regions 20 are arranged in the longitudinal direction and the lateral direction in the semiconductor device, and the diode regions 20 are surrounded by the IGBT region 10. That is, a plurality of diode regions 20 are arranged in an island shape in the IGBT region 10. Figure 2 In the figure, the diode regions 20 are arranged in a matrix structure with 4 columns in the left-right direction of the paper and 2 rows in the up-down direction of the paper, but the number and configuration of the diode regions 20 are not limited to this. It is sufficient as long as one or more diode regions 20 are dispersedly arranged in the IGBT region 10 and each diode region 20 is surrounded by the IGBT region 10.

[0077] like Figure 2As shown, a pad region 40 is provided adjacent to the lower side of the IGBT region 10. The pad region 40 is a region where a control pad 410 for controlling the semiconductor device 101 is provided. The IGBT region 10 and the diode region 20 are collectively referred to as a cell region. A termination region 30 is provided around the region where the cell region and the pad region 40 are combined for the purpose of maintaining the withstand voltage of the semiconductor device 101. A known withstand voltage maintaining structure can be appropriately selected and provided in the termination region 30. For example, the withstand voltage maintaining structure can be configured such that an FLR (Field Limiting Ring) is provided on the first main surface side, which is the front side of the semiconductor device 101, where a p-type termination well layer of a p-type semiconductor surrounds the region where the cell region and the pad region 40 are combined, and a VLD (Variation of Lateral Doping) is provided where a p-type well layer with a concentration gradient surrounds the cell region. The number of annular p-type termination well layers used for the FLR and the concentration distribution used for the VLD can be appropriately selected according to the withstand voltage design of the semiconductor device 101. Alternatively, a p-type termination well layer may be provided over almost the entire pad region 40 , or an IGBT cell and a diode cell may be provided in the pad region 40 .

[0078] The control pad 410 may be, for example, a current sensing pad 410a, a Kelvin emitter pad 410b, a gate pad 410c, and temperature sensing diode pads 410d and 410e. The current sensing pad 410a is a control pad for detecting a current flowing to the cell region of the semiconductor device 101, and is a control pad electrically connected to an IGBT cell or a diode cell that is part of the cell region so that when a current flows to the cell region of the semiconductor device 101, a current of a fraction to tens of thousands of the current flowing to the entire cell region flows.

[0079] The Kelvin emitter pad 410b and the gate pad 410c are control pads to which a gate drive voltage for on / off control of the semiconductor device 101 is applied. The Kelvin emitter pad 410b is connected to the p-type base layer and n-type base layer of the IGBT cell. + The Kelvin emitter pad 410b and the p-type base layer can also be electrically connected via the p + The temperature sensing diode pads 410d and 410e are control pads electrically connected to the anode and cathode of the temperature sensing diode provided in the semiconductor device 101. The temperature of the semiconductor device 101 is measured by measuring the voltage between the anode and cathode of the temperature sensing diode (not shown) provided in the cell region.

[0080] (3) General Structure of IGBT Region 10

[0081] Figure 3 1 is a partially enlarged top view showing the structure of the IGBT region of the semiconductor device as an RC-IGBT. Figure 4 and Figure 5 It is a cross-sectional view showing the structure of an IGBT region of a semiconductor device which is an RC-IGBT. Figure 3 Zoom in to show Figure 1 The semiconductor device 100 or Figure 2 A region 82 surrounded by a dotted line in the semiconductor device 101 is shown. Figure 4 yes Figure 3 The semiconductor device 100 or Figure 2 The semiconductor device 101 is shown in a cross-sectional view in the direction of the arrows along the dashed line AA. Figure 5 yes Figure 3 The semiconductor device 100 or the semiconductor device 101 is shown in a cross-sectional view taken along the dashed line BB.

[0082] like Figure 3 As shown, in the IGBT region 10, the active trench gate 11 and the dummy trench gate 12 are provided in a stripe shape. In the semiconductor device 100, the active trench gate 11 and the dummy trench gate 12 extend in the long side direction of the IGBT region 10, and the long side direction of the IGBT region 10 becomes the long side direction of the active trench gate 11 and the dummy trench gate 12. On the other hand, in the semiconductor device 101, there is no particular distinction between the long side direction and the short side direction in the IGBT region 10, but the left-right direction of the paper can be used as the long side direction of the active trench gate 11 and the dummy trench gate 12, and the up-down direction of the paper can also be used as the long side direction of the active trench gate 11 and the dummy trench gate 12.

[0083] The active trench gate 11 is formed by providing a gate trench electrode 11a in a trench formed in a semiconductor substrate with the aid of a gate trench insulating film 11b. The dummy trench gate 12 is formed by providing a dummy trench electrode 12a in a trench formed in a semiconductor substrate with the aid of a dummy trench insulating film 12b. The gate trench electrode 11a of the active trench gate 11 is electrically connected to the gate pad 410c. The dummy trench electrode 12a of the dummy trench gate 12 is electrically connected to an emitter electrode provided on the first main surface of the semiconductor device 100 or the semiconductor device 101.

[0084] n + The type source layer 13 is provided on both sides of the active trench gate 11 in the width direction so as to be in contact with the gate trench insulating film 11b. + The source layer 13 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity. The concentration of the n-type impurity is 1.0×10 17 / cm 3~1.0×10 20 / cm 3 .n + The type source layer 13 is connected to the p-type source layer 13 along the extension direction of the active trench gate 11. + The type contact layers 14 are arranged alternately. + The type contact layer 14 is also disposed between two adjacent dummy trench gates 12. + The p-type contact layer 14 is a semiconductor layer containing boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0×10 15 / cm 3 ~1.0×10 20 / cm 3 .

[0085] like Figure 3 As shown, the following structure is formed in the IGBT region 10 of the semiconductor device 100 or the semiconductor device 101: three dummy trench gates 12 are arranged next to the three active trench gates 11, and three active trench gates 11 are arranged next to the three dummy trench gates 12. The IGBT region 10 has a structure in which groups of active trench gates 11 and groups of dummy trench gates 12 are alternately arranged. Figure 3 In the embodiment, the number of active trench gates 11 included in one group of active trench gates 11 is set to 3, but it only needs to be 1 or more. In addition, the number of dummy trench gates 12 included in one group of dummy trench gates 12 may be 1 or more, or the number of dummy trench gates 12 may be 0. That is, all trenches provided in the IGBT region 10 may be set to active trench gates 11.

[0086] Figure 4 The semiconductor device 100 or the semiconductor device 101 Figure 3 The cross-sectional view along the dashed line AA in FIG. 1 is a cross-sectional view of the IGBT region 10. The semiconductor device 100 or the semiconductor device 101 includes a second semiconductor layer formed of a semiconductor substrate. — Type drift layer 1. n — The drift layer 1 is a semiconductor layer containing arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0×10 12 / cm 3 ~1.0×10 15 / cm 3 .exist Figure 4 In the semiconductor substrate, + Type source layer 13 and p + The range from the p-type contact layer 14 to the p-type collector layer 16. Figure 4 In the + Type source layer 13 and p+ The upper end of the p-type contact layer 14 on the paper is called the first main surface of the semiconductor substrate, and the lower end of the p-type collector layer 16 on the paper is called the second main surface of the semiconductor substrate. The first main surface of the semiconductor substrate is the main surface on the front side of the semiconductor device 100, and the second main surface of the semiconductor substrate is the main surface on the back side of the semiconductor device 100. The semiconductor device 100 has an n-type contact layer 14 on the paper upper end and a p-type collector layer 16 on the paper lower end. The p-type contact layer 14 on the paper upper end is called the first main surface of the semiconductor substrate, and the p-type collector layer 16 on the paper lower end is called the second main surface of the semiconductor substrate. The first main surface of the semiconductor substrate is the main surface on the front side of the semiconductor device 100, and the second main surface of the semiconductor substrate is the main surface on the back side of the semiconductor device 100. The semiconductor device 100 has an n-type contact layer 14 on the paper upper end and a p-type collector layer 16 on the paper lower end. — Type drift layer 1.

[0087] like Figure 4 As shown, in the IGBT region 10, at n — The first main surface side of the type drift layer 1 is provided with n-type impurities having a concentration higher than n — The n-type carrier storage layer 2 is an n-type drift layer 1. The n-type carrier storage layer 2 is a semiconductor layer containing arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0×10 13 / cm 3 ~1.0×10 17 / cm 3 In addition, the semiconductor device 100 or the semiconductor device 101 may be configured without providing the n-type carrier storage layer 2. Figure 4 The region of the n-type carrier storage layer 2 shown is also provided with n — By providing the n-type carrier storage layer 2, the conduction loss when the current flows to the IGBT region 10 can be reduced. — The type drift layer 1 is collectively referred to as the drift layer.

[0088] The n-type carrier storage layer 2 is formed by — The semiconductor substrate of the type drift layer 1 is ion-implanted with n-type impurities, and then annealed to make the implanted n-type impurities move to the n-type drift layer 1. — The type drift layer 1 is formed by diffusion in the semiconductor substrate.

[0089] A p-type base layer 15 is provided on the first main surface side of the n-type carrier storage layer 2. The p-type base layer 15 is a semiconductor layer containing boron or aluminum as a p-type impurity, for example, and the concentration of the p-type impurity is 1.0×10 12 / cm 3 ~1.0×10 19 / cm 3 The p-type base layer 15 is in contact with the gate trench insulating film 11 b of the active trench gate 11 . On the first main surface side of the p-type base layer 15 , an n-type base layer 15 is provided in contact with the gate trench insulating film 11 b of the active trench gate 11 . + type source layer 13, and a p + Type contact layer 14.+ Type source layer 13 and p + The p-type contact layer 14 constitutes the first main surface of the semiconductor substrate. + The p-type contact layer 14 is a region where the concentration of p-type impurities is higher than that of the p-type base layer 15. + In the case of the p-type contact layer 14 and the p-type base layer 15, each may be referred to independently, or the p + The p-type contact layer 14 and the p-type base layer 15 are collectively referred to as a p-type base layer.

[0090] In addition, the semiconductor device 100 or the semiconductor device 101 is — The second main surface side of the type drift layer 1 is provided with n-type impurity having a concentration higher than n — The n-type buffer layer 3 is provided to suppress the penetration of the depletion layer extending from the p-type base layer 15 to the second main surface when the semiconductor device 100 is in the off state. The n-type buffer layer 3 may be implanted with phosphorus (P) or protons (H + ) can also be formed by injecting phosphorus (P) and protons (H + ) on both sides. The concentration of n-type impurities in the n-type buffer layer 3 is 1.0×10 12 / cm 3 ~1.0×10 18 / cm 3 .

[0091] Alternatively, the semiconductor device 100 or the semiconductor device 101 may be configured without providing the n-type buffer layer 3. Figure 4 The region of the n-type buffer layer 3 shown is also provided with n — The structure of the n-type drift layer 1 can also be formed by forming the n-type buffer layer 3 and the n-type — The type drift layer 1 is collectively referred to as the drift layer.

[0092] The semiconductor device 100 or the semiconductor device 101 includes a p-type collector layer 16 disposed on the second main surface side of the n-type buffer layer 3. — A p-type collector layer 16 is provided between the drift layer 1 and the second main surface. The p-type collector layer 16 is a semiconductor layer containing boron or aluminum as a p-type impurity, for example. The concentration of the p-type impurity is 1.0×10 16 / cm 3 ~1.0×10 20 / cm 3The p-type collector layer 16 constitutes the second main surface of the semiconductor substrate. The p-type collector layer 16 is provided not only in the IGBT region 10 but also in the terminal region 30, and the portion of the p-type collector layer 16 provided in the terminal region 30 constitutes a p-type terminal collector layer 16a. In addition, the p-type collector layer 16 may be provided so that a portion thereof extends from the IGBT region 10 toward the diode region 20.

[0093] like Figure 4 As shown, the semiconductor device 100 or the semiconductor device 101 has a first main surface of the semiconductor substrate that penetrates the p-type base layer 15 and reaches the n-type base layer 15. — The active trench gate 11 is formed by providing a gate trench electrode 11a in the trench via a gate trench insulating film 11b. The gate trench electrode 11a is connected to the n-type drift layer 1 via the gate trench insulating film 11b. — The dummy trench electrode 12a is disposed in the trench via the dummy trench insulating film 12b, thereby forming the dummy trench gate 12. The dummy trench electrode 12a is disposed between the dummy trench insulating film 12b and the n type drift layer 1. — The gate trench insulating film 11b of the active trench gate 11 is opposite to the p-type base layer 15 and the n-type drift layer 1. + When a gate driving voltage is applied to the gate trench electrode 11 a , a channel is formed in the p-type base layer 15 in contact with the gate trench insulating film 11 b of the active trench gate 11 .

[0094] like Figure 4 As shown in FIG. 1 , an interlayer insulating film 4 is provided on the gate trench electrode 11a of the active trench gate 11. A barrier metal 5 is formed on a region of the first main surface of the semiconductor substrate where the interlayer insulating film 4 is not provided and on the interlayer insulating film 4. The barrier metal 5 may be, for example, a conductor containing titanium (Ti), such as titanium nitride, or TiSi alloyed with titanium and silicon (Si). Figure 4 As shown, the barrier metal 5 and n + Type source layer 13, p + The type contact layer 14 and the dummy trench electrode 12a are in ohmic contact with the n + Type source layer 13, p +The type contact layer 14 and the dummy trench electrode 12a are electrically connected. An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 can be formed of an aluminum alloy such as an aluminum silicon alloy (Al-Si alloy), or can be an electrode composed of a multilayer metal film on which a plating film is formed by electroless plating or electroplating on an electrode formed of an aluminum alloy. The plating film formed by electroless plating or electroplating can be, for example, a nickel (Ni) plating film. In addition, when there is a tiny area such as between adjacent interlayer insulating films 4 and it is an area where good embedding cannot be obtained by the emitter electrode 6, tungsten with better embedding properties than the emitter electrode 6 can be arranged in a tiny area and the emitter electrode 6 can be provided on the tungsten. In addition, it is also possible not to provide a barrier metal 5 and to form a n + Type source layer 13, p + The emitter electrode 6 is provided on the n-type contact layer 14 and the dummy trench electrode 12a. + A barrier metal 5 is provided on an n-type semiconductor layer such as an n-type source layer 13. The barrier metal 5 and the emitter electrode 6 may be collectively referred to as an emitter electrode. Figure 4 , the interlayer insulating film 4 is not provided on the dummy trench electrode 12a of the dummy trench gate 12, but the interlayer insulating film 4 may be formed on the dummy trench electrode 12a of the dummy trench gate 12. When the interlayer insulating film 4 is formed on the dummy trench electrode 12a of the dummy trench gate 12, it is sufficient to electrically connect the emitter electrode 6 and the dummy trench electrode 12a in other cross sections.

[0095] A collector electrode 7 is provided on the second main surface side of the p-type collector layer 16. The collector electrode 7 may be made of an aluminum alloy or an aluminum alloy and a plated film, similarly to the emitter electrode 6. In addition, the collector electrode 7 may be made of a different structure from the emitter electrode 6. The collector electrode 7 is in ohmic contact with the p-type collector layer 16 and is electrically connected to the p-type collector layer 16.

[0096] Figure 5 The semiconductor device 100 or the semiconductor device 101 Figure 3 The cross-sectional view in the direction of the arrow at the dotted line BB in FIG. 1 is a cross-sectional view of the IGBT region 10. Figure 5 The n-type gate electrode 11 is not visible in the cross section along the arrow direction of the dashed line BB. + Type source layer 13, this point is Figure 4 The cross-sectional view in the direction of the arrow at the dashed line AA shown is different. Figure 3 As shown, n + The p-type source layer 13 is selectively provided on the first main surface side of the p-type base layer. The p-type base layer referred to here refers to the p-type base layer 15 and the p-type +The p-type contact layer 14 is collectively referred to as a p-type base layer.

[0097] (4) General Structure of the Diode Region 20

[0098] Figure 6 1 is a partially enlarged top view showing the structure of the diode region of a semiconductor device as an RC-IGBT. Figure 7 and Figure 8 It is a cross-sectional view showing the structure of a diode region of a semiconductor device as an RC-IGBT. Figure 6 Zoom in to show Figure 1 A region 83 surrounded by a dotted line in the semiconductor device 100 or the semiconductor device 101 is shown. Figure 7 yes Figure 6 The semiconductor device 100 is shown in a cross-sectional view taken along a dashed line CC. Figure 8 yes Figure 6 The semiconductor device 100 is shown in a cross-sectional view taken along the dashed line DD.

[0099] The diode trench gate 21 extends from one end side of the diode region 20 as a unit region toward the other end side opposite thereto along the first main surface of the semiconductor device 100 or the semiconductor device 101. The diode trench gate 21 is formed by providing a diode trench electrode 21a in a trench formed in the semiconductor substrate of the diode region 20 via a diode trench insulating film 21b. The diode trench electrode 21a is sandwiched between the diode trench insulating film 21b and the n — A p-type drift layer 1 is disposed between two adjacent diode trench gates 21. + The p-type contact layer 24 and the p-type anode layer 25 as the third semiconductor layer. + The p-type contact layer 24 is a semiconductor layer containing boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0×10 15 / cm 3 ~1.0×10 20 / cm 3 The p-type anode layer 25 is a semiconductor layer containing boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0×10 12 / cm 3 ~1.0×10 19 / cm 3 . p + The p-type contact layers 24 and the p-type anode layers 25 are alternately provided in the longitudinal direction of the diode trench gate 21 .

[0100] Figure 7 The semiconductor device 100 or the semiconductor device 101 Figure 6The cross-sectional view along the dashed line CC in FIG. 1 is a cross-sectional view of the diode region 20. The semiconductor device 100 or the semiconductor device 101 also has an n-type semiconductor substrate in the diode region 20 similarly to the IGBT region 10. — Type drift layer 1. Diode region 20 n — The n-type drift layer 1 and the IGBT region 10 — The drift layer 1 is continuous and integrally formed and is composed of the same semiconductor substrate. Figure 7 In the semiconductor substrate, the + The n-type contact layer 24 is connected to the first semiconductor layer. + The range of the cathode layer 26. Figure 7 In the + The upper end of the paper surface of the type contact layer 24 is called the first main surface of the semiconductor substrate, and the n + The lower end of the cathode layer 26 is referred to as the second main surface of the semiconductor substrate. The first main surface of the diode region 20 is the same as the first main surface of the IGBT region 10 , and the second main surface of the diode region 20 is the same as the second main surface of the IGBT region 10 .

[0101] like Figure 7 As shown, in the diode region 20, similarly to the IGBT region 10, — An n-type carrier storage layer 2 is provided on the first main surface side of the n-type drift layer 1. — An n-type buffer layer 3 is provided on the second main surface side of the type drift layer 1. The n-type carrier accumulation layer 2 and the n-type buffer layer 3 provided in the diode region 20 have the same structure as the n-type carrier accumulation layer 2 and the n-type buffer layer 3 provided in the IGBT region 10. In addition, it is not necessary to provide the n-type carrier accumulation layer 2 in the IGBT region 10 and the diode region 20. Even if the n-type carrier accumulation layer 2 is provided in the IGBT region 10, the n-type carrier accumulation layer 2 may not be provided in the diode region 20. In addition, similarly to the IGBT region 10, the n-type carrier accumulation layer 2 may be provided in the diode region 20. — The n-type drift layer 1, the n-type carrier accumulation layer 2 and the n-type buffer layer 3 are collectively referred to as a drift layer.

[0102] A p-type anode layer 25 is provided on the first main surface side of the n-type carrier storage layer 2. The p-type anode layer 25 is provided on the n-type carrier storage layer 2. —The p-type drift layer 1 and the first main surface are provided between the p-type anode layer 25 and the p-type base layer 15 of the IGBT region 10. The p-type anode layer 25 and the p-type base layer 15 can be formed simultaneously by making the concentration of the p-type impurities in the p-type anode layer 25 the same as the concentration of the p-type impurities in the p-type base layer 15 of the IGBT region 10. In addition, the concentration of the p-type impurities in the p-type anode layer 25 can be made lower than the concentration of the p-type impurities in the p-type base layer 15 of the IGBT region 10 to reduce the amount of holes injected into the diode region 20 during the diode operation. By reducing the amount of holes injected during the diode operation, the recovery loss during the diode operation can be reduced.

[0103] On the first main surface side of the p-type anode layer 25, a p + Type contact layer 24. + The concentration of the p-type impurity in the p-type contact layer 24 may be equal to that of the p-type impurity in the IGBT region 10. + The p-type impurity in the p-type contact layer 14 may have the same concentration or different concentrations. + The p-type contact layer 24 constitutes the first main surface of the semiconductor substrate. + The p-type contact layer 24 is a region where the concentration of p-type impurities is higher than that of the p-type anode layer 25. + In the case of the p-type contact layer 24 and the p-type anode layer 25, each may be referred to independently, or the p + The p-type contact layer 24 and the p-type anode layer 25 are collectively referred to as a p-type anode layer.

[0104] In the diode region 20, an n-type buffer layer 3 is provided on the second main surface side. + Type cathode layer 26. + The type cathode layer 26 is provided on the n — Between the drift layer 1 and the second main surface. + The cathode layer 26 is a semiconductor layer containing arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0×10 16 / cm 3 ~1.0×10 21 / cm 3 .like Figure 2 As shown, n + The cathode layer 26 is provided on a part or the whole of the diode region 20. + The n-type cathode layer 26 constitutes the second main surface of the semiconductor substrate. In addition, although not shown in the figure, as described above, it is possible to form an n-type cathode layer 26 on the second main surface of the semiconductor substrate. + The region of the cathode layer 26 is also selectively implanted with p-type impurities to form an n-type cathode layer. + A portion of the region of the p-type cathode layer 26 is provided as a p-type semiconductor. + Thus, n type cathode layers are alternately arranged along the second main surface of the semiconductor substrate. +Type cathode layer and p + The cathode layer diode is also called RFC (Relaxed Field of Cathode) diode.

[0105] like Figure 7 As shown, in the diode region 20 of the semiconductor device 100 or the semiconductor device 101, a diode is formed which penetrates the p-type anode layer 25 from the first main surface of the semiconductor substrate and reaches the n-type anode layer 25. — The diode trench electrode 21a is provided in the trench of the diode region 20 via the diode trench insulating film 21b, thereby forming the diode trench gate 21. The diode trench electrode 21a is connected to the n-type drift layer 1 via the diode trench insulating film 21b. — type drift layer 1 is opposite.

[0106] like Figure 7 As shown, in the diode trench electrodes 21a and p + A barrier metal 5 is provided on the type contact layer 24. The barrier metal 5 is connected to the diode trench electrode 21a and the p + The type contact layer 24 is in ohmic contact with the diode trench electrode and p + The barrier metal 5 may be the same structure as the barrier metal 5 of the IGBT region 10. An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 provided in the diode region 20 is formed continuously with the emitter electrode 6 provided in the IGBT region 10. In addition, as in the case of the IGBT region 10, the diode trench electrode 21a and the diode trench electrode 21a may be provided without providing the barrier metal 5. + The type contact layer 24 is in ohmic contact with the emitter electrode 6. Figure 7 , the interlayer insulating film 4 is not provided on the diode trench electrode 21a of the diode trench gate 21, but the interlayer insulating film 4 may be formed on the diode trench electrode 21a of the diode trench gate 21. When the interlayer insulating film 4 is formed on the diode trench electrode 21a of the diode trench gate 21, it is sufficient to electrically connect the emitter electrode 6 and the diode trench electrode 21a in other cross sections.

[0107] In n + The collector electrode 7 is provided on the second main surface side of the n-type cathode layer 26. Similar to the emitter electrode 6, the collector electrode 7 of the diode region 20 is formed continuously with the collector electrode 7 provided in the IGBT region 10. + The cathode layer 26 is in ohmic contact with n + The cathode layer 26 is electrically connected to the cathode electrode and also functions as a cathode electrode.

[0108] Figure 8The semiconductor device 100 or the semiconductor device 101 Figure 6 The cross-sectional view in the direction of the arrow at the dashed line DD in FIG. 1 is a cross-sectional view in the direction of the arrow of the diode region 20. No p-type anode layer 25 is provided between the p-type anode layer 25 and the barrier metal 5. + The first main surface of the semiconductor substrate is formed by the p-type contact layer 24 and the p-type anode layer 25. Figure 7 The cross-sectional view in the direction of the arrow at the dashed line CC shown is different. That is, Figure 7 The p shown + The p-type contact layer 24 is selectively provided on the first main surface side of the p-type anode layer 25 .

[0109] (5) Boundary region between the IGBT region 10 and the diode region 20

[0110] Fig. 9 It is a cross-sectional view showing the structure of the boundary between the IGBT region and the diode region of the semiconductor device which is the RC-IGBT. Fig. 9 yes Figure 1 The semiconductor device 100 or the semiconductor device 101 is shown in a cross-sectional view taken along the dashed line GG.

[0111] like Fig. 9 As shown in FIG. 1 , the p-type collector layer 16 provided on the second main surface side of the IGBT region 10 is provided to extend from the boundary between the IGBT region 10 and the diode region 20 to the diode region 20 side by a distance U1. In this way, by providing the p-type collector layer 16 to extend toward the diode region 20, the n-type collector layer 16 of the diode region 20 can be made + The distance between the cathode layer 26 and the active trench gate 11 is increased, and even when a gate driving voltage is applied to the gate trench electrode 11a during the operation of the freewheeling diode, the current can be suppressed from flowing from the channel formed adjacent to the active trench gate 11 of the IGBT region 10 to the n-type cathode layer 26. + The type cathode layer 26 flows. The distance U1 may be, for example, 100 μm. In addition, depending on the application of the semiconductor device 100 or the semiconductor device 101 as an RC-IGBT, the distance U1 may be zero or a distance less than 100 μm.

[0112] (6) General Structure of Terminal Area 30

[0113] Fig.10 and Fig.11 It is a cross-sectional view showing the structure of a terminal region of a semiconductor device as an RC-IGBT. Fig.10 yes Figure 1 or Figure 2 The cross-sectional view in the direction of the arrow at the dotted line EE in FIG. 1 is a cross-sectional view from the IGBT region 10 to the terminal region 30. In addition, Fig.11 yes Figure 1 The cross-sectional view in the direction of the arrow at the dotted line FF in FIG. 1 is a cross-sectional view from the diode region 20 to the terminal region 30 .

[0114] like Fig.10 and Fig.11 As shown, the termination region 30 of the semiconductor device 100 has n between the first main surface and the second main surface of the semiconductor substrate. — The first main surface and the second main surface of the terminal region 30 are the same as the first main surface and the second main surface of the IGBT region 10 and the diode region 20, respectively. — The type drift layer 1 is respectively connected to the n-type drift layer of the IGBT region 10 and the diode region 20. — The drift layer 1 has the same structure and is continuously formed as a whole.

[0115] In n — The first main surface side of the type drift layer 1, that is, the first main surface of the semiconductor substrate and the n — A p-type termination well layer 31 is provided between the p-type drift layers 1. The p-type termination well layer 31 is a semiconductor layer having boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0×10 14 / cm 3 ~1.0×10 19 / cm 3 The p-type terminal well layer 31 is arranged around the cell region including the IGBT region 10 and the diode region 20. The p-type terminal well layer 31 is arranged in a plurality of rings, and the number of the p-type terminal well layers 31 is appropriately selected according to the withstand voltage design of the semiconductor device 100 or the semiconductor device 101. In addition, an n-type terminal well layer 31 is arranged on the outer edge side. + Type channel stop layer 32, n + The p-type channel stopper layer 32 surrounds the p-type termination well layer 31 .

[0116] In n — A p-type terminal collector layer 16a is provided between the type drift layer 1 and the second main surface of the semiconductor substrate. The p-type terminal collector layer 16a is continuously formed as one with the p-type collector layer 16 provided in the cell region. Therefore, the p-type terminal collector layer 16a may be included and referred to as the p-type collector layer 16. In addition, as Figure 1 As in the semiconductor device 100 shown in FIG. 1 , in a configuration in which the diode region 20 and the terminal region 30 are adjacently provided, as shown in FIG. Fig.11 As shown in FIG. 1 , the end of the p-type terminal collector layer 16a on the diode region 20 side is extended toward the diode region 20 by a distance U2. In this way, by extending the p-type terminal collector layer 16a toward the diode region 20, the n-type terminal collector layer 16a of the diode region 20 can be made +The distance between the p-type cathode layer 26 and the p-type termination well layer 31 is increased, and the p-type termination well layer 31 can be prevented from operating as the anode of the diode. The distance U2 may be, for example, 100 μm.

[0117] A collector electrode 7 is provided on the second main surface of the semiconductor substrate. The collector electrode 7 is formed integrally and continuously from the cell region including the IGBT region 10 and the diode region 20 to the terminal region 30. On the other hand, an emitter electrode 6 continuous from the cell region and a terminal electrode 6a separated from the emitter electrode 6 are provided on the first main surface of the semiconductor substrate in the terminal region 30.

[0118] The emitter electrode 6 and the terminal electrode 6a are electrically connected via a semi-insulating film 33. The semi-insulating film 33 may be, for example, sinSiN (semi-insulating Silicon Nitride). + The type channel stopper layer 32 is electrically connected via a contact hole formed in the interlayer insulating film 4 provided on the first main surface of the termination region 30. In addition, in the termination region 30, a termination protection film 34 is provided to cover the emitter electrode 6, the termination electrode 6a and the semi-insulating film 33. The termination protection film 34 can be formed of, for example, polyimide.

[0119] (7) General manufacturing method of RC-IGBT

[0120] Figure 12 to Figure 22 It is a diagram showing a method of manufacturing a semiconductor device as an RC-IGBT. Figures 12 to 19 1 is a diagram showing a process of forming the front side of the semiconductor device 100 or the semiconductor device 101. Figure 20 to Figure 22 The diagram shows a process of forming the back side of the semiconductor device 100 or the semiconductor device 101 .

[0121] First, if Fig.12 As shown, prepare to form n — The semiconductor substrate may be a so-called FZ wafer made by the FZ (Floating Zone) method or a so-called MCZ wafer made by the MCZ (Magneticfield applied Czochralski) method. The semiconductor substrate may be an n-type wafer containing n-type impurities. The concentration of n-type impurities contained in the semiconductor substrate is appropriately selected according to the withstand voltage of the semiconductor device to be manufactured. For example, in a semiconductor device with a withstand voltage of 1200V, the concentration of n-type impurities constituting the semiconductor substrate may be selected to be 100%. — The concentration of the n-type impurity is adjusted so that the relative resistance of the n-type drift layer 1 is about 40 to 120 Ω·cm. Fig.12As shown, in the process of preparing the semiconductor substrate, the entire semiconductor substrate becomes n — The semiconductor device 100 or the semiconductor device 101 is manufactured by injecting p-type or n-type impurity ions from the first main surface side or the second main surface side of such a semiconductor substrate and then diffusing them into the semiconductor substrate by heat treatment, thereby forming a p-type or n-type semiconductor layer.

[0122] like Fig.12 As shown, it constitutes n — The semiconductor substrate of the type drift layer 1 includes regions that become the IGBT region 10 and the diode region 20. In addition, although not shown in the figure, a region that becomes the termination region 30 is provided around the regions that become the IGBT region 10 and the diode region 20. Hereinafter, the manufacturing method of the configuration of the IGBT region 10 and the diode region 20 of the semiconductor device 100 or the semiconductor device 101 will be mainly described, but the termination region 30 of the semiconductor device 100 or the semiconductor device 101 can be manufactured by a known manufacturing method. For example, when an FLR having a p-type termination well layer 31 is formed in the termination region 30 as a withstand voltage holding structure, it can be formed by implanting p-type impurity ions before processing the IGBT region 10 and the diode region 20 of the semiconductor device 100 or the semiconductor device 101, or it can be formed by implanting p-type impurity ions simultaneously when ion implanting p-type impurities into the IGBT region 10 or the diode region 20 of the semiconductor device 100.

[0123] Next, if Fig.13 As shown, n-type impurities such as phosphorus (P) are injected from the first main surface side of the semiconductor substrate to form an n-type carrier accumulation layer 2. In addition, p-type impurities such as boron (B) are injected from the first main surface side of the semiconductor substrate to form a p-type base layer 15 and a p-type anode layer 25. The n-type carrier accumulation layer 2, the p-type base layer 15, and the p-type anode layer 25 are formed by diffusing the impurity ions by heat treatment after impurity ions are injected into the semiconductor substrate. Since the n-type impurities and the p-type impurities are ion-implanted after masking is performed on the first main surface of the semiconductor substrate, they are selectively formed on the first main surface side of the semiconductor substrate. The n-type carrier accumulation layer 2, the p-type base layer 15, and the p-type anode layer 25 are formed in the IGBT region 10 and the diode region 20, and are connected to the p-type terminal well layer 31 in the terminal region 30. Among them, mask processing refers to coating a resist on a semiconductor substrate, using photolithography technology to form an opening in a specified area of ​​the resist, and forming a mask on the semiconductor substrate in order to perform ion implantation and etching in a specified area of ​​the semiconductor substrate through the opening.

[0124] The p-type base layer 15 and the p-type anode layer 25 may be formed by ion implanting p-type impurities at the same time. In this case, the depth and p-type impurity concentration of the p-type base layer 15 and the p-type anode layer 25 become the same and have the same structure. In addition, by ion implanting p-type impurities into the p-type base layer 15 and the p-type anode layer 25 respectively through mask processing, the depth and p-type impurity concentration of the p-type base layer 15 and the p-type anode layer 25 can be made different.

[0125] In addition, the p-type terminal well layer 31 formed in other cross sections may be formed by ion implanting p-type impurities simultaneously with the p-type anode layer 25. In this case, the depth and p-type impurity concentration of the p-type terminal well layer 31 and the p-type anode layer 25 can be the same and have the same structure. In addition, the p-type terminal well layer 31 and the p-type anode layer 25 may be formed by ion implanting p-type impurities simultaneously, and the p-type impurity concentrations of the p-type terminal well layer 31 and the p-type anode layer 25 may be different. In this case, the aperture ratio may be changed by making one or both masks a mesh-shaped mask.

[0126] Alternatively, the depths and p-type impurity concentrations of the p-type terminal well layer 31 and the p-type anode layer 25 may be different by ion implanting p-type impurities into the p-type terminal well layer 31 and the p-type anode layer 25 using a mask process. The p-type terminal well layer 31, the p-type base layer 15, and the p-type anode layer 25 may be formed by ion implanting p-type impurities at the same time.

[0127] Next, if Fig.14 As shown, n-type impurities are selectively implanted into the first main surface side of the p-type base layer 15 of the IGBT region 10 by mask processing to form n + The n-type impurities injected may be, for example, arsenic (As) or phosphorus (P). In addition, by masking, p-type impurities are selectively injected into the first main surface side of the p-type base layer 15 of the IGBT region 10 to form a p-type source layer 13. The n-type impurities injected may be, for example, arsenic (As) or phosphorus (P). + The p-type contact layer 14 is formed by selectively implanting p-type impurities into the first main surface side of the p-type anode layer 25 of the diode region 20. + The p-type contact layer 24. The implanted p-type impurities may be, for example, boron (B) or aluminum (Al).

[0128] Next, if Fig.15 As shown, a first main surface side of the semiconductor substrate is formed to penetrate the p-type base layer 15 and the p-type anode layer 25 to reach the n — The trench 8 of the type drift layer 1. In the IGBT region 10, the n + The sidewalls of the trench 8 of the type source layer 13 constitute n + The SiO 2After the oxide film is deposited on the semiconductor substrate, an opening is formed in the oxide film at the portion where the groove 8 is to be formed by masking, and the semiconductor substrate is etched using the oxide film with the opening as a mask to form the groove 8. Fig.15 In the embodiment, the pitch of the trenches 8 is formed at the same level in the IGBT region 10 and the diode region 20, but the pitch of the trenches 8 may be different in the IGBT region 10 and the diode region 20. The pattern of the pitch of the trenches 8 in a plan view can be appropriately changed according to the mask pattern of the mask process.

[0129] Next, if Fig.16 As shown, the semiconductor substrate is heated in an atmosphere containing oxygen to form an oxide film 9 on the inner wall of the trench 8 and the first main surface of the semiconductor substrate. Among the oxide films 9 formed on the inner wall of the trench 8, the oxide films 9 formed in the trench 8 of the IGBT region 10 are the gate trench insulating film 11b of the active trench gate 11 and the dummy trench insulating film 12b of the dummy trench gate 12. In addition, the oxide film 9 formed in the trench 8 of the diode region 20 is the diode trench insulating film 21b. The oxide film 9 formed on the first main surface of the semiconductor substrate is removed in a subsequent process.

[0130] Next, if Fig.17 As shown, in the trench 8 having the oxide film 9 formed on the inner wall, polysilicon doped with n-type or p-type impurities is deposited by CVD (chemical vapor deposition) or the like to form the gate trench electrode 11a, the dummy trench electrode 12a and the diode trench electrode 21a.

[0131] Next, if Fig.18 As shown in FIG. 1 , after the interlayer insulating film 4 is formed on the gate trench electrode 11a of the active trench gate 11 of the IGBT region 10, the oxide film 9 formed on the first main surface of the semiconductor substrate is removed. The interlayer insulating film 4 may be, for example, SiO 2 Then, a contact hole is formed in the deposited interlayer insulating film 4 by masking. The contact hole is formed at n + On the source layer 13, p + On the p-type contact layer 14, + type contact layer 24, on the dummy trench electrode 12a and on the diode trench electrode 21a.

[0132] Next, if Fig.19 As shown, a barrier metal 5 is formed on the first main surface of the semiconductor substrate and the interlayer insulating film 4, and an emitter electrode 6 is formed on the barrier metal 5. The barrier metal 5 is formed by forming a titanium nitride film by PDV (physical vapor deposition) or CVD.

[0133] The emitter electrode 6 can be formed, for example, by depositing an aluminum silicon alloy (Al-Si alloy) on the barrier metal 5 by PVD such as sputtering or evaporation. In addition, a nickel alloy (Ni alloy) can be formed on the formed aluminum silicon alloy by electroless plating or electroplating as the emitter electrode 6. If the emitter electrode 6 is formed by plating, since a thick metal film can be easily formed as the emitter electrode 6, the heat capacity of the emitter electrode 6 can be increased to improve the heat resistance. In addition, when a nickel alloy is formed by plating after the emitter electrode 6 composed of the aluminum silicon alloy is formed by PVD, the plating process for forming the nickel alloy can also be implemented after the processing of the second main surface side of the semiconductor substrate is performed.

[0134] Next, if Fig. 20 As shown, the second main surface side of the semiconductor substrate is polished to thin the semiconductor substrate to a predetermined thickness as designed. The thickness of the semiconductor substrate after polishing can be, for example, 80 μm to 200 μm.

[0135] Next, if Fig.21 As shown, n-type impurities are injected from the second main surface side of the semiconductor substrate to form an n-type buffer layer 3. Furthermore, p-type impurities are injected from the second main surface side of the semiconductor substrate to form a p-type collector layer 16. The n-type buffer layer 3 may be formed in the IGBT region 10, the diode region 20, and the terminal region 30, or may be formed only in the IGBT region 10 or the diode region 20.

[0136] The n-type buffer layer 3 may be formed by implanting phosphorus (P) ions, for example. Alternatively, protons (H + ). Furthermore, it can be formed by injecting both protons and phosphorus. Protons can be injected into a deep position from the second main surface of the semiconductor substrate with a relatively low acceleration energy. In addition, by changing the acceleration energy, the depth of the injected protons can be changed relatively easily. Therefore, when the n-type buffer layer 3 is formed by using protons, if the acceleration energy is changed and the injection is performed multiple times, an n-type buffer layer 3 having a wider width in the thickness direction of the semiconductor substrate can be formed compared to when it is formed by using phosphorus.

[0137] In addition, since phosphorus can increase the activation rate as an n-type impurity compared to protons, by forming the n-type buffer layer 3 with phosphorus, even with a thinned semiconductor substrate, it is possible to more reliably suppress the depletion layer from punching through. In order to further thin the semiconductor substrate, it is preferred to form the n-type buffer layer 3 by injecting both protons and phosphorus, and in this case, the protons are injected deeper than the phosphorus from the second main surface.

[0138] The p-type collector layer 16 can be formed by, for example, implanting boron (B). The p-type collector layer 16 is also formed in the termination region 30, and the p-type collector layer 16 in the termination region 30 becomes the p-type termination collector layer 16a. After ion implantation from the second main surface side of the semiconductor substrate, laser annealing is performed by irradiating the second main surface with laser light, thereby activating the implanted boron and forming the p-type collector layer 16. At this time, phosphorus for the n-type buffer layer 3, which is implanted from the second main surface of the semiconductor substrate to a relatively shallow position, is also activated at the same time. On the other hand, since protons are activated at a relatively low annealing temperature such as 350°C to 500°C, it is necessary to be careful not to increase the temperature of the entire semiconductor substrate to a temperature higher than 350°C to 500°C except for the process for proton activation after proton implantation. Since laser annealing can make only the vicinity of the second main surface of the semiconductor substrate high temperature, it can be used for activation of n-type impurities and p-type impurities even after proton implantation.

[0139] Next, if Fig. 22 As shown, n is formed in the diode region 20. + Type cathode layer 26. + The cathode layer 26 can be formed by injecting phosphorus (P), for example. Fig. 22 As shown, the p-type collector layer 16 and the n + Phosphorus is selectively implanted from the second main surface side by masking so that the boundary of the n-type cathode layer 26 is located at a distance U1 from the boundary between the IGBT region 10 and the diode region 20 toward the diode region 20. + The amount of n-type impurities implanted into the p-type cathode layer 26 is greater than the amount of p-type impurities implanted into the p-type collector layer 16. Fig. 22 In the same manner, the p-type collector layer 16 and the n-type collector layer 16 are shown from the second main surface. + The depth of the cathode layer 26 is n + The depth of the p-type cathode layer 26 is greater than the depth of the p-type collector layer 16. + As for the region of the type cathode layer 26, since it is necessary to inject n-type impurities into the region where p-type impurities have been injected to form an n-type semiconductor, + The concentration of the p-type impurity implanted in the entire region of the cathode layer 26 is higher than the concentration of the n-type impurity.

[0140] Next, by forming a collector electrode 7 on the second main surface of the semiconductor substrate, a Fig. 9The cross-sectional structure shown. The collector electrode 7 is formed over the entire surface of the IGBT region 10, the diode region 20 and the terminal region 30 of the second main surface. In addition, the collector electrode 7 can be formed over the entire surface of the second main surface of the n-type wafer as the semiconductor substrate. The collector electrode 7 can be formed by depositing aluminum silicon alloy (Ai-Si alloy) or titanium (Ti) by PVD such as sputtering or evaporation, or by stacking multiple metals such as aluminum silicon alloy, titanium, nickel or gold. In addition, a metal film can be further formed on the metal film formed by PVD by electroless plating or electroplating to form the collector electrode 7.

[0141] Through the above steps, the semiconductor device 100 or the semiconductor device 101 is manufactured. Since a plurality of semiconductor devices 100 or semiconductor devices 101 are manufactured in a matrix form on one n-type wafer, the semiconductor device 100 or semiconductor device 101 is cut into individual semiconductor devices 100 or semiconductor devices 101 by laser dicing or blade dicing, thereby completing the semiconductor device 100 or semiconductor device 101.

[0142] <Implementation method 1>

[0143] Fig.23 is a partial top view showing the structure of the RC-IGBT 1000 according to the first embodiment. Figure 3 Therefore, the overall planar structure of RC-IGBT1000 is similar to Figure 1 The semiconductor device 100 or Figure 2 The semiconductor devices 101 shown are the same.

[0144] exist Fig.23 In the figure, it is shown Figure 3 The interlayer insulating film 4 on the active trench gate 11 is omitted in the figure. The interlayer insulating film 4 is provided on the first main surface of the semiconductor substrate and is provided so as to overlap with the active trench gate 11.

[0145] like Fig.23 As shown, in the RC-IGBT 1000, the width of the interlayer insulating film 4 on the active trench gate 11 is partially narrowed. Hereinafter, this structure is expressed as a narrow width portion 35. In the narrow width portion 35, in the Y direction that intersects with the X direction that is the extension direction of the active trench gate 11 when viewed from above, that is, the width direction, recesses CP are locally provided on both side surfaces of the interlayer insulating film 4. The width of the interlayer insulating film 4 in the portion where the recesses CP are provided is narrowed to the same degree as the width of the active trench gate 11. Therefore, if an emitter electrode 6 ( Figure 4), the width of the interlayer insulating film 4 in the narrow width portion 35 is compared with the portion having a normal width, and the distance between the gate trench electrode 11a and the emitter electrode 6 becomes shorter. This may cause concentration of the electric field and increase in leakage current.

[0146] Here, when an abnormality occurs, such as when the film thickness of the gate trench insulating film 11b is reduced during manufacturing, or when the interlayer insulating film 4 is shifted in the width direction of the active trench gate 11 due to mask shift during patterning of the interlayer insulating film 4, the distance between the gate trench electrode 11a and the emitter electrode 6 may be further shortened, and it may become a point that is easily broken when a voltage is applied between the gate and the emitter. If a voltage is applied between the gate and the emitter at such a point, the narrow width portion 35 is partially dielectrically broken, so that an effect equivalent to screening of the dielectric breakdown resistance of the gate, i.e., a screening effect, can be provided.

[0147] In addition, in the RC-IGBT 1000, although the narrow width portion 35 is provided in the interlayer insulating film 4, the width of the interlayer insulating film 4 other than the portion provided with the narrow width portion 35 is not wide, so the contact area with the emitter electrode 6 does not become narrow. Therefore, the current path in the on-state of the IGBT does not become narrow, the on-resistance does not increase, and the loss of the transistor does not increase.

[0148] In order to provide the narrow width portion 35 in the interlayer insulating film 4, as shown in FIG. Fig.18 As described above, when the contact hole is formed in the interlayer insulating film 4 by mask processing, it can be set by simultaneously patterning using the same mask, but it can also be set by forming only the recess CP using another mask after forming the contact hole. Preferably, the recess CP is sized to at least not reach the top of the gate trench electrode 11a.

[0149] Among them, Fig.23 , an example is shown in which a narrow portion 35 is provided at one location of the interlayer insulating film 4 on a gate trench electrode 11a, but the present invention is not limited thereto, and narrow portions 35 can be provided on the interlayer insulating film 4 on a plurality of gate trench electrodes 11a, and the number of narrow portions 35 is not limited.

[0150] It goes without saying that even when the narrow width portion 35 is provided, the product can function normally under normal use conditions and the product life can be ensured.

[0151] <Implementation method 2>

[0152] <Device Configuration>

[0153] Fig.24 is an overall plan view showing the configuration of the RC-IGBT2000 according to the second embodiment. Figure 1 The same as the semiconductor device 100 shown in FIG. Figure 2 The semiconductor device 101 shown has the same appearance and has no features in appearance.

[0154] The RC-IGBT 2000 according to the second embodiment is characterized in that a step portion is provided between the IGBT region 10 and the termination region 30 , and the interlayer insulating film on the upper portion of the step portion is recessed.

[0155] Fig.25 yes Fig.24 The cross-sectional view in the direction of the arrow at the dotted line EE in FIG. 1 is a cross-sectional view from the IGBT region 10 to the terminal region 30 , and is a cross-sectional view in a direction intersecting with the extending direction of the active trench gate 11 . Fig.26 yes Fig.24 The cross-sectional view in the direction of the arrow at the dotted line HH in FIG. 1 is a cross-sectional view from the IGBT region 10 to the terminal region 30 , and is a cross-sectional view in the extending direction of the active trench gate 11 .

[0156] Fig.25 and Fig.26 Basically Fig.10 and Fig.11 The cross-sectional view shown is the same, but a step portion 37 having a height of about 50 nm is formed where the first main surface of the semiconductor substrate on the termination region 30 side is retreated from the boundary between the IGBT region 10 and the termination region 30 toward the collector electrode 7 .

[0157] Since there is a step difference portion 37, Fig.26 As shown, the interlayer insulating film 4 is recessed above the step portion 37 .

[0158] Fig. 27 Yes means Fig.26 A partial cross-sectional view of a region 94 surrounded by a dotted line in FIG. 1 and a partial top view including a narrow width portion 35 . Fig. 27 The upper figure is a partial enlarged view, and the lower figure is a partial top view, which shows the structure from the bottom of the interlayer insulating film 4 for convenience. Fig. 27 As shown in the figure above, there is a step 37 of the semiconductor substrate at a position closer to the terminal region 30 than the boundary between the IGBT region 10 and the terminal region 30, that is, at a position corresponding to the end of the p-type terminal well layer 31 closest to the IGBT region 10, and the interlayer insulating film 4 above it is recessed. If the interlayer insulating film 4 is recessed, when the interlayer insulating film 4 is patterned on the active trench gate 11, the recessed portion is as shown in FIG. Fig. 27 As shown in the lower figure of , the narrow width portion 35 is formed. As a result, it is possible to provide a screening effect similar to the RC-IGBT 1000 of the first embodiment.

[0159] In addition, Fig. 27 , an active region 38 and an inactive region 39 in the termination region 30 are shown. The active region 38 is a region where the p-type termination well layer 31 is formed, and the inactive region 39 is a region from the boundary between the IGBT region 10 and the termination region 30 to the step portion 37 .

[0160] Here, in the active region 38, as Fig. 27 As shown in the upper figure, a gate wiring 42 is provided adjacent to the inactive region 39, and the gate wiring 42 is connected to the gate trench electrode 11a via a gate pull-up portion 43 penetrating the interlayer insulating film 4. Fig. 27 In the above figure, a structure in which the gate trench electrode 11 a is connected via the barrier metal 5 is disclosed, but the arrangement of the barrier metal 5 is arbitrary.

[0161] The gate wiring 42 and the gate pad 410c ( Fig.24 ) and is electrically connected to the emitter electrode 6. Fig. 27 As shown in the upper figure, a terminal protection film 34 is arranged between the gate wiring 42 and the emitter electrode 6 to insulate the gate wiring 42 from the emitter electrode 6 .

[0162] <Manufacturing method>

[0163] Next, using the cross-sectional view showing the manufacturing process in order, Figure 28 to Figure 35 , a method for manufacturing RC-IGBT2000 is described. Figure 28 to Figure 35 is with Fig.26 The cross-sectional view shown corresponds to FIG.

[0164] like Fig.28 As shown in FIG. 1 , a resist mask RM1 having an opening OP is formed in the region where the p-type terminal well layer 31 is to be formed, and p-type impurities are ion-implanted using the resist mask RM1 as an ion implantation mask to form the p-type terminal well layer 31. The p-type terminal well layer 31 is, for example, a semiconductor layer having boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0×10 14 / cm 3 ~1.0×10 19 / cm 3 .

[0165] Next, in Fig.29 In the process shown, the area where the p-type terminal well layer 31 is formed is covered with an anti-etching mask RM2, and in the trench whose inner wall has a gate trench insulating film 11b, polysilicon doped with n-type or p-type impurities is deposited by CVD or the like to form a gate trench electrode 11a, thereby forming an active trench gate 11. Fig.29 is with Fig.17 The process shown in the figure corresponds to, Figure 29 to Figure 35 It indicated Fig.17 The manufacturing process after the process shown. Fig.29 As shown, in the trench having the gate trench insulating film 11b formed on the inner wall, polysilicon doped with n-type or p-type impurities is deposited by CVD or the like to form a gate trench electrode 11a, thereby forming an active trench gate 11. Then, as shown in FIG. Fig.30 As shown, the resist mask RM2 is removed.

[0166] Next, in Fig.31 In the process shown, the first main surface of the semiconductor substrate is retreated, and a resist mask RM21 is formed on the first main surface of the semiconductor substrate except for the region where the step portion 37 is provided. The region where the step portion 37 is provided becomes the opening OP1.

[0167] Then, the first main surface of the semiconductor substrate is etched using the resist mask RM21 as an etching mask, and the first main surface of the semiconductor substrate not covered by the resist mask RM21 is removed by about 50 nm to form a step portion 37 .

[0168] Next, in Fig.32 In the process shown, the formation of n + The region of the channel stopper layer 32 has a resist mask RM3 having an opening OP2, and n-type impurities are ion-implanted using the resist mask RM3 as an ion implantation mask to form an n-type channel stopper layer 32. + Type channel stop layer 32.

[0169] Next, in Fig.33 In the process shown, the interlayer insulating film 4 is formed entirely on the first main surface of the semiconductor substrate.

[0170] Then, in Fig.34 In the process shown, a resist mask RM4 is formed in which an opening portion of the interlayer insulating film 4 is patterned on the active trench gate 11, a portion of the interlayer insulating film 4 where the gate pull-up portion 43 is formed becomes an opening portion OP3, and a portion where the contact hole is formed becomes an opening portion OP4.

[0171] Next, in Fig.35 In the process shown, the anti-etching mask RM4 is used as an etching mask to pattern the interlayer insulating film 4, the interlayer insulating film 4 covers the active trench gate 11, and an opening portion OP11 is formed in the gate pull-up portion 43, and an opening portion OP12 is formed in the portion where the contact hole is formed.

[0172] When the resist mask RM4 is patterned, the shape of the resist mask RM4 changes due to a focus shift during exposure in the resist mask RM4 on the step portion 37 , thereby forming a narrow width portion 35 where the width of the interlayer insulating film 4 is narrowed.

[0173] exist Fig.35 In the top view of the IGBT region 10 and the terminal region 30, the arrow direction of the line XX near the boundary is the same as Fig. 27 The following figure corresponds to .

[0174] In this way, if the step portion 37 is provided at the position where the narrow width portion 35 is to be formed, the narrow width portion 35 can be formed by using an existing resist mask for patterning the interlayer insulating film 4 , so that the manufacturing process can be simplified.

[0175] <Implementation method 3>

[0176] Fig.36 is a partial top view showing the structure of the RC-IGBT3000 according to the third embodiment. Figure 3 Therefore, the overall planar structure of RC-IGBT3000 is similar to Figure 1 The semiconductor device 100 or Figure 2 The semiconductor devices 101 shown are the same.

[0177] exist Fig.36 In the figure, it is shown Figure 3 The interlayer insulating film 4 on the active trench gate 11 is omitted in the figure. The interlayer insulating film 4 is provided on the first main surface of the semiconductor substrate and is provided so as to overlap with the active trench gate 11.

[0178] like Fig.36 As shown, in the RC-IGBT 3000, the narrow width portion 35 of the interlayer insulating film 4 is formed at the same width as the n + The p-type source layer 13 is provided adjacent to the p + type contact layer 14.

[0179] Fig.37 is an enlarged view of the narrow width portion 35. Fig.38 yes Fig.37 A cross-sectional view of the arrow direction at the dashed line II of FIG. In tests such as RBSOA and short-circuit tests where a large current flows, when the IGBT cuts off the current, the holes existing inside are removed from the p + At this time, in the narrow width portion 35, the current is concentrated on Fig.38 The arrows in the figure indicate such a path. As a result, a larger amount of heat is generated compared to other parts, which leads to a narrow effect such as easy destruction.

[0180] In the RBSOA and short-circuit tests, the measurement conditions are gradually tightened, such as increasing the amount of current flowing, and the test is performed until the IGBT is destroyed. Therefore, by providing the narrow width portion 35, the measurement conditions for the destruction of the IGBT to be tested can be limited by the narrow width effect, and the variation of the breakdown tolerance can be reduced. Here, the variation of the breakdown tolerance means that even if the IGBT is manufactured under the same process conditions, there will be a variation in the conditions under which it can be operated in a non-destructive manner in the destruction test such as the RBSOA and short-circuit test.

[0181] In addition, Fig.36 , an example in which the narrow width portion 35 is provided on the interlayer insulating film 4 on two gate trench electrodes 11 a is shown, but the present invention is not limited thereto. The narrow width portion 35 may be provided on the interlayer insulating film 4 on only one gate trench electrode 11 a , and the number of the narrow width portions 35 is not limited.

[0182] Even when the narrow width portion 35 is provided, the RC-IGBT 3000 functions normally under normal use conditions and the product life can be ensured. The screening effect of the dielectric breakdown resistance of the gate provided by the narrow width portion 35 is the same as that of the first embodiment.

[0183] <Implementation method 4>

[0184] Fig.39 is a partial top view showing the structure of the RC-IGBT4000 according to the fourth embodiment. Figure 3 Therefore, the overall planar structure of RC-IGBT4000 is similar to Figure 1 The semiconductor device 100 or Figure 2 The semiconductor devices 101 shown are the same.

[0185] exist Fig.39 In, with Fig.36 As in the RC-IGBT 3000 shown in FIG. 1 , the narrow width portion 35 of the interlayer insulating film 4 is formed at the same position as the n + The p-type source layer 13 is provided adjacent to the p + type contact layer 14, and in contact with the p + The n-type contact layer 14 is adjacent to the + Intersecting interlayer insulating films 40a and 40b are also formed on the upper portion of the type source layer 13, and a region 41 surrounded by the interlayer insulating film 4 having the narrow width portion 35 and the intersecting interlayer insulating films 40a and 40b is formed.

[0186] In tests such as RBSOA and short-circuit tests where a large current flows, when the IGBT cuts off the current, the holes existing inside are removed from the p +At this time, by providing the region 41, since the current flows from the periphery of the region 41 to the inside of the region 41, the current is further concentrated on the narrow width portion 35 compared with the case of the third embodiment. As a result, the narrow width effect is further enhanced, and the variation in breakdown withstand capacity can be further reduced.

[0187] In addition, even if the region 41 including the narrow portion 35 is provided, the RC-IGBT4000 will function normally under normal usage conditions and the product life can be guaranteed. The screening effect of providing the gate with dielectric breakdown resistance by providing the region 41 including the narrow portion 35 is the same as that in embodiment 1.

[0188] <Implementation method 5>

[0189] Next, a method for manufacturing the RC-IGBT of the first, third, and fourth embodiments will be described. Fig.40 This is a flowchart illustrating a method for manufacturing an RC-IGBT. Figure 41 to Figure 45 The following description will describe a method for forming a narrow width portion by providing a step portion on the first main surface of a semiconductor substrate.

[0190] like Fig.40 As shown in FIG. 1 , first, a step difference is formed on the first main surface which is the surface of the semiconductor substrate (step S1). Fig.41 The process is schematically shown in Fig.41 The top view is shown in the upper figure, and the cross-sectional view in the direction of the arrow at the dotted line JJ in the upper figure is shown in the lower figure.

[0191] like Fig.41 As shown, a resist mask RM5 for forming a step difference portion 37 is formed on the first main surface of the semiconductor substrate on which the n-type carrier accumulation layer 2 and the p-type base layer 15 are formed, and the resist mask RM5 is used as an etching mask to remove about 50nm of the first main surface of the semiconductor substrate by dry etching or wet etching to form the step difference portion 37. In this case, the step difference portion 37 is set to intersect with the extension direction of the active trench gate 11.

[0192] Then, after using Figure 14 to Figure 17 The process described, such as Fig.42 As shown, n is formed in the semiconductor substrate + Type source layer 13, p + The gate trench electrode 11a is a gate trench insulating film 11b. Fig.42 In the figure, a top view is shown in the upper figure, and a cross-sectional view in the direction of the arrow at the dotted line KK in the upper figure is shown in the lower figure. Fig.42 In the example, by crossing adjacent n +Although the step portion 37 is formed between the source layers 13, the position where the step portion 37 is provided is not limited thereto.

[0193] Here, return to Fig.40 As described above, an interlayer insulating film 4 is formed on the entire first main surface of the semiconductor substrate (step S2). The interlayer insulating film 4 can be, for example, SiO2 formed by CVD. 2 .exist Fig.43 The process is schematically shown in Fig.43 The top view is shown in the upper figure, and the cross-sectional view in the direction of the arrow at the dotted line LL in the upper figure is shown in the lower figure.

[0194] like Fig.43 As shown in the lower figure, by providing the step portion 37 on the semiconductor substrate, the interlayer insulating film 4 above the step portion 37 is recessed.

[0195] Here, return to Fig.40 The following resist mask RM6 is formed on the upper part of the interlayer insulating film 4: n is formed as a contact region with the emitter electrode as the surface electrode + Type source layer 13 and p + The upper portion of the type contact layer 14 becomes the opening OP5 (step S3).

[0196] exist Fig.44 The process is schematically shown in Fig.44 The top view is shown in the upper figure, and the cross-sectional view in the direction of the arrow at the dotted line MM in the upper figure is shown in the lower figure.

[0197] like Fig.44 As shown in the above figure, the interlayer insulating film 4 at the upper part of the step difference portion 37 is recessed, so that the focus of the anti-etching mask RM6 on the interlayer insulating film 4 is offset during exposure, the shape of the anti-etching mask RM6 in the step difference portion 37 and the part outside it is changed, and the width of the anti-etching mask RM6 is locally narrowed.

[0198] Here, return to Fig.40 As described above, the interlayer insulating film 4 in the contact region with the emitter electrode serving as the surface electrode is removed by etching using the resist mask RM6 as an etching mask (step S4).

[0199] Fig.45 1 is a plan view schematically showing this process. The portion of the interlayer insulating film 4 above the active trench gate 11 corresponding to the step portion 37 becomes the narrow width portion 35 .

[0200] In this way, if the step portion 37 is provided at the position where the narrow width portion 35 is to be formed, the narrow width portion 35 can be formed by using an existing resist mask for patterning the interlayer insulating film 4 , so that the manufacturing process can be simplified.

[0201] <Other manufacturing methods>

[0202] In the manufacturing method of the fifth embodiment, a method of forming the narrow width portion by providing the step portion on the first main surface of the semiconductor substrate has been described, but the narrow width portion can also be formed without providing the step portion.

[0203] Fig.46 This is a flowchart for explaining a method for manufacturing an RC-IGBT in the case where a narrow width portion is formed without providing a step portion.

[0204] like Fig.46 As shown in FIG. 1 , an interlayer insulating film 4 is formed on the entire first main surface of the semiconductor substrate (step S11). The semiconductor substrate at this stage is Figure 14 to Figure 17 The process described, such as Fig.42 As shown in FIG. 1 , n is formed in the semiconductor substrate. + Type source layer 13, p + The interlayer insulating film 4 can be, for example, SiO2 formed by CVD. 2 .

[0205] Next, the following resist mask is formed on the upper portion of the interlayer insulating film 4: an n-type resist mask which becomes a contact region with the emitter electrode as a surface electrode; + Type source layer 13 and p + The upper portion of the type contact layer 14 becomes an opening (step S12).

[0206] In this process, in the resist mask used in the masking process, the width of the resist in the portion where the narrow width portion 35 is to be provided in the interlayer insulating film 4 is formed to be as narrow as the narrow width portion 35. Thus, the narrow width portion can be formed without providing a step portion, and by providing the step portion, an increase in the number of processes can be suppressed.

[0207] Here, in Fig.47 The exposure pattern when the resist material is a positive type is shown in FIG. Fig.47 As shown, when the resist material is a positive type, the unexposed region NEX has the same pattern as the interlayer insulating film 4 having the narrow width portion 35, and the exposed region EX has the same pattern as the contact region with the emitter electrode.

[0208] By exposing a positive resist material with such an exposure pattern, a Fig.48In addition, when the resist material is a negative type, it becomes Fig.47 The exposure pattern is an inversion of the unexposed area NEX and the exposed area EX.

[0209] Here, return to Fig.46 As described above, the interlayer insulating film 4 in the contact region with the emitter electrode serving as the surface electrode is removed by etching using the resist mask RM7 as an etching mask (step S13).

[0210] <Other manufacturing methods of the step portion>

[0211] In implementation 2, use Figure 28 to Figure 32 The manufacturing method of the step portion 37 has been described above. However, in order to reduce the number of resist masks, it is possible to cite Figures 49 to 51 The manufacturing method shown.

[0212] First, if Fig.49 As shown, a resist mask RM1 having an opening OP is formed in the region where the p-type termination well layer 31 is to be formed, and p-type impurities are ion-implanted using the resist mask RM1 as an ion implantation mask to form the p-type termination well layer 31. This process is similar to the process using Fig.28 The described process is the same.

[0213] Next, in Fig.50 In the process shown, the first main surface of the semiconductor substrate is retreated using the resist mask RM1 as an etching mask to form the step portion 37. In this case, the uppermost surface of the p-type termination well layer 31 is also retreated.

[0214] Next, in Fig.51 In the process shown, the area where the p-type terminal well layer 31 is formed is covered with an anti-etching mask RM8, and a gate trench insulating film 11b is formed in the trench on the inner wall. Polysilicon doped with n-type or p-type impurities is deposited by CVD or the like to form a gate trench electrode 11a, thereby forming an active trench gate 11. Fig.29 is with Fig.17 The process shown corresponds to the figure.

[0215] In this way, by using the resist mask used to form the p-type termination well layer 31 also as an etching mask when forming the step portion 37 , the number of resist masks can be reduced, thereby reducing the manufacturing cost.

[0216] <Other application examples>

[0217] In the above-described embodiments 1 to 5, examples of applying the present disclosure to RC-IGBT are shown, but the present disclosure is not limited to the application to RC-IGBT, and can also be applied to IGBT and MOSFET (MOS Field Effect Transistor). In this case, the same effect as the case of applying to RC-IGBT can be obtained.

[0218] In addition, the present disclosure can freely combine the various embodiments, appropriately modify, or omit the various embodiments within the scope of the disclosure.

[0219] The present disclosure described above is summarized as notes.

[0220] (Note 1)

[0221] A semiconductor device is a semiconductor device in which a transistor is formed on a semiconductor substrate having a first main surface and a second main surface, wherein:

[0222] The semiconductor substrate has a transistor region in which the transistor is formed.

[0223] The transistor region has:

[0224] a first main electrode electrically connected to the first main surface;

[0225] a second main electrode electrically connected to the second main surface;

[0226] a first semiconductor layer of a first conductivity type;

[0227] a second semiconductor layer of a second conductivity type provided on the first main surface side relative to the first semiconductor layer;

[0228] a third semiconductor layer of the first conductivity type, provided closer to the first main surface than the second semiconductor layer, and electrically connected to the first main electrode;

[0229] a trench gate extending from the first main surface in a thickness direction through the third semiconductor layer and the second semiconductor layer and reaching into the first semiconductor layer; and

[0230] An interlayer insulating film is provided on the trench gate.

[0231] The interlayer insulating film has at least one narrow width portion in which the length in the width direction intersecting the extending direction of the trench gate is locally narrowed in a plan view.

[0232] The length of the narrow width portion in the width direction is longer than the length of the trench gate in the width direction.

[0233] (Note 2)

[0234] A semiconductor device according to note 1, wherein:

[0235] The narrow width portion is formed above a step portion formed on the first main surface of the semiconductor substrate in a direction intersecting the extending direction of the trench gate in a plan view.

[0236] (Note 3)

[0237] A semiconductor device according to note 2, wherein:

[0238] The semiconductor substrate has a terminal region surrounding a cell region, and the cell region includes at least the transistor region.

[0239] The step portion is formed at a position closer to the termination region than a boundary between the transistor region and the termination region.

[0240] (Note 4)

[0241] A semiconductor device according to note 2, wherein:

[0242] The step portion has a height of at least 50 nm.

[0243] (Note 5)

[0244] A semiconductor device according to note 1, wherein:

[0245] The transistor region has a fourth semiconductor layer of the second conductivity type, the fourth semiconductor layer of the second conductivity type being the same layer as the third semiconductor layer, being disposed adjacent to the third semiconductor layer and being electrically connected to the first main electrode.

[0246] The narrow width portion is formed at a portion where the interlayer insulating film and the fourth semiconductor layer are adjacent to each other in a plan view.

[0247] (Note 6)

[0248] A semiconductor device according to note 5, wherein:

[0249] The above-mentioned fourth semiconductor layer adjacent to the above-mentioned narrow width portion of the above-mentioned interlayer insulating film is surrounded by the above-mentioned interlayer insulating film and the cross-direction interlayer insulating film. The above-mentioned cross-direction interlayer insulating film is arranged on the adjacent above-mentioned third semiconductor layer and extends in a direction intersecting with the above-mentioned extension direction of the above-mentioned trench gate.

[0250] (Note 7)

[0251] A semiconductor device according to note 1, wherein:

[0252] The narrow width portion has recessed portions on both side surfaces of the interlayer insulating film in the width direction intersecting the extending direction of the trench gate.

[0253] The length of the interlayer insulating film in the width direction is partially narrowed at a portion where the recess is provided.

[0254] (Note 8)

[0255] A semiconductor device according to note 1, wherein:

[0256] The semiconductor substrate has a diode region in which a diode is formed.

[0257] (Note 9)

[0258] A method for manufacturing a semiconductor device, wherein:

[0259] The method for manufacturing the semiconductor device comprises:

[0260] (a) a step of preparing a semiconductor substrate,

[0261] The semiconductor substrate has a first main surface and a second main surface, and has a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type provided at a position closer to the first main surface than the first semiconductor layer, and a third semiconductor layer of the first conductivity type provided at a position closer to the first main surface than the second semiconductor layer;

[0262] (b) forming a trench gate, wherein the trench gate penetrates the third semiconductor layer and the second semiconductor layer from the first main surface in the thickness direction and reaches into the first semiconductor layer; and

[0263] (c) forming an interlayer insulating film on the trench gate,

[0264] The step (c) includes forming at least one narrow width portion in which the length of the width direction intersecting the extending direction of the trench gate is locally narrowed in the interlayer insulating film when viewed from above,

[0265] The length of the narrow width portion in the width direction is longer than the length of the trench gate in the width direction.

[0266] (Note 10)

[0267] The method for manufacturing a semiconductor device according to appended note 9, wherein:

[0268] Prior to the step (c), the step of forming a step portion on the first main surface of the semiconductor substrate in a direction intersecting with the extending direction of the trench gate in a plan view is included.

Claims

1. A semiconductor device comprising a transistor formed on a semiconductor substrate having a first main surface and a second main surface, wherein: The semiconductor substrate has a transistor region in which the transistor is formed. The transistor region has: a first main electrode electrically connected to the first main surface; a second main electrode electrically connected to the second main surface; a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided closer to the first main surface than the first semiconductor layer; a third semiconductor layer of the first conductivity type, provided closer to the first main surface than the second semiconductor layer, and electrically connected to the first main electrode; a trench gate extending from the first main surface through the third semiconductor layer and the second semiconductor layer in a thickness direction and reaching into the first semiconductor layer; as well as an interlayer insulating film, disposed on the trench gate, The interlayer insulating film has at least one narrow width portion in which the length in the width direction intersecting the extending direction of the trench gate is locally narrowed in a plan view. The length of the narrow width portion in the width direction is longer than the length of the trench gate in the width direction.

2. The semiconductor device according to claim 1, wherein: The narrow width portion is formed above a step portion formed on the first main surface of the semiconductor substrate in a direction intersecting the extending direction of the trench gate in a plan view.

3. The semiconductor device according to claim 2, wherein: The semiconductor substrate has a terminal region surrounding a cell region, wherein the cell region includes at least the transistor region. The step portion is formed at a position closer to the termination region than a boundary between the transistor region and the termination region.

4. The semiconductor device according to claim 2, wherein: The step difference has a height of at least 50 nm.

5. The semiconductor device according to claim 1, wherein: The transistor region has a fourth semiconductor layer of the second conductivity type, the fourth semiconductor layer of the second conductivity type being the same layer as the third semiconductor layer, being disposed adjacent to the third semiconductor layer and being electrically connected to the first main electrode, The narrow width portion is formed at a portion where the interlayer insulating film and the fourth semiconductor layer are adjacent to each other in a plan view.

6. The semiconductor device according to claim 5, wherein: The fourth semiconductor layer adjacent to the narrow portion of the interlayer insulating film is surrounded by the interlayer insulating film and a cross-direction interlayer insulating film, and the cross-direction interlayer insulating film is arranged on the adjacent third semiconductor layer and extends in a direction intersecting with the extension direction of the trench gate.

7. The semiconductor device according to claim 1, wherein: The narrow width portion has recessed portions on both side surfaces of the interlayer insulating film in the width direction intersecting the extending direction of the trench gate. The length of the interlayer insulating film in the width direction is locally narrowed at a portion where the recess is provided.

8. The semiconductor device according to claim 1, wherein: The semiconductor substrate has a diode region in which a diode is formed.

9. A method for manufacturing a semiconductor device, characterized in that: The method for manufacturing a semiconductor device comprises: (a) preparing a semiconductor substrate having a first main surface and a second main surface, and comprising a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type provided on a side closer to the first main surface than the first semiconductor layer, and a third semiconductor layer of the first conductivity type provided on a side closer to the first main surface than the second semiconductor layer; (b) forming a trench gate, wherein the trench gate penetrates the third semiconductor layer and the second semiconductor layer from the first main surface in the thickness direction and reaches into the first semiconductor layer; as well as (c) forming an interlayer insulating film on the trench gate, The step (c) includes forming at least one narrow width portion in the interlayer insulating film in which the length of the width direction intersecting the extending direction of the trench gate is locally narrowed when viewed from above, The length of the narrow width portion in the width direction is longer than the length of the trench gate in the width direction.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The method further comprises the step of forming a step portion on the first main surface of the semiconductor substrate in a direction intersecting with the extending direction of the trench gate in a plan view before the step (c).

Images