Structure for improving CGC capacitance of IGBT device and preparation method

Abstract

The invention belongs to the technical field of semiconductor device manufacturing, and particularly relates to a structure for improving CGC capacitance of an IGBT device and a preparation method, the structure comprises a base layer, a gate layer, a first P-type electrode layer and a second P-type electrode layer, the first P-type electrode layer covers the upper surface of the base layer, the gate layer is arranged above the second P-type electrode layer, and the gate layer is arranged above the second P-type electrode layer. An insulating layer is filled between the gate layer and the second P-type electrode layer, and the opposite sides of the first P-type electrode layer and the second P-type electrode layer are respectively covered with a first N-type emitter region and a second N-type emitter region; an N-type drift region is filled between the first N-type emitter region and the second N-type emitter region, and two symmetrically arranged P-type body regions and a first P-type ring region are fixedly connected in the second P-type electrode layer. Through the arrangement of the separated Dummy gate structure, on the premise that the CGE capacitor is not increased, the large CGC capacitor is obtained, the dv / dt under the small current is improved, the dv / dt under the large current is not affected, and the small opening loss under the small RG configuration is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and in particular to a structure for improving a CGC capacitor of an IGBT device and a preparation method thereof. Background Art

[0002] Semiconductor power devices are basic electronic components for energy control and conversion in power electronics systems. The continuous development of power electronics technology has opened up a wide range of application areas for semiconductor power devices. MOS-type semiconductor power devices, represented by IGBT, VDMOS, and CoolMOS, are the mainstream devices in the field of power electronics today. Among them, the most representative semiconductor power device is IGBT.

[0003] IGBT (Insulated Gate Bipolar Transistor) is a voltage-controlled MOS / BJT composite device. Structurally, the structure of IGBT is very similar to that of VDMOS, except that the N+ substrate of VDMOS is adjusted to P+ substrate. However, the conductivity modulation effect introduced overcomes the contradiction between the on-resistance and breakdown voltage inherent in VDMOS itself, so that IGBT has the main advantages of both bipolar power transistors and power MOSFETs: high input impedance, low input drive power, low on-voltage drop, large current capacity, fast switching speed, etc. It is precisely because of the unique and irreplaceable performance advantages of IGBT that it has been widely used in many fields since the launch of practical products, such as new energy technology, advanced transportation vehicles represented by motor vehicles and high-speed railways, hybrid vehicles, office automation, and household appliances. Under the demand for a resource-saving society that advocates low-carbon and environmental protection, IGBT, as a high-performance and high-efficiency switch control component, has received more attention and development, and has put forward higher requirements for safety, reliability, and intelligence.

[0004] IGBT high-speed switching operation can reduce turn-on loss, but high-speed switching operation will bring higher turn-on dv / dt. High dv / dt is a source of electromagnetic interference (EMI) radiation noise, which will stress the user's motor insulation. Usually, it is necessary to increase the gate resistance (R G ) to limit the turn-on dv / dt below a certain value, however, the larger R G It will reduce the switching speed of the IGBT module and lead to higher turn-on losses. Summary of the invention

[0005] 1. Technical issues to be solved

[0006] The purpose of the present invention is to solve the problem of large R GIn order to solve the problem that the switching speed of the IGBT module is reduced, a structure and preparation method for improving the CGC capacitor of the IGBT device are proposed.

[0007] 2. Technical solution

[0008] In order to achieve the above object, the present invention adopts the following technical solutions:

[0009] A structure for improving the CGC capacitance of an IGBT device, comprising a base layer, a gate layer, a first P-type electrode layer and a second P-type electrode layer, wherein the first P-type electrode layer covers the upper surface of the base layer, the gate layer is arranged above the second P-type electrode layer, an insulating layer is filled between the gate layer and the second P-type electrode layer, and the first P-type electrode layer and the second P-type electrode layer are respectively covered with a first N-type emitter region and a second N-type emitter region on opposite sides thereof;

[0010] An N-type drift region is filled between the first N-type emitter region and the second N-type emitter region, two symmetrically arranged P-type body regions and a first P-type ring region are fixedly connected in the second P-type electrode layer, and a second P-type ring region is provided between the P-type body region and the first P-type ring region and between the two first P-type ring regions;

[0011] The outsides of the first P-type ring area and the second P-type ring area are covered with a composite gate electrode, and the bottom of the gate layer is fixedly connected to multiple collectors. The bottoms of the multiple collectors penetrate the insulating layer and extend into the second P-type electrode layer, the first P-type ring area, and the second P-type ring area respectively.

[0012] Preferably, the base layer is a metal base layer.

[0013] Preferably, the insulating layer is a photoresist layer.

[0014] Preferably, a P-type floating region is provided between the P-type body region and the first P-type ring region.

[0015] Preferably, the first P-type ring region and the second P-type ring region have the same width.

[0016] The present invention also proposes a method for preparing a structure of a CGC capacitor of an IGBT device, comprising the following steps:

[0017] Step 1: providing a base layer and a gate layer, and then disposing a first P-type electrode layer on the surface of the base layer, and disposing a second P-type electrode layer on the surface of the gate layer;

[0018] Step 2: Then fill the first N-type emitter region, the second N-type emitter region and the N-type drift region between the first P-type electrode layer and the second P-type electrode layer, introduce a composite gate electrode into the first P-type electrode layer, the second N-type emitter region and the N-type drift region, and implant P-type ions into the composite gate electrode to form a P-type body region and a first P-type ring region and a second P-type ring region in the first P-type electrode layer;

[0019] Step 3: Finally, the collector and gate layers are covered on the surface of the first P-type electrode layer, and the bottom of the collector is made to enter the corresponding second P-type electrode layer, the first P-type ring area and the second P-type ring area.

[0020] 3. Beneficial effects

[0021] Compared with the prior art, the advantages of the present invention are:

[0022] In the present invention, by separating the Dummy gate structure, without increasing C GE capacitor, a larger C GC Capacitors improve dv / dt at low currents without affecting dv / dt at high currents, achieving small R G Small opening loss under configuration. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of the structure of the collector region in a structure for improving the CGC capacitance of an IGBT device proposed by the present invention;

[0024] Figure 2 A schematic diagram of the structure of the gate emitter region in a structure for improving the CGC capacitance of an IGBT device proposed by the present invention;

[0025] Figure 3 The present invention is a schematic flow chart of a method for improving the structure of a CGC capacitor of an IGBT device.

[0026] In the figure: 1 base layer, 2 surface collector, 3 first P-type electrode layer, 4 second P-type electrode layer, 5 insulating layer, 6 first N-type emitter region, 7 second N-type emitter region, 8 N-type drift region, 9 P-type body region, 10 first P-type ring region, 11 second P-type ring region, 12 composite gate electrode, 13 collector, 14 P-type floating region, 15. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0028] Embodiment 1:

[0029] Reference Figure 1 and 2 , a structure for improving the CGC capacitance of an IGBT device, comprising a base layer 1, a gate layer 2, a first P-type electrode layer 3 and a second P-type electrode layer 4, wherein the base layer 1 is a metal base layer, the first P-type electrode layer 3 covers the upper surface of the base layer 1, and the gate layer 2 is arranged above the second P-type electrode layer 4;

[0030] In the present invention, an insulating layer 5 is filled between the gate layer 2 and the second P-type electrode layer 4, and the insulating layer 5 is a photoresist layer. The first P-type electrode layer 3 and the second P-type electrode layer 4 are respectively covered with a first N-type emitter region 6 and a second N-type emitter region 7 on the opposite side.

[0031] In the present invention, an N-type drift region 8 is filled between the first N-type emitter region 6 and the second N-type emitter region 7, two symmetrically arranged P-type body regions 9 and a first P-type ring region 10 are fixedly connected in the second P-type electrode layer 4, a P-type floating region 14 is provided between the P-type body region 9 and the first P-type ring region 10, a second P-type ring region 11 is provided between the P-type body region 9 and the first P-type ring region 10 and between the two first P-type ring regions 10, and the widths of the first P-type ring region 10 and the second P-type ring region 11 are the same;

[0032] In the present invention, the outside of the first P-type ring region 10 and the second P-type ring region 11 are covered with a composite gate electrode 12, and a plurality of collector electrodes 13 are fixedly connected to the bottom of the gate layer 2. The bottoms of the plurality of collector electrodes 13 penetrate the insulating layer 5 and extend into the second P-type electrode layer 4, the first P-type ring region 10, and the second P-type ring region 11, respectively.

[0033] Reference Figure 3 , a preparation method for improving the structure of CGC capacitor of IGBT device, comprising the following steps:

[0034] Step 1: providing a base layer 1 and a gate layer 2, and then disposing a first P-type electrode layer 3 on the surface of the base layer 1, and disposing a second P-type electrode layer 4 on the surface of the gate layer 2;

[0035] Step 2: Then fill the first N-type emitter region 6, the second N-type emitter region 7 and the N-type drift region 8 between the first P-type electrode layer 3 and the second P-type electrode layer 4, and introduce the composite gate electrode 12 into the first P-type electrode layer 3, the second N-type emitter region 7 and the N-type drift region 8, and perform P-type ion implantation in the composite gate electrode 12 to form the P-type body region 9 and the first P-type ring region 10 and the second P-type ring region 11 in the first P-type electrode layer 3;

[0036] Step 3: Finally, the collector 13 and the gate layer 2 are covered on the surface of the first P-type electrode layer 3 , and the bottom of the collector 13 enters the corresponding second P-type electrode layer 4 , the first P-type ring area 10 and the second P-type ring area 11 .

[0037] In the present invention, by separating the Dummy gate structure, without increasing C GE capacitor, a larger C GC Capacitors improve dv / dt at low currents without affecting dv / dt at high currents, achieving small R G Small opening loss under configuration.

[0038] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A structure for improving the CGC capacitance of an IGBT device, comprising an emitter region and a gate emitter region arranged in parallel, characterized in that: The emitter region and the gate emitter region both comprise a base layer (1), a first P-type electrode layer (3) and a second P-type electrode layer (4); the first P-type electrode layer (3) covers the upper surface of the base layer (1); the top of the second P-type electrode layer (4) is covered with an insulating layer (5); the surface of the insulating layer (5) of the emitter region is covered with a surface collector (2); the surface of the emitter region is covered with a gate layer (15); the first P-type electrode layer (3) and the second P-type electrode layer (4) are respectively covered with a first N-type emitter region (6) and a second N-type emitter region (7); An N-type drift region (8) is filled between the first N-type emitter region (6) and the second N-type emitter region (7); two symmetrically arranged P-type body regions (9) and a first P-type ring region (10) are fixedly connected in the second P-type electrode layer (4); and a second P-type ring region (11) is provided between the P-type body region (9) and the first P-type ring region (10) and between the two first P-type ring regions (10); The outsides of the first P-type ring region (10) and the second P-type ring region (11) are both covered with a composite gate electrode (12); the bottom of the surface collector (2) is fixedly connected to a plurality of collector electrodes (13); the bottoms of the plurality of collector electrodes (13) penetrate the insulating layer (5) and extend into the second P-type electrode layer (4), the first P-type ring region (10) and the second P-type ring region (11), respectively.

2. The structure for improving the CGC capacitance of an IGBT device according to claim 1, characterized in that: The base layer (1) is a metal base layer.

3. The structure for improving the CGC capacitance of an IGBT device according to claim 1, characterized in that: The insulating layer (5) is a photoresist layer.

4. The structure for improving the CGC capacitance of an IGBT device according to claim 1, characterized in that: A P-type floating region (14) is provided between the P-type body region (9) and the first P-type ring region (10).

5. The structure and preparation method for improving the CGC capacitor of an IGBT device according to claim 1, characterized in that: The first P-type ring region (10) and the second P-type ring region (11) have the same width.

6. The method for preparing a structure of improving the CGC capacitor of an IGBT device according to claim 1, characterized in that: The following steps are involved: Step 1: providing a first P-type electrode layer (3) and a second P-type electrode layer (4); then filling a first N-type emitter region (6), a second N-type emitter region (7) and an N-type drift region (8) between the first P-type electrode layer (3) and the second P-type electrode layer (4), and introducing a composite gate electrode (12) into the first P-type electrode layer (3), the second N-type emitter region (7) and the N-type drift region (8); Step 2: Then, the emitter region is subjected to photolithography and etching, and the composite gate electrode (12) in the emitter region is subjected to polycrystalline oxidation to form a separation isolation oxide layer, and then polycrystalline growth and back etching are performed, and then P-type ions are implanted into the composite gate electrode (12) to form a P-type body region (9) and a first P-type ring region (10) and a second P-type ring region (11) in the first P-type electrode layer (3), and then photoresist is implanted and pushed in to form an insulating layer (5); Step 3: Finally, ILD deposition is performed on the insulating layer (5) of the gate emitter region, the emitter region and the bottom of the gate emitter region are covered with the first P-type electrode layer (3) and the metal base layer, and the surface of the insulating layer (5) on the emitter region and the gate emitter region is covered with the surface collector (2) and the gate layer (15) respectively.

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