Manufacturing method of semiconductor structure

Abstract

The invention provides a manufacturing method of a semiconductor structure, which is applied to the technical field of semiconductors. According to the invention, before the second conductive layer is formed, the ion implantation process is carried out on the substrate, so that the first ion implantation region is formed in the substrate below the deep trench, and the second ion implantation region is synchronously formed in the substrate at two sides of the deep trench, thereby saving an ion implantation process. The conduction type of the first ion implantation region (located between the control gate and the drain electrode) is opposite to that of the substrate, so that carriers can be mutually depleted, and the purpose of increasing a depletion region and the breakdown voltage is achieved; and then a second conductive layer is formed and deposited in the deep trench, and a control gate in a special shape is formed by combining a first conductive layer on the side wall of the deep trench, so that the purposes of reducing the overlapping area between the control gate and a drain electrode, reducing the gate-drain capacitance of the power semiconductor device, reducing the switching loss and finally improving the switching speed are achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure. Background Art

[0002] In traditional power conversion circuits, silicon-based metal-oxide-semiconductor field-effect transistors (MOSFETs) are usually used when higher switching frequencies are required. In high-power conversion applications, the capacitance between the polysilicon gate of the power semiconductor device and the drain of the semiconductor device (i.e., the gate-drain capacitance) is too large, which will affect the reliability of the device and the switching speed of the device. Therefore, the existing technology or structure needs to be further improved to effectively improve the performance and reliability of the relevant power semiconductor devices. Summary of the invention

[0003] The object of the present invention is to provide a method for manufacturing a semiconductor structure to reduce the gate-drain capacitance of a power semiconductor device, lower the switching loss, and increase the switching speed.

[0004] In order to solve the above technical problem, the present invention provides a method for manufacturing a semiconductor structure, comprising: providing a substrate.

[0005] A deep trench and a first isolation layer are formed, wherein the deep trench is located in the substrate, and the first isolation layer is located at the bottom and sidewalls of the deep trench.

[0006] A first conductive layer is formed on the first isolation layer, and the first conductive layer includes: The first portion is located on the first isolation layer on a side wall of the deep trench.

[0007] The second portion is located on the first isolation layer on the other sidewall of the deep trench and is not in direct contact with the first portion.

[0008] An ion implantation process is performed on the substrate to form a first ion implantation region in a portion of the substrate below the deep trench, and a second ion implantation region is formed in a portion of the substrate on both sides of the deep trench.

[0009] A second isolation layer and a second conductive layer are formed, wherein the second isolation layer is located between the first portion and the second portion of the first conductive layer and is in direct contact with the first isolation layer, and the second conductive layer is located on the second isolation layer and is connected to the first conductive layer to serve as a control gate of the semiconductor structure.

[0010] In some of the optional examples, the deep groove may include a first groove portion and a second groove portion, the second groove portion may be located below the first groove portion in the vertical direction, and the width of the second groove portion in the horizontal direction may be smaller than the width of the first groove portion in the horizontal direction.

[0011] In some optional examples, the step of forming the first isolation layer may include: A third conductive layer is formed in the second trench portion of the deep trench.

[0012] The substrate is thermally oxidized to oxidize and convert the portion of the substrate exposed by the third conductive layer and the sidewall of the first groove portion of the deep groove into the first isolation layer; wherein the thickness of the first isolation layer in the second groove portion of the deep groove is greater than its thickness on the sidewall of the deep groove.

[0013] In some optional examples, materials of the first conductive layer, the second conductive layer, and the third conductive layer may all include polysilicon.

[0014] In some optional examples, the step of forming the first conductive layer may include: A polysilicon material layer is formed on the first isolation layer.

[0015] The polysilicon material layer on the top surface of the second trench portion of the deep trench is removed to expose the top surface of the first isolation layer in the second trench portion of the deep trench.

[0016] In some of the optional examples, a top surface of the second isolation layer may be lower than a top surface of the first conductive layer.

[0017] In some of the optional examples, after the substrate is subjected to an ion implantation process, the method may further include: performing a heat treatment on the first ion implantation region and the second ion implantation region to perform doping, wherein the conductivity type of the doped ions is the same as the conductivity type of the ions implanted when the substrate is subjected to the ion implantation process.

[0018] In some optional examples, the process parameters of the doping heat treatment include: a temperature range of 1300° C. to 1600° C., and a time range of 3 min to 7 min.

[0019] In some optional examples, the base is a doped silicon substrate, and the conductivity type of the doped ions in the silicon substrate may be opposite to the conductivity type of the doped ions implanted in the first ion implantation region.

[0020] In some optional examples, the second isolation layer and the first isolation layer may have different dielectric constants.

[0021] In some optional examples, the method for manufacturing the semiconductor structure may further include: A source electrode and a drain electrode are formed, wherein the source electrode is located in the surface layer of the substrate at both sides of the deep trench, and the drain electrode is located in another surface layer of the substrate opposite to the surface layer of the substrate where the source electrode is formed.

[0022] Compared with the prior art, the technical solution provided by the present invention has at least one of the following beneficial effects: The present invention provides a method for manufacturing a semiconductor structure, comprising: providing a substrate, forming a deep trench and a first isolation layer, wherein the deep trench is located in the substrate, the first isolation layer is located at the bottom and side walls of the deep trench, forming a first conductive layer, which is located on the first isolation layer, and the first conductive layer comprises: a first part, which is located on the first isolation layer on one side wall of the deep trench, and a second part, which is located on the first isolation layer on the other side wall of the deep trench and is not in direct contact with the first part, performing an ion implantation process on the substrate to form a first ion implantation region in a portion of the substrate below the deep trench, and a second ion implantation region in a portion of the substrate on both sides of the deep trench, to form a second isolation layer and a second conductive layer, the second isolation layer is located between the first portion and the second portion of the first conductive layer and is in direct contact with the first isolation layer, and the second conductive layer is located on the second isolation layer and is connected to the first conductive layer to serve as a control gate of the semiconductor structure.

[0023] In the present invention, firstly, by utilizing the characteristic that the oxidation rate of polycrystalline silicon is faster than that of the substrate (such as single crystal silicon), first isolation layers with different thicknesses are formed in different parts of the deep trench to increase the distance between the control gate and the drain, thereby achieving the purpose of reducing the gate-drain capacitance; secondly, by advancing the process technology of the second ion implantation region as the body region to before the formation of the control gate including the second conductive layer, and utilizing the ion implantation process to synchronously form the first ion implantation region in the corresponding substrate at the bottom of the deep trench, the unexpected effect is obtained: one ion implantation process is saved, and the first ion implantation region (located between the control gate and the drain) is opposite to the conductive type of the substrate, so that carriers can be mutually depleted, thereby achieving the purpose of increasing the depletion region and the breakdown voltage; then, a second conductive layer is deposited in the deep trench, and combined with the first conductive layer located on the side wall of the deep trench, a control gate of a special shape is formed, thereby achieving the unexpected effect of reducing the overlapping area between the control gate and the drain, reducing the gate-drain capacitance of the power semiconductor device, reducing the switching loss, and ultimately improving the switching speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present application but do not constitute a limitation to the present application. In the accompanying drawings: Figure 1 It is a schematic diagram of a process of manufacturing a semiconductor structure in one embodiment of the present invention.

[0025] Figure 2 It is a structural schematic diagram of a deep trench having a first trench portion and a second trench portion formed in a substrate in one embodiment of the present invention.

[0026] Figure 3 It is a structural schematic diagram of forming a third conductive layer in the second trench portion of the deep trench in one embodiment of the present invention.

[0027] Figure 4 It is a structural schematic diagram of forming a first isolation layer in a first trench portion and a second trench portion of a deep trench in one embodiment of the present invention.

[0028] Figure 5 It is a structural schematic diagram of forming a polysilicon material layer in a first trench portion of a deep trench in one embodiment of the present invention.

[0029] Figure 6 It is a schematic structural diagram of forming a first conductive layer on both side walls of a first trench portion of a deep trench in one embodiment of the present invention.

[0030] Figure 7 It is a structural schematic diagram of forming a first ion implantation region and a second ion implantation region on a substrate below a deep trench and on both sides of the deep trench respectively in an embodiment of the present invention.

[0031] Figure 8 It is a schematic structural diagram of forming a second isolation layer in a partial region of a first trench portion of a deep trench in one embodiment of the present invention.

[0032] Fig. 9 It is a schematic structural diagram of forming a second conductive layer in the remaining area of ​​the first trench portion of the deep trench in one embodiment of the present invention.

[0033] Fig.10 It is a schematic structural diagram of forming a source electrode and a drain electrode in the surface layers of two contrasting surfaces of a substrate respectively in one embodiment of the present invention.

[0034] Wherein, the accompanying drawings are marked as follows: 100-substrate, 101-deep trench, 101.1-first trench portion, 101.2-second trench portion, 110-third conductive layer, 120-first isolation layer, 130-polysilicon material layer, 130'-first conductive layer, 130'a-first part of the first conductive layer, 130'b-second part of the first conductive layer, 141-first ion implantation region, 142-second ion implantation region, 150-second isolation layer, 160-second conductive layer, 170-control gate, 181-source, 182-drain.

[0035] In the drawings, the same reference numerals are used for the same components, and the drawings are not drawn to scale. DETAILED DESCRIPTION

[0036] In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0037] It will be understood that the meanings of “on,” “over,” and “over” in the present invention should be interpreted in the broadest manner, so that “on” not only means that it is “on” something without any intervening features or layers (i.e., directly on something), but also includes the meaning that it is “on” something with any intervening features or layers.

[0038] In the embodiments of the present invention, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be noted that the technical solutions recorded in the embodiments of the present invention can be combined arbitrarily without conflict.

[0039] Please refer to Figure 1 As shown, Figure 1 FIG. 1 is a flow chart of a method for manufacturing a semiconductor structure in one embodiment of the present invention. Figure 1 As shown, the method for manufacturing the semiconductor structure may include at least the following steps: Step S101, providing a substrate.

[0040] Step S102 , forming a deep trench and a first isolation layer, wherein the deep trench is located in the substrate, and the first isolation layer is located at the bottom and sidewalls of the deep trench.

[0041] Step S103, forming a first conductive layer located on the first isolation layer, and the first conductive layer includes: a first portion located on the first isolation layer on one side wall of the deep trench; and a second portion located on the first isolation layer on the other side wall of the deep trench and not in direct contact with the first portion.

[0042] Step S104 , performing an ion implantation process on the substrate to form a first ion implantation region in a portion of the substrate below the deep trench, and a second ion implantation region in a portion of the substrate on both sides of the deep trench.

[0043] Step S105, forming a second isolation layer and a second conductive layer, wherein the second isolation layer is located between the first part and the second part of the first conductive layer and is in direct contact with the first isolation layer, and the second conductive layer is located on the second isolation layer and is connected to the first conductive layer to serve as a control gate of the semiconductor structure.

[0044] In order to enable a person skilled in the art to which the present invention belongs to easily understand the method for manufacturing a semiconductor structure in the embodiment of the present invention, the method for manufacturing a semiconductor structure proposed by the present invention will be further described below in conjunction with various structural schematic diagrams of the manufacturing method during the preparation process. Figure 2~Figure 10 This is a schematic diagram of the structure of the semiconductor structure manufacturing method provided in one embodiment of the present invention during the manufacturing process. Figure 2 to Figure 10 The method for manufacturing the semiconductor structure provided in this embodiment is described in detail.

[0045] For ease of understanding, the direction parallel to the substrate 100 and the direction perpendicular to the surface of the substrate 100 are defined below, and for simplicity of description, the direction parallel to the surface of the substrate 100 is referred to as a horizontal direction, and the direction perpendicular to the surface of the substrate 100 is referred to as a vertical direction.

[0046] Please refer to Figure 2 , illustrated is a schematic structural diagram of a deep trench having a first trench portion and a second trench portion formed in a substrate in one embodiment of the present invention.

[0047] like Figure 2As shown, step S101 is performed: providing a substrate 100, wherein the substrate 100 is used as a platform for the subsequent formation of the trench gate MOSFET including the deep trench, source, drain and other components and / or parts. In one embodiment, the substrate 100 is any suitable substrate material known in the art, for example, it can be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, an epitaxial silicon substrate (Epitaxial Silicon Substrate), a silicon on insulator (Silicon on Insulator, referred to as SOI) substrate or a germanium on insulator (Germanium on Insulator, referred to as GOI) substrate, or a substrate composed of other suitable materials, but not limited thereto. Those skilled in the art should easily understand that various required active components and / or passive components, such as epitaxial layers and / or well regions (not shown) can be further formed on or in the substrate 100 according to actual device requirements, but not limited thereto. Preferably, in the embodiment of the present invention, after providing the substrate 100, the substrate 100 may be further doped by an ion implantation process to form a P-type or N-type well (not shown, i.e., the doped substrate 100). The specific doping type may be determined according to the actual device requirements, and it is required to satisfy the corresponding doping relationship with the first ion implantation region and / or the second conductive ion implantation region formed subsequently, but is not limited thereto. Exemplarily, in the embodiment of the present invention, the ions doped with the substrate 100 are N-type ions, and the corresponding well formed is an N-type well (not shown).

[0048] Please continue to refer to Figure 2 , performing step S102: using at least one of deposition processes such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc., to sequentially form a hard mask layer (not shown) and a patterned photoresist layer (not shown) on the surface of the substrate 100, and using the patterned photoresist layer as a mask, using at least one of etching processes such as dry etching or wet etching to form at least one deep trench 101 in the substrate 100, and the deep trench 101 details may include a first trench portion 101.1 and a second trench portion 101.2 that are connected in a vertical direction and located in an upper and lower position relationship (it can also be understood that the first trench portion 101.1 is located above the second trench portion 101.2 in the vertical direction). In one embodiment, the bottom surface of the second trench portion 101.2 of the deep trench 101 is higher than the bottom surface of the N-type well formed in the substrate 100, that is, the groove body of the deep trench 101 along the direction perpendicular to the surface of the substrate 100 is entirely located in the N-type well.

[0049] Please refer to Figure 3 , illustrated is a structural schematic diagram of forming a third conductive layer in the second trench portion of the deep trench in one embodiment of the present invention.

[0050] like Figure 3 As shown, continue to perform step S102: a third conductive layer 110 may be formed in the second groove portion 101.2 (i.e., the bottom of the deep groove) of the deep groove 101 by using at least one of a deposition process such as a physical vapor deposition process, a chemical vapor deposition process, and an atomic layer deposition process. In one embodiment, the material of the third conductive layer 110 may be a conductive material, such as polysilicon, and the top surface of the polysilicon is lower than the top surface of the substrate 100, and preferably only the polysilicon that at least covers the second groove portion 101.2 of the deep groove 101 is formed, but not limited thereto. In other words, in some embodiments, the third conductive layer 110 may fill the second groove portion 101.2 of the deep groove 101 so that its top surface is flush with the top surface of the second groove portion 101.2 of the deep groove 101, while in other embodiments, it may also fill part of the space of the second groove portion 101.2 of the deep groove 101 so that the top surface of the third conductive layer 110 located in the deep groove 101 is lower than the top surface of the second groove portion 101.2 of the deep groove 101.

[0051] Please refer to Figure 4 , illustrated is a schematic structural diagram of forming a first isolation layer in a first trench portion and a second trench portion of a deep trench in one embodiment of the present invention.

[0052] like Figure 4 As shown, continue to perform step S102: in an environment with a preset temperature and oxygen, perform thermal oxidation treatment on the substrate 100 to oxidize and convert the third conductive layer 110 made of polysilicon and the exposed substrate 100 of the sidewall of the remaining area of ​​the deep trench 101 not filled with the third conductive layer 110 into silicon dioxide, and use the silicon dioxide as the first isolation layer 120. In one embodiment, since the second trench portion 101.2 of the deep trench 101 is shallow in the vertical direction, the third conductive layer 110 filled therein will be completely converted into silicon dioxide during the thermal oxidation process of the above step S102, thereby forming the following structure. Figure 4The structure shown in FIG. 1 is a structure in which the thickness of the first isolation layer 120 in the second groove portion 101.2 of the deep groove 101 is greater than the thickness in the first groove portion 101.1 of the deep groove 101. Under this setting, since the oxidation rate of the polysilicon of the third conductive layer 110 is faster than that of the substrate 100 (e.g., single crystal silicon), the thickness of the first isolation layer 120 in the second groove portion 101.2 of the deep groove 101 is thicker than the thickness on the side wall of the first groove portion 101.1 of the deep groove 101, so that the first isolation layer 120 increases the distance between the control gate 170 and the drain 182 in the vertical direction, thereby achieving the purpose of reducing the gate-drain capacitance.

[0053] It should be understood that in order to simplify Figure 2~Figure 10 , in the embodiment of the present invention Figure 2~Figure 10 It is only exemplary that a deep trench 101 and subsequent components formed based on the deep trench 101 are formed in the substrate 100. In other embodiments, a plurality of deep trenches 101 may be formed, but the structure formed in each deep trench 101 may be the same, but this is not limited thereto.

[0054] Please refer to Figure 5 , illustrated is a structural schematic diagram of forming a polysilicon material layer in a first trench portion of a deep trench in one embodiment of the present invention.

[0055] like Figure 5 As shown, step S103 is performed: using at least one of deposition processes such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc., a polysilicon material layer 130 is further deposited in the first groove portion 101.1 of the deep groove 101. Specifically, the polysilicon material layer 130 is specifically located on the surface of the first isolation layer 120 formed in the deep groove 101, that is, located in the second groove portion 101.2 of the deep groove 101 and on the surface of the first isolation layer 120 corresponding to the side wall of the first groove portion 101.1. In one embodiment, the thickness of the polysilicon material layer 130 is relatively thin, for example, the thickness can be about 100Å, and the material of the polysilicon material layer 130 can be the same as the material of the third conductive layer 110, but is not limited thereto.

[0056] Please refer to Figure 6 , illustrated is a structural schematic diagram of forming a first conductive layer on both side walls of a first trench portion of a deep trench in one embodiment of the present invention.

[0057] like Figure 6As shown, continue to perform step S103: using an etching process, such as an anisotropic etching process, to remove the polysilicon material layer 130 corresponding to the first groove portion 101.1 region of the deep groove 101 (i.e., the top surface of the second groove portion 101.2 of the deep groove 101) to expose the first isolation layer 120 thereunder. In one embodiment, the polysilicon material layer 130 remaining after a portion of the polysilicon material layer 130 is removed by etching in this step is used as the first conductive layer 130', and the first conductive layer 130' includes two parts, namely, a first part 130'a located on the first isolation layer 120 on one side wall of the first groove portion 101.1 of the deep groove 101 and a second part 130'b located on the first isolation layer 120 on the other side wall of the first groove portion 101.1 of the deep groove 101; that is, the first part 130' 0'a and the second part 130'b are relatively and symmetrically arranged on the area corresponding to the side wall of the first groove portion 101.1 of the deep groove 101 and the two are not in direct contact; illustratively, the shapes of the first part 130'a and the second part 130'b can be the same, and the bottom thereof is conformal to the bottom surface contour of the first isolation layer 120 formed by the second groove portion 101.2 of the deep groove 101 and has an arc shape that is concave in the direction of the perpendicular midline of the first groove portion 101.1 of the deep groove 101, but is not limited to this.

[0058] Please refer to Figure 7 , illustrated is a schematic structural diagram of forming a first ion implantation region and a second ion implantation region on a substrate below a deep trench and on both sides of the deep trench, respectively, in one embodiment of the present invention.

[0059] like Figure 7As shown, step S104 is performed: an ion implantation process is performed on the substrate 100, so as to form a first ion implantation region 141 in a portion of the substrate 100 below the deep trench 101 by using the ion implantation process, and simultaneously form a second ion implantation region 142 in a portion of the substrate 100 on both sides of the deep trench 101. Specifically, the type of ions implanted by the ion implantation process should be opposite to the type of ions implanted when the substrate 100 is doped, that is, in the embodiment of the present invention, the doping ion type for forming the first ion implantation 141 and the second ion implantation 142 can be P-type, such as boron ions, phosphorus ions, etc., but is not limited thereto. In one embodiment, the second ion implantation region 142 can be used as the body region of a semiconductor structure such as a trench gate MOSFET, and the first ion implantation region 141, because of the opposite type of ion conductivity to that doped with the substrate 100, can achieve mutual depletion of carriers, thereby achieving the purpose of increasing the depletion region and the breakdown voltage; and, since the embodiment of the present invention utilizes the ion implantation process for forming the second ion implantation region 142 as the body region to advance and simultaneously form the second ion implantation region 142, this step can also achieve the purpose of saving one ion implantation process.

[0060] In one embodiment, after the first ion implantation area 141 and the second ion implantation area 142 are formed by the ion implantation process, the first ion implantation area 141 and the second ion implantation area 142 may be further subjected to a doping heat treatment, wherein the conductivity type of the doped ions is the same as the conductivity type of the ions implanted when the substrate is subjected to the ion implantation process, for example, the ions of the doping heat treatment may include argon ions, and the process parameters of the doping heat treatment may have a temperature of 1300°C to 1600°C and a time of 3min to 7min, but are not limited thereto. Preferably, the temperature of the doping heat treatment is 1500°C and the time is 5min. Under this setting, the added argon ion doping heat treatment process can repair the surface defects of the substrate 100 surface caused during the ion implantation process, increase the mobility of carriers in the trench gate MOSFET, reduce the on-resistance, and ultimately increase the switching speed of the device.

[0061] Please refer to Figure 8 , illustrated is a structural schematic diagram of forming a second isolation layer in a partial area of ​​a first trench portion of a deep trench in one embodiment of the present invention.

[0062] like Figure 8As shown, step S105 is performed: using at least one of the above deposition processes, a second isolation layer 150 is deposited in the remaining space in the first groove portion 101.1 of the deep groove 101. In one embodiment, the second isolation layer 150 is specifically located between the first part 130'a and the second part 130'b of the first conductive layer 130' and is in direct contact with the first isolation layer 120 (located in the second groove portion 101.2 of the deep groove 101) located therebelow, and the top surface of the second isolation layer 150 needs to be lower than the top surface of the first conductive layer 130', that is, to leave space for the subsequent formation of the second conductive layer. The material of the second isolation layer 150 can be the same as that of the first isolation layer 120 (for example, oxide, silicon dioxide), or it can be different (for example, silicon nitride, silicon dioxide), or the second isolation layer 150 can also be a material different from the material of the first isolation layer 120 and having the same or different dielectric constant, for example, the material of the second conductive layer 150 is hafnium dioxide (HfO2), but it is not limited thereto.

[0063] Please refer to Fig. 9 , illustrated is a schematic structural diagram of forming a second conductive layer in the remaining area of ​​the first trench portion of the deep trench in one embodiment of the present invention.

[0064] like Fig. 9 As shown, continue to perform step S105: further use at least one of the above deposition processes to fill the second conductive layer 160 in the remaining space of the first groove portion 101.1 of the deep groove 101. In one embodiment, the second conductive layer 160 is specifically located on the second isolation layer 150 in the first groove portion 101.1 of the deep groove 101 and is connected to the first portion 130'a and the second portion 130'b of the first conductive layer 130' in the horizontal direction, so as to serve as the control gate 170 of the semiconductor structure, such as a trench gate MOSFET. The second conductive layer 160 is made of the same material as the first conductive layer 130', such as polysilicon, but not limited thereto. Under this setting, the overlapping area between the control gate 170 of the semiconductor structure in the embodiment of the present invention, such as the trench gate MOSFET, and the subsequently formed drain 182 is the area between the second conductive layer 160 and the drain 182, and does not include the width of the first part 130'a and the second part 130'b of the first conductive layer 130' in the horizontal direction. Therefore, the overlapping area between the control gate 170 and the drain 182 is reduced, the gate-drain capacitance of the power semiconductor device is reduced, the switching loss is reduced, and the switching speed is ultimately improved.

[0065] Please refer to Fig.10 , illustrated is a schematic structural diagram of forming a source electrode and a drain electrode in the surface layers of two relatively opposite surfaces of a substrate in one embodiment of the present invention.

[0066] like Fig.10 As shown, the step S105 is then executed: the source 181 and the drain 182 can be formed on the second ion implantation area 142 and the surface of the other side of the substrate 100 (which can be called the bottom surface) by further using an ion implantation process. Specifically, the source 181 is located in the surface layer of the substrate 100 on both sides of the deep trench 101, and the drain 182 is located in another surface layer of the substrate 100 opposite to the surface layer of the substrate 100 where the source 181 is formed. In addition, the doping types of the source 181 and the drain 182 can be specifically distinguished according to the type of the actual device. This is a prior art and will not be described in detail in the embodiments of the present invention.

[0067] It should be understood that based on the above-mentioned method for manufacturing a semiconductor structure, the present invention can obtain a corresponding semiconductor structure, which may specifically include: Substrate 100.

[0068] The first isolation layer 120 is located at the bottom and sidewalls of the deep trench 101 in the substrate 100 .

[0069] The first ion implantation region 141 is located in a portion of the substrate 100 below the deep trench 101 .

[0070] The second ion implantation region 142 is located in a portion of the substrate 100 on both sides of the deep trench 101 .

[0071] The control gate 170 is located in the deep trench 101, and the control gate 170 includes: a first conductive layer 130', the first conductive layer 130' includes a first portion 130'a located on the first isolation layer 120 on one side wall of the first trench portion 101.1 of the deep trench 101 and a second portion 130'b located on the first isolation layer 120 on the other side wall of the first trench portion 101.1 of the deep trench 101 and not in direct contact with the first portion 130'a.

[0072] and a second conductive layer 160 , which is located between the first portion 130 ′ a and the second portion 130 ′ b of the first conductive layer 130 ′ and is connected to the first conductive layer 130 ′.

[0073] The second isolation layer 150 is located below the second conductive layer 160 between the first portion 130 ′ a and the second portion 130 ′ b of the first conductive layer 130 ′ and is in direct contact with the first isolation layer 120 .

[0074] A source electrode 181 and a drain electrode 182 , wherein the source electrode 181 is located in the surface layer of the substrate 100 at both sides of the deep trench 101 , and the drain electrode 182 is located in another surface layer of the substrate 100 opposite to the surface layer of the substrate 100 where the source electrode 181 is formed.

[0075] In summary, the present invention provides a method for manufacturing a semiconductor structure, including: providing a substrate, forming a deep trench and a first isolation layer, the deep trench being located in the substrate, the first isolation layer being located at the bottom and side walls of the deep trench, forming a first conductive layer, which is located on the first isolation layer, and the first conductive layer includes: a first part, which is located on the first isolation layer on one side wall of the deep trench, and a second part, which is located on the first isolation layer on the other side wall of the deep trench and is not in direct contact with the first part, performing an ion implantation process on the substrate to form a first ion implantation region in a portion of the substrate below the deep trench, and forming a second ion implantation region in a portion of the substrate on both sides of the deep trench, to form a second isolation layer and a second conductive layer, the second isolation layer is located between the first portion and the second portion of the first conductive layer and is in direct contact with the first isolation layer, and the second conductive layer is located on the second isolation layer and is connected to the first conductive layer to serve as a control gate of the semiconductor structure.

[0076] In the present invention, firstly, by utilizing the characteristic that the oxidation rate of polycrystalline silicon is faster than that of the substrate (such as single crystal silicon), first isolation layers with different thicknesses are formed in different parts of the deep trench to increase the distance between the control gate and the drain, thereby achieving the purpose of reducing the gate-drain capacitance; secondly, by advancing the process technology of the second ion implantation region as the body region to before the formation of the control gate including the second conductive layer, and utilizing the ion implantation process to synchronously form the first ion implantation region in the corresponding substrate at the bottom of the deep trench, the unexpected effect is obtained: one ion implantation process is saved, and the first ion implantation region (located between the control gate and the drain) is opposite to the conductive type of the substrate, so that carriers can be mutually depleted, thereby achieving the purpose of increasing the depletion region and the breakdown voltage; then, a second conductive layer is deposited in the deep trench, and combined with the first conductive layer located on the side wall of the deep trench, a control gate of a special shape is formed, thereby achieving the unexpected effect of reducing the overlapping area between the control gate and the drain, reducing the gate-drain capacitance of the power semiconductor device, reducing the switching loss, and ultimately improving the switching speed.

[0077] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0078] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device, electronic device, and computer-readable storage medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0079] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; forming a deep trench and a first isolation layer, wherein the deep trench is located in the substrate, and the first isolation layer is located at the bottom and sidewalls of the deep trench; A first conductive layer is formed on the first isolation layer, and the first conductive layer includes: A first portion is located on a first isolation layer on a side wall of the deep trench; a second portion, located on the first isolation layer on the other sidewall of the deep trench and not in direct contact with the first portion; Performing an ion implantation process on the substrate to form a first ion implantation region in a portion of the substrate below the deep trench, and a second ion implantation region in a portion of the substrate on both sides of the deep trench; A second isolation layer and a second conductive layer are formed, wherein the second isolation layer is located between the first portion and the second portion of the first conductive layer and is in direct contact with the first isolation layer, and the second conductive layer is located on the second isolation layer and is connected to the first conductive layer to serve as a control gate of the semiconductor structure.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The deep groove includes a first groove portion and a second groove portion, the second groove portion is located below the first groove portion in a vertical direction, and a width of the second groove portion in a horizontal direction is smaller than a width of the first groove portion in the horizontal direction.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein: The step of forming the first isolation layer comprises: forming a third conductive layer in the second trench portion of the deep trench; The substrate is subjected to thermal oxidation treatment to oxidize and convert the exposed substrate of the third conductive layer and the sidewall of the first groove portion of the deep groove into the first isolation layer; wherein the thickness of the first isolation layer in the second groove portion of the deep groove is greater than its thickness on the sidewall of the first groove portion of the deep groove.

4. The method for manufacturing a semiconductor structure according to claim 3, wherein: The materials of the first conductive layer, the second conductive layer and the third conductive layer include polysilicon.

5. The method for manufacturing a semiconductor structure according to claim 4, wherein: The step of forming the first conductive layer comprises: forming a polysilicon material layer on the first isolation layer; The polysilicon material layer on the top surface of the second trench portion of the deep trench is removed to expose the top surface of the first isolation layer in the second trench portion of the deep trench.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein: A top surface of the second isolation layer is lower than a top surface of the first conductive layer.

7. The method for manufacturing a semiconductor structure according to claim 1, wherein: After the substrate is subjected to an ion implantation process, the method further comprises: The first ion implantation region and the second ion implantation region are subjected to a doping heat treatment, wherein the conductivity type of the doped ions is the same as the conductivity type of the ions implanted during the ion implantation process on the substrate.

8. The method for manufacturing a semiconductor structure according to claim 7, wherein: The process parameters of the doping heat treatment include: a temperature range of 1300° C. to 1600° C., and a time range of 3 min to 7 min.

9. The method for manufacturing a semiconductor structure according to claim 1, wherein: The second isolation layer has a different dielectric constant from the first isolation layer.

10. The method for manufacturing a semiconductor structure according to claim 1, wherein: Also includes: A source electrode and a drain electrode are formed, wherein the source electrode is located in the surface layer of the substrate at both sides of the deep trench, and the drain electrode is located in another surface layer of the substrate opposite to the surface layer of the substrate where the source electrode is formed.

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