Semiconductor assembly

Abstract

A semiconductor device mainly includes a first fin structure and a second fin structure disposed on a substrate, a bump disposed between the first fin structure and the second fin structure, a first recess disposed between the first fin structure and the bump, and a second recess disposed between the second fin structure and the bump. Wherein the top surface of the bump comprises an upper concave curved surface, the width of the bump is more than twice greater than the width of the first fin-shaped structure, and the height of the bump is less than one fourth of the height of the first fin-shaped structure.

Description

Technical Field

[0001] The invention relates to a semiconductor component, in particular to a semiconductor component with a concave curved bump formed between fin-shaped structures. Background Art

[0002] In recent years, as the size of field effect transistors (FETs) components continues to shrink, the development of existing planar field effect transistor components has faced the limit of manufacturing process. In order to overcome the limitation of manufacturing process, it has become the current mainstream development trend to replace planar transistor components with non-planar field effect transistor components, such as fin field effect transistor (Fin FET) components. Since the three-dimensional structure of the fin field effect transistor component can increase the contact area between the gate and the fin structure, the gate can further increase the control of the carrier channel area, thereby reducing the drain induced barrier lowering (DIBL) effect faced by small-sized components and suppressing the short channel effect (SCE). Furthermore, since the fin field effect transistor component has a wider channel width at the same gate length, it can obtain double the drain drive current. Even more, the threshold voltage of the transistor component can be regulated by adjusting the work function of the gate.

[0003] In the current manufacturing process of fin field effect transistor components, after shallow trench isolation is formed around the fin structure, defects are often caused on the top due to etching or various factors in the manufacturing process, thus affecting the product yield. Therefore, how to improve the existing fin field effect transistor manufacturing process and architecture is an important issue today. Summary of the invention

[0004] An embodiment of the present invention discloses a semiconductor component, which mainly includes a first fin-shaped structure and a second fin-shaped structure disposed on a substrate, a bump disposed between the first fin-shaped structure and the second fin-shaped structure, a first groove disposed between the first fin-shaped structure and the bump, and a second groove disposed between the second fin-shaped structure and the bump. The top surface of the bump includes an upward concave surface, the width of the bump is more than twice the width of the first fin-shaped structure, and the height of the bump is less than one-fourth of the height of the first fin-shaped structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figures 1 to 6 It is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0006] Explanation of symbols

[0007] 12: Base

[0008] 14: Fin structure

[0009] 16: Fin structure

[0010] 18: Fin structure

[0011] 20: Fin structure

[0012] 22: Fin structure

[0013] 24: Bump

[0014] 26: Groove

[0015] 28: Groove

[0016] 30: Shallow Trench Isolation

[0017] 32: Gate structure

[0018] 34: Gate dielectric layer

[0019] 36: Gate material layer

[0020] 42: Bump

[0021] 44: Bump

[0022] 46: Bump DETAILED DESCRIPTION

[0023] Please refer to Figures 1 to 6 , Figures 1 to 6 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor component according to an embodiment of the present invention, wherein Figure 1 A top view of a semiconductor device is shown in accordance with an embodiment of the present invention. Figures 2 to 6 Then Figure 1 Schematic diagram of the cross section along the tangent line AA'. Figure 1 to Figure 2 As shown, a substrate 12 is first provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, and then a plurality of fin structures 14, 16, 18, 20, 22 are formed to extend along a first direction (such as the X direction) on the substrate 12. In this embodiment, although five fin structures 14, 16, 18, 20, 22 are provided on the substrate 12, the number of fin structures provided can be adjusted arbitrarily according to product requirements and is not limited thereto.

[0024] According to one embodiment of the present invention, the fin structures 14, 16, 18, 20, and 22 are preferably manufactured by sidewall image transfer (SIT) technology, and the procedure generally includes: providing a layout pattern to a computer system, and defining the corresponding pattern in a photomask through appropriate calculations. Subsequently, a plurality of equidistant and equal-width patterned sacrificial layers can be formed on the substrate through photolithography and etching processes, so that their individual appearances are strip-shaped. Thereafter, deposition and etching processes are sequentially performed to form spacers on each sidewall of the patterned sacrificial layer. Subsequently, the patterned sacrificial layer is removed, and an etching process is performed under the coverage of the spacers, so that the pattern formed by the spacers is transferred to the substrate, and then the desired patterned structure, such as strip-shaped patterned fin structures 14, 16, 18, 20, and 22, is obtained by a fin structure cutting process (fin cut).

[0025] In addition, the formation method of the fin-shaped structures 14, 16, 18, 20, 22 may include first forming a patterned mask (not shown) on the substrate 12, and then performing an etching process to transfer the pattern of the patterned mask to the substrate 12 to form the fin-shaped structures 14, 16, 18, 20, 22. In addition, the formation method of the fin-shaped structures 14, 16, 18, 20, 22 may also include first forming a patterned hard mask layer (not shown) on the substrate 12, and using an epitaxial process to grow a semiconductor layer such as silicon germanium on the substrate 12 exposed from the patterned hard mask layer, and this semiconductor layer can serve as the corresponding fin-shaped structures 14, 16, 18, 20, 22. These embodiments of forming the fin-shaped structures 14, 16, 18, 20, 22 are all within the scope of the present invention.

[0026] Then Figure 3 As shown, a fin structure removal and / or fin structure cutting process (fin cut) can be performed. For example, a patterned mask (not shown) such as a patterned photoresist can be first formed to cover the leftmost and rightmost fin structures 14 and 22, and then the three middle fin structures 16, 18, and 20 are removed by etching, so that the remaining surface of the substrate 12 between the fin structure 14 and the fin structure 22 forms a large-area bump 24 that is slightly higher than the left side of the fin structure 14 and the right side of the fin structure 22, a groove 26 is arranged between the left fin structure 14 and the bump 24, and another groove 28 is arranged between the right fin structure 22 and the bump 24.

[0027] In this embodiment, the etching process performed when removing the three middle fin structures 16, 18, 20 is preferably performed to reduce carbon tetrafluoride (CF 4) and adding hydrogen bromide (HBr) and other gas components to remove the fin structures 16, 18, 20 and form the aforementioned bumps 24. In other words, the etching process at this stage is to increase the hydrogen bromide (HBr) to carbon tetrafluoride (CF 4 ) to achieve the ratio.

[0028] From the details, the top surface of the bump 24 formed in this stage preferably has an upward concave surface, wherein the angle between the middle bottom of the concave surface and the left upward surface or the middle bottom and the right upward surface is preferably less than 40 degrees or more preferably between 20-30 degrees. In addition, since the original five fin-like structures 14, 16, 18, 20, 22 preferably have the same width and the same spacing and the bump 24 itself is formed after removing the three middle fin-like structures 16, 18, 20, the overall width of the bump 24 is preferably greater than twice or three times the width of the left fin structure 14 or the right fin structure 22 itself, or preferably between four and six times the width of the left fin structure 14 or the right fin structure 22 itself. Secondly, the height of the bump 24 is preferably less than one-fourth of the height of the left fin structure 14 or the right fin structure 22 itself, wherein the so-called height of the bump 24 preferably refers to the distance from the bottom of the bump 24 to the highest point on both sides of the bump 24.

[0029] Then as Figure 4 As shown, a shallow trench isolation (STI) 30 is formed to surround the fin structures 14 and 22, for example, surround the fin structures 14 and 22 on both sides and be disposed on the bump 24. In the present embodiment, the shallow trench isolation 30 can be formed by first using a flowable chemical vapor deposition (FCVD) process to form a silicon oxide layer on the substrate 12 and completely cover the fin structures 14 and 22. Then, a chemical mechanical polishing (CMP) process is used in combination with an etching process to remove part of the silicon oxide layer, so that the remaining silicon oxide layer is slightly lower than the surface of the fin structures 14 and 22 to form the shallow trench isolation 30.

[0030] Please refer to Figure 5 , Figure 5 FIG. 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention, wherein Figure 5 The left half is a schematic diagram of the structure of different types of bumps, and Figure 5 The right half is a schematic diagram of the structure of different types of bumps corresponding to the top of the fin structure. Figure 5As shown, after actually using the aforementioned etching recipe to remove the three middle fin structures 16, 18, and 20, the present invention can use different etching parameters to adjust different types of bumps, including a bump 42 with a flat top, a bump 44 with a wavy top surface, a bump 46 with a mountain-shaped top surface, and the bump 24 with an upper concave surface in the aforementioned embodiment, wherein the width of each bump 42, 44, and 46 is smaller than the width of the bump 24, for example, the width of each bump 42, 44, and 46 is preferably smaller than 90%, 80%, 70%, 60%, 50%, or even less than 50% of the width of the bump 24.

[0031] It should be noted that after the oxide is filled into the upper part of the bumps 24, 42, 44, 46 to form the shallow trench isolation 30, a stress is preferably generated between the left fin structure 14 and the right fin structure 22, and this stress can cause the left fin structure 14 and the right fin structure 22 to bend under the best condition. According to the experimental data of the preferred embodiment of the present invention, the bending degree of the fin structure is preferably inversely proportional to the defect count of the component, that is, the bump 24 with the concave surface formed by the aforementioned manufacturing process generates stress to cause the fin structure to bend, which can ultimately reduce the defect count of the component as a whole. However, it should be noted that according to the experimental data of the present invention, Figure 5 From the bending of the top of the right half of the fin-shaped structure, the degree of bending of the bump 24 with the upper concave surface is better than that of the bump 44 with the wavy top surface, the degree of bending of the bump 44 with the wavy top surface is better than that of the bump 42 with the flat top, and the degree of bending of the bump 42 with the flat top is better than that of the bump 46 with the mountain-shaped top surface. In other words, from the overall defect count, the number of defects of the bump 24 with the upper concave surface is better than that of the bump 44 with the wavy top surface, the number of defects of the bump 44 with the wavy top surface is less than that of the bump 42 with the flat top, and the number of defects of the bump 42 with the flat top is greater than that of the bump 46 with the mountain-shaped top surface. Overall, the bump 24 with the upper concave surface is better than the other bumps 42, 44, and 46 in terms of bending and defect count.

[0032] Please refer to Figure 6 , Figure 6 Continuation of an embodiment of the present invention Figure 4 Schematic diagram of the manufacturing process. Figure 6As shown, at least one gate structure 32 may then be formed on the fin structures 14, 22 and the shallow trench isolation 30. In the present embodiment, the gate structure 32 may be fabricated by a gate first fabrication process, a gate last fabrication process of a high-k first fabrication process, or a gate last fabrication process of a high-k last fabrication process according to the fabrication process requirements. For example, a gate dielectric layer 34 or a dielectric layer composed of silicon oxide, a gate material layer 36 composed of polycrystalline silicon, and a selective hard mask (not shown) can be sequentially formed on the substrate 12, and a pattern transfer process is performed using a patterned photoresist (not shown) as a mask to remove part of the gate material layer 36 and part of the gate dielectric layer 34 by a single etching or successive etching steps, and then the patterned photoresist is stripped off to form a gate structure 32 composed of the patterned gate dielectric layer 34 and the patterned gate material layer 36 on the substrate 12.

[0033] Then, a subsequent standard transistor manufacturing process may be performed according to the manufacturing process requirements, for example, a spacer may be formed on the sidewalls of the gate structure 32, a source / drain region may be formed in the substrate 12 or the fin structure 14, 22 on both sides of the spacer, an interlayer dielectric layer may be formed on the gate structure 32, and a contact plug may be formed in the interlayer dielectric layer to electrically connect the source / drain region. Since the standard transistor manufacturing process is well known in the art, it will not be described in detail here.

[0034] In summary, the present invention mainly adjusts the recipe of etching gas during the fin structure removal or cutting process, such as increasing hydrogen bromide (HBr) to carbon tetrafluoride (CF 4 ) to remove most (such as three in the aforementioned embodiment) of the multiple (such as a total of five) fin-like structures, and thereby form a large-area bump between the remaining two fin structures. According to a preferred embodiment of the present invention, the width of the formed bump itself is not only greater than two or three times the width of the remaining fin structures on both sides, but its top surface also preferably has an upward concave surface. The special contour of this concave surface can generate stress after the subsequent formation of shallow trench isolation and cause the fin-like structures on both sides to bend. As the degree of bending of the fin structure increases, the number of defects of the entire component will also decrease, thereby improving the overall yield of the product.

[0035] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor component, characterized in that: Include: A first fin-shaped structure and a second fin-shaped structure are disposed on a substrate; and The bump is disposed between the first fin-shaped structure and the second fin-shaped structure, wherein the top surface of the bump comprises an upward concave curved surface.

2. The semiconductor device according to claim 1, further comprising: A first groove is disposed between the first fin-shaped structure and the bump; and The second groove is disposed between the second fin-shaped structure and the protrusion. 3 . The semiconductor device as claimed in claim 1 , wherein the width of the bump is more than twice the width of the first fin structure. The semiconductor device as claimed in claim 2 , wherein the width of the bump is more than three times greater than the width of the first fin structure. The semiconductor device as claimed in claim 2 , wherein the bump height is less than one quarter of the height of the first fin structure.

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