Semiconductor device

Abstract

Embodiments relate to a semiconductor device. According to one embodiment, a semiconductor device includes first to fourth electrodes, first to third semiconductor regions, first and second insulating portions, and a connecting portion. The third electrode includes: a first electrode region extending in the second direction and aligned with the second semiconductor region in the third direction; a second electrode region extending along the third direction and arranged with the second semiconductor region in the second direction; and a third electrode region connecting the first electrode region and the second electrode region. The first insulating portion includes: a first insulating region including first and second insulating portions; a second insulating region including third and fourth insulating portions; and a third insulating region including a fifth insulating portion and a sixth insulating portion. The fourth electrode is arranged with the first semiconductor region and the third electrode. The connecting portion has: a first connecting portion located between the third insulating region and the second insulating portion; and a second connecting portion between the third insulating region and the first connecting portion.

Description

[0001] Related Applications

[0002] This application claims priority based on Japanese Patent Application No. 2023-156430 (filing date: September 21, 2023), and the entire contents of the application are incorporated herein by reference. Technical Field

[0003] Embodiments relate to a semiconductor device. Background Art

[0004] Semiconductor devices such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor) are used for power conversion, etc. It is desired to improve the avalanche resistance of semiconductor devices. Summary of the invention

[0005] A semiconductor device of an embodiment includes: a first electrode; a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type; a third semiconductor region of the first conductivity type; a second electrode; a third electrode; a first insulating portion; a fourth electrode; a second insulating portion and a connecting portion. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The second electrode is provided on the third semiconductor region. The second electrode is electrically connected to the third semiconductor region. The third electrode includes a first electrode region, a second electrode region and a third electrode region. The first electrode region extends along a second direction. The second direction is perpendicular to a first direction from the first electrode toward the second electrode. The first electrode region is arranged with the second semiconductor region in a third direction. The third direction is perpendicular to the first direction and intersects with the second direction. The second electrode region extends along the third direction. The second electrode region is arranged with the second semiconductor region in the second direction. The third electrode region connects the first electrode region and the second electrode region. The first insulating portion includes a first insulating region, a second insulating region and a third insulating region. The first insulating region includes a first insulating portion and a second insulating portion. The first insulating portion is arranged between the second semiconductor region and the first electrode region in the third direction. The second insulating portion is arranged between the first semiconductor region and the first electrode region in the first direction. The second insulating region includes a third insulating portion and a fourth insulating portion. The third insulating portion is arranged between the second semiconductor region and the second electrode region in the second direction. The fourth insulating portion is arranged between the first semiconductor region and the second electrode region in the first direction. The third insulating region connects the first insulating region and the second insulating region. The third insulating region includes a fifth insulating portion and a sixth insulating portion. The fifth insulating portion is arranged between the second semiconductor region and the third electrode region in the fourth direction. The fourth direction is perpendicular to the first direction and intersects with the second direction and the third direction. The sixth insulating portion is arranged between the first semiconductor region and the third electrode region in the first direction. The fourth electrode is arranged with the first semiconductor region and the third electrode in the second direction and the third direction. The second insulating portion is arranged between the fourth electrode and the first semiconductor region and between the fourth electrode and the third electrode in the second direction and the third direction. The connecting portion is arranged between the third insulating region and the second insulating portion in the second direction, the third direction and the fourth direction. The connection portion electrically connects the second electrode and the second semiconductor region.The connection portion includes a first connection portion and a second connection portion. The first connection portion is located between the third insulating region and the second insulating portion in the second direction, the third direction, and the fourth direction. The second connection portion is located between the third insulating region and the first connection portion in the fourth direction.

[0006] A semiconductor device of an embodiment includes: a first electrode; a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type; a third semiconductor region of the first conductivity type; a second electrode; a third electrode; a first insulating portion; a fourth electrode; a second insulating portion and a connecting portion. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The second electrode is provided on the third semiconductor region. The second electrode is electrically connected to the third semiconductor region. The third electrode includes a first electrode region, a second electrode region and a third electrode region. The first electrode region extends along a second direction. The second direction is perpendicular to a first direction from the first electrode toward the second electrode. The first electrode region is arranged with the second semiconductor region in a third direction. The third direction is perpendicular to the first direction and intersects with the second direction. The second electrode region extends along the third direction. The second electrode region is arranged with the second semiconductor region in the second direction. The third electrode region connects the first electrode region and the second electrode region. The first insulating portion includes a first insulating region, a second insulating region and a third insulating region. The first insulating region includes a first insulating portion and a second insulating portion. The first insulating portion is arranged between the second semiconductor region and the first electrode region in the third direction. The second insulating portion is arranged between the first semiconductor region and the first electrode region in the first direction. The second insulating region includes a third insulating portion and a fourth insulating portion. The third insulating portion is arranged between the second semiconductor region and the second electrode region in the second direction. The fourth insulating portion is arranged between the first semiconductor region and the second electrode region in the first direction. The third insulating region connects the first insulating region and the second insulating region. The third insulating region includes a fifth insulating portion and a sixth insulating portion. The fifth insulating portion is arranged between the second semiconductor region and the third electrode region in the fourth direction. The fourth direction is perpendicular to the first direction and intersects with the second direction and the third direction. The sixth insulating portion is arranged between the first semiconductor region and the third electrode region in the first direction. The fourth electrode is arranged with the first semiconductor region and the third electrode in the second direction and the third direction. The second insulating portion is arranged between the fourth electrode and the first semiconductor region and between the fourth electrode and the third electrode in the second direction and the third direction. The connecting portion is arranged between the third insulating region and the second insulating portion in the second direction, the third direction and the fourth direction. The connection portion electrically connects the second electrode and the second semiconductor region.The width of the connection portion in the fourth direction is greater than the width of the connection portion in the second direction and the width of the connection portion in the third direction.

[0007] According to the present embodiment, a semiconductor device capable of improving avalanche resistance can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a plan view showing the semiconductor device according to the first embodiment.

[0009] Figure 2 It is a plan view showing a part of the semiconductor device according to the first embodiment.

[0010] Figure 3 It is a cross-sectional view showing a part of the semiconductor device according to the first embodiment.

[0011] Figure 4 It is a cross-sectional view showing a part of the semiconductor device according to the first embodiment.

[0012] Figure 5 It is a cross-sectional view showing a part of the semiconductor device according to the first embodiment.

[0013] Figure 6 This is a cross-sectional view showing a portion of a semiconductor device according to a first modification of the first embodiment.

[0014] Figure 7 This is a cross-sectional view showing a portion of a semiconductor device according to a second modification of the first embodiment.

[0015] Figure 8 This is a cross-sectional view showing a portion of a semiconductor device according to a third modified example of the first embodiment.

[0016] Fig. 9 It is a plan view showing a part of the semiconductor device according to the second embodiment.

[0017] Fig.10 It is a cross-sectional view showing a part of the semiconductor device according to the second embodiment.

[0018] Fig.11 It is a plan view showing a part of the semiconductor device according to the third embodiment.

[0019] Fig.12 It is a cross-sectional view showing a part of the semiconductor device according to the third embodiment.

[0020] Fig.13 It is a plan view showing a part of the semiconductor device according to the fourth embodiment.

[0021] Fig.14It is a cross-sectional view showing a part of the semiconductor device according to the fourth embodiment.

[0022] Fig.15 (a)~ Fig.15 (h) is a cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the first embodiment.

[0023] Fig.16 (a)~ Fig.16 (h) is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second embodiment. DETAILED DESCRIPTION

[0024] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0025] The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the size between parts, etc. are not necessarily the same as the actual ones. Even when the same part is shown, the size and ratio may be shown differently depending on the drawings.

[0026] In the present specification and each drawing, the same reference numerals are given to the same elements as those already described, and detailed description thereof will be appropriately omitted.

[0027] In the following description and drawings, n + 、n - and p + , p indicate the relative level of each impurity concentration. That is, the expression marked with "+" has a relatively higher impurity concentration than the expression without any "+" or "-", and the expression marked with "-" has a relatively lower impurity concentration than the expression without any "+" or "-". These expressions indicate the relative level of the actual impurity concentration after these impurities compensate for each other when both p-type impurities and n-type impurities are included in each region.

[0028] Each embodiment described below may be implemented by inverting the p-type and n-type of each semiconductor region.

[0029] (First Embodiment)

[0030] Figure 1 It is a plan view showing the semiconductor device according to the first embodiment.

[0031] Figure 2 It is a plan view showing a part of the semiconductor device according to the first embodiment.

[0032] Figure 3 to Figure 5 It is a cross-sectional view showing a part of the semiconductor device according to the first embodiment.

[0033] Figure 2express Figure 1 Region II is shown.

[0034] Figure 3 yes Figure 2 A cross-sectional view taken along line III-III is shown.

[0035] Figure 4 yes Figure 2 A cross-sectional view taken along line IV-IV is shown.

[0036] Figure 5 yes Figure 2 A cross-sectional view taken along line VV is shown.

[0037] The semiconductor device 100 of the first embodiment is a vertical MOSFET. The semiconductor device 100 is a MOSFET of a so-called dot FP structure.

[0038] like Figure 1 to Figure 5 As shown, the semiconductor device 100 includes a drain electrode 11 (first electrode), a source electrode 12 (second electrode), a gate electrode 13 (third electrode), an FP electrode 14 (fourth electrode), a gate pad 15, - type drift region 21 (first semiconductor region), p-type base region 22 (second semiconductor region), n + type source region 23 (third semiconductor region), p + Type contact area 27, n + The first conductivity type is n-type and the second conductivity type is p-type. Figure 2 In FIG. 5 , the source electrode 12 and the insulating layer 51 are omitted.

[0039] In the description of each of the following embodiments, a first direction D1, a second direction D2, and a third direction D3 are used. The direction from the drain electrode 11 toward the source electrode 12 is set as the first direction D1. One of the directions perpendicular to the first direction D1 is set as the second direction D2. One of the directions intersecting the first direction D1 and the second direction D2 is set as the third direction D3. The third direction D3 can be a direction perpendicular to the second direction D2 or a direction inclined relative to the second direction D2. In addition, a direction perpendicular to the first direction D1 and intersecting the second direction D2 and the third direction D3 is set as a fourth direction D4. In addition, in order to facilitate the understanding of the description, the direction from the drain electrode 11 toward the source electrode 12 is set as the top, and the opposite direction is set as the bottom, but these directions are not related to the direction of gravity. Observation from above is set as "looking down".

[0040] like Figure 1As shown, a source electrode 12 and a gate pad 15 are provided on the upper surface of the semiconductor device 100. The source electrode 12 and the gate pad 15 are electrically isolated from each other.

[0041] like Figure 3 to Figure 5 As shown in FIG. 1 , a drain electrode 11 is provided on the lower surface of the semiconductor device 100. + The n-type drain electrode 28 is provided with an n-type drift region 21. The n-type drift region 21 is provided with an n-type drift region 21. + The p-type drain electrode 28 is electrically connected to the drain electrode 11. A p-type base region 22 is provided on the n-type drift region 21. + Type source region 23 and p + In the p-type base region 22 and n + The source electrode 12 is provided on the type source region 23 via the insulating layer 51. The source electrode 12 is connected to the source region 23 via the connecting portion 40 and the p + The p-type contact region 27 and the p-type base region 22 and the n-type + The type source region 23 is electrically connected.

[0042] The gate electrode 13 is arranged with the p-type base region 22 in the second direction D2, the third direction D3, and the fourth direction D4. Figure 2 to Figure 5 As shown, the gate electrode 13 includes a first electrode region 13 a , a second electrode region 13 b and a third electrode region 13 c .

[0043] The first electrode region 13a extends along the second direction D2. The first electrode region 13a is aligned with the p-type base region 22 in the third direction D3. In the semiconductor device 100, a portion of the first electrode region 13a is aligned with the n-type base region 22 in the third direction D3. - In the semiconductor device 100, a portion of the first electrode region 13a is aligned with the n-type drift region 21 in the third direction D3. + The first electrode region 13a is aligned with the connecting portion 40 in the third direction D3 in the semiconductor device 100.

[0044] The second electrode region 13b extends along the third direction D3. The second electrode region 13b is aligned with the p-type base region 22 in the second direction D2. In the semiconductor device 100, a portion of the second electrode region 13b is aligned with the n-type base region 22 in the second direction D2. - In the semiconductor device 100, a portion of the second electrode region 13b is aligned with the n-type drift region 21 in the second direction D2. + The second electrode region 13 b is aligned with the type source region 23. In the semiconductor device 100, a portion of the second electrode region 13 b is aligned with the connection portion 40 in the second direction D2.

[0045] The third electrode region 13c connects the first electrode region 13a and the second electrode region 13b. The third electrode region 13c is located at the intersection of the first electrode region 13a and the second electrode region 13b. In the semiconductor device 100, the third electrode region 13c is aligned with the p-type base region 22 in the fourth direction D4. In the semiconductor device 100, a portion of the third electrode region 13c is aligned with the n-type base region 22 in the fourth direction D4. - In the semiconductor device 100, a portion of the third electrode region 13c is aligned with the n-type drift region 21 in the fourth direction D4. + In the semiconductor device 100, a portion of the third electrode region 13c is aligned with the p-type source region 23 in the fourth direction D4. + The contact area 27 and the connecting portion 40 are arranged.

[0046] In the semiconductor device 100, the upper end of the third electrode region 13c is located below the upper end of the first electrode region 13a. The upper end of the third electrode region 13c is located below the upper end of the second electrode region 13b. The upper end of the first electrode region 13a is located at the same height as the upper end of the second electrode region 13b. The upper end of the first electrode region 13a may be located at a different height from the upper end of the second electrode region 13b.

[0047] In the semiconductor device 100, the lower ends of the first electrode region 13a, the second electrode region 13b, and the third electrode region 13c are located at the same height. The lower ends of the first electrode region 13a, the second electrode region 13b, and the third electrode region 13c may be located at different heights.

[0048] In the semiconductor device 100, the lower ends of the first electrode region 13a, the second electrode region 13b, and the third electrode region 13c are respectively located above the lower end of the FP electrode 14. In the semiconductor device 100, the lower ends of the first electrode region 13a, the second electrode region 13b, and the third electrode region 13c are respectively located above the center of the upper end of the FP electrode 14 and the lower end of the FP electrode 14. Figure 3 to Figure 5 In FIG. 1 , the position of the center between the upper end of the FP electrode 14 and the lower end of the FP electrode 14 is indicated by a single-dot chain line.

[0049] The gate insulating portion 31 is disposed between the gate electrode 13 and the p-type base region 22 in the second direction D2, the third direction D3, and the fourth direction D4. Figure 2 to Figure 5 As shown, the gate insulating portion 31 includes a first insulating region 31 a , a second insulating region 31 b and a third insulating region 31 c .

[0050] The first insulating region 31a includes a first insulating portion 31a1 and a second insulating portion 31a2. The first insulating portion 31a1 is disposed between the p-type base region 22 and the first electrode region 13a in the third direction D3. The second insulating portion 31a2 is disposed between the n-type drift region 21 and the first electrode region 13a in the first direction D1. The second insulating portion 31a2 is located below the first electrode region 13a.

[0051] The second insulating region 31b includes a third insulating portion 31b1 and a fourth insulating portion 31b2. The third insulating portion 31b1 is disposed between the p-type substrate region 22 and the second electrode region 13b in the second direction D2. The fourth insulating portion 31b2 is disposed between the n-type substrate region 22 and the second electrode region 13b in the first direction D1. - The fourth insulating portion 31b2 is located between the type drift region 21 and the second electrode region 13b.

[0052] The third insulating region 31c connects the first insulating region 31a and the second insulating region 31b. The third insulating region 31c is located at the intersection of the first insulating region 31a and the second insulating region 31b. Figure 5 As shown, the third insulating region 31c includes a fifth insulating portion 31c1 and a sixth insulating portion 31c2. The fifth insulating portion 31c1 is disposed between the p-type base region 22 and the third electrode region 13c in the fourth direction D4. The sixth insulating portion 31c2 is disposed between the n-type drift region 21 and the third electrode region 13c in the first direction D1. The sixth insulating portion 31c2 is located below the third electrode region 13c.

[0053] In the semiconductor device 100, the lower end of the second insulating portion 31a2 (first insulating region 31a), the lower end of the fourth insulating portion 31b2 (second insulating region 31b), and the lower end of the sixth insulating portion 31c2 (third insulating region 31c) are located at the same height. The lower end of the second insulating portion 31a2 (first insulating region 31a), the lower end of the fourth insulating portion 31b2 (second insulating region 31b), and the lower end of the sixth insulating portion 31c2 (third insulating region 31c) may also be located at different heights.

[0054] In the semiconductor device 100, the lower end of the second insulating portion 31a2 (first insulating region 31a), the lower end of the fourth insulating portion 31b2 (second insulating region 31b), and the lower end of the sixth insulating portion 31c2 (third insulating region 31c) are respectively located above the lower end of the FP electrode 14. In the semiconductor device 100, the lower end of the second insulating portion 31a2 (first insulating region 31a), the lower end of the fourth insulating portion 31b2 (second insulating region 31b), and the lower end of the sixth insulating portion 31c2 (third insulating region 31c) are respectively located above the center of the upper end of the FP electrode 14 and the lower end of the FP electrode 14.

[0055] In the semiconductor device 100, the thickness T1 of the first insulating portion 31a1 in the third direction D3, the thickness T3 of the third insulating portion 31b1 in the second direction D2, and the thickness T5 of the fifth insulating portion 31c1 in the fourth direction D4 are the same. The thickness T1, thickness T3, and thickness T5 may be different.

[0056] In the semiconductor device 100, the thickness T2 of the second insulating portion 31a2 in the first direction D1, the thickness T4 of the fourth insulating portion 31b2 in the first direction D1, and the thickness T6 of the sixth insulating portion 31c2 in the first direction D1 are the same. The thickness T2, thickness T4, and thickness T6 may be different.

[0057] In the semiconductor device 100, the thickness T2 is the same as the thickness T1. The thickness T2 may be different from the thickness T1. In the semiconductor device 100, the thickness T4 is the same as the thickness T3. The thickness T4 may be different from the thickness T3. In the semiconductor device 100, the thickness T6 is the same as the thickness T5. The thickness T6 may be different from the thickness T5.

[0058] The gate electrode 13 is electrically connected to the gate pad 15. The gate pad 15 is electrically isolated from the source electrode 12. The gate electrode 13 may be electrically connected to the gate pad 15 via a gate wiring layer (not shown).

[0059] The FP electrode 14 is connected to the n electrode in the second direction D2, the third direction D3 and the fourth direction D4. - In the semiconductor device 100, a portion of the FP electrode 14 is aligned with the p-type base region 22 in the second direction D2, the third direction D3, and the fourth direction D4. A portion of the FP electrode 14 is aligned with the n-type base region 22 in the second direction D2, the third direction D3, and the fourth direction D4. + Type source region 23 is arranged.

[0060] The FP insulating portion 32 is disposed between the FP electrode 14 and the n electrode 14 in the second direction D2, the third direction D3, and the fourth direction D4.- In the semiconductor device 100, a portion of the FP insulating portion 32 is provided between the FP electrode 14 and the p-type base region 22 in the second direction D2, the third direction D3, and the fourth direction D4. A portion of the FP insulating portion 32 is provided between the FP electrode 14 and the n-type drift region 21 in the second direction D2, the third direction D3, and the fourth direction D4. + A portion of the FP insulating portion 32 is disposed between the FP electrode 14 and the n type source region 23 in the first direction D1. - The FP electrode 14 is electrically connected to the source electrode 12.

[0061] The connection portion 40 is disposed between the third insulating region 31c of the gate insulating portion 31 and the FP insulating portion 32 in the second direction D2, the third direction D3, and the fourth direction D4. The connection portion 40 connects the source electrode 12 and the p-type base region 22 (p + The connection portion 40 includes a first connection portion 41 and a second connection portion 42.

[0062] The first connection portion 41 is located between the third insulating region 31c of the gate insulating portion 31 and the FP insulating portion 32 in the second direction D2, the third direction D3, and the fourth direction D4. In the first direction D1, a p-type substrate region 22 is provided between the first connection portion 41 and the p-type substrate region 22. + The first connection portion 41 connects the source electrode 12 to the p-type base region 22 (p + Type contact area 27) is electrically connected.

[0063] The second connection portion 42 is located between the third insulating region 31c and the first connection portion 41 in the fourth direction D4. In the first direction D1, a p-type substrate region 22 is provided between the second connection portion 42 and the p-type substrate region 22. + The second connection portion 42 connects the source electrode 12 to the p-type base region 22 (p + Type contact area 27) is electrically connected.

[0064] In the semiconductor device 100, the second connection portion 42 contacts the third insulating region 31c. In the semiconductor device 100, the upper end of the third electrode region 13c is located below the lower end of the second connection portion 42. In the semiconductor device 100, the third electrode region 13c is not aligned with the second connection portion 42 in the fourth direction D4.

[0065] In the semiconductor device 100, the width W3a of the first connection portion 41 in the fourth direction D4 is the same as the width W3b of the second connection portion 42 in the fourth direction D4. The width W3a may be different from the width W3b. In addition, the width W3a and the width W3b are the same as the width W1 of the first connection portion 41 in the second direction D2 and the width W2 of the first connection portion 41 in the third direction D3. At least one of the width W3a and the width W3b may be different from the width W1 and the width W2.

[0066] In the semiconductor device 100, the p-type base region 22 includes a first direction D1 and a second direction D2. + The portion overlapping the n-type source region 23 and the portion not overlapping the n-type source region 23 in the first direction D1 + The portion overlapping the type source region 23. + The p-type source region 23 is aligned with a portion of the p-type base region 22 in the fourth direction D4. In the semiconductor device 100, the second connection portion 42 is disposed between the p-type base region 22 and the n-type source region 23. + The second connection portion 42 does not overlap with the n-type source region 23 in the first direction D1. + The second connection portion 42 may also be provided between the p-type base region 22 and the n-type source region 23. + The second connection portion 42 may also overlap with the n type source region 23 in the first direction D1. + Type source region 23 is in contact.

[0067] In the semiconductor device 100, the first connection portion 41 is provided between the p-type base region 22 and the n-type base region 22. + The first connection portion 41 overlaps with the n type source region 23 in the first direction D1. + The first connection portion 41 may also be provided between the p-type base region 22 and the n-type source region 23. + The first connection portion 41 may not overlap with the n-type source region 23 in the first direction D1. + Type source region 23 is in contact.

[0068] like Figure 2 As shown, in the semiconductor device 100 , a plurality of FP electrodes 14 and FP insulating portions 32 are provided in a plan view. The FP electrodes 14 are arranged in a quadrilateral shape in a plan view. The FP electrodes 14 may also be arranged in a triangular shape in a plan view, for example. The gate electrode 13 is provided between the plurality of FP electrodes 14 .

[0069] like Figure 2As shown, in the semiconductor device 100, the FP electrode 14 and the FP insulating portion 32 are circular in plan view. The FP electrode 14 and the FP insulating portion 32 may be polygonal in plan view, such as a triangle, a quadrilateral, or a hexagon.

[0070] The operation of the semiconductor device 100 will be described.

[0071] In a state where a positive voltage is applied to the drain electrode 11 relative to the source electrode 12, a voltage above the threshold is applied to the gate electrode 13. As a result, a channel (inversion layer) is formed in the p-type base region 22, and the semiconductor device 100 is turned on. Electrons flow from the source electrode 12 to the drain electrode 11 through the channel. Thereafter, if the voltage applied to the gate electrode 13 is lower than the threshold, the channel in the p-type base region 22 disappears, and the semiconductor device 100 is turned off.

[0072] When the semiconductor device 100 is switched to the off state, the positive voltage applied to the drain electrode 11 relative to the source electrode 12 increases. - The potential difference between the drift region 21 and the FP electrode 14 increases. Due to the increase in the potential difference, the depletion layer is formed from the FP insulating portion 32 and the n - The interface of the drift region 21 is n - The depletion layer 21 is expanded. By expanding the depletion layer, the withstand voltage of the semiconductor device 100 can be increased. Alternatively, the n-type drift region 21 can be increased while maintaining the withstand voltage of the semiconductor device 100. - The concentration of the impurities that serve as donors in the drift region 21 is reduced, thereby reducing the on-resistance of the semiconductor device 100 .

[0073] An example of the material of each component of the semiconductor device 100 is described.

[0074] The drain electrode 11 , the source electrode 12 , and the gate pad 15 include metal such as aluminum or copper.

[0075] n - type drift region 21, p-type base region 22, n + type source region 23, and the p + Type semiconductor region 24, p + type contact region 27, and n + The drain-source region 28 includes silicon, silicon carbide, gallium nitride, or gallium arsenide as a semiconductor material. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as an impurity that serves as a donor, and boron can be used as an impurity that serves as an acceptor.

[0076] The gate electrode 13 and the FP electrode 14 are made of a conductive material such as polysilicon. Impurities may be added to the conductive material.

[0077] The gate insulating portion 31 , the FP insulating portion 32 , and the insulating layer 51 include an insulating material. The gate insulating portion 31 , the FP insulating portion 32 , and the insulating layer 51 include, for example, silicon oxide or silicon nitride.

[0078] The connection portion 40 (the first connection portion 41 and the second connection portion 42 ) includes a metal such as tungsten, aluminum, or copper.

[0079] The effects of the first embodiment will be described.

[0080] In the semiconductor device 100, a plurality of FP electrodes 14 are provided in the second direction D2 and the third direction D3. According to this structure, compared with a case where the FP electrode 14 extends continuously in one direction, the number of n current paths can be reduced. - The volume of the type drift region 21 increases. As a result, the on-resistance of the semiconductor device 100 can be reduced. In addition, in the semiconductor device 100, the gate electrode 13 includes a first electrode region 13a extending along the third direction D3 and a second electrode region 13b extending along the second direction D2. According to this structure, compared with the case where the gate electrode 13 extends continuously in one direction, channels are formed in more regions. The channel density is increased, and the on-resistance of the semiconductor device 100 is further reduced. For example, if the on-resistance of the semiconductor device 100 is reduced, the current density flowing through the semiconductor device 100 can be increased. By increasing the current density, the miniaturization of the semiconductor device 100 can be achieved. Alternatively, the number of semiconductor devices 100 required to flow a specified current can be reduced.

[0081] In addition, in the semiconductor device 100, as Figure 5 As shown, a second connection portion 42 is provided near the third electrode region 13c of the gate electrode 13. Thus, holes in a region where holes are difficult to escape during avalanche breakdown can be easily removed through the second connection portion 42. Thus, by suppressing the potential rise of the p-type base region 22 and suppressing the conduction of the parasitic bipolar, the avalanche withstand can be improved.

[0082] In addition, the second connection portion 42 is in contact with the third insulating region 31c, and the upper end of the third electrode region 13c is located below the lower end of the second connection portion 42, thereby making it possible to make the thickness of the portion of the gate insulating portion 31 located between the gate electrode 13 and the second connection portion 42 of the source electrode 12 greater than the thickness of the fifth insulating portion 31c. As a result, the short circuit between the gate electrode 13 and the source electrode 12 can be suppressed, and the avalanche resistance can be improved.

[0083] In addition, the second connection portion 42 is disposed between the p-type base region 22 and the n-type base region 22. +The n-type source region 23 does not overlap in the first direction D1, so there is no n-type source region 23 near the second connection portion 42. + Type source region 23, so n + type source region 23, p-type base region 22, n - The parasitic bipolar electrode of the type drift region 21 is not formed. Thus, the conduction of the parasitic bipolar electrode caused by the hole current during avalanche breakdown can be suppressed.

[0084] (First Modification)

[0085] Figure 6 This is a cross-sectional view showing a portion of a semiconductor device according to a first modification of the first embodiment.

[0086] Figure 6 Representation and Figure 2 The cross section at the position corresponding to the VV line shown.

[0087] like Figure 6 As shown, in the semiconductor device 100A according to the first modification of the first embodiment, the shape of the p-type base region 22 and the n + The shape of the type source region 23 is different from that of the semiconductor device 100 . Other than that, it is the same as the semiconductor device 100 .

[0088] In the semiconductor device 100A, the p-type base region 22 does not include a region that is not adjacent to the n-type base region in the first direction D1. + In the semiconductor device 100A, the second connection portion 42 is provided between the p-type base region 22 and the n-type source region 23. + The second connection portion 42 overlaps with the n type source region 23 in the first direction D1. + Type source region 23 is in contact.

[0089] By providing the second connection portion 42 between the p-type base region 22 and the n-type base region 22, + The position where the type source region 23 overlaps in the first direction D1 can obtain source contact on the side of the second connection portion 42, and the source contact area is increased, so the source contact resistance can be reduced. In addition, since the channel area is not reduced, the channel resistance is not increased.

[0090] (Second Modification)

[0091] Figure 7 This is a cross-sectional view showing a portion of a semiconductor device according to a second modification of the first embodiment.

[0092] Figure 7 Representation and Figure 2 The cross section at the position corresponding to the VV line shown.

[0093] like Figure 7 As shown in FIG. 1 , in the semiconductor device 100B according to the second modification of the first embodiment, the position of the second connection portion 42 is different from that of the semiconductor device 100 . Other than that, the semiconductor device 100 is the same as the semiconductor device 100 .

[0094] In the semiconductor device 100B, the second connection portion 42 is not in contact with the third insulating region 31c. In the semiconductor device 100B, the upper end of the third electrode region 13c is located above the lower end of the second connection portion 42. In the semiconductor device 100B, the third electrode region 13c is aligned with the second connection portion 42 in the fourth direction D4.

[0095] The second connection portion 42 does not contact the third insulating region 31c, and the upper end of the third electrode region 13c is located above the lower end of the second connection portion 42, thereby making it possible to make the thickness of the portion of the gate insulating portion 31 between the gate electrode 13 and the second connection portion 42 with the source electrode 12 greater than the thickness of the fifth insulating portion 31c. Thus, the short circuit between the gate electrode 13 and the source electrode 12 can be suppressed, and the avalanche resistance can be improved. In addition, the current path of the holes during avalanche breakdown can be shortened, and the rise in the potential of the p-type base region 22 caused by the hole current (conduction of the parasitic bipolar) can be effectively suppressed.

[0096] (Third Modification)

[0097] Figure 8 This is a cross-sectional view showing a portion of a semiconductor device according to a third modified example of the first embodiment.

[0098] Figure 8 Representation and Figure 2 The cross section at the position corresponding to the VV line shown.

[0099] like Figure 8 As shown in FIG. 1 , in the semiconductor device 100C according to the third modification of the first embodiment, the position of the second connection portion 42 is different from that of the semiconductor device 100A. Other than that, the semiconductor device 100C is the same as the semiconductor device 100A.

[0100] In the semiconductor device 100C, the second connection portion 42 is not in contact with the third insulating region 31c. In the semiconductor device 100C, the upper end of the third electrode region 13c is located above the lower end of the second connection portion 42. In the semiconductor device 100C, the third electrode region 13c is aligned with the second connection portion 42 in the fourth direction D4.

[0101] The second connection portion 42 does not contact the third insulating region 31c, and the upper end of the third electrode region 13c is located above the lower end of the second connection portion 42, thereby making it possible to make the thickness of the portion of the gate insulating portion 31 between the gate electrode 13 and the second connection portion 42 with the source electrode 12 greater than the thickness of the fifth insulating portion 31c. Thus, the short circuit between the gate electrode 13 and the source electrode 12 can be suppressed, and the avalanche resistance can be improved. In addition, the current path of the holes during avalanche breakdown can be shortened, and the rise in the potential of the p-type base region 22 caused by the hole current (conduction of the parasitic bipolar) can be effectively suppressed.

[0102] (Second Embodiment)

[0103] Fig. 9 It is a plan view showing a part of the semiconductor device according to the second embodiment.

[0104] Fig.10 It is a cross-sectional view showing a part of the semiconductor device according to the second embodiment.

[0105] Fig.10 express Fig. 9 The cross section along line XX is shown.

[0106] Fig. 9 The cross section at line III-III and the cross section at line IV-IV are respectively Figure 3 , Figure 4 Same, so omitted.

[0107] like Fig. 9 and Fig.10 As shown, the semiconductor device 200 of the second embodiment is different from the semiconductor device 100 in that the shape of the gate electrode 13 (third electrode region 13c), the shape of the gate insulating portion 31 (third insulating region 31c), and the provision of p + Type semiconductor region 24. Other than this, it is the same as the semiconductor device 100.

[0108] The semiconductor device 200 further includes + Type semiconductor region 24. + The type semiconductor region 24 is provided under the sixth insulating portion 31c2. + The type semiconductor region 24 is connected to the n-type semiconductor region 24 in the second direction D2, the third direction D3 and the fourth direction D4. - The type drift region 21 and the FP electrode 14 are arranged. As a result, the electric field under the third electrode region 13c can be relaxed. In addition, the avalanche resistance under the third electrode region 13c can be improved. In addition, the capacitance between the gate electrode 13 and the drain electrode 11 can be reduced. Figure 3 , Figure 4 as well as Fig.10 As shown, in the semiconductor device 200, p + The type semiconductor region 24 is provided under the third insulating region 31c (sixth insulating portion 31c2) in the gate insulating portion 31, and is not provided under the first insulating region 31a (second insulating portion 31a2) and under the second insulating region 31b (fourth insulating portion 31b2). + The semiconductor region 24 may not be provided.

[0109] In the semiconductor device 200, p + The p-type semiconductor region 24 includes a first semiconductor portion 24a and a second semiconductor portion 24b. As a result, the capacitance (Cgd) between the gate electrode 13 and the drain electrode 11 can be reduced. In addition, the hole current path of avalanche breakdown can be increased. In addition, the holes flowing from the trench side during avalanche breakdown can be removed with low resistance to the first connection portion 41 and the second connection portion 42 (trench contact portion). As a result, the parasitic bipolar caused by the potential rise of the p-type base region 22 is difficult to conduct, and the avalanche tolerance is improved. The first semiconductor portion 24a overlaps with the gate electrode 13 (third electrode region 13c) in the first direction D1. The second semiconductor portion 24b does not overlap with the gate electrode 13 (third electrode region 13c) in the first direction D1. p + The semiconductor region 24 may not include the first semiconductor portion 24a and the second semiconductor portion 24b.

[0110] In the semiconductor device 200, p + The semiconductor region 24 includes a third semiconductor portion 24c and a fourth semiconductor portion 24d. + type semiconductor region 24. Thus, the electric field can be relaxed and the reduced n - The area of ​​the depletion layer of the type drift region 21 can suppress the reduction in the withstand voltage caused by the reduction in the area of ​​the depletion layer. The third semiconductor portion 24c is in contact with the third insulating region 31c of the gate insulating portion 31. The fourth semiconductor portion 24d is provided below the third semiconductor portion 24c. In the semiconductor device 200, the fourth semiconductor portion 24d is separated from the third semiconductor portion 24c. The fourth semiconductor portion 24d may also be in contact with the third semiconductor portion 24c. + The type semiconductor region 24 may not include the third semiconductor portion 24c and the fourth semiconductor portion 24d.

[0111] In the semiconductor device 200, p +The semiconductor region 24 includes a fifth semiconductor portion 24e and a sixth semiconductor portion 24f. As a result, the hole current path flowing from the gate electrode 13 side to the first connection portion 41 is expanded, and low resistance can be achieved. In addition, the capacitance (Cgs) between the gate electrode 13 and the source electrode 12 can be reduced. The fifth semiconductor portion 24e overlaps with the gate electrode 13 (third electrode region 13c) in the fourth direction D4. The sixth semiconductor portion 24f does not overlap with the gate electrode 13 (third electrode region 13c) in the fourth direction D4. In the semiconductor device 200, the sixth semiconductor portion 24f is in contact with the fifth semiconductor portion 24e. + The type semiconductor region 24 may not include the fifth semiconductor portion 24e and the sixth semiconductor portion 24f.

[0112] In the semiconductor device 200, p + The lower end of the FP-type semiconductor region 24 is located above the lower end of the FP electrode 14. This can prevent the depletion layer from extending toward the substrate side more than necessary, for example, preventing the substrate from connecting to the depletion layer (punch-through) during avalanche breakdown. + The lower end of the semiconductor region 24 is located above the center between the upper end of the FP electrode 14 and the lower end of the FP electrode 14. Fig.10 In FIG. 1 , the position of the center between the upper end of the FP electrode 14 and the lower end of the FP electrode 14 is indicated by a single-dot chain line. + The lower end of the FP-type semiconductor region 24 may be located at the same height as the lower end of the FP electrode 14. + The lower end of the FP type semiconductor region 24 may be located below the lower end of the FP electrode 14 .

[0113] In the semiconductor device 200, the lower end of the sixth insulating portion 31c2 (third insulating region 31c) is located below the lower end of the second insulating portion 31a2 (first insulating region 31a). The lower end of the sixth insulating portion 31c2 (third insulating region 31c) is located below the lower end of the fourth insulating portion 31b2 (second insulating region 31b). Thus, the electric field below the third electrode region 13c can be relaxed. The lower end of the sixth insulating portion 31c2 (third insulating region 31c) may be located at the same height as the lower end of the second insulating portion 31a2 (first insulating region 31a). The lower end of the sixth insulating portion 31c2 (third insulating region 31c) may be located at the same height as the lower end of the fourth insulating portion 31b2 (second insulating region 31b). In the semiconductor device 200, the lower end of the second insulating portion 31a2 (first insulating region 31a) is located at the same height as the lower end of the fourth insulating portion 31b2 (second insulating region 31b). The lower end of the second insulating portion 31a2 (first insulating region 31a) may also be located at a different height from the lower end of the fourth insulating portion 31b2 (second insulating region 31b).

[0114] In the semiconductor device 200, the thickness T6 is greater than the thickness T2. The thickness T6 is greater than the thickness T4. Thus, the electric field below the third electrode region 13c can be relaxed. In addition, the capacitance between the gate electrode 13 and the drain electrode 11 can be reduced. The thickness T6 can also be the same as the thickness T2. The thickness T6 can also be smaller than the thickness T2. The thickness T6 can also be the same as the thickness T4. The thickness T6 can also be smaller than the thickness T4. In the semiconductor device 200, the thickness T2 is the same as the thickness T4. The thickness T2 can also be different from the thickness T4.

[0115] In the semiconductor device 200, the thickness T6 is greater than the thickness T5. Thus, the capacitance (Cgd) between the gate electrode 13 and the drain electrode 11 can be reduced. In addition, by filling the area where the distance between the FP electrodes 14 is large and the effect is difficult to take effect with an oxide film, etc., it is possible to suppress the reduction in withstand voltage. The thickness T6 may be the same as the thickness T5. The thickness T6 may be smaller than the thickness T5. In the semiconductor device 200, the thickness T2 is the same as the thickness T1. The thickness T2 may be different from the thickness T1. In the semiconductor device 200, the thickness T4 is the same as the thickness T3. The thickness T4 may be different from the thickness T3. In the semiconductor device 200, the thickness T1, the thickness T3, and the thickness T5 are respectively the same. The thickness T1, the thickness T3, and the thickness T5 may be respectively different.

[0116] In the semiconductor device 200, the thickness T6 is larger than half of the length L1 of the third electrode region 13c in the first direction D1. As a result, the following effects can be obtained: the cross-sectional area of ​​the gate electrode 13 is not reduced beyond necessity (that is, the gate resistance is suppressed from becoming too large), and the reduction of the capacitance (Cgd) between the gate electrode 13 and the drain electrode 11 and the reduction of the withstand voltage are suppressed. The thickness T6 may also be smaller than half of the length L1. In the semiconductor device 200, the thickness T6 is smaller than the length L1. The thickness T6 may also be the same as the length L1. The thickness T6 may also be larger than the length L1.

[0117] In the semiconductor device 200, the lower end of the third electrode region 13c is located below the lower end of the first electrode region 13a. The lower end of the third electrode region 13c is located below the lower end of the second electrode region 13b. Thus, the electric field below the third electrode region 13c can be relaxed. The lower end of the third electrode region 13c may be located at the same height as the lower end of the first electrode region 13a. The lower end of the third electrode region 13c may be located above the lower end of the first electrode region 13a. The lower end of the third electrode region 13c may be located at the same height as the lower end of the second electrode region 13b. The lower end of the third electrode region 13c may be located above the lower end of the second electrode region 13b. In the semiconductor device 200, the lower end of the first electrode region 13a is located at the same height as the lower end of the second electrode region 13b. The lower end of the first electrode region 13a may be located at a different height from the lower end of the second electrode region 13b.

[0118] In the semiconductor device 200, the lower end of the third electrode region 13c is located above the lower end of the FP electrode 14. As a result, it is possible to suppress the depletion layer from expanding toward the substrate side more than necessary, for example, it is possible to prevent the substrate from connecting to the depletion layer (punch-through) during avalanche breakdown. In the semiconductor device 200, the lower end of the third electrode region 13c is located above the center between the upper end of the FP electrode 14 and the lower end of the FP electrode 14. The lower end of the third electrode region 13c may also be located at the same height as the lower end of the FP electrode 14. The lower end of the third electrode region 13c may also be located below the lower end of the FP electrode 14.

[0119] In the semiconductor device 200, the second connection portion 42 is provided between the third insulating region 31c of the gate insulating portion 31 and the first connection portion 41 in the fourth direction D4. This can improve avalanche resistance below the third electrode region 13c and reduce capacitance between the gate electrode 13 and the drain electrode 11.

[0120] In the semiconductor device 200, the second connection portion 42 is in contact with the third insulating region 31c. The upper end of the third electrode region 13c is located below the lower end of the second connection portion 42. Thus, the thickness of the portion of the gate insulating portion 31 located between the gate electrode 13 and the second connection portion 42 of the source electrode 12 can be made greater than the thickness of the fifth insulating portion 31c1. Thus, a short circuit between the gate electrode 13 and the source electrode 12 can be suppressed.

[0121] In addition, the second connection portion 42 may also be isolated from the third insulating region 31c. In this case, the upper end of the third electrode region 13c is preferably located above the lower end of the second connection portion 42. Thus, the current path of the holes during avalanche breakdown can be shortened, and the potential rise of the p-type base region 22 caused by the hole current (conduction of the parasitic bipolar) can be effectively suppressed.

[0122] In the semiconductor device 200, the upper end of the third electrode region 13c is located below the lower end of the second connection portion 42, and the lower end of the third electrode region 13c is located below the lower end of the first electrode region 13a. Thus, a short circuit between the gate electrode 13 and the source electrode 12 can be suppressed, and the cross-sectional area of ​​the gate electrode 13 can be suppressed from becoming too small (that is, the gate resistance becomes too large).

[0123] In the semiconductor device 200, the lower end of the first connection portion 41 is located at the same height as the lower end of the second connection portion 42. The lower end of the first connection portion 41 may be located above or below the lower end of the second connection portion 42.

[0124] In the semiconductor device 200, the lower ends of the first connection portion 41 and the second connection portion 42 are located above the lower end of the p-type base region 22. The lower end of the second connection portion 42 may also be located below the lower end of the p-type base region 22. + type semiconductor region 24, so that, for example, when the lower end of the second connection portion 42 is located below the lower end of the p-type base region 22, leakage between the source electrode 12 and the drain electrode 11 can be suppressed and avalanche resistance can be further improved.

[0125] In the semiconductor device 200, the second connection portion 42 does not extend along the second direction D2 and the third direction D3. The second connection portion 42 may extend along the second direction D2 and the third direction D3. The second connection portion 42 may also be an L-shape having a portion along the first electrode region 13a of the gate electrode 13 and a portion along the second electrode region 13b.

[0126] (Third Embodiment)

[0127] Fig.11 It is a plan view showing a part of the semiconductor device according to the third embodiment.

[0128] Fig.12 It is a cross-sectional view showing a part of the semiconductor device according to the third embodiment.

[0129] Fig.12 express Fig.11 The cross section at line XII-XII is shown.

[0130] Fig.11 The cross section at line III-III and the cross section at line IV-IV are respectively Figure 3 , Figure 4 Same, so omitted.

[0131] like Fig.11 and Fig.12 As shown in FIG. 1 , in the semiconductor device 300 of the third embodiment, the shape of the connection portion 40 is different from that of the semiconductor device 100 . Other than that, the semiconductor device 300 is the same as the semiconductor device 100 .

[0132] In the semiconductor device 300, the connection portion 40 includes a third connection portion 43 in addition to the first connection portion 41 and the second connection portion 42. The third connection portion 43 is located between the source electrode 12 and the first connection portion 41 and between the source electrode 12 and the second connection portion 42 in the first direction D1. The first connection portion 41 and the second connection portion 42 are connected to the source electrode 12 via the third connection portion 43. In the semiconductor device 300, the third connection portion 43 is connected to the p-type base region 22 and the n-type base region 22. + The third connection portion 43 may not be in contact with the p-type base region 22 and the n-type source region 23. + Type source region 23 is in contact.

[0133] In the semiconductor device 300, Fig.12 As shown, a second connection portion 42 is provided near the third electrode region 13c of the gate electrode 13. Thus, holes in a region where holes are difficult to escape during avalanche breakdown can be easily removed through the second connection portion 42. Thus, by suppressing the potential rise of the p-type base region 22 and suppressing the conduction of the parasitic bipolar, the avalanche withstand can be improved.

[0134] In the semiconductor device 300, the width W3 of the connection portion 40 in the fourth direction D4 is greater than the width W1 of the connection portion 40 in the second direction D2. The width W3 is greater than the width W2 of the connection portion 40 in the third direction D3. The width W1 is equivalent to Figure 4 The width W2 is equivalent to the width of the first connecting portion 41 in the second direction D2 shown. Figure 3The width of the first connection portion 41 in the third direction D3 is shown. The width W3 is, for example, greater than 1.5 times the width W1. The width W3 is, for example, greater than 1.5 times the width W2.

[0135] By making the width W3 larger than the width W1 and the width W2, the contact area between the source electrode 12 and the p-type base region 22 can be increased, and the contact resistance between the source electrode 12 and the p-type base region 22 can be reduced. In addition, holes in the region where holes are difficult to escape during avalanche breakdown can be easily removed by the connection portion 40. Thus, by suppressing the potential rise of the p-type base region 22 and suppressing the conduction of the parasitic bipolar, the avalanche withstand can be improved.

[0136] Furthermore, the structures of the first to third modified examples of the first embodiment can also be applied to the semiconductor device 300 .

[0137] (Fourth Embodiment)

[0138] Fig.13 It is a plan view showing a part of the semiconductor device according to the fourth embodiment.

[0139] Fig.14 It is a cross-sectional view showing a part of the semiconductor device according to the fourth embodiment.

[0140] Fig.14 express Fig.13 A cross section along line XIV-XIV is shown.

[0141] Fig.13 The cross section at line III-III and the cross section at line IV-IV are respectively Figure 3 , Figure 4 Same, so omitted.

[0142] like Fig.13 and Fig.14 As shown in FIG. 1 , in the semiconductor device 400 of the fourth embodiment, the shape of the connection portion 40 is different from that of the semiconductor device 100 . Other than that, the semiconductor device 400 is the same as the semiconductor device 100 .

[0143] In the semiconductor device 400, the width W3 of the connection portion 40 in the fourth direction D4 is greater than the width W1 of the connection portion 40 in the second direction D2. The width W3 is greater than the width W2 of the connection portion 40 in the third direction D3. The width W1 is equivalent to Figure 4 The width W2 is equivalent to the width of the first connecting portion 41 in the second direction D2 shown. Figure 3 The width of the first connection portion 41 in the third direction D3 is shown. The width W3 is, for example, greater than 1.5 times the width W1. The width W3 is, for example, greater than 1.5 times the width W2.

[0144] By making the width W3 larger than the width W1 and the width W2, the contact area between the source electrode 12 and the p-type base region 22 can be increased, and the contact resistance between the source electrode 12 and the p-type base region 22 can be reduced. In addition, holes in the region where holes are difficult to escape during avalanche breakdown can be easily removed by the connection portion 40. Thus, by suppressing the potential rise of the p-type base region 22 and suppressing the conduction of the parasitic bipolar, the avalanche withstand can be improved.

[0145] In the semiconductor device 400, the entire lower surface of the connection portion 40 is provided with a p + type contact region 27. Thus, the hole current path can be expanded and the avalanche resistance can be improved.

[0146] Furthermore, the structures of the first to third modified examples of the first embodiment can also be applied to the semiconductor device 400 .

[0147] (First Manufacturing Method)

[0148] Fig.15 (a)~ Fig.15 (h) is a cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the first embodiment.

[0149] like Fig.15 (a)~ Fig.15 As shown in (h), the first manufacturing method includes the first to eighth steps. The second step is performed after the first step. The third step is performed after the second step. The fourth step is performed after the third step. The fifth step is performed after the fourth step. The sixth step is performed after the fifth step. The seventh step is performed after the sixth step. The eighth step is performed after the seventh step. Fig.15 (a) corresponds to the first step. Fig.15 (b) corresponds to the second step. Fig.15 (c) corresponds to the third step. Fig.15 (d) corresponds to the fourth step. Fig.15 (e) corresponds to the fifth step. Fig.15 (f) corresponds to the sixth step. Fig.15 (g) corresponds to the seventh step. Fig.15 (h) corresponds to the eighth step. Each step will be described below.

[0150] like Fig.15 As shown in (a), in the first step, a trench 65 is formed in a semiconductor region 61a of a first conductivity type (eg, n-type). Fig.15 (a)~ Fig.15 (h) shows the position of the intersection of the trench 65. The semiconductor region 61a corresponds to the above-mentioned n -type drift region 21. The trench 65 is formed by, for example, etching or the like.

[0151] like Fig.15 As shown in (b), in the second step, an insulating region 62a is formed inside the trench 65 and on the semiconductor region 61a. The insulating region 62a corresponds to the gate insulating portion 31 (third insulating region 31c) described above. The insulating region 62a is formed by, for example, thermal oxidation.

[0152] like Fig.15 As shown in (c), in the third step, first, a conductive region 63a is formed inside the trench 65 in which the insulating region 62a is formed. The conductive region 63a is equivalent to the above-mentioned gate electrode 13 (third electrode region 13c). The formation of the conductive region 63a is performed, for example, by embedding a metal such as polysilicon or tungsten (W). Polysilicon may be undoped with impurities or may be doped with impurities. On the conductive region 63a, a part of the conductive region 63a is oxidized by an annealing process when forming the conductive region 63a, thereby forming an insulating region 62b. The insulating region 62b is equivalent to the above-mentioned insulating layer 51.

[0153] like Fig.15 As shown in (d), in the fourth step, the insulating region 62a formed on the semiconductor region 61a and the insulating region 62b formed on the conductive region 63a are removed. The insulating region 62a and the insulating region 62b are removed by, for example, CMP (Chemical Mechanical Polishing).

[0154] like Fig.15 As shown in (e) of FIG. 5 , in the fifth step, a part (upper part) of the conductive region 63a is removed to form a through hole 66. The through hole 66 is formed by, for example, etching.

[0155] like Fig.15 As shown in (f), in the sixth step, an insulating region 62c is formed inside the through hole 66, and an insulating region 62d is formed on the insulating region 62c and the semiconductor region 61a. The insulating region 62c corresponds to the gate insulating portion 31 (third insulating region 31c) described above. The insulating region 62d corresponds to the insulating layer 51 described above. The insulating region 62c and the insulating region 62d are formed, for example, by thermal oxidation or CVD (Chemical Vapor Deposition).

[0156] like Fig.15As shown in (g), in the seventh step, a semiconductor region 61b of a second conductivity type (e.g., p-type) is formed on the upper portion of the semiconductor region 61a. The semiconductor region 61b corresponds to the above-mentioned p-type base region 22. The formation of the semiconductor region 61b is performed, for example, by injecting impurities containing boron (B), BF2, and at least one of them into the semiconductor region 61a.

[0157] like Fig.15 As shown in (h), in the eighth step, first, conductive regions 63b are formed on both sides of the portion of the insulating region 62c located above the conductive region 63a. The conductive region 63b corresponds to the second connecting portion 42 described above. The conductive region 63b is formed, for example, by CVD embedding of tungsten (W), sputtering of a barrier metal, etc. In the eighth step, then, a conductive region 63c is formed on the insulating region 62c and the conductive region 63b. The conductive region 63c corresponds to the source electrode 12 described above. The conductive region 63c is formed, for example, by the deposition of a metal such as aluminum (Al).

[0158] According to the first manufacturing method, it is possible to easily manufacture a semiconductor device in which the second connection portion 42 is provided on the side of the third insulating region 31c of the gate insulating portion 31. Therefore, it is possible to easily manufacture a semiconductor device capable of relaxing an electric field.

[0159] (Second Manufacturing Method)

[0160] Fig.16 (a)~ Fig.16 (h) is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second embodiment.

[0161] like Fig.16 (a)~ Fig.16 As shown in (h), the second manufacturing method includes the first to eighth steps. The second step is performed after the first step. The third step is performed after the second step. The fourth step is performed after the third step. The fifth step is performed after the fourth step. The sixth step is performed after the fifth step. The seventh step is performed after the sixth step. The eighth step is performed after the seventh step. Fig.16 (a) corresponds to the first step. Fig.16 (b) corresponds to the second step. Fig.16 (c) corresponds to the third step. Fig.16 (d) corresponds to the fourth step. Fig.16 (e) corresponds to the fifth step. Fig.16 (f) corresponds to the sixth step. Fig.16 (g) corresponds to the seventh step. Fig.16 (h) corresponds to the eighth step. Each step will be described below.

[0162] like Fig.16 As shown in (a), in the first step, a trench 75 is formed in a semiconductor region 71a of a first conductivity type (eg, n-type). Fig.16 (a)~ Fig.16 (h) shows the position of the intersection of the trench 75. The semiconductor region 71a corresponds to the above-mentioned n - type drift region 21. The trench 75 is formed by, for example, etching or the like.

[0163] like Fig.16 As shown in (b), in the second step, a semiconductor region 71b of a second conductivity type (e.g., p-type) is formed under the trench 75. The semiconductor region 71b is formed, for example, by injecting impurities containing boron (B), BF2, and at least one of them into the semiconductor region 71a.

[0164] like Fig.16 As shown in (c), in the third step, the semiconductor region 71b is changed into the insulating region 72a, and the insulating region 72b is formed inside the trench 75 and on the semiconductor region 71a. The insulating region 72a and the insulating region 72b are equivalent to the above-mentioned gate insulating portion 31 (third insulating region 31c). The formation of the insulating region 72a and the insulating region 72b is performed, for example, by accelerated oxidation.

[0165] like Fig.16 As shown in (d), in the fourth step, a semiconductor region 71c and a semiconductor region 71d of the second conductivity type (for example, p-type) are formed under the insulating region 72a. The semiconductor region 71c and the semiconductor region 71d correspond to the p-type semiconductor region 71c and the p-type semiconductor region 71d described above. + type semiconductor region 24. The semiconductor region 71c and the semiconductor region 71d are formed by, for example, implanting impurities including boron (B), BF2, and at least one of them into the semiconductor region 71a.

[0166] like Fig.16 As shown in (e), in the fifth step, first, a conductive region 73a is formed inside the trench 75 in which the insulating region 72b is formed. The conductive region 73a corresponds to the gate electrode 13 (third electrode region 13c) described above. The conductive region 73a is formed, for example, by embedding a metal such as polysilicon or tungsten (W). Polysilicon may be undoped with impurities or may be doped with impurities. On the conductive region 73a, a portion of the conductive region 73a is oxidized by an annealing step when the conductive region 73a is formed, thereby forming the insulating region 72c.

[0167] like Fig.16As shown in (f), in the sixth step, first, the insulating region 72b formed on the semiconductor region 71a and the insulating region 72c formed on the conductive region 73a are removed. The removal of the insulating region 72b and the insulating region 72c is performed, for example, by CMP or etching. The etching is, for example, CDE (Chemical Dry Etching). In the sixth step, then, a part (upper part) of the conductive region 73a is removed to form a through hole 76. The formation of the through hole 76 is performed, for example, by etching.

[0168] like Fig.16 As shown in (g), in the seventh step, first, an insulating region 72d is formed inside the through hole 76, and an insulating region 72e is formed on the insulating region 72d and the semiconductor region 71a. The insulating region 72d is equivalent to the above-mentioned gate insulating portion 31 (third insulating region 31c). The insulating region 72e is equivalent to the above-mentioned insulating layer 51. The formation of the insulating region 72d and the insulating region 72e is performed, for example, by thermal oxidation or CVD. In the seventh step, then, a semiconductor region 71e of a second conductivity type (for example, p-type) is formed on the upper part of the semiconductor region 71a. The semiconductor region 71e is equivalent to the above-mentioned p-type base region 22. The formation of the semiconductor region 71e is performed, for example, by injecting impurities containing boron (B), BF2, and at least any one of them into the semiconductor region 71a.

[0169] like Fig.16 As shown in (h), in the eighth step, first, conductive regions 73b are formed on both sides of the portion of the insulating region 72d located above the conductive region 73a. The conductive region 73b corresponds to the second connecting portion 42 described above. The conductive region 73b is formed, for example, by CVD embedding of tungsten (W), sputtering of a barrier metal, etc. In the eighth step, then, a conductive region 73c is formed on the insulating region 72e and the conductive region 73b. The conductive region 73c corresponds to the source electrode 12 described above. The conductive region 73c is formed, for example, by the deposition of a metal such as aluminum (Al).

[0170] According to the second manufacturing method, a semiconductor device can be easily manufactured in which a p-type semiconductor device is provided under the third electrode region 13c of the gate electrode 13. + The gate insulating portion 31 has a third insulating region 31c (sixth insulating portion 31c2) with a lower end that is located below the lower end of the first insulating region 31a (second insulating portion 31a2) and the lower end of the second insulating region 31b (fourth insulating portion 31b2), and a second connecting portion 42 is provided on the side of the third insulating region 31c of the gate insulating portion 31. Therefore, a semiconductor device capable of relaxing an electric field can be easily manufactured.

[0171] The embodiments may include the following structures.

[0172] (Structure 1)

[0173] A semiconductor device comprising:

[0174] a first electrode;

[0175] A first semiconductor region of a first conductivity type, disposed on the first electrode;

[0176] A second semiconductor region of a second conductivity type, disposed on the first semiconductor region;

[0177] The third semiconductor region of the first conductivity type is disposed on the second semiconductor region;

[0178] A second electrode, disposed on the third semiconductor region and electrically connected to the third semiconductor region;

[0179] The third electrode includes a first electrode region, a second electrode region and a third electrode region,

[0180] The first electrode region extends along a second direction, the second direction is perpendicular to the first direction from the first electrode toward the second electrode, the first electrode region is arranged with the second semiconductor region in a third direction, the third direction is perpendicular to the first direction and intersects the second direction,

[0181] The second electrode region extends along the third direction and is aligned with the second semiconductor region in the second direction.

[0182] The third electrode region connects the first electrode region and the second electrode region;

[0183] A first insulating portion, comprising a first insulating region, a second insulating region and a third insulating region;

[0184] The first insulating region includes a first insulating portion and a second insulating portion, the first insulating portion is arranged between the second semiconductor region and the first electrode region in the third direction, and the second insulating portion is arranged between the first semiconductor region and the first electrode region in the first direction.

[0185] The second insulating region includes a third insulating portion and a fourth insulating portion, the third insulating portion is arranged between the second semiconductor region and the second electrode region in the second direction, and the fourth insulating portion is arranged between the first semiconductor region and the second electrode region in the first direction.

[0186] The third insulating region connects the first insulating region and the second insulating region, the third insulating region includes a fifth insulating portion and a sixth insulating portion, the fifth insulating portion is arranged between the second semiconductor region and the third electrode region in a fourth direction, the fourth direction is perpendicular to the first direction and intersects the second direction and the third direction, and the sixth insulating portion is arranged between the first semiconductor region and the third electrode region in the first direction;

[0187] a fourth electrode arranged with the first semiconductor region and the third electrode in the second direction and the third direction;

[0188] a second insulating portion provided between the fourth electrode and the first semiconductor region and between the fourth electrode and the third electrode in the second direction and the third direction; and

[0189] a connecting portion, disposed between the third insulating region and the second insulating portion in the second direction, the third direction, and the fourth direction, and electrically connecting the second electrode and the second semiconductor region,

[0190] The connection portion includes: a first connection portion located between the third insulating region and the second insulating portion in the second direction, the third direction, and the fourth direction; and a second connection portion located between the third insulating region and the first connection portion in the fourth direction.

[0191] (Structure 2)

[0192] The semiconductor device according to Structure 1, wherein:

[0193] The second connecting portion is in contact with the third insulating region,

[0194] An upper end of the third electrode region is located below a lower end of the second connecting portion.

[0195] (Structure 3)

[0196] The semiconductor device according to Structure 1, wherein:

[0197] The second connecting portion is isolated from the third insulating region,

[0198] An upper end of the third electrode region is located above a lower end of the second connecting portion.

[0199] (Structure 4)

[0200] A semiconductor device comprising:

[0201] a first electrode;

[0202] A first semiconductor region of a first conductivity type, disposed on the first electrode;

[0203] A second semiconductor region of a second conductivity type, disposed on the first semiconductor region;

[0204] The third semiconductor region of the first conductivity type is disposed on the second semiconductor region;

[0205] A second electrode, disposed on the third semiconductor region and electrically connected to the third semiconductor region;

[0206] The third electrode includes a first electrode region, a second electrode region and a third electrode region,

[0207] The first electrode region extends along a second direction, the second direction is perpendicular to the first direction from the first electrode toward the second electrode, the first electrode region is arranged with the second semiconductor region in a third direction, the third direction is perpendicular to the first direction and intersects the second direction,

[0208] The second electrode region extends along the third direction and is aligned with the second semiconductor region in the second direction.

[0209] The third electrode region connects the first electrode region and the second electrode region;

[0210] A first insulating portion, comprising a first insulating region, a second insulating region and a third insulating region;

[0211] The first insulating region includes a first insulating portion and a second insulating portion, the first insulating portion is arranged between the second semiconductor region and the first electrode region in the third direction, and the second insulating portion is arranged between the first semiconductor region and the first electrode region in the first direction.

[0212] The second insulating region includes a third insulating portion and a fourth insulating portion, the third insulating portion is arranged between the second semiconductor region and the second electrode region in the second direction, and the fourth insulating portion is arranged between the first semiconductor region and the second electrode region in the first direction.

[0213] The third insulating region connects the first insulating region and the second insulating region, the third insulating region includes a fifth insulating portion and a sixth insulating portion, the fifth insulating portion is arranged between the second semiconductor region and the third electrode region in a fourth direction, the fourth direction is perpendicular to the first direction and intersects the second direction and the third direction, and the sixth insulating portion is arranged between the first semiconductor region and the third electrode region in the first direction;

[0214] a fourth electrode arranged with the first semiconductor region and the third electrode in the second direction and the third direction;

[0215] a second insulating portion provided between the fourth electrode and the first semiconductor region and between the fourth electrode and the third electrode in the second direction and the third direction; and

[0216] a connecting portion, disposed between the third insulating region and the second insulating portion in the second direction, the third direction, and the fourth direction, and electrically connecting the second electrode and the second semiconductor region,

[0217] The width of the connection portion in the fourth direction is greater than the width of the connection portion in the second direction and the width of the connection portion in the third direction.

[0218] (Structure 5)

[0219] The semiconductor device according to any one of Structures 1 to 4, further comprising a fourth semiconductor region of the second conductivity type provided under the sixth insulating portion.

[0220] (Structure 6)

[0221] The semiconductor device according to any one of Structures 1 to 5, wherein a lower end of the sixth insulating portion is located below a lower end of the second insulating portion and a lower end of the fourth insulating portion.

[0222] As described above, according to the embodiment, a semiconductor device capable of improving avalanche resistance can be provided.

[0223] The embodiments of the present invention are described above, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the main purpose of the invention. These embodiments and their variations are included in the scope and main purpose of the invention, and are included in the scope of the invention and its equivalents recorded in the claims.

[0224] [Explanation of Reference Numerals]

[0225] 11: Drain electrode (first electrode)

[0226] 12: Source electrode (second electrode)

[0227] 13: Gate electrode (third electrode)

[0228] 13a: First electrode region

[0229] 13b: Second electrode region

[0230] 13c: Third electrode region

[0231] 14: FP electrode (fourth electrode)

[0232] 15: Gate pad

[0233] 21:n - Type drift region (first semiconductor region)

[0234] 22: p-type base region (second semiconductor region)

[0235] 23:n + Type source region (third semiconductor region)

[0236] 24: p + Type semiconductor region (fourth semiconductor region)

[0237] 24a: First semiconductor portion

[0238] 24b: Second semiconductor portion

[0239] 24c: The third semiconductor part

[0240] 24d: The fourth semiconductor part

[0241] 24e: Fifth Semiconductor Section

[0242] 24f: The sixth semiconductor part

[0243] 27: p + Type contact area

[0244] 28:n + Type Drain Region

[0245] 31: Gate insulating portion (first insulating portion)

[0246] 31a: First insulation area

[0247] 31a1: First insulating part

[0248] 31a2: Second insulating part

[0249] 31b: Second insulation area

[0250] 31b1: The third insulating part

[0251] 31b2: Fourth insulating part

[0252] 31c: The third insulating area

[0253] 31c1: Fifth insulating part

[0254] 31c2: Sixth insulating part

[0255] 32: FP insulating part (second insulating part)

[0256] 40: Connection

[0257] 41: First connection part

[0258] 42: Second connection part

[0259] 43: Third connection

[0260] 51: Insulation layer

[0261] 61a, 61b: semiconductor region

[0262] 62a, 62b, 62c, 62d: Insulation area

[0263] 63a, 63b, 63c: Conductive area

[0264] 65: Groove

[0265] 66: Through hole

[0266] 71a, 71b, 71c, 71d, 71e: semiconductor region

[0267] 72a, 72b, 72c, 72d, 72e: Insulation area

[0268] 73a, 73b, 73c: Conductive area

[0269] 75: Groove

[0270] 76: Through hole

[0271] 100, 100A, 100B, 100C, 200, 300, 400: semiconductor devices.

Claims

1. A semiconductor device comprising: a first electrode; A first semiconductor region of a first conductivity type, disposed on the first electrode; A second semiconductor region of a second conductivity type, disposed on the first semiconductor region; The third semiconductor region of the first conductivity type is disposed on the second semiconductor region; A second electrode, disposed on the third semiconductor region and electrically connected to the third semiconductor region; The third electrode includes a first electrode region, a second electrode region and a third electrode region, The first electrode region extends along a second direction, the second direction is perpendicular to the first direction from the first electrode toward the second electrode, the first electrode region is arranged with the second semiconductor region in a third direction, the third direction is perpendicular to the first direction and intersects the second direction, The second electrode region extends along the third direction and is aligned with the second semiconductor region in the second direction. The third electrode region connects the first electrode region and the second electrode region; A first insulating portion, comprising a first insulating region, a second insulating region and a third insulating region; The first insulating region includes a first insulating portion and a second insulating portion, the first insulating portion is arranged between the second semiconductor region and the first electrode region in the third direction, and the second insulating portion is arranged between the first semiconductor region and the first electrode region in the first direction. The second insulating region includes a third insulating portion and a fourth insulating portion, the third insulating portion is arranged between the second semiconductor region and the second electrode region in the second direction, and the fourth insulating portion is arranged between the first semiconductor region and the second electrode region in the first direction. The third insulating region connects the first insulating region and the second insulating region, the third insulating region includes a fifth insulating portion and a sixth insulating portion, the fifth insulating portion is arranged between the second semiconductor region and the third electrode region in a fourth direction, the fourth direction is perpendicular to the first direction and intersects the second direction and the third direction, and the sixth insulating portion is arranged between the first semiconductor region and the third electrode region in the first direction; a fourth electrode arranged with the first semiconductor region and the third electrode in the second direction and the third direction; a second insulating portion, disposed between the fourth electrode and the first semiconductor region and between the fourth electrode and the third electrode in the second direction and the third direction; as well as a connecting portion, disposed between the third insulating region and the second insulating portion in the second direction, the third direction, and the fourth direction, and electrically connecting the second electrode and the second semiconductor region, The connection portion includes: a first connection portion located between the third insulating region and the second insulating portion in the second direction, the third direction, and the fourth direction; and a second connection portion located between the third insulating region and the first connection portion in the fourth direction.

2. The semiconductor device according to claim 1, wherein The second connecting portion is in contact with the third insulating region, An upper end of the third electrode region is located below a lower end of the second connecting portion.

3. The semiconductor device according to claim 1, wherein The second connecting portion is isolated from the third insulating region, An upper end of the third electrode region is located above a lower end of the second connecting portion.

4. The semiconductor device according to claim 1, wherein The device further includes a fourth semiconductor region of the second conductivity type provided under the sixth insulating portion.

5. The semiconductor device according to claim 1, wherein A lower end of the sixth insulating portion is located below lower ends of the second insulating portion and the fourth insulating portion.

6. The semiconductor device according to claim 1, wherein The connecting portion further includes a third connecting portion, and the third connecting portion is located between the second electrode and the first connecting portion and between the second electrode and the second connecting portion in the first direction. The first connection portion and the second connection portion are connected to the second electrode via the third connection portion.

7. A semiconductor device comprising: a first electrode; A first semiconductor region of a first conductivity type, disposed on the first electrode; A second semiconductor region of a second conductivity type, disposed on the first semiconductor region; The third semiconductor region of the first conductivity type is disposed on the second semiconductor region; A second electrode, disposed on the third semiconductor region and electrically connected to the third semiconductor region; The third electrode includes a first electrode region, a second electrode region and a third electrode region, The first electrode region extends along a second direction, the second direction is perpendicular to the first direction from the first electrode toward the second electrode, the first electrode region is arranged with the second semiconductor region in a third direction, the third direction is perpendicular to the first direction and intersects the second direction, The second electrode region extends along the third direction and is aligned with the second semiconductor region in the second direction. The third electrode region connects the first electrode region and the second electrode region; A first insulating portion, comprising a first insulating region, a second insulating region and a third insulating region; The first insulating region includes a first insulating portion and a second insulating portion, the first insulating portion is arranged between the second semiconductor region and the first electrode region in the third direction, and the second insulating portion is arranged between the first semiconductor region and the first electrode region in the first direction. The second insulating region includes a third insulating portion and a fourth insulating portion, the third insulating portion is arranged between the second semiconductor region and the second electrode region in the second direction, and the fourth insulating portion is arranged between the first semiconductor region and the second electrode region in the first direction. The third insulating region connects the first insulating region and the second insulating region, the third insulating region includes a fifth insulating portion and a sixth insulating portion, the fifth insulating portion is arranged between the second semiconductor region and the third electrode region in a fourth direction, the fourth direction is perpendicular to the first direction and intersects the second direction and the third direction, and the sixth insulating portion is arranged between the first semiconductor region and the third electrode region in the first direction; a fourth electrode arranged with the first semiconductor region and the third electrode in the second direction and the third direction; a second insulating portion, disposed between the fourth electrode and the first semiconductor region and between the fourth electrode and the third electrode in the second direction and the third direction; as well as a connecting portion, disposed between the third insulating region and the second insulating portion in the second direction, the third direction, and the fourth direction, and electrically connecting the second electrode and the second semiconductor region, The width of the connection portion in the fourth direction is greater than the width of the connection portion in the second direction and the width of the connection portion in the third direction.

8. The semiconductor device according to claim 7, wherein: The device further includes a fourth semiconductor region of the second conductivity type provided under the sixth insulating portion.

9. The semiconductor device according to claim 7, wherein: A lower end of the sixth insulating portion is located below lower ends of the second insulating portion and the fourth insulating portion.

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