Semiconductor device
By designing a multi-layer electric field relieving structure in a semiconductor device, and using the specific arrangement and connection of multiple electrodes and insulating regions, the problem of insufficient electric field relieving efficiency in the prior art is solved, and more efficient electric field relieving and conduction performance improvements are achieved.
Patent Information
- Application Number
- CN202311727844.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-09-21
- Filing Date
- 2023-12-15
- Publication Date
- 2025-03-25
AI Technical Summary
The existing semiconductor devices have problems with insufficient efficiency in easing the electric field.
A semiconductor device is designed, which includes a plurality of electrodes and insulating regions, and forms a multi-layered electric field relief structure through the arrangement and connection of specific electrodes and insulating regions.
More efficient electric field relieving is achieved, the on-resistance is reduced, the current density is increased, and the electric field can be relaxed without increasing the gate capacitance.
Smart Images
Figure CN119698030A_ABST
Abstract
Description
[0001] Related Applications
[0002] This application claims priority based on Japanese Patent Application No. 2023-156429 (filing date: September 21, 2023), and the entire contents of the application are incorporated herein by reference. Technical Field
[0003] Embodiments relate to a semiconductor device. Background Art
[0004] Semiconductor devices such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor) are used for power conversion, etc. In semiconductor devices, it is desired to relax the electric field. Summary of the invention
[0005] A semiconductor device of an embodiment includes: a first electrode; a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type; a third semiconductor region of the first conductivity type; a second electrode; a third electrode; a first insulating portion; a fourth electrode; and a second insulating portion. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The second electrode is provided on the third semiconductor region. The second electrode is electrically connected to the third semiconductor region. The third electrode includes a first electrode region, a second electrode region, and a third electrode region. The first electrode region extends along a second direction. The second direction is perpendicular to a first direction from the first electrode toward the second electrode. The first electrode region is arranged with the second semiconductor region in a third direction. The third direction is perpendicular to the first direction and intersects with the second direction. The second electrode region extends along the third direction. The second electrode region is arranged with the second semiconductor region in the second direction. The third electrode region connects the first electrode region and the second electrode region. The first insulating portion includes a first insulating region, a second insulating region, and a third insulating region. The first insulating region includes a first insulating portion and a second insulating portion. The first insulating portion is arranged between the second semiconductor region and the first electrode region in the third direction. The second insulating portion is arranged between the first semiconductor region and the first electrode region in the first direction. The second insulating region includes a third insulating portion and a fourth insulating portion. The third insulating portion is arranged between the second semiconductor region and the second electrode region in the second direction. The fourth insulating portion is arranged between the first semiconductor region and the second electrode region in the first direction. The third insulating region connects the first insulating region and the second insulating region. The third insulating region includes a fifth insulating portion and a sixth insulating portion. The fifth insulating portion is arranged between the second semiconductor region and the third electrode region in the fourth direction. The fourth direction is perpendicular to the first direction and intersects the second direction and the third direction. The sixth insulating portion is arranged between the first semiconductor region and the third electrode region in the first direction. The fourth electrode is arranged with the first semiconductor region and the third electrode in the second direction and the third direction. The second insulating portion is arranged between the fourth electrode and the first semiconductor region and between the fourth electrode and the third electrode in the second direction and the third direction. The lower end of the sixth insulating portion is located below the lower end of the second insulating portion and the lower end of the fourth insulating portion.
[0006] According to this embodiment, a semiconductor device capable of relaxing an electric field can be provided. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Figure 1 It is a plan view showing the semiconductor device according to the first embodiment.
[0008] Figure 2 It is a plan view showing a part of the semiconductor device according to the first embodiment.
[0009] Figure 3 It is a cross-sectional view showing a part of the semiconductor device according to the first embodiment.
[0010] Figure 4 It is a cross-sectional view showing a part of the semiconductor device according to the first embodiment.
[0011] Figure 5 It is a cross-sectional view showing a part of the semiconductor device according to the first embodiment.
[0012] Figure 6 This is a cross-sectional view showing a portion of a semiconductor device according to a first modification of the first embodiment.
[0013] Figure 7 This is a cross-sectional view showing a portion of a semiconductor device according to a second modification of the first embodiment.
[0014] Figure 8 This is a cross-sectional view showing a portion of a semiconductor device according to a third modified example of the first embodiment.
[0015] Fig. 9 It is a plan view showing a part of the semiconductor device according to the second embodiment.
[0016] Fig.10 It is a cross-sectional view showing a part of the semiconductor device according to the second embodiment.
[0017] Fig.11 (a)~ Fig.11 (e) is a cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the first embodiment.
[0018] Fig.12 (a)~ Fig.12 (e) is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to a second modification of the first embodiment.
[0019] Fig.13 (a)~ Fig.13 (h) is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second embodiment. DETAILED DESCRIPTION
[0020] Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0021] The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the size between parts, etc. are not necessarily the same as the actual ones. Even when the same part is shown, the size and ratio may be shown differently depending on the drawings.
[0022] In the present specification and each drawing, the same reference numerals are given to the same elements as those already described, and detailed description thereof will be appropriately omitted.
[0023] In the following description and drawings, n + 、n - and p + , p indicate the relative level of each impurity concentration. That is, the expression marked with "+" has a relatively higher impurity concentration than the expression without any "+" or "-", and the expression marked with "-" has a relatively lower impurity concentration than the expression without any "+" or "-". These expressions indicate the relative level of the actual impurity concentration after these impurities compensate for each other when both p-type impurities and n-type impurities are included in each region.
[0024] Each embodiment described below may be implemented by inverting the p-type and n-type of each semiconductor region.
[0025] (First Embodiment)
[0026] Figure 1 It is a plan view showing the semiconductor device according to the first embodiment.
[0027] Figure 2 It is a plan view showing a part of the semiconductor device according to the first embodiment.
[0028] Figure 3 to Figure 5 It is a cross-sectional view showing a part of the semiconductor device according to the first embodiment.
[0029] Figure 2 express Figure 1 Region II is shown.
[0030] Figure 3 yes Figure 2 A cross-sectional view taken along line III-III is shown.
[0031] Figure 4 yes Figure 2 A cross-sectional view taken along line IV-IV is shown.
[0032] Figure 5 yes Figure 2 A cross-sectional view taken along line VV is shown.
[0033] The semiconductor device 100 of the first embodiment is a vertical MOSFET. The semiconductor device 100 is a MOSFET of a so-called dot FP structure.
[0034] like Figure 1 to Figure 5 As shown, the semiconductor device 100 includes a drain electrode 11 (first electrode), a source electrode 12 (second electrode), a gate electrode 13 (third electrode), an FP electrode 14 (fourth electrode), a gate pad 15, - type drift region 21 (first semiconductor region), p-type base region 22 (second semiconductor region), n + type source region 23 (third semiconductor region), p + Type contact area 27, n + The first conductive type is n-type and the second conductive type is p-type. Figure 2 In FIG. 5 , the source electrode 12 and the insulating layer 51 are omitted.
[0035] In the description of each of the following embodiments, a first direction D1, a second direction D2, and a third direction D3 are used. The direction from the drain electrode 11 toward the source electrode 12 is set as the first direction D1. One of the directions perpendicular to the first direction D1 is set as the second direction D2. One of the directions intersecting the first direction D1 and the second direction D2 is set as the third direction D3. The third direction D3 can be a direction perpendicular to the second direction D2 or a direction inclined relative to the second direction D2. In addition, a direction perpendicular to the first direction D1 and intersecting the second direction D2 and the third direction D3 is set as a fourth direction D4. In addition, in order to facilitate the understanding of the description, the direction from the drain electrode 11 toward the source electrode 12 is set as the top, and the opposite direction is set as the bottom, but these directions are not related to the direction of gravity. Observation from above is set as "looking down".
[0036] like Figure 1 As shown, a source electrode 12 and a gate pad 15 are provided on the upper surface of the semiconductor device 100. The source electrode 12 and the gate pad 15 are electrically isolated from each other.
[0037] like Figure 3 to Figure 5 As shown in FIG. 1 , a drain electrode 11 is provided on the lower surface of the semiconductor device 100. + The type drain electrode 28 is provided with n - Type drift region 21. - The drift region 21 is separated by n + The type drain electrode 28 is electrically connected to the drain electrode 11.- A p-type base region 22 is provided on the p-type drift region 21. + Type source region 23 and p + In the p-type base region 22 and n + The source electrode 12 is provided on the type source region 23 via the insulating layer 51. The source electrode 12 is connected to the first connecting portion 41 and the p + The p-type contact region 27 and the p-type base region 22 and the n-type + The type source region 23 is electrically connected.
[0038] The gate electrode 13 is arranged with the p-type base region 22 in the second direction D2, the third direction D3, and the fourth direction D4. Figure 2 to Figure 5 As shown, the gate electrode 13 includes a first electrode region 13 a , a second electrode region 13 b and a third electrode region 13 c .
[0039] The first electrode region 13a extends along the second direction D2. The first electrode region 13a is aligned with the p-type base region 22 in the third direction D3. In the semiconductor device 100, a portion of the first electrode region 13a is aligned with the n-type base region 22 in the third direction D3. - In the semiconductor device 100, a portion of the first electrode region 13a is aligned with the n-type drift region 21 in the third direction D3. + The first type source region 23 is aligned. In the semiconductor device 100, a portion of the first electrode region 13a is aligned with the first connection portion 41 in the third direction D3.
[0040] The second electrode region 13b extends along the third direction D3. The second electrode region 13b is aligned with the p-type base region 22 in the second direction D2. In the semiconductor device 100, a portion of the second electrode region 13b is aligned with the n-type base region 22 in the second direction D2. - In the semiconductor device 100, a portion of the second electrode region 13b is aligned with the n-type drift region 21 in the second direction D2. + The second electrode region 13 b is aligned with the first connection portion 41 in the second direction D2 in the semiconductor device 100 .
[0041] The third electrode region 13c connects the first electrode region 13a and the second electrode region 13b. The third electrode region 13c is located at the intersection of the first electrode region 13a and the second electrode region 13b. In the semiconductor device 100, the third electrode region 13c is aligned with the p-type base region 22 in the fourth direction D4. In the semiconductor device 100, a portion of the third electrode region 13c is aligned with the n-type base region 22 in the fourth direction D4. -In the semiconductor device 100, a portion of the third electrode region 13c is aligned with the n-type drift region 21 in the fourth direction D4. + In the semiconductor device 100, a portion of the third electrode region 13c is aligned with the p-type source region 23 in the fourth direction D4. + The type contact area 27 and the first connecting portion 41 are arranged.
[0042] In the semiconductor device 100, the upper ends of the first electrode region 13a, the second electrode region 13b, and the third electrode region 13c are located at the same height. The upper ends of the first electrode region 13a, the second electrode region 13b, and the third electrode region 13c may be located at different heights.
[0043] In the semiconductor device 100, the lower ends of the first electrode region 13a, the second electrode region 13b, and the third electrode region 13c are located at the same height. The lower ends of the first electrode region 13a, the second electrode region 13b, and the third electrode region 13c may be located at different heights.
[0044] In the semiconductor device 100, the lower ends of the first electrode region 13a, the second electrode region 13b, and the third electrode region 13c are respectively located above the lower end of the FP electrode 14. In the semiconductor device 100, the lower ends of the first electrode region 13a, the second electrode region 13b, and the third electrode region 13c are respectively located above the center of the upper end of the FP electrode 14 and the lower end of the FP electrode 14. Figure 3 to Figure 5 In FIG. 1 , the position of the center between the upper end of the FP electrode 14 and the lower end of the FP electrode 14 is indicated by a single-dot chain line.
[0045] The gate insulating portion 31 is disposed between the gate electrode 13 and the p-type base region 22 in the second direction D2, the third direction D3, and the fourth direction D4. Figure 2 to Figure 5 As shown, the gate insulating portion 31 includes a first insulating region 31 a , a second insulating region 31 b and a third insulating region 31 c .
[0046] The first insulating region 31a includes a first insulating portion 31a1 and a second insulating portion 31a2. The first insulating portion 31a1 is disposed between the p-type substrate region 22 and the first electrode region 13a in the third direction D3. The second insulating portion 31a2 is disposed between the n-type substrate region 22 and the first electrode region 13a in the first direction D1. - The second insulating portion 31a2 is located between the drift region 21 and the first electrode region 13a.
[0047] The second insulating region 31b includes a third insulating portion 31b1 and a fourth insulating portion 31b2. The third insulating portion 31b1 is disposed between the p-type substrate region 22 and the second electrode region 13b in the second direction D2. The fourth insulating portion 31b2 is disposed between the n-type substrate region 22 and the second electrode region 13b in the first direction D1. - The fourth insulating portion 31b2 is located between the type drift region 21 and the second electrode region 13b.
[0048] The third insulating region 31c connects the first insulating region 31a and the second insulating region 31b. The third insulating region 31c is located at the intersection of the first insulating region 31a and the second insulating region 31b. The third insulating region 31c includes a fifth insulating portion 31c1 and a sixth insulating portion 31c2. The fifth insulating portion 31c1 is disposed between the p-type base region 22 and the third electrode region 13c in the fourth direction D4. The sixth insulating portion 31c2 is disposed between the p-type base region 22 and the third electrode region 13c in the first direction D1. - The sixth insulating portion 31c2 is located between the type drift region 21 and the third electrode region 13c.
[0049] In the semiconductor device 100, the lower end of the sixth insulating portion 31c2 (third insulating region 31c) is located below the lower end of the second insulating portion 31a2 (first insulating region 31a). The lower end of the sixth insulating portion 31c2 (third insulating region 31c) is located below the lower end of the fourth insulating portion 31b2 (second insulating region 31b). The lower end of the second insulating portion 31a2 (first insulating region 31a) is located at the same height as the lower end of the fourth insulating portion 31b2 (second insulating region 31b).
[0050] In the semiconductor device 100, the lower end of the second insulating portion 31a2 (first insulating region 31a), the lower end of the fourth insulating portion 31b2 (second insulating region 31b), and the lower end of the sixth insulating portion 31c2 (third insulating region 31c) are respectively located above the lower end of the FP electrode 14. In the semiconductor device 100, the lower end of the second insulating portion 31a2 (first insulating region 31a), the lower end of the fourth insulating portion 31b2 (second insulating region 31b), and the lower end of the sixth insulating portion 31c2 (third insulating region 31c) are respectively located above the center of the upper end of the FP electrode 14 and the lower end of the FP electrode 14.
[0051] In the semiconductor device 100, the thickness T1 of the first insulating portion 31a1 in the third direction D3, the thickness T3 of the third insulating portion 31b1 in the second direction D2, and the thickness T5 of the fifth insulating portion 31c1 in the fourth direction D4 are the same. The thickness T1, thickness T3, and thickness T5 may be different.
[0052] In the semiconductor device 100, the thickness T6 of the sixth insulating portion 31c2 in the first direction D1 is greater than the thickness T2 of the second insulating portion 31a2 in the first direction D1. The thickness T6 is greater than the thickness T4 of the fourth insulating portion 31b2 in the first direction D1. The thickness T2 is the same as the thickness T4. The thickness T2 may also be different from the thickness T4.
[0053] In the semiconductor device 100, the thickness T6 is greater than the thickness T5. In the semiconductor device 100, the thickness T2 is the same as the thickness T1. The thickness T2 may be different from the thickness T1. In the semiconductor device 100, the thickness T4 is the same as the thickness T3. The thickness T4 may be different from the thickness T3.
[0054] In the semiconductor device 100 , the thickness T6 is larger than half the length L1 of the third electrode region 13 c in the first direction D1 . In the semiconductor device 100 , the thickness T6 is smaller than the length L1 .
[0055] In the semiconductor device 100, a width W2 of the sixth insulating portion 31c2 in the fourth direction D4 is smaller than a width W1 of the third electrode region 13c in the fourth direction D4. In the semiconductor device 100, the width W2 is greater than half of the width W1.
[0056] The gate electrode 13 is electrically connected to the gate pad 15. The gate pad 15 is electrically isolated from the source electrode 12. The gate electrode 13 may be electrically connected to the gate pad 15 via a gate wiring layer (not shown).
[0057] The FP electrode 14 is connected to the n electrode in the second direction D2, the third direction D3 and the fourth direction D4. - In the semiconductor device 100, a portion of the FP electrode 14 is aligned with the p-type base region 22 in the second direction D2, the third direction D3, and the fourth direction D4. A portion of the FP electrode 14 is aligned with the n-type base region 22 in the second direction D2, the third direction D3, and the fourth direction D4. + Type source region 23 is arranged.
[0058] The FP insulating portion 32 is disposed between the FP electrode 14 and the n electrode 14 in the second direction D2, the third direction D3, and the fourth direction D4. - In the semiconductor device 100, a portion of the FP insulating portion 32 is provided between the FP electrode 14 and the p-type base region 22 in the second direction D2, the third direction D3, and the fourth direction D4. A portion of the FP insulating portion 32 is provided between the FP electrode 14 and the n-type drift region 21 in the second direction D2, the third direction D3, and the fourth direction D4. +A portion of the FP insulating portion 32 is disposed between the FP electrode 14 and the n type source region 23 in the first direction D1. - The FP electrode 14 is electrically connected to the source electrode 12.
[0059] The first connection portion 41 is provided between the third insulating region 31c of the gate insulating portion 31 and the FP insulating portion 32 in the second direction D2, the third direction D3, and the fourth direction D4. In the first direction D1, a p-type substrate region 22 is provided between the first connection portion 41 and the p-type substrate region 22. + The first connection portion 41 connects the source electrode 12 to the p-type base region 22 (p + Type contact area 27) is electrically connected.
[0060] like Figure 2 As shown, in the semiconductor device 100 , a plurality of FP electrodes 14 and FP insulating portions 32 are provided in a plan view. The FP electrodes 14 are arranged in a quadrilateral shape in a plan view. The FP electrodes 14 may also be arranged in a triangular shape in a plan view, for example. The gate electrode 13 is provided between the plurality of FP electrodes 14 .
[0061] like Figure 2 As shown, in the semiconductor device 100, the FP electrode 14 and the FP insulating portion 32 are circular in plan view. The FP electrode 14 and the FP insulating portion 32 may be polygonal in plan view, such as a triangle, a quadrilateral, or a hexagon.
[0062] The operation of the semiconductor device 100 will be described.
[0063] In a state where a positive voltage is applied to the drain electrode 11 relative to the source electrode 12, a voltage above the threshold is applied to the gate electrode 13. As a result, a channel (inversion layer) is formed in the p-type base region 22, and the semiconductor device 100 is turned on. Electrons flow from the source electrode 12 to the drain electrode 11 through the channel. Thereafter, if the voltage applied to the gate electrode 13 is lower than the threshold, the channel in the p-type base region 22 disappears, and the semiconductor device 100 is turned off.
[0064] When the semiconductor device 100 is switched to the off state, the positive voltage applied to the drain electrode 11 relative to the source electrode 12 increases. - The potential difference between the drift region 21 and the FP electrode 14 increases. Due to the increase in the potential difference, the depletion layer is formed from the FP insulating portion 32 and the n - The interface of the drift region 21 is n - The depletion layer 21 is expanded. By expanding the depletion layer, the withstand voltage of the semiconductor device 100 can be increased. Alternatively, the n-type drift region 21 can be increased while maintaining the withstand voltage of the semiconductor device 100.- The concentration of the impurities that serve as donors in the drift region 21 is reduced, thereby reducing the on-resistance of the semiconductor device 100 .
[0065] An example of the material of each component of the semiconductor device 100 is described.
[0066] The drain electrode 11 , the source electrode 12 , and the gate pad 15 include metal such as aluminum or copper.
[0067] n - type drift region 21, p-type base region 22, n + type source region 23, and the p + Type semiconductor region 24, p + type contact region 27, and n + The drain-source region 28 includes silicon, silicon carbide, gallium nitride, or gallium arsenide as a semiconductor material. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as an impurity that serves as a donor, and boron can be used as an impurity that serves as an acceptor.
[0068] The gate electrode 13 and the FP electrode 14 are made of a conductive material such as polysilicon. Impurities may be added to the conductive material.
[0069] The gate insulating portion 31 , the FP insulating portion 32 , and the insulating layer 51 include an insulating material. The gate insulating portion 31 , the FP insulating portion 32 , and the insulating layer 51 include, for example, silicon oxide or silicon nitride.
[0070] The first connection portion 41 and the second connection portion 42 described later are made of metal such as tungsten, aluminum, or copper.
[0071] The effects of the first embodiment will be described.
[0072] In the semiconductor device 100, a plurality of FP electrodes 14 are provided in the second direction D2 and the third direction D3. According to this structure, compared with a case where the FP electrode 14 extends continuously in one direction, the number of n current paths can be reduced. -The volume of the type drift region 21 increases. As a result, the on-resistance of the semiconductor device 100 can be reduced. In addition, in the semiconductor device 100, the gate electrode 13 includes a first electrode region 13a extending along the third direction D3 and a second electrode region 13b extending along the second direction D2. According to this structure, compared with the case where the gate electrode 13 extends continuously in one direction, channels are formed in more regions. The channel density is increased, and the on-resistance of the semiconductor device 100 is further reduced. For example, if the on-resistance of the semiconductor device 100 is reduced, the current density flowing through the semiconductor device 100 can be increased. By increasing the current density, the miniaturization of the semiconductor device 100 can be achieved. Alternatively, the number of semiconductor devices 100 required to flow a specified current can be reduced.
[0073] In addition, in the semiconductor device 100, as Figure 5 As shown, the lower end of the third insulating region 31c (the lower end of the sixth insulating portion 31c2) located below the third electrode region 13c is located below the lower end of the first insulating region 31a (the lower end of the second insulating portion 31a2) located below the first electrode region 13a and the lower end of the second insulating region 31b (the fourth insulating portion 31b2) located below the second electrode region 13b. Thus, the electric field below the third electrode region 13c can be mitigated.
[0074] Furthermore, by making the thickness T6 larger than the thickness T2 and the thickness T4, the electric field below the third electrode region 13 c can be relaxed, and the capacitance between the gate electrode 13 and the drain electrode 11 can be reduced.
[0075] In addition, the thickness T6 is greater than the thickness T5, so that the capacitance (Cgd) between the gate electrode 13 and the drain electrode 11 can be reduced without increasing the thickness of the fifth insulating portion 31c1, and the FOM (Figure of Merit) can be improved. In addition, by filling the area where the distance between the FP electrodes 14 is large and the effect is difficult to take effect with an oxide film, the reduction in the withstand voltage can be suppressed.
[0076] In addition, the thickness T6 is larger than half of the length L1, so that the electric field can be relaxed by the sixth insulating portion 31c2 without increasing the gate capacitance (Qg). In addition, the following effects can be obtained: the cross-sectional area of the gate electrode 13 is not reduced more than necessary (that is, the gate resistance is suppressed from becoming too large), and the reduction of the capacitance (Cgd) between the gate electrode 13 and the drain electrode 11 and the reduction of the withstand voltage can be suppressed.
[0077] (First Modification)
[0078] Figure 6 This is a cross-sectional view showing a portion of a semiconductor device according to a first modification of the first embodiment.
[0079] Figure 6 Representation and Figure 2 The cross section at the position corresponding to the VV line shown.
[0080] like Figure 6 As shown, in the semiconductor device 100A according to the first modification of the first embodiment, the shape of the sixth insulating portion 31c2 is different from that of the semiconductor device 100. Other than that, it is the same as the semiconductor device 100.
[0081] In the semiconductor device 100A, the thickness T6 is greater than the length L1. In the semiconductor device 100A, the width W2 is the same as the width W1.
[0082] The thickness T6 is greater than the length L1, so that the electric field can be relaxed in a wider range. In addition, the width W2 is equal to the width W1, so that the sixth insulating portion 31c2 under the gate electrode 13 can be prevented from having an unusual shape and the electric field concentration in the sixth insulating portion 31c2 can be relaxed.
[0083] In the semiconductor device 100A, the lower end of the sixth insulating portion 31c2 is located above the lower end of the FP electrode 14. The lower end of the sixth insulating portion 31c2 may be located at the same height as the lower end of the FP electrode 14, or may be located below the lower end of the FP electrode 14. Thus, the electric field can be relaxed over a wider range. For example, even if the lower end of the sixth insulating portion 31c2 is located below the lower end of the FP electrode 14, the depletion layer itself does not extend, and thus does not cause punch-through with the substrate.
[0084] (Second Modification)
[0085] Figure 7 This is a cross-sectional view showing a portion of a semiconductor device according to a second modification of the first embodiment.
[0086] Figure 7 Representation and Figure 2 The cross section at the position corresponding to the VV line shown.
[0087] like Figure 7 As shown, in the semiconductor device 100B according to the second modification of the first embodiment, the shape of the sixth insulating portion 31c2 is different from that of the semiconductor device 100. Other than this, it is the same as the semiconductor device 100.
[0088] In the semiconductor device 100B, the thickness T6 is greater than the length L1. In the semiconductor device 100B, the width W2 is less than half of the width W1.
[0089] The thickness T6 is greater than the length L1, so that the electric field can be relaxed over a wider range. In addition, the width W2 is less than half the width W1, so that the effective area can be reduced while relaxing the electric field. Thus, an increase in on-resistance can be suppressed.
[0090] (Third Modification)
[0091] Figure 8 This is a cross-sectional view showing a portion of a semiconductor device according to a third modified example of the first embodiment.
[0092] Figure 8 Representation and Figure 2 The cross section at the position corresponding to the VV line shown.
[0093] like Figure 8 As shown, in the semiconductor device 100C of the third modification of the first embodiment, the shape of the gate electrode 13 (third electrode region 13c) and the shape of the gate insulating portion 31 (third insulating region 31c) are different from those of the semiconductor device 100. Other than that, it is the same as the semiconductor device 100.
[0094] In the semiconductor device 100C, the lower end of the third electrode region 13c is located below the lower end of the first electrode region 13a. The lower end of the third electrode region 13c is located below the lower end of the second electrode region 13b. In the semiconductor device 100C, the lower end of the first electrode region 13a is located at the same height as the lower end of the second electrode region 13b. The lower end of the first electrode region 13a may be located at a different height from the lower end of the second electrode region 13b.
[0095] In the semiconductor device 100C, the lower end of the third electrode region 13c is located above the lower end of the FP electrode 14. In the semiconductor device 100C, the lower end of the third electrode region 13c is located above the center between the upper end of the FP electrode 14 and the lower end of the FP electrode 14. Figure 8 In FIG. 1 , the position of the center between the upper end of the FP electrode 14 and the lower end of the FP electrode 14 is indicated by a single-dot chain line.
[0096] The lower end of the third electrode region 13 c is located below the lower end of the first electrode region 13 a and the lower end of the second electrode region 13 b , so that the electric field below the third electrode region 13 c can be relaxed.
[0097] The lower end of the third electrode region 13c is located above the lower end of the FP electrode 14, so that the same effect as the FP electrode 14 can be obtained, and the electric field can be relaxed. In addition, the depletion layer can be suppressed from extending toward the substrate side more than necessary, for example, it can be prevented from connecting (punching through) the substrate and the depletion layer during avalanche breakdown.
[0098] (Second Embodiment)
[0099] Fig. 9 It is a plan view showing a part of the semiconductor device according to the second embodiment.
[0100] Fig.10 It is a cross-sectional view showing a part of the semiconductor device according to the second embodiment.
[0101] Fig.10 express Fig. 9 The cross section along line XX is shown.
[0102] Fig. 9 The cross section at line III-III and the cross section at line IV-IV are respectively Figure 3 , Figure 4 Same, so omitted.
[0103] like Fig. 9 and Fig.10 As shown, the semiconductor device 200 of the second embodiment is different from the semiconductor device 100 in that the shape of the gate electrode 13 (third electrode region 13c), the shape of the gate insulating portion 31 (third insulating region 31c), and the provision of p + The semiconductor region 24 and the second connection portion 42 are provided. Other than this, the semiconductor device 100 is the same as that of the semiconductor device 100 .
[0104] The semiconductor device 200 further includes + Type semiconductor region 24. + The type semiconductor region 24 is provided under the sixth insulating portion 31c2. + The type semiconductor region 24 is connected to the n-type semiconductor region 24 in the second direction D2, the third direction D3 and the fourth direction D4. - The type drift region 21 and the FP electrode 14 are arranged. As a result, the electric field under the third electrode region 13c can be relaxed. In addition, the avalanche resistance under the third electrode region 13c can be improved. In addition, the capacitance between the gate electrode 13 and the drain electrode 11 can be reduced. Figure 3 , Figure 4 as well as Fig.10 As shown, in the semiconductor device 200, p + The type semiconductor region 24 is provided under the third insulating region 31c (sixth insulating portion 31c2) in the gate insulating portion 31, and is not provided under the first insulating region 31a (second insulating portion 31a2) and under the second insulating region 31b (fourth insulating portion 31b2). + The semiconductor region 24 may not be provided.
[0105] In the semiconductor device 200, p +The p-type semiconductor region 24 includes a first semiconductor portion 24a and a second semiconductor portion 24b. As a result, the capacitance (Cgd) between the gate electrode 13 and the drain electrode 11 can be reduced. In addition, the hole current path of avalanche breakdown can be increased. In addition, the holes flowing from the trench side during avalanche breakdown can be removed with low resistance to the first connection portion 41 and the second connection portion 42 (trench contact portion). As a result, the parasitic bipolar caused by the potential rise of the p-type base region 22 is difficult to conduct, and the avalanche tolerance is improved. The first semiconductor portion 24a overlaps with the gate electrode 13 (third electrode region 13c) in the first direction D1. The second semiconductor portion 24b does not overlap with the gate electrode 13 (third electrode region 13c) in the first direction D1. p + The semiconductor region 24 may not include the first semiconductor portion 24a and the second semiconductor portion 24b.
[0106] In the semiconductor device 200, p + The semiconductor region 24 includes a third semiconductor portion 24c and a fourth semiconductor portion 24d. + type semiconductor region 24. Thus, the electric field can be relaxed and the reduced n - The area of the depletion layer of the type drift region 21 can suppress the reduction in the withstand voltage caused by the reduction in the area of the depletion layer. The third semiconductor portion 24c is in contact with the third insulating region 31c of the gate insulating portion 31. The fourth semiconductor portion 24d is provided below the third semiconductor portion 24c. In the semiconductor device 200, the fourth semiconductor portion 24d is separated from the third semiconductor portion 24c. The fourth semiconductor portion 24d may also be in contact with the third semiconductor portion 24c. + The type semiconductor region 24 may not include the third semiconductor portion 24c and the fourth semiconductor portion 24d.
[0107] In the semiconductor device 200, p + The semiconductor region 24 includes a fifth semiconductor portion 24e and a sixth semiconductor portion 24f. As a result, the hole current path flowing from the gate electrode 13 side to the first connection portion 41 is expanded, and low resistance can be achieved. In addition, the capacitance (Cgs) between the gate electrode 13 and the source electrode 12 can be reduced. The fifth semiconductor portion 24e overlaps with the gate electrode 13 (third electrode region 13c) in the fourth direction D4. The sixth semiconductor portion 24f does not overlap with the gate electrode 13 (third electrode region 13c) in the fourth direction D4. In the semiconductor device 200, the sixth semiconductor portion 24f is in contact with the fifth semiconductor portion 24e. + The type semiconductor region 24 may not include the fifth semiconductor portion 24e and the sixth semiconductor portion 24f.
[0108] In the semiconductor device 200, p + The lower end of the FP-type semiconductor region 24 is located above the lower end of the FP electrode 14. This can prevent the depletion layer from extending toward the substrate side more than necessary, for example, preventing the substrate from connecting to the depletion layer (punch-through) during avalanche breakdown. + The lower end of the semiconductor region 24 is located above the center between the upper end of the FP electrode 14 and the lower end of the FP electrode 14. Fig.10 In FIG. 1 , the position of the center between the upper end of the FP electrode 14 and the lower end of the FP electrode 14 is indicated by a single-dot chain line. + The lower end of the FP-type semiconductor region 24 may be located at the same height as the lower end of the FP electrode 14. + The lower end of the FP type semiconductor region 24 may be located below the lower end of the FP electrode 14 .
[0109] In the semiconductor device 200, the lower end of the sixth insulating portion 31c2 (third insulating region 31c) is located below the lower end of the second insulating portion 31a2 (first insulating region 31a). The lower end of the sixth insulating portion 31c2 (third insulating region 31c) is located below the lower end of the fourth insulating portion 31b2 (second insulating region 31b). Thus, the electric field below the third electrode region 13c can be mitigated. The lower end of the second insulating portion 31a2 (first insulating region 31a) is located at the same height as the lower end of the fourth insulating portion 31b2 (second insulating region 31b). The lower end of the second insulating portion 31a2 (first insulating region 31a) may also be located at a different height from the lower end of the fourth insulating portion 31b2 (second insulating region 31b).
[0110] In the semiconductor device 200, the thickness T6 is greater than the thickness T2. The thickness T6 is greater than the thickness T4. Thus, the electric field below the third electrode region 13c can be relaxed. In addition, the capacitance between the gate electrode 13 and the drain electrode 11 can be reduced. The thickness T6 can also be the same as the thickness T2. The thickness T6 can also be smaller than the thickness T2. The thickness T6 can also be the same as the thickness T4. The thickness T6 can also be smaller than the thickness T4. In the semiconductor device 200, the thickness T2 is the same as the thickness T4. The thickness T2 can also be different from the thickness T4.
[0111] In the semiconductor device 200, the thickness T6 is greater than the thickness T5. Thus, the capacitance (Cgd) between the gate electrode 13 and the drain electrode 11 can be reduced. In addition, by filling the area where the distance between the FP electrodes 14 is large and the effect is difficult to take effect with an oxide film, etc., it is possible to suppress the reduction in withstand voltage. The thickness T6 may be the same as the thickness T5. The thickness T6 may be smaller than the thickness T5. In the semiconductor device 200, the thickness T2 is the same as the thickness T1. The thickness T2 may be different from the thickness T1. In the semiconductor device 200, the thickness T4 is the same as the thickness T3. The thickness T4 may be different from the thickness T3. In the semiconductor device 200, the thickness T1, the thickness T3, and the thickness T5 are respectively the same. The thickness T1, the thickness T3, and the thickness T5 may be respectively different.
[0112] In the semiconductor device 200, the thickness T6 is larger than half of the length L1 of the third electrode region 13c in the first direction D1. As a result, the following effects can be obtained: the cross-sectional area of the gate electrode 13 is not reduced beyond necessity (that is, the gate resistance is suppressed from becoming too large), and the reduction of the capacitance (Cgd) between the gate electrode 13 and the drain electrode 11 and the reduction of the withstand voltage are suppressed. The thickness T6 may also be smaller than half of the length L1. In the semiconductor device 200, the thickness T6 is smaller than the length L1. The thickness T6 may also be the same as the length L1. The thickness T6 may also be larger than the length L1.
[0113] In the semiconductor device 200, the lower end of the third electrode region 13c is located below the lower end of the first electrode region 13a. The lower end of the third electrode region 13c is located below the lower end of the second electrode region 13b. Thus, the electric field below the third electrode region 13c can be relaxed. The lower end of the third electrode region 13c may be located at the same height as the lower end of the first electrode region 13a. The lower end of the third electrode region 13c may be located above the lower end of the first electrode region 13a. The lower end of the third electrode region 13c may be located at the same height as the lower end of the second electrode region 13b. The lower end of the third electrode region 13c may be located above the lower end of the second electrode region 13b. In the semiconductor device 200, the lower end of the first electrode region 13a is located at the same height as the lower end of the second electrode region 13b. The lower end of the first electrode region 13a may be located at a different height from the lower end of the second electrode region 13b.
[0114] In the semiconductor device 200, the lower end of the third electrode region 13c is located above the lower end of the FP electrode 14. As a result, it is possible to suppress the depletion layer from expanding toward the substrate side more than necessary, for example, it is possible to prevent the substrate from connecting to the depletion layer (punch-through) during avalanche breakdown. In the semiconductor device 200, the lower end of the third electrode region 13c is located above the center between the upper end of the FP electrode 14 and the lower end of the FP electrode 14. The lower end of the third electrode region 13c may also be located at the same height as the lower end of the FP electrode 14. The lower end of the third electrode region 13c may also be located below the lower end of the FP electrode 14.
[0115] In the semiconductor device 200, the thickness T6 is larger than the thickness T2 and the thickness T4, and the lower end of the third electrode region 13c is located below the lower ends of the first electrode region 13a and the second electrode region 13b. Thus, for example, compared with the semiconductor device 100C of the third modification of the first embodiment, the increase in capacitance can be alleviated.
[0116] The semiconductor device 200 includes a second connection portion 42 in addition to the first connection portion 41. The second connection portion 42 is provided between the third insulating region 31c of the gate insulating portion 31 and the first connection portion 41 in the fourth direction D4. In the first direction D1, a p-type base region 22 is provided between the second connection portion 42 and the p-type base region 22. + The second connection portion 42 connects the source electrode 12 to the p-type base region 22 (p + The gate electrode 13 and the drain electrode 11 are electrically connected to each other. Thus, the avalanche resistance below the third electrode region 13c can be improved. In addition, the capacitance between the gate electrode 13 and the drain electrode 11 can be reduced. The second connection portion 42 may not be provided.
[0117] In the semiconductor device 200, the second connection portion 42 is in contact with the third insulating region 31c. The upper end of the third electrode region 13c is located below the lower end of the second connection portion 42. Thus, the thickness of the portion of the gate insulating portion 31 located between the gate electrode 13 and the second connection portion 42 of the source electrode 12 can be made greater than the thickness of the fifth insulating portion 31c1. Thus, a short circuit between the gate electrode 13 and the source electrode 12 can be suppressed.
[0118] In addition, the second connection portion 42 may also be isolated from the third insulating region 31c. In this case, the upper end of the third electrode region 13c is preferably located above the lower end of the second connection portion 42. Thus, the current path of the holes during avalanche breakdown can be shortened, and the potential rise of the p-type base region 22 caused by the hole current (conduction of the parasitic bipolar) can be effectively suppressed.
[0119] In the semiconductor device 200, the upper end of the third electrode region 13c is located below the lower end of the second connection portion 42, and the lower end of the third electrode region 13c is located below the lower end of the first electrode region 13a. Thus, a short circuit between the gate electrode 13 and the source electrode 12 can be suppressed, and the cross-sectional area of the gate electrode 13 can be suppressed from becoming too small (that is, the gate resistance becomes too large).
[0120] In the semiconductor device 200, the lower end of the first connection portion 41 is located at the same height as the lower end of the second connection portion 42. The lower end of the first connection portion 41 may be located above or below the lower end of the second connection portion 42.
[0121] In the semiconductor device 200, the lower ends of the first connection portion 41 and the second connection portion 42 are located above the lower end of the p-type base region 22. The lower end of the second connection portion 42 may also be located below the lower end of the p-type base region 22. + type semiconductor region 24, so that, for example, when the lower end of the second connection portion 42 is located below the lower end of the p-type base region 22, leakage between the source electrode 12 and the drain electrode 11 can be suppressed and avalanche resistance can be further improved.
[0122] In the semiconductor device 200, the second connection portion 42 does not extend along the second direction D2 and the third direction D3. The second connection portion 42 may extend along the second direction D2 and the third direction D3. The second connection portion 42 may also be an L-shape having a portion along the first electrode region 13a of the gate electrode 13 and a portion along the second electrode region 13b.
[0123] (First Manufacturing Method)
[0124] Fig.11 (a)~ Fig.11 (e) is a cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the first embodiment.
[0125] like Fig.11 (a)~ Fig.11 As shown in (e), the first manufacturing method includes the first to fifth steps. The second step is performed after the first step. The third step is performed after the second step. The fourth step is performed after the third step. The fifth step is performed after the fourth step. Fig.11 (a) corresponds to the first step. Fig.11 (b) corresponds to the second step. Fig.11 (c) corresponds to the third step. Fig.11 (d) corresponds to the fourth step. Fig.11(e) corresponds to the fifth step. Each step will be described below.
[0126] like Fig.11 As shown in (a), in the first step, a trench 65 is formed in a semiconductor region 61a of a first conductivity type (eg, n-type). Fig.11 (a)~ Fig.11 In (e), the position of the intersection of the trench 65 is shown. The semiconductor region 61a corresponds to the above-mentioned n - type drift region 21. The trench 65 is formed by, for example, etching or the like.
[0127] like Fig.11 As shown in (b), in the second step, a semiconductor region 61b of a second conductivity type (e.g., p-type) is formed under the trench 65. The semiconductor region 61b is formed, for example, by injecting impurities containing boron (B), BF2, and at least one of them into the semiconductor region 61a.
[0128] like Fig.11 As shown in (c), in the third step, the semiconductor region 61b is changed into the insulating region 62a, and the insulating region 62b is formed inside the trench 65 and on the semiconductor region 61a. The insulating region 62a and the insulating region 62b are equivalent to the above-mentioned gate insulating portion 31 (third insulating region 31c). The formation of the insulating region 62a and the insulating region 62b is performed, for example, by accelerated oxidation.
[0129] like Fig.11 As shown in (d), in the fourth step, first, a conductive region 63a is formed inside the trench 65 in which the insulating region 62b is formed. The conductive region 63a is equivalent to the above-mentioned gate electrode 13 (third electrode region 13c). The conductive region 63a is formed, for example, by embedding polysilicon or a metal such as tungsten (W). Polysilicon may be undoped with impurities or may be doped with impurities. In the fourth step, then, an insulating region 62c is formed on the conductive region 63a. The insulating region 62c is equivalent to the above-mentioned insulating layer 51. The insulating region 62c is formed, for example, by thermal oxidation or CVD (Chemical Vapor Deposition). The insulating region 62c may also be formed, for example, by oxidizing a portion of the conductive region 63a through an annealing process when the conductive region 63a is formed.
[0130] like Fig.11As shown in (e), in the fifth step, a semiconductor region 61c of a second conductivity type (e.g., p-type) is formed on the upper portion of the semiconductor region 61a. The semiconductor region 61c corresponds to the above-mentioned p-type base region 22. The formation of the semiconductor region 61c is performed, for example, by injecting impurities containing boron (B), BF2, and at least one of them into the semiconductor region 61a.
[0131] According to the first manufacturing method, a semiconductor device in which the thickness T6 is larger than the thickness T2 and the thickness T4 can be easily manufactured. That is, according to the first manufacturing method, a semiconductor device in which the lower end of the sixth insulating portion 31c2 (third insulating region 31c) is located below the lower end of the second insulating portion 31a2 (first insulating region 31a) and the lower end of the fourth insulating portion 31b2 (second insulating region 31b) can be easily manufactured. Therefore, a semiconductor device capable of relaxing an electric field can be easily manufactured.
[0132] (Second Manufacturing Method)
[0133] Fig.12 (a)~ Fig.12 (e) is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to a second modification of the first embodiment.
[0134] like Fig.12 (a)~ Fig.12 As shown in (e), the second manufacturing method includes the first to fifth steps. The second step is performed after the first step. The third step is performed after the second step. The fourth step is performed after the third step. The fifth step is performed after the fourth step. Fig.12 (a) corresponds to the first step. Fig.12 (b) corresponds to the second step. Fig.12 (c) corresponds to the third step. Fig.12 (d) corresponds to the fourth step. Fig.12 (e) corresponds to the fifth step. Each step will be described below.
[0135] like Fig.12 As shown in (a), in the first step, a trench 65 is formed in a semiconductor region 61a of a first conductivity type (eg, n-type). Fig.12 (a)~ Fig.12 In (e), the position of the intersection of the trench 65 is shown. The semiconductor region 61a corresponds to the above-mentioned n - type drift region 21. The trench 65 is formed by, for example, etching or the like.
[0136] like Fig.12As shown in (b) of FIG. 6 , in the second step, a through hole 66 is formed below the intersection of the trench 65. The through hole 66 is formed by, for example, etching or the like.
[0137] like Fig.12 As shown in (c), in the third step, an insulating region 62a is formed inside the through hole 66, and an insulating region 62b is formed inside the trench 65 and on the semiconductor region 61a. The insulating region 62a and the insulating region 62b correspond to the gate insulating portion 31 (third insulating region 31c) described above. The insulating region 62a and the insulating region 62b are formed, for example, by etching and embedding a CVD film therein or by thermal oxidation.
[0138] like Fig.12 As shown in (d), in the fourth step, first, a conductive region 63a is formed inside the trench 65 in which the insulating region 62b is formed. The conductive region 63a is equivalent to the above-mentioned gate electrode 13 (third electrode region 13c). The formation of the conductive region 63a is performed, for example, by embedding polysilicon or a metal such as tungsten (W). Polysilicon may be undoped with impurities or may be doped with impurities. In the fourth step, then, an insulating region 62c is formed on the conductive region 63a. The insulating region 62c is equivalent to the above-mentioned insulating layer 51. The formation of the insulating region 62c is performed, for example, by thermal oxidation or CVD. The insulating region 62c may also be formed by oxidizing a portion of the conductive region 63a, for example, by an annealing step when the conductive region 63a is formed.
[0139] like Fig.12 As shown in (e), in the fifth step, a semiconductor region 61c of a second conductivity type (e.g., p-type) is formed on the upper portion of the semiconductor region 61a. The semiconductor region 61c corresponds to the above-mentioned p-type base region 22. The formation of the semiconductor region 61c is performed, for example, by injecting impurities containing boron (B), BF2, and at least one of them into the semiconductor region 61a.
[0140] According to the second manufacturing method, a semiconductor device in which the thickness T6 is larger than the thickness T2 and the thickness T4 can be easily manufactured. That is, according to the second manufacturing method, a semiconductor device in which the lower end of the sixth insulating portion 31c2 (third insulating region 31c) is located below the lower end of the second insulating portion 31a2 (first insulating region 31a) and the lower end of the fourth insulating portion 31b2 (second insulating region 31b) can be easily manufactured. Therefore, a semiconductor device capable of relaxing an electric field can be easily manufactured.
[0141] (Third Manufacturing Method)
[0142] Fig.13 (a)~ Fig.13(h) is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second embodiment.
[0143] like Fig.13 (a)~ Fig.13 As shown in (h), the third manufacturing method includes the first to eighth steps. The second step is performed after the first step. The third step is performed after the second step. The fourth step is performed after the third step. The fifth step is performed after the fourth step. The sixth step is performed after the fifth step. The seventh step is performed after the sixth step. The eighth step is performed after the seventh step. Fig.13 (a) corresponds to the first step. Fig.13 (b) corresponds to the second step. Fig.13 (c) corresponds to the third step. Fig.13 (d) corresponds to the fourth step. Fig.13 (e) is equivalent to the fifth step. Fig.13 (f) corresponds to the sixth step. Fig.13 (g) corresponds to the seventh step. Fig.13 (h) corresponds to the eighth step. Each step will be described below.
[0144] like Fig.12 As shown in (a), in the first step, a trench 75 is formed in a semiconductor region 71a of a first conductivity type (eg, n-type). Fig.13 (a)~ Fig.13 (h) shows the position of the intersection of the trench 75. The semiconductor region 71a corresponds to the above-mentioned n - type drift region 21. The trench 75 is formed by, for example, etching or the like.
[0145] like Fig.13 As shown in (b), in the second step, a semiconductor region 71b of a second conductivity type (e.g., p-type) is formed under the trench 75. The semiconductor region 71b is formed, for example, by injecting impurities containing boron (B), BF2, and at least one of them into the semiconductor region 71a.
[0146] like Fig.13 As shown in (c), in the third step, the semiconductor region 71b is changed into the insulating region 72a, and the insulating region 72b is formed inside the trench 75 and on the semiconductor region 71a. The insulating region 72a and the insulating region 72b are equivalent to the above-mentioned gate insulating portion 31 (third insulating region 31c). The formation of the insulating region 72a and the insulating region 72b is performed, for example, by accelerated oxidation.
[0147] like Fig.13As shown in (d), in the fourth step, a semiconductor region 71c and a semiconductor region 71d of the second conductivity type (for example, p-type) are formed under the insulating region 72a. The semiconductor region 71c and the semiconductor region 71d correspond to the p-type semiconductor region 71c and the p-type semiconductor region 71d described above. + type semiconductor region 24. The semiconductor region 71c and the semiconductor region 71d are formed by, for example, implanting impurities including boron (B), BF2, and at least one of them into the semiconductor region 71a.
[0148] like Fig.13 As shown in (e), in the fifth step, first, a conductive region 73a is formed inside the trench 75 in which the insulating region 72b is formed. The conductive region 73a corresponds to the gate electrode 13 (third electrode region 13c) described above. The conductive region 73a is formed, for example, by embedding a metal such as polysilicon or tungsten (W). Polysilicon may be undoped with impurities or may be doped with impurities. On the conductive region 73a, a portion of the conductive region 73a is oxidized by an annealing step when the conductive region 73a is formed, thereby forming the insulating region 72c.
[0149] like Fig.13 As shown in (f), in the sixth step, first, the insulating region 72b formed on the semiconductor region 71a and the insulating region 72c formed on the conductive region 73a are removed. The removal of the insulating region 72b and the insulating region 72c is performed, for example, by CMP (Chemical Mechanical Polishing) or etching. Etching is, for example, CDE (Chemical Dry Etching). In the sixth step, then, a portion (upper portion) of the conductive region 73a is removed to form a through hole 76. The formation of the through hole 76 is performed, for example, by etching.
[0150] like Fig.13 As shown in (g), in the seventh step, first, an insulating region 72d is formed inside the through hole 76, and an insulating region 72e is formed on the insulating region 72d and the semiconductor region 71a. The insulating region 72d is equivalent to the above-mentioned gate insulating portion 31 (third insulating region 31c). The insulating region 72e is equivalent to the above-mentioned insulating layer 51. The formation of the insulating region 72d and the insulating region 72e is performed, for example, by thermal oxidation or CVD. In the seventh step, then, a semiconductor region 71e of a second conductivity type (for example, p-type) is formed on the upper part of the semiconductor region 71a. The semiconductor region 71e is equivalent to the above-mentioned p-type base region 22. The formation of the semiconductor region 71e is performed, for example, by injecting impurities containing boron (B), BF2, and at least any one of them into the semiconductor region 71a.
[0151] like Fig.13 As shown in (h), in the eighth step, first, conductive regions 73b are formed on both sides of the portion of the insulating region 72d located above the conductive region 73a. The conductive region 73b corresponds to the second connecting portion 42 described above. The conductive region 73b is formed, for example, by CVD embedding of tungsten (W), sputtering of a barrier metal, etc. In the eighth step, then, a conductive region 73c is formed on the insulating region 72e and the conductive region 73b. The conductive region 73c corresponds to the source electrode 12 described above. The conductive region 73c is formed, for example, by the deposition of a metal such as aluminum (Al).
[0152] According to the third manufacturing method, a semiconductor device can be easily manufactured in which a p-type semiconductor device is provided under the third electrode region 13c of the gate electrode 13. + The gate insulating portion 31 has a third insulating region 31c (sixth insulating portion 31c2) with a lower end that is located below the lower end of the first insulating region 31a (second insulating portion 31a2) and the lower end of the second insulating region 31b (fourth insulating portion 31b2), and a second connecting portion 42 is provided on the side of the third insulating region 31c of the gate insulating portion 31. Therefore, a semiconductor device capable of relaxing an electric field can be easily manufactured.
[0153] The embodiments may include the following structures.
[0154] (Structure 1)
[0155] A semiconductor device comprising:
[0156] a first electrode;
[0157] A first semiconductor region of a first conductivity type, disposed on the first electrode;
[0158] A second semiconductor region of a second conductivity type, disposed on the first semiconductor region;
[0159] The third semiconductor region of the first conductivity type is disposed on the second semiconductor region;
[0160] A second electrode, disposed on the third semiconductor region and electrically connected to the third semiconductor region;
[0161] The third electrode includes a first electrode region, a second electrode region and a third electrode region,
[0162] The first electrode region extends along a second direction, the second direction is perpendicular to the first direction from the first electrode toward the second electrode, the first electrode region is arranged with the second semiconductor region in a third direction, the third direction is perpendicular to the first direction and intersects the second direction,
[0163] The second electrode region extends along the third direction and is aligned with the second semiconductor region in the second direction.
[0164] The third electrode region connects the first electrode region and the second electrode region;
[0165] A first insulating portion, comprising a first insulating region, a second insulating region and a third insulating region;
[0166] The first insulating region includes a first insulating portion and a second insulating portion, the first insulating portion is arranged between the second semiconductor region and the first electrode region in the third direction, and the second insulating portion is arranged between the first semiconductor region and the first electrode region in the first direction.
[0167] The second insulating region includes a third insulating portion and a fourth insulating portion, the third insulating portion is arranged between the second semiconductor region and the second electrode region in the second direction, and the fourth insulating portion is arranged between the first semiconductor region and the second electrode region in the first direction.
[0168] The third insulating region connects the first insulating region and the second insulating region, the third insulating region includes a fifth insulating portion and a sixth insulating portion, the fifth insulating portion is arranged between the second semiconductor region and the second electrode region in a fourth direction, the fourth direction is perpendicular to the first direction and intersects the second direction and the third direction, and the sixth insulating portion is arranged between the first semiconductor region and the third electrode region in the first direction;
[0169] a fourth electrode arranged with the first semiconductor region and the third electrode in the second direction and the third direction; and
[0170] A second insulating portion is provided between the fourth electrode and the first semiconductor region and between the fourth electrode and the third electrode in the second direction and the third direction,
[0171] A lower end of the sixth insulating portion is located below lower ends of the second insulating portion and the fourth insulating portion.
[0172] (Structure 2)
[0173] The semiconductor device according to Structure 1, wherein a thickness of the sixth insulating portion in the first direction is greater than a thickness of the second insulating portion in the first direction and a thickness of the fourth insulating portion in the first direction.
[0174] (Structure 3)
[0175] The semiconductor device according to Structure 1 or 2, wherein a thickness of the sixth insulating portion in the first direction is greater than a thickness of the fifth insulating portion in the fourth direction.
[0176] (Structure 4)
[0177] The semiconductor device according to any one of Structures 1 to 3, wherein a thickness of the sixth insulating portion in the first direction is greater than a half of a length of the third electrode region in the first direction.
[0178] (Structure 5)
[0179] The semiconductor device according to any one of Structures 1 to 4, wherein a lower end of the third electrode region is located below lower ends of the first electrode region and the second electrode region.
[0180] (Structure 6)
[0181] The semiconductor device according to any one of Structures 1 to 5, wherein a lower end of the third electrode region is located above a lower end of the fourth electrode.
[0182] (Structure 7)
[0183] The semiconductor device according to any one of Structures 1 to 6, further comprising a fourth semiconductor region of the second conductivity type provided under the sixth insulating portion.
[0184] (Structure 8)
[0185] The semiconductor device according to any one of Structures 1 to 7, further comprising:
[0186] a first connecting portion, disposed between the third insulating region and the second insulating portion in the second direction and the third direction, electrically connecting the second electrode and the second semiconductor region; and
[0187] The second connection portion is provided between the third insulating region and the first connection portion in the fourth direction, and electrically connects the second electrode and the second semiconductor region.
[0188] As described above, according to the embodiment, a semiconductor device capable of relaxing an electric field can be provided.
[0189] The embodiments of the present invention are described above, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the main purpose of the invention. These embodiments and their variations are included in the scope and main purpose of the invention, and are included in the scope of the invention and its equivalents recorded in the claims.
[0190] [Explanation of Reference Numerals]
[0191] 11: Drain electrode (first electrode)
[0192] 12: Source electrode (second electrode)
[0193] 13: Gate electrode (third electrode)
[0194] 13a: First electrode region
[0195] 13b: Second electrode region
[0196] 13c: Third electrode region
[0197] 14: FP electrode (fourth electrode)
[0198] 15: Gate pad
[0199] 21:n - Type drift region (first semiconductor region)
[0200] 22: p-type base region (second semiconductor region)
[0201] 23:n + Type source region (third semiconductor region)
[0202] 24: p + Type semiconductor region (fourth semiconductor region)
[0203] 24a: First semiconductor portion
[0204] 24b: Second semiconductor portion
[0205] 24c: The third semiconductor part
[0206] 24d: The fourth semiconductor part
[0207] 24e: Fifth Semiconductor Section
[0208] 24f: The sixth semiconductor part
[0209] 27: p + Type contact area
[0210] 28:n +Type Drain Region
[0211] 31: Gate insulating portion (first insulating portion)
[0212] 31a: First insulation area
[0213] 31a1: First insulating part
[0214] 31a2: Second insulating part
[0215] 31b: Second insulation area
[0216] 31b1: The third insulating part
[0217] 31b2: Fourth insulating part
[0218] 31c: The third insulation area
[0219] 31c1: Fifth insulating part
[0220] 31c2: Sixth insulating part
[0221] 32: FP insulating part (second insulating part)
[0222] 41: First connection part
[0223] 42: Second connection part
[0224] 51: Insulation layer
[0225] 61a, 61b, 61c: semiconductor region
[0226] 62a, 62b, 62c: Insulation area
[0227] 63a: Conductive area
[0228] 65: Groove
[0229] 66: Through hole
[0230] 71a, 71b, 71c, 71d, 71e: semiconductor region
[0231] 72a, 72b, 72c, 72d, 72e: Insulation area
[0232] 73a, 73b, 73c: Conductive area
[0233] 75: Groove
[0234] 76: Through hole
[0235] 100, 100A, 100B, 100C, 200: semiconductor devices.
Claims
1. A semiconductor device comprising: a first electrode; A first semiconductor region of a first conductivity type, disposed on the first electrode; A second semiconductor region of a second conductivity type, disposed on the first semiconductor region; The third semiconductor region of the first conductivity type is disposed on the second semiconductor region; A second electrode, disposed on the third semiconductor region and electrically connected to the third semiconductor region; The third electrode includes a first electrode region, a second electrode region and a third electrode region, The first electrode region extends along a second direction, the second direction is perpendicular to the first direction from the first electrode toward the second electrode, the first electrode region is arranged with the second semiconductor region in a third direction, the third direction is perpendicular to the first direction and intersects the second direction, The second electrode region extends along the third direction and is aligned with the second semiconductor region in the second direction. The third electrode region connects the first electrode region and the second electrode region; A first insulating portion, comprising a first insulating region, a second insulating region and a third insulating region; The first insulating region includes a first insulating portion and a second insulating portion, the first insulating portion is arranged between the second semiconductor region and the first electrode region in the third direction, and the second insulating portion is arranged between the first semiconductor region and the first electrode region in the first direction. The second insulating region includes a third insulating portion and a fourth insulating portion, the third insulating portion is arranged between the second semiconductor region and the second electrode region in the second direction, and the fourth insulating portion is arranged between the first semiconductor region and the second electrode region in the first direction. The third insulating region connects the first insulating region and the second insulating region, the third insulating region includes a fifth insulating portion and a sixth insulating portion, the fifth insulating portion is arranged between the second semiconductor region and the second electrode region in a fourth direction, the fourth direction is perpendicular to the first direction and intersects the second direction and the third direction, and the sixth insulating portion is arranged between the first semiconductor region and the third electrode region in the first direction; a fourth electrode arranged with the first semiconductor region and the third electrode in the second direction and the third direction; as well as A second insulating portion is provided between the fourth electrode and the first semiconductor region and between the fourth electrode and the third electrode in the second direction and the third direction, A lower end of the sixth insulating portion is located below lower ends of the second insulating portion and the fourth insulating portion.
2. The semiconductor device according to claim 1, wherein The thickness of the sixth insulating portion in the first direction is greater than the thickness of the second insulating portion in the first direction and the thickness of the fourth insulating portion in the first direction.
3. The semiconductor device according to claim 2, wherein: A thickness of the sixth insulating portion in the first direction is greater than a thickness of the fifth insulating portion in the fourth direction.
4. The semiconductor device according to claim 2, wherein: A thickness of the sixth insulating portion in the first direction is greater than a half of a length of the third electrode region in the first direction.
5. The semiconductor device according to claim 1, wherein The lower end of the third electrode region is located below the lower ends of the first electrode region and the second electrode region.
6. The semiconductor device according to claim 5, wherein: The lower end of the third electrode region is located above the lower end of the fourth electrode.
7. The semiconductor device according to claim 1, wherein The device further includes a fourth semiconductor region of the second conductivity type provided under the sixth insulating portion.
8. The semiconductor device according to claim 1, wherein Also available: a first connecting portion, disposed between the third insulating region and the second insulating portion in the second direction and the third direction, and electrically connecting the second electrode and the second semiconductor region; as well as The second connection portion is provided between the third insulating region and the first connection portion in the fourth direction, and electrically connects the second electrode and the second semiconductor region.
9. The semiconductor device according to claim 1, wherein: A width of the sixth insulating portion in the fourth direction is smaller than a width of the third electrode region in the fourth direction.
10. The semiconductor device according to claim 1, wherein A width of the sixth insulating portion in the fourth direction is the same as a width of the third electrode region in the fourth direction.
11. The semiconductor device according to claim 1, wherein The lower ends of the second insulating portion, the fourth insulating portion, and the sixth insulating portion are respectively located above the center of the upper end of the fourth electrode and the lower end of the fourth electrode.
Citation Information
Patent Citations
Method and drug for regulating and controlling GLP-1 / GLP-1r
JP2023156429A